1//===- NVPTXInstrFormats.td - NVPTX Instruction Formats-------*- tblgen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Describe NVPTX instructions format 11// 12//===----------------------------------------------------------------------===// 13 14// Vector instruction type enum 15class VecInstTypeEnum<bits<4> val> { 16 bits<4> Value=val; 17} 18def VecNOP : VecInstTypeEnum<0>; 19 20// Generic NVPTX Format 21 22class NVPTXInst<dag outs, dag ins, string asmstr, list<dag> pattern> 23 : Instruction { 24 field bits<14> Inst; 25 26 let Namespace = "NVPTX"; 27 dag OutOperandList = outs; 28 dag InOperandList = ins; 29 let AsmString = asmstr; 30 let Pattern = pattern; 31 32 // TSFlagFields 33 bits<4> VecInstType = VecNOP.Value; 34 bit IsSimpleMove = false; 35 bit IsLoad = false; 36 bit IsStore = false; 37 38 bit IsTex = false; 39 bit IsSust = false; 40 bit IsSurfTexQuery = false; 41 bit IsTexModeUnified = false; 42 43 // The following field is encoded as log2 of the vector size minus one, 44 // with 0 meaning the operation is not a surface instruction. For example, 45 // if IsSuld == 2, then the instruction is a suld instruction with vector size 46 // 2**(2-1) = 2. 47 bits<2> IsSuld = 0; 48 49 let TSFlags{3...0} = VecInstType; 50 let TSFlags{4...4} = IsSimpleMove; 51 let TSFlags{5...5} = IsLoad; 52 let TSFlags{6...6} = IsStore; 53 let TSFlags{7} = IsTex; 54 let TSFlags{9...8} = IsSuld; 55 let TSFlags{10} = IsSust; 56 let TSFlags{11} = IsSurfTexQuery; 57 let TSFlags{12} = IsTexModeUnified; 58} 59