1//===- NVPTX.td - Describe the NVPTX Target Machine -----------*- tblgen -*-==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// This is the top level entry point for the NVPTX target. 9//===----------------------------------------------------------------------===// 10 11//===----------------------------------------------------------------------===// 12// Target-independent interfaces 13//===----------------------------------------------------------------------===// 14 15include "llvm/Target/Target.td" 16 17include "NVPTXRegisterInfo.td" 18include "NVPTXInstrInfo.td" 19 20//===----------------------------------------------------------------------===// 21// Subtarget Features. 22// - We use the SM version number instead of explicit feature table. 23// - Need at least one feature to avoid generating zero sized array by 24// TableGen in NVPTXGenSubtarget.inc. 25//===----------------------------------------------------------------------===// 26 27class FeatureSM<string sm, int value>: 28 SubtargetFeature<"sm_"# sm, "FullSmVersion", 29 "" # value, 30 "Target SM " # sm>; 31 32class FeaturePTX<int version>: 33 SubtargetFeature<"ptx"# version, "PTXVersion", 34 "" # version, 35 "Use PTX version " # version>; 36 37foreach sm = [20, 21, 30, 32, 35, 37, 50, 52, 53, 38 60, 61, 62, 70, 72, 75, 80, 86, 87, 89, 90] in 39 def SM#sm: FeatureSM<""#sm, !mul(sm, 10)>; 40 41def SM90a: FeatureSM<"90a", 901>; 42 43foreach version = [32, 40, 41, 42, 43, 50, 60, 61, 63, 64, 65, 44 70, 71, 72, 73, 74, 75, 76, 77, 78, 80, 81, 82, 83] in 45 def PTX#version: FeaturePTX<version>; 46 47//===----------------------------------------------------------------------===// 48// NVPTX supported processors. 49//===----------------------------------------------------------------------===// 50 51class Proc<string Name, list<SubtargetFeature> Features> 52 : Processor<Name, NoItineraries, Features>; 53 54def : Proc<"sm_20", [SM20, PTX32]>; 55def : Proc<"sm_21", [SM21, PTX32]>; 56def : Proc<"sm_30", [SM30]>; 57def : Proc<"sm_32", [SM32, PTX40]>; 58def : Proc<"sm_35", [SM35, PTX32]>; 59def : Proc<"sm_37", [SM37, PTX41]>; 60def : Proc<"sm_50", [SM50, PTX40]>; 61def : Proc<"sm_52", [SM52, PTX41]>; 62def : Proc<"sm_53", [SM53, PTX42]>; 63def : Proc<"sm_60", [SM60, PTX50]>; 64def : Proc<"sm_61", [SM61, PTX50]>; 65def : Proc<"sm_62", [SM62, PTX50]>; 66def : Proc<"sm_70", [SM70, PTX60]>; 67def : Proc<"sm_72", [SM72, PTX61]>; 68def : Proc<"sm_75", [SM75, PTX63]>; 69def : Proc<"sm_80", [SM80, PTX70]>; 70def : Proc<"sm_86", [SM86, PTX71]>; 71def : Proc<"sm_87", [SM87, PTX74]>; 72def : Proc<"sm_89", [SM89, PTX78]>; 73def : Proc<"sm_90", [SM90, PTX78]>; 74def : Proc<"sm_90a", [SM90a, PTX80]>; 75 76def NVPTXInstrInfo : InstrInfo { 77} 78 79def NVPTX : Target { 80 let InstructionSet = NVPTXInstrInfo; 81} 82