1//===- NVPTX.td - Describe the NVPTX Target Machine -----------*- tblgen -*-==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// This is the top level entry point for the NVPTX target. 9//===----------------------------------------------------------------------===// 10 11//===----------------------------------------------------------------------===// 12// Target-independent interfaces 13//===----------------------------------------------------------------------===// 14 15include "llvm/Target/Target.td" 16 17include "NVPTXRegisterInfo.td" 18include "NVPTXInstrInfo.td" 19 20//===----------------------------------------------------------------------===// 21// Subtarget Features. 22// - We use the SM version number instead of explicit feature table. 23// - Need at least one feature to avoid generating zero sized array by 24// TableGen in NVPTXGenSubtarget.inc. 25//===----------------------------------------------------------------------===// 26 27// SM Versions 28def SM20 : SubtargetFeature<"sm_20", "SmVersion", "20", 29 "Target SM 2.0">; 30def SM21 : SubtargetFeature<"sm_21", "SmVersion", "21", 31 "Target SM 2.1">; 32def SM30 : SubtargetFeature<"sm_30", "SmVersion", "30", 33 "Target SM 3.0">; 34def SM32 : SubtargetFeature<"sm_32", "SmVersion", "32", 35 "Target SM 3.2">; 36def SM35 : SubtargetFeature<"sm_35", "SmVersion", "35", 37 "Target SM 3.5">; 38def SM37 : SubtargetFeature<"sm_37", "SmVersion", "37", 39 "Target SM 3.7">; 40def SM50 : SubtargetFeature<"sm_50", "SmVersion", "50", 41 "Target SM 5.0">; 42def SM52 : SubtargetFeature<"sm_52", "SmVersion", "52", 43 "Target SM 5.2">; 44def SM53 : SubtargetFeature<"sm_53", "SmVersion", "53", 45 "Target SM 5.3">; 46def SM60 : SubtargetFeature<"sm_60", "SmVersion", "60", 47 "Target SM 6.0">; 48def SM61 : SubtargetFeature<"sm_61", "SmVersion", "61", 49 "Target SM 6.1">; 50def SM62 : SubtargetFeature<"sm_62", "SmVersion", "62", 51 "Target SM 6.2">; 52def SM70 : SubtargetFeature<"sm_70", "SmVersion", "70", 53 "Target SM 7.0">; 54def SM72 : SubtargetFeature<"sm_72", "SmVersion", "72", 55 "Target SM 7.2">; 56def SM75 : SubtargetFeature<"sm_75", "SmVersion", "75", 57 "Target SM 7.5">; 58 59// PTX Versions 60def PTX32 : SubtargetFeature<"ptx32", "PTXVersion", "32", 61 "Use PTX version 3.2">; 62def PTX40 : SubtargetFeature<"ptx40", "PTXVersion", "40", 63 "Use PTX version 4.0">; 64def PTX41 : SubtargetFeature<"ptx41", "PTXVersion", "41", 65 "Use PTX version 4.1">; 66def PTX42 : SubtargetFeature<"ptx42", "PTXVersion", "42", 67 "Use PTX version 4.2">; 68def PTX43 : SubtargetFeature<"ptx43", "PTXVersion", "43", 69 "Use PTX version 4.3">; 70def PTX50 : SubtargetFeature<"ptx50", "PTXVersion", "50", 71 "Use PTX version 5.0">; 72def PTX60 : SubtargetFeature<"ptx60", "PTXVersion", "60", 73 "Use PTX version 6.0">; 74def PTX61 : SubtargetFeature<"ptx61", "PTXVersion", "61", 75 "Use PTX version 6.1">; 76def PTX63 : SubtargetFeature<"ptx63", "PTXVersion", "63", 77 "Use PTX version 6.3">; 78def PTX64 : SubtargetFeature<"ptx64", "PTXVersion", "64", 79 "Use PTX version 6.4">; 80 81//===----------------------------------------------------------------------===// 82// NVPTX supported processors. 83//===----------------------------------------------------------------------===// 84 85class Proc<string Name, list<SubtargetFeature> Features> 86 : Processor<Name, NoItineraries, Features>; 87 88def : Proc<"sm_20", [SM20]>; 89def : Proc<"sm_21", [SM21]>; 90def : Proc<"sm_30", [SM30]>; 91def : Proc<"sm_32", [SM32, PTX40]>; 92def : Proc<"sm_35", [SM35]>; 93def : Proc<"sm_37", [SM37, PTX41]>; 94def : Proc<"sm_50", [SM50, PTX40]>; 95def : Proc<"sm_52", [SM52, PTX41]>; 96def : Proc<"sm_53", [SM53, PTX42]>; 97def : Proc<"sm_60", [SM60, PTX50]>; 98def : Proc<"sm_61", [SM61, PTX50]>; 99def : Proc<"sm_62", [SM62, PTX50]>; 100def : Proc<"sm_70", [SM70, PTX60]>; 101def : Proc<"sm_72", [SM72, PTX61]>; 102def : Proc<"sm_75", [SM75, PTX63]>; 103 104def NVPTXInstrInfo : InstrInfo { 105} 106 107def NVPTX : Target { 108 let InstructionSet = NVPTXInstrInfo; 109} 110