1 //===-- NVPTX.h - Top-level interface for NVPTX representation --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the entry points for global functions defined in 10 // the LLVM NVPTX back-end. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTX_H 15 #define LLVM_LIB_TARGET_NVPTX_NVPTX_H 16 17 #include "llvm/Pass.h" 18 #include "llvm/Support/CodeGen.h" 19 20 namespace llvm { 21 class NVPTXTargetMachine; 22 class FunctionPass; 23 class MachineFunctionPass; 24 class formatted_raw_ostream; 25 26 namespace NVPTXCC { 27 enum CondCodes { 28 EQ, 29 NE, 30 LT, 31 LE, 32 GT, 33 GE 34 }; 35 } 36 37 FunctionPass *createNVPTXISelDag(NVPTXTargetMachine &TM, 38 llvm::CodeGenOpt::Level OptLevel); 39 ModulePass *createNVPTXAssignValidGlobalNamesPass(); 40 ModulePass *createGenericToNVVMPass(); 41 FunctionPass *createNVVMIntrRangePass(unsigned int SmVersion); 42 FunctionPass *createNVVMReflectPass(unsigned int SmVersion); 43 MachineFunctionPass *createNVPTXPrologEpilogPass(); 44 MachineFunctionPass *createNVPTXReplaceImageHandlesPass(); 45 FunctionPass *createNVPTXImageOptimizerPass(); 46 FunctionPass *createNVPTXLowerArgsPass(const NVPTXTargetMachine *TM); 47 FunctionPass *createNVPTXLowerAllocaPass(); 48 MachineFunctionPass *createNVPTXPeephole(); 49 MachineFunctionPass *createNVPTXProxyRegErasurePass(); 50 51 namespace NVPTX { 52 enum DrvInterface { 53 NVCL, 54 CUDA 55 }; 56 57 // A field inside TSFlags needs a shift and a mask. The usage is 58 // always as follows : 59 // ((TSFlags & fieldMask) >> fieldShift) 60 // The enum keeps the mask, the shift, and all valid values of the 61 // field in one place. 62 enum VecInstType { 63 VecInstTypeShift = 0, 64 VecInstTypeMask = 0xF, 65 66 VecNOP = 0, 67 VecLoad = 1, 68 VecStore = 2, 69 VecBuild = 3, 70 VecShuffle = 4, 71 VecExtract = 5, 72 VecInsert = 6, 73 VecDest = 7, 74 VecOther = 15 75 }; 76 77 enum SimpleMove { 78 SimpleMoveMask = 0x10, 79 SimpleMoveShift = 4 80 }; 81 enum LoadStore { 82 isLoadMask = 0x20, 83 isLoadShift = 5, 84 isStoreMask = 0x40, 85 isStoreShift = 6 86 }; 87 88 namespace PTXLdStInstCode { 89 enum AddressSpace { 90 GENERIC = 0, 91 GLOBAL = 1, 92 CONSTANT = 2, 93 SHARED = 3, 94 PARAM = 4, 95 LOCAL = 5 96 }; 97 enum FromType { 98 Unsigned = 0, 99 Signed, 100 Float, 101 Untyped 102 }; 103 enum VecType { 104 Scalar = 1, 105 V2 = 2, 106 V4 = 4 107 }; 108 } 109 110 /// PTXCvtMode - Conversion code enumeration 111 namespace PTXCvtMode { 112 enum CvtMode { 113 NONE = 0, 114 RNI, 115 RZI, 116 RMI, 117 RPI, 118 RN, 119 RZ, 120 RM, 121 RP, 122 123 BASE_MASK = 0x0F, 124 FTZ_FLAG = 0x10, 125 SAT_FLAG = 0x20 126 }; 127 } 128 129 /// PTXCmpMode - Comparison mode enumeration 130 namespace PTXCmpMode { 131 enum CmpMode { 132 EQ = 0, 133 NE, 134 LT, 135 LE, 136 GT, 137 GE, 138 LO, 139 LS, 140 HI, 141 HS, 142 EQU, 143 NEU, 144 LTU, 145 LEU, 146 GTU, 147 GEU, 148 NUM, 149 // NAN is a MACRO 150 NotANumber, 151 152 BASE_MASK = 0xFF, 153 FTZ_FLAG = 0x100 154 }; 155 } 156 } 157 } // end namespace llvm; 158 159 // Defines symbolic names for NVPTX registers. This defines a mapping from 160 // register name to register number. 161 #define GET_REGINFO_ENUM 162 #include "NVPTXGenRegisterInfo.inc" 163 164 // Defines symbolic names for the NVPTX instructions. 165 #define GET_INSTRINFO_ENUM 166 #include "NVPTXGenInstrInfo.inc" 167 168 #endif 169