1 //===-- MipsTargetTransformInfo.cpp - Mips specific TTI ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MipsTargetTransformInfo.h" 10 11 using namespace llvm; 12 13 bool MipsTTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) const { 14 EVT VT = TLI->getValueType(DL, DataType); 15 return TLI->isOperationLegalOrCustom(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, 16 VT); 17 } 18 19 bool MipsTTIImpl::isLSRCostLess(const TargetTransformInfo::LSRCost &C1, 20 const TargetTransformInfo::LSRCost &C2) const { 21 // MIPS specific here are "instruction number 1st priority". 22 // If we need to emit adds inside the loop to add up base registers, then 23 // we need at least one extra temporary register. 24 unsigned C1NumRegs = C1.NumRegs + (C1.NumBaseAdds != 0); 25 unsigned C2NumRegs = C2.NumRegs + (C2.NumBaseAdds != 0); 26 return std::tie(C1.Insns, C1NumRegs, C1.AddRecCost, C1.NumIVMuls, 27 C1.NumBaseAdds, C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 28 std::tie(C2.Insns, C2NumRegs, C2.AddRecCost, C2.NumIVMuls, 29 C2.NumBaseAdds, C2.ScaleCost, C2.ImmCost, C2.SetupCost); 30 } 31