1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // Implements the info about Mips target spec. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MipsTargetMachine.h" 14 #include "MCTargetDesc/MipsABIInfo.h" 15 #include "MCTargetDesc/MipsMCTargetDesc.h" 16 #include "Mips.h" 17 #include "Mips16ISelDAGToDAG.h" 18 #include "MipsSEISelDAGToDAG.h" 19 #include "MipsSubtarget.h" 20 #include "MipsTargetObjectFile.h" 21 #include "TargetInfo/MipsTargetInfo.h" 22 #include "llvm/ADT/Optional.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringRef.h" 25 #include "llvm/Analysis/TargetTransformInfo.h" 26 #include "llvm/CodeGen/BasicTTIImpl.h" 27 #include "llvm/CodeGen/GlobalISel/IRTranslator.h" 28 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" 29 #include "llvm/CodeGen/GlobalISel/Legalizer.h" 30 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h" 31 #include "llvm/CodeGen/MachineFunction.h" 32 #include "llvm/CodeGen/Passes.h" 33 #include "llvm/CodeGen/TargetPassConfig.h" 34 #include "llvm/IR/Attributes.h" 35 #include "llvm/IR/Function.h" 36 #include "llvm/InitializePasses.h" 37 #include "llvm/MC/TargetRegistry.h" 38 #include "llvm/Support/CodeGen.h" 39 #include "llvm/Support/Debug.h" 40 #include "llvm/Support/raw_ostream.h" 41 #include "llvm/Target/TargetOptions.h" 42 #include <string> 43 44 using namespace llvm; 45 46 #define DEBUG_TYPE "mips" 47 48 static cl::opt<bool> 49 EnableMulMulFix("mfix4300", cl::init(false), 50 cl::desc("Enable the VR4300 mulmul bug fix."), cl::Hidden); 51 52 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTarget() { 53 // Register the target. 54 RegisterTargetMachine<MipsebTargetMachine> X(getTheMipsTarget()); 55 RegisterTargetMachine<MipselTargetMachine> Y(getTheMipselTarget()); 56 RegisterTargetMachine<MipsebTargetMachine> A(getTheMips64Target()); 57 RegisterTargetMachine<MipselTargetMachine> B(getTheMips64elTarget()); 58 59 PassRegistry *PR = PassRegistry::getPassRegistry(); 60 initializeGlobalISel(*PR); 61 initializeMipsDelaySlotFillerPass(*PR); 62 initializeMipsBranchExpansionPass(*PR); 63 initializeMicroMipsSizeReducePass(*PR); 64 initializeMipsPreLegalizerCombinerPass(*PR); 65 initializeMipsMulMulBugFixPass(*PR); 66 } 67 68 static std::string computeDataLayout(const Triple &TT, StringRef CPU, 69 const TargetOptions &Options, 70 bool isLittle) { 71 std::string Ret; 72 MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions); 73 74 // There are both little and big endian mips. 75 if (isLittle) 76 Ret += "e"; 77 else 78 Ret += "E"; 79 80 if (ABI.IsO32()) 81 Ret += "-m:m"; 82 else 83 Ret += "-m:e"; 84 85 // Pointers are 32 bit on some ABIs. 86 if (!ABI.IsN64()) 87 Ret += "-p:32:32"; 88 89 // 8 and 16 bit integers only need to have natural alignment, but try to 90 // align them to 32 bits. 64 bit integers have natural alignment. 91 Ret += "-i8:8:32-i16:16:32-i64:64"; 92 93 // 32 bit registers are always available and the stack is at least 64 bit 94 // aligned. On N64 64 bit registers are also available and the stack is 95 // 128 bit aligned. 96 if (ABI.IsN64() || ABI.IsN32()) 97 Ret += "-n32:64-S128"; 98 else 99 Ret += "-n32-S64"; 100 101 return Ret; 102 } 103 104 static Reloc::Model getEffectiveRelocModel(bool JIT, 105 Optional<Reloc::Model> RM) { 106 if (!RM.hasValue() || JIT) 107 return Reloc::Static; 108 return *RM; 109 } 110 111 // On function prologue, the stack is created by decrementing 112 // its pointer. Once decremented, all references are done with positive 113 // offset from the stack/frame pointer, using StackGrowsUp enables 114 // an easier handling. 115 // Using CodeModel::Large enables different CALL behavior. 116 MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT, 117 StringRef CPU, StringRef FS, 118 const TargetOptions &Options, 119 Optional<Reloc::Model> RM, 120 Optional<CodeModel::Model> CM, 121 CodeGenOpt::Level OL, bool JIT, 122 bool isLittle) 123 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, 124 CPU, FS, Options, getEffectiveRelocModel(JIT, RM), 125 getEffectiveCodeModel(CM, CodeModel::Small), OL), 126 isLittle(isLittle), TLOF(std::make_unique<MipsTargetObjectFile>()), 127 ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)), 128 Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this, None), 129 NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16", 130 isLittle, *this, None), 131 Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16", 132 isLittle, *this, None) { 133 Subtarget = &DefaultSubtarget; 134 initAsmInfo(); 135 136 // Mips supports the debug entry values. 137 setSupportsDebugEntryValues(true); 138 } 139 140 MipsTargetMachine::~MipsTargetMachine() = default; 141 142 void MipsebTargetMachine::anchor() {} 143 144 MipsebTargetMachine::MipsebTargetMachine(const Target &T, const Triple &TT, 145 StringRef CPU, StringRef FS, 146 const TargetOptions &Options, 147 Optional<Reloc::Model> RM, 148 Optional<CodeModel::Model> CM, 149 CodeGenOpt::Level OL, bool JIT) 150 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} 151 152 void MipselTargetMachine::anchor() {} 153 154 MipselTargetMachine::MipselTargetMachine(const Target &T, const Triple &TT, 155 StringRef CPU, StringRef FS, 156 const TargetOptions &Options, 157 Optional<Reloc::Model> RM, 158 Optional<CodeModel::Model> CM, 159 CodeGenOpt::Level OL, bool JIT) 160 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {} 161 162 const MipsSubtarget * 163 MipsTargetMachine::getSubtargetImpl(const Function &F) const { 164 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 165 Attribute FSAttr = F.getFnAttribute("target-features"); 166 167 std::string CPU = 168 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU; 169 std::string FS = 170 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS; 171 bool hasMips16Attr = F.getFnAttribute("mips16").isValid(); 172 bool hasNoMips16Attr = F.getFnAttribute("nomips16").isValid(); 173 174 bool HasMicroMipsAttr = F.getFnAttribute("micromips").isValid(); 175 bool HasNoMicroMipsAttr = F.getFnAttribute("nomicromips").isValid(); 176 177 // FIXME: This is related to the code below to reset the target options, 178 // we need to know whether or not the soft float flag is set on the 179 // function, so we can enable it as a subtarget feature. 180 bool softFloat = F.getFnAttribute("use-soft-float").getValueAsBool(); 181 182 if (hasMips16Attr) 183 FS += FS.empty() ? "+mips16" : ",+mips16"; 184 else if (hasNoMips16Attr) 185 FS += FS.empty() ? "-mips16" : ",-mips16"; 186 if (HasMicroMipsAttr) 187 FS += FS.empty() ? "+micromips" : ",+micromips"; 188 else if (HasNoMicroMipsAttr) 189 FS += FS.empty() ? "-micromips" : ",-micromips"; 190 if (softFloat) 191 FS += FS.empty() ? "+soft-float" : ",+soft-float"; 192 193 auto &I = SubtargetMap[CPU + FS]; 194 if (!I) { 195 // This needs to be done before we create a new subtarget since any 196 // creation will depend on the TM and the code generation flags on the 197 // function that reside in TargetOptions. 198 resetTargetOptions(F); 199 I = std::make_unique<MipsSubtarget>( 200 TargetTriple, CPU, FS, isLittle, *this, 201 MaybeAlign(F.getParent()->getOverrideStackAlignment())); 202 } 203 return I.get(); 204 } 205 206 void MipsTargetMachine::resetSubtarget(MachineFunction *MF) { 207 LLVM_DEBUG(dbgs() << "resetSubtarget\n"); 208 209 Subtarget = &MF->getSubtarget<MipsSubtarget>(); 210 } 211 212 namespace { 213 214 /// Mips Code Generator Pass Configuration Options. 215 class MipsPassConfig : public TargetPassConfig { 216 public: 217 MipsPassConfig(MipsTargetMachine &TM, PassManagerBase &PM) 218 : TargetPassConfig(TM, PM) { 219 // The current implementation of long branch pass requires a scratch 220 // register ($at) to be available before branch instructions. Tail merging 221 // can break this requirement, so disable it when long branch pass is 222 // enabled. 223 EnableTailMerge = !getMipsSubtarget().enableLongBranchPass(); 224 } 225 226 MipsTargetMachine &getMipsTargetMachine() const { 227 return getTM<MipsTargetMachine>(); 228 } 229 230 const MipsSubtarget &getMipsSubtarget() const { 231 return *getMipsTargetMachine().getSubtargetImpl(); 232 } 233 234 void addIRPasses() override; 235 bool addInstSelector() override; 236 void addPreEmitPass() override; 237 void addPreRegAlloc() override; 238 bool addIRTranslator() override; 239 void addPreLegalizeMachineIR() override; 240 bool addLegalizeMachineIR() override; 241 bool addRegBankSelect() override; 242 bool addGlobalInstructionSelect() override; 243 244 std::unique_ptr<CSEConfigBase> getCSEConfig() const override; 245 }; 246 247 } // end anonymous namespace 248 249 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) { 250 return new MipsPassConfig(*this, PM); 251 } 252 253 std::unique_ptr<CSEConfigBase> MipsPassConfig::getCSEConfig() const { 254 return getStandardCSEConfigForOpt(TM->getOptLevel()); 255 } 256 257 void MipsPassConfig::addIRPasses() { 258 TargetPassConfig::addIRPasses(); 259 addPass(createAtomicExpandPass()); 260 if (getMipsSubtarget().os16()) 261 addPass(createMipsOs16Pass()); 262 if (getMipsSubtarget().inMips16HardFloat()) 263 addPass(createMips16HardFloatPass()); 264 } 265 // Install an instruction selector pass using 266 // the ISelDag to gen Mips code. 267 bool MipsPassConfig::addInstSelector() { 268 addPass(createMipsModuleISelDagPass()); 269 addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel())); 270 addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel())); 271 return false; 272 } 273 274 void MipsPassConfig::addPreRegAlloc() { 275 addPass(createMipsOptimizePICCallPass()); 276 } 277 278 TargetTransformInfo 279 MipsTargetMachine::getTargetTransformInfo(const Function &F) { 280 if (Subtarget->allowMixed16_32()) { 281 LLVM_DEBUG(errs() << "No Target Transform Info Pass Added\n"); 282 // FIXME: This is no longer necessary as the TTI returned is per-function. 283 return TargetTransformInfo(F.getParent()->getDataLayout()); 284 } 285 286 LLVM_DEBUG(errs() << "Target Transform Info Pass Added\n"); 287 return TargetTransformInfo(BasicTTIImpl(this, F)); 288 } 289 290 // Implemented by targets that want to run passes immediately before 291 // machine code is emitted. 292 void MipsPassConfig::addPreEmitPass() { 293 // Expand pseudo instructions that are sensitive to register allocation. 294 addPass(createMipsExpandPseudoPass()); 295 296 // The microMIPS size reduction pass performs instruction reselection for 297 // instructions which can be remapped to a 16 bit instruction. 298 addPass(createMicroMipsSizeReducePass()); 299 300 // This pass inserts a nop instruction between two back-to-back multiplication 301 // instructions when the "mfix4300" flag is passed. 302 if (EnableMulMulFix) 303 addPass(createMipsMulMulBugPass()); 304 305 // The delay slot filler pass can potientially create forbidden slot hazards 306 // for MIPSR6 and therefore it should go before MipsBranchExpansion pass. 307 addPass(createMipsDelaySlotFillerPass()); 308 309 // This pass expands branches and takes care about the forbidden slot hazards. 310 // Expanding branches may potentially create forbidden slot hazards for 311 // MIPSR6, and fixing such hazard may potentially break a branch by extending 312 // its offset out of range. That's why this pass combine these two tasks, and 313 // runs them alternately until one of them finishes without any changes. Only 314 // then we can be sure that all branches are expanded properly and no hazards 315 // exists. 316 // Any new pass should go before this pass. 317 addPass(createMipsBranchExpansion()); 318 319 addPass(createMipsConstantIslandPass()); 320 } 321 322 bool MipsPassConfig::addIRTranslator() { 323 addPass(new IRTranslator(getOptLevel())); 324 return false; 325 } 326 327 void MipsPassConfig::addPreLegalizeMachineIR() { 328 addPass(createMipsPreLegalizeCombiner()); 329 } 330 331 bool MipsPassConfig::addLegalizeMachineIR() { 332 addPass(new Legalizer()); 333 return false; 334 } 335 336 bool MipsPassConfig::addRegBankSelect() { 337 addPass(new RegBankSelect()); 338 return false; 339 } 340 341 bool MipsPassConfig::addGlobalInstructionSelect() { 342 addPass(new InstructionSelect(getOptLevel())); 343 return false; 344 } 345