xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MipsTargetMachine.cpp (revision cfd6422a5217410fbd66f7a7a8a64d9d85e61229)
1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about Mips target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsTargetMachine.h"
14 #include "MCTargetDesc/MipsABIInfo.h"
15 #include "MCTargetDesc/MipsMCTargetDesc.h"
16 #include "Mips.h"
17 #include "Mips16ISelDAGToDAG.h"
18 #include "MipsSEISelDAGToDAG.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetObjectFile.h"
21 #include "TargetInfo/MipsTargetInfo.h"
22 #include "llvm/ADT/Optional.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/Analysis/TargetTransformInfo.h"
26 #include "llvm/CodeGen/BasicTTIImpl.h"
27 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
28 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
29 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
30 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/CodeGen/TargetPassConfig.h"
34 #include "llvm/IR/Attributes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/InitializePasses.h"
37 #include "llvm/Support/CodeGen.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/TargetRegistry.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
42 #include <string>
43 
44 using namespace llvm;
45 
46 #define DEBUG_TYPE "mips"
47 
48 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTarget() {
49   // Register the target.
50   RegisterTargetMachine<MipsebTargetMachine> X(getTheMipsTarget());
51   RegisterTargetMachine<MipselTargetMachine> Y(getTheMipselTarget());
52   RegisterTargetMachine<MipsebTargetMachine> A(getTheMips64Target());
53   RegisterTargetMachine<MipselTargetMachine> B(getTheMips64elTarget());
54 
55   PassRegistry *PR = PassRegistry::getPassRegistry();
56   initializeGlobalISel(*PR);
57   initializeMipsDelaySlotFillerPass(*PR);
58   initializeMipsBranchExpansionPass(*PR);
59   initializeMicroMipsSizeReducePass(*PR);
60   initializeMipsPreLegalizerCombinerPass(*PR);
61 }
62 
63 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
64                                      const TargetOptions &Options,
65                                      bool isLittle) {
66   std::string Ret;
67   MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions);
68 
69   // There are both little and big endian mips.
70   if (isLittle)
71     Ret += "e";
72   else
73     Ret += "E";
74 
75   if (ABI.IsO32())
76     Ret += "-m:m";
77   else
78     Ret += "-m:e";
79 
80   // Pointers are 32 bit on some ABIs.
81   if (!ABI.IsN64())
82     Ret += "-p:32:32";
83 
84   // 8 and 16 bit integers only need to have natural alignment, but try to
85   // align them to 32 bits. 64 bit integers have natural alignment.
86   Ret += "-i8:8:32-i16:16:32-i64:64";
87 
88   // 32 bit registers are always available and the stack is at least 64 bit
89   // aligned. On N64 64 bit registers are also available and the stack is
90   // 128 bit aligned.
91   if (ABI.IsN64() || ABI.IsN32())
92     Ret += "-n32:64-S128";
93   else
94     Ret += "-n32-S64";
95 
96   return Ret;
97 }
98 
99 static Reloc::Model getEffectiveRelocModel(bool JIT,
100                                            Optional<Reloc::Model> RM) {
101   if (!RM.hasValue() || JIT)
102     return Reloc::Static;
103   return *RM;
104 }
105 
106 // On function prologue, the stack is created by decrementing
107 // its pointer. Once decremented, all references are done with positive
108 // offset from the stack/frame pointer, using StackGrowsUp enables
109 // an easier handling.
110 // Using CodeModel::Large enables different CALL behavior.
111 MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT,
112                                      StringRef CPU, StringRef FS,
113                                      const TargetOptions &Options,
114                                      Optional<Reloc::Model> RM,
115                                      Optional<CodeModel::Model> CM,
116                                      CodeGenOpt::Level OL, bool JIT,
117                                      bool isLittle)
118     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
119                         CPU, FS, Options, getEffectiveRelocModel(JIT, RM),
120                         getEffectiveCodeModel(CM, CodeModel::Small), OL),
121       isLittle(isLittle), TLOF(std::make_unique<MipsTargetObjectFile>()),
122       ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)),
123       Subtarget(nullptr),
124       DefaultSubtarget(TT, CPU, FS, isLittle, *this,
125                        MaybeAlign(Options.StackAlignmentOverride)),
126       NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
127                         isLittle, *this,
128                         MaybeAlign(Options.StackAlignmentOverride)),
129       Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
130                       isLittle, *this,
131                       MaybeAlign(Options.StackAlignmentOverride)) {
132   Subtarget = &DefaultSubtarget;
133   initAsmInfo();
134 
135   // Mips supports the debug entry values.
136   setSupportsDebugEntryValues(true);
137 }
138 
139 MipsTargetMachine::~MipsTargetMachine() = default;
140 
141 void MipsebTargetMachine::anchor() {}
142 
143 MipsebTargetMachine::MipsebTargetMachine(const Target &T, const Triple &TT,
144                                          StringRef CPU, StringRef FS,
145                                          const TargetOptions &Options,
146                                          Optional<Reloc::Model> RM,
147                                          Optional<CodeModel::Model> CM,
148                                          CodeGenOpt::Level OL, bool JIT)
149     : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
150 
151 void MipselTargetMachine::anchor() {}
152 
153 MipselTargetMachine::MipselTargetMachine(const Target &T, const Triple &TT,
154                                          StringRef CPU, StringRef FS,
155                                          const TargetOptions &Options,
156                                          Optional<Reloc::Model> RM,
157                                          Optional<CodeModel::Model> CM,
158                                          CodeGenOpt::Level OL, bool JIT)
159     : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
160 
161 const MipsSubtarget *
162 MipsTargetMachine::getSubtargetImpl(const Function &F) const {
163   Attribute CPUAttr = F.getFnAttribute("target-cpu");
164   Attribute FSAttr = F.getFnAttribute("target-features");
165 
166   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
167                         ? CPUAttr.getValueAsString().str()
168                         : TargetCPU;
169   std::string FS = !FSAttr.hasAttribute(Attribute::None)
170                        ? FSAttr.getValueAsString().str()
171                        : TargetFS;
172   bool hasMips16Attr =
173       !F.getFnAttribute("mips16").hasAttribute(Attribute::None);
174   bool hasNoMips16Attr =
175       !F.getFnAttribute("nomips16").hasAttribute(Attribute::None);
176 
177   bool HasMicroMipsAttr =
178       !F.getFnAttribute("micromips").hasAttribute(Attribute::None);
179   bool HasNoMicroMipsAttr =
180       !F.getFnAttribute("nomicromips").hasAttribute(Attribute::None);
181 
182   // FIXME: This is related to the code below to reset the target options,
183   // we need to know whether or not the soft float flag is set on the
184   // function, so we can enable it as a subtarget feature.
185   bool softFloat =
186       F.hasFnAttribute("use-soft-float") &&
187       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
188 
189   if (hasMips16Attr)
190     FS += FS.empty() ? "+mips16" : ",+mips16";
191   else if (hasNoMips16Attr)
192     FS += FS.empty() ? "-mips16" : ",-mips16";
193   if (HasMicroMipsAttr)
194     FS += FS.empty() ? "+micromips" : ",+micromips";
195   else if (HasNoMicroMipsAttr)
196     FS += FS.empty() ? "-micromips" : ",-micromips";
197   if (softFloat)
198     FS += FS.empty() ? "+soft-float" : ",+soft-float";
199 
200   auto &I = SubtargetMap[CPU + FS];
201   if (!I) {
202     // This needs to be done before we create a new subtarget since any
203     // creation will depend on the TM and the code generation flags on the
204     // function that reside in TargetOptions.
205     resetTargetOptions(F);
206     I = std::make_unique<MipsSubtarget>(
207         TargetTriple, CPU, FS, isLittle, *this,
208         MaybeAlign(Options.StackAlignmentOverride));
209   }
210   return I.get();
211 }
212 
213 void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
214   LLVM_DEBUG(dbgs() << "resetSubtarget\n");
215 
216   Subtarget = &MF->getSubtarget<MipsSubtarget>();
217 }
218 
219 namespace {
220 
221 /// Mips Code Generator Pass Configuration Options.
222 class MipsPassConfig : public TargetPassConfig {
223 public:
224   MipsPassConfig(MipsTargetMachine &TM, PassManagerBase &PM)
225       : TargetPassConfig(TM, PM) {
226     // The current implementation of long branch pass requires a scratch
227     // register ($at) to be available before branch instructions. Tail merging
228     // can break this requirement, so disable it when long branch pass is
229     // enabled.
230     EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
231   }
232 
233   MipsTargetMachine &getMipsTargetMachine() const {
234     return getTM<MipsTargetMachine>();
235   }
236 
237   const MipsSubtarget &getMipsSubtarget() const {
238     return *getMipsTargetMachine().getSubtargetImpl();
239   }
240 
241   void addIRPasses() override;
242   bool addInstSelector() override;
243   void addPreEmitPass() override;
244   void addPreRegAlloc() override;
245   bool addIRTranslator() override;
246   void addPreLegalizeMachineIR() override;
247   bool addLegalizeMachineIR() override;
248   bool addRegBankSelect() override;
249   bool addGlobalInstructionSelect() override;
250 
251   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
252 };
253 
254 } // end anonymous namespace
255 
256 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
257   return new MipsPassConfig(*this, PM);
258 }
259 
260 std::unique_ptr<CSEConfigBase> MipsPassConfig::getCSEConfig() const {
261   return getStandardCSEConfigForOpt(TM->getOptLevel());
262 }
263 
264 void MipsPassConfig::addIRPasses() {
265   TargetPassConfig::addIRPasses();
266   addPass(createAtomicExpandPass());
267   if (getMipsSubtarget().os16())
268     addPass(createMipsOs16Pass());
269   if (getMipsSubtarget().inMips16HardFloat())
270     addPass(createMips16HardFloatPass());
271 }
272 // Install an instruction selector pass using
273 // the ISelDag to gen Mips code.
274 bool MipsPassConfig::addInstSelector() {
275   addPass(createMipsModuleISelDagPass());
276   addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel()));
277   addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel()));
278   return false;
279 }
280 
281 void MipsPassConfig::addPreRegAlloc() {
282   addPass(createMipsOptimizePICCallPass());
283 }
284 
285 TargetTransformInfo
286 MipsTargetMachine::getTargetTransformInfo(const Function &F) {
287   if (Subtarget->allowMixed16_32()) {
288     LLVM_DEBUG(errs() << "No Target Transform Info Pass Added\n");
289     // FIXME: This is no longer necessary as the TTI returned is per-function.
290     return TargetTransformInfo(F.getParent()->getDataLayout());
291   }
292 
293   LLVM_DEBUG(errs() << "Target Transform Info Pass Added\n");
294   return TargetTransformInfo(BasicTTIImpl(this, F));
295 }
296 
297 // Implemented by targets that want to run passes immediately before
298 // machine code is emitted. return true if -print-machineinstrs should
299 // print out the code after the passes.
300 void MipsPassConfig::addPreEmitPass() {
301   // Expand pseudo instructions that are sensitive to register allocation.
302   addPass(createMipsExpandPseudoPass());
303 
304   // The microMIPS size reduction pass performs instruction reselection for
305   // instructions which can be remapped to a 16 bit instruction.
306   addPass(createMicroMipsSizeReducePass());
307 
308   // The delay slot filler pass can potientially create forbidden slot hazards
309   // for MIPSR6 and therefore it should go before MipsBranchExpansion pass.
310   addPass(createMipsDelaySlotFillerPass());
311 
312   // This pass expands branches and takes care about the forbidden slot hazards.
313   // Expanding branches may potentially create forbidden slot hazards for
314   // MIPSR6, and fixing such hazard may potentially break a branch by extending
315   // its offset out of range. That's why this pass combine these two tasks, and
316   // runs them alternately until one of them finishes without any changes. Only
317   // then we can be sure that all branches are expanded properly and no hazards
318   // exists.
319   // Any new pass should go before this pass.
320   addPass(createMipsBranchExpansion());
321 
322   addPass(createMipsConstantIslandPass());
323 }
324 
325 bool MipsPassConfig::addIRTranslator() {
326   addPass(new IRTranslator());
327   return false;
328 }
329 
330 void MipsPassConfig::addPreLegalizeMachineIR() {
331   addPass(createMipsPreLegalizeCombiner());
332 }
333 
334 bool MipsPassConfig::addLegalizeMachineIR() {
335   addPass(new Legalizer());
336   return false;
337 }
338 
339 bool MipsPassConfig::addRegBankSelect() {
340   addPass(new RegBankSelect());
341   return false;
342 }
343 
344 bool MipsPassConfig::addGlobalInstructionSelect() {
345   addPass(new InstructionSelect());
346   return false;
347 }
348