1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares the Mips specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H 14 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H 15 16 #include "MCTargetDesc/MipsABIInfo.h" 17 #include "MipsFrameLowering.h" 18 #include "MipsISelLowering.h" 19 #include "MipsInstrInfo.h" 20 #include "llvm/CodeGen/SelectionDAGTargetInfo.h" 21 #include "llvm/CodeGen/TargetSubtargetInfo.h" 22 #include "llvm/CodeGen/GlobalISel/CallLowering.h" 23 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 24 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" 25 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" 26 #include "llvm/IR/DataLayout.h" 27 #include "llvm/MC/MCInstrItineraries.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include <string> 30 31 #define GET_SUBTARGETINFO_HEADER 32 #include "MipsGenSubtargetInfo.inc" 33 34 namespace llvm { 35 class StringRef; 36 37 class MipsTargetMachine; 38 39 class MipsSubtarget : public MipsGenSubtargetInfo { 40 virtual void anchor(); 41 42 enum MipsArchEnum { 43 MipsDefault, 44 Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max, 45 Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6 46 }; 47 48 enum class CPU { P5600 }; 49 50 // Used to avoid printing dsp warnings multiple times. 51 static bool DspWarningPrinted; 52 53 // Used to avoid printing msa warnings multiple times. 54 static bool MSAWarningPrinted; 55 56 // Used to avoid printing crc warnings multiple times. 57 static bool CRCWarningPrinted; 58 59 // Used to avoid printing ginv warnings multiple times. 60 static bool GINVWarningPrinted; 61 62 // Used to avoid printing virt warnings multiple times. 63 static bool VirtWarningPrinted; 64 65 // Mips architecture version 66 MipsArchEnum MipsArchVersion; 67 68 // Processor implementation (unused but required to exist by 69 // tablegen-erated code). 70 CPU ProcImpl; 71 72 // IsLittle - The target is Little Endian 73 bool IsLittle; 74 75 // IsSoftFloat - The target does not support any floating point instructions. 76 bool IsSoftFloat; 77 78 // IsSingleFloat - The target only supports single precision float 79 // point operations. This enable the target to use all 32 32-bit 80 // floating point registers instead of only using even ones. 81 bool IsSingleFloat; 82 83 // IsFPXX - MIPS O32 modeless ABI. 84 bool IsFPXX; 85 86 // NoABICalls - Disable SVR4-style position-independent code. 87 bool NoABICalls; 88 89 // Abs2008 - Use IEEE 754-2008 abs.fmt instruction. 90 bool Abs2008; 91 92 // IsFP64bit - The target processor has 64-bit floating point registers. 93 bool IsFP64bit; 94 95 /// Are odd single-precision registers permitted? 96 /// This corresponds to -modd-spreg and -mno-odd-spreg 97 bool UseOddSPReg; 98 99 // IsNan2008 - IEEE 754-2008 NaN encoding. 100 bool IsNaN2008bit; 101 102 // IsGP64bit - General-purpose registers are 64 bits wide 103 bool IsGP64bit; 104 105 // IsPTR64bit - Pointers are 64 bit wide 106 bool IsPTR64bit; 107 108 // HasVFPU - Processor has a vector floating point unit. 109 bool HasVFPU; 110 111 // CPU supports cnMIPS (Cavium Networks Octeon CPU). 112 bool HasCnMips; 113 114 // CPU supports cnMIPSP (Cavium Networks Octeon+ CPU). 115 bool HasCnMipsP; 116 117 // isLinux - Target system is Linux. Is false we consider ELFOS for now. 118 bool IsLinux; 119 120 // UseSmallSection - Small section is used. 121 bool UseSmallSection; 122 123 /// Features related to the presence of specific instructions. 124 125 // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32 126 bool HasMips3_32; 127 128 // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2 129 bool HasMips3_32r2; 130 131 // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32 132 bool HasMips4_32; 133 134 // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2 135 bool HasMips4_32r2; 136 137 // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2 138 bool HasMips5_32r2; 139 140 // InMips16 -- can process Mips16 instructions 141 bool InMips16Mode; 142 143 // Mips16 hard float 144 bool InMips16HardFloat; 145 146 // InMicroMips -- can process MicroMips instructions 147 bool InMicroMipsMode; 148 149 // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE. 150 bool HasDSP, HasDSPR2, HasDSPR3; 151 152 // Has3D -- Supports Mips3D ASE. 153 bool Has3D; 154 155 // Allow mixed Mips16 and Mips32 in one source file 156 bool AllowMixed16_32; 157 158 // Optimize for space by compiling all functions as Mips 16 unless 159 // it needs floating point. Functions needing floating point are 160 // compiled as Mips32 161 bool Os16; 162 163 // HasMSA -- supports MSA ASE. 164 bool HasMSA; 165 166 // UseTCCInDIV -- Enables the use of trapping in the assembler. 167 bool UseTCCInDIV; 168 169 // Sym32 -- On Mips64 symbols are 32 bits. 170 bool HasSym32; 171 172 // HasEVA -- supports EVA ASE. 173 bool HasEVA; 174 175 // nomadd4 - disables generation of 4-operand madd.s, madd.d and 176 // related instructions. 177 bool DisableMadd4; 178 179 // HasMT -- support MT ASE. 180 bool HasMT; 181 182 // HasCRC -- supports R6 CRC ASE 183 bool HasCRC; 184 185 // HasVirt -- supports Virtualization ASE 186 bool HasVirt; 187 188 // HasGINV -- supports R6 Global INValidate ASE 189 bool HasGINV; 190 191 // Use hazard variants of the jump register instructions for indirect 192 // function calls and jump tables. 193 bool UseIndirectJumpsHazard; 194 195 // Disable use of the `jal` instruction. 196 bool UseLongCalls = false; 197 198 // Assume 32-bit GOT. 199 bool UseXGOT = false; 200 201 /// The minimum alignment known to hold of the stack frame on 202 /// entry to the function and which must be maintained by every function. 203 Align stackAlignment; 204 205 /// The overridden stack alignment. 206 MaybeAlign StackAlignOverride; 207 208 InstrItineraryData InstrItins; 209 210 // We can override the determination of whether we are in mips16 mode 211 // as from the command line 212 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode; 213 214 const MipsTargetMachine &TM; 215 216 Triple TargetTriple; 217 218 const SelectionDAGTargetInfo TSInfo; 219 std::unique_ptr<const MipsInstrInfo> InstrInfo; 220 std::unique_ptr<const MipsFrameLowering> FrameLowering; 221 std::unique_ptr<const MipsTargetLowering> TLInfo; 222 223 public: 224 bool isPositionIndependent() const; 225 /// This overrides the PostRAScheduler bit in the SchedModel for each CPU. 226 bool enablePostRAScheduler() const override; 227 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override; 228 CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override; 229 230 bool isABI_N64() const; 231 bool isABI_N32() const; 232 bool isABI_O32() const; 233 const MipsABIInfo &getABI() const; 234 bool isABI_FPXX() const { return isABI_O32() && IsFPXX; } 235 236 /// This constructor initializes the data members to match that 237 /// of the specified triple. 238 MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little, 239 const MipsTargetMachine &TM, MaybeAlign StackAlignOverride); 240 241 /// ParseSubtargetFeatures - Parses features string setting specified 242 /// subtarget options. Definition of function is auto generated by tblgen. 243 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); 244 245 bool hasMips1() const { return MipsArchVersion >= Mips1; } 246 bool hasMips2() const { return MipsArchVersion >= Mips2; } 247 bool hasMips3() const { return MipsArchVersion >= Mips3; } 248 bool hasMips4() const { return MipsArchVersion >= Mips4; } 249 bool hasMips5() const { return MipsArchVersion >= Mips5; } 250 bool hasMips4_32() const { return HasMips4_32; } 251 bool hasMips4_32r2() const { return HasMips4_32r2; } 252 bool hasMips32() const { 253 return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) || 254 hasMips64(); 255 } 256 bool hasMips32r2() const { 257 return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) || 258 hasMips64r2(); 259 } 260 bool hasMips32r3() const { 261 return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) || 262 hasMips64r2(); 263 } 264 bool hasMips32r5() const { 265 return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) || 266 hasMips64r5(); 267 } 268 bool hasMips32r6() const { 269 return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) || 270 hasMips64r6(); 271 } 272 bool hasMips64() const { return MipsArchVersion >= Mips64; } 273 bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; } 274 bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; } 275 bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; } 276 bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; } 277 278 bool hasCnMips() const { return HasCnMips; } 279 bool hasCnMipsP() const { return HasCnMipsP; } 280 281 bool isLittle() const { return IsLittle; } 282 bool isABICalls() const { return !NoABICalls; } 283 bool isFPXX() const { return IsFPXX; } 284 bool isFP64bit() const { return IsFP64bit; } 285 bool useOddSPReg() const { return UseOddSPReg; } 286 bool noOddSPReg() const { return !UseOddSPReg; } 287 bool isNaN2008() const { return IsNaN2008bit; } 288 bool inAbs2008Mode() const { return Abs2008; } 289 bool isGP64bit() const { return IsGP64bit; } 290 bool isGP32bit() const { return !IsGP64bit; } 291 unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; } 292 bool isPTR64bit() const { return IsPTR64bit; } 293 bool isPTR32bit() const { return !IsPTR64bit; } 294 bool hasSym32() const { 295 return (HasSym32 && isABI_N64()) || isABI_N32() || isABI_O32(); 296 } 297 bool isSingleFloat() const { return IsSingleFloat; } 298 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); } 299 bool hasVFPU() const { return HasVFPU; } 300 bool inMips16Mode() const { return InMips16Mode; } 301 bool inMips16ModeDefault() const { 302 return InMips16Mode; 303 } 304 // Hard float for mips16 means essentially to compile as soft float 305 // but to use a runtime library for soft float that is written with 306 // native mips32 floating point instructions (those runtime routines 307 // run in mips32 hard float mode). 308 bool inMips16HardFloat() const { 309 return inMips16Mode() && InMips16HardFloat; 310 } 311 bool inMicroMipsMode() const { return InMicroMipsMode && !InMips16Mode; } 312 bool inMicroMips32r6Mode() const { 313 return inMicroMipsMode() && hasMips32r6(); 314 } 315 bool hasDSP() const { return HasDSP; } 316 bool hasDSPR2() const { return HasDSPR2; } 317 bool hasDSPR3() const { return HasDSPR3; } 318 bool has3D() const { return Has3D; } 319 bool hasMSA() const { return HasMSA; } 320 bool disableMadd4() const { return DisableMadd4; } 321 bool hasEVA() const { return HasEVA; } 322 bool hasMT() const { return HasMT; } 323 bool hasCRC() const { return HasCRC; } 324 bool hasVirt() const { return HasVirt; } 325 bool hasGINV() const { return HasGINV; } 326 bool useIndirectJumpsHazard() const { 327 return UseIndirectJumpsHazard && hasMips32r2(); 328 } 329 bool useSmallSection() const { return UseSmallSection; } 330 331 bool hasStandardEncoding() const { return !InMips16Mode && !InMicroMipsMode; } 332 333 bool useSoftFloat() const { return IsSoftFloat; } 334 335 bool useLongCalls() const { return UseLongCalls; } 336 337 bool useXGOT() const { return UseXGOT; } 338 339 bool enableLongBranchPass() const { 340 return hasStandardEncoding() || inMicroMipsMode() || allowMixed16_32(); 341 } 342 343 /// Features related to the presence of specific instructions. 344 bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); } 345 bool hasMTHC1() const { return hasMips32r2(); } 346 347 bool allowMixed16_32() const { return inMips16ModeDefault() | 348 AllowMixed16_32; } 349 350 bool os16() const { return Os16; } 351 352 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); } 353 354 bool isXRaySupported() const override { return true; } 355 356 // for now constant islands are on for the whole compilation unit but we only 357 // really use them if in addition we are in mips16 mode 358 static bool useConstantIslands(); 359 360 Align getStackAlignment() const { return stackAlignment; } 361 362 // Grab relocation model 363 Reloc::Model getRelocationModel() const; 364 365 MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS, 366 const TargetMachine &TM); 367 368 /// Does the system support unaligned memory access. 369 /// 370 /// MIPS32r6/MIPS64r6 require full unaligned access support but does not 371 /// specify which component of the system provides it. Hardware, software, and 372 /// hybrid implementations are all valid. 373 bool systemSupportsUnalignedAccess() const { return hasMips32r6(); } 374 375 // Set helper classes 376 void setHelperClassesMips16(); 377 void setHelperClassesMipsSE(); 378 379 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override { 380 return &TSInfo; 381 } 382 const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); } 383 const TargetFrameLowering *getFrameLowering() const override { 384 return FrameLowering.get(); 385 } 386 const MipsRegisterInfo *getRegisterInfo() const override { 387 return &InstrInfo->getRegisterInfo(); 388 } 389 const MipsTargetLowering *getTargetLowering() const override { 390 return TLInfo.get(); 391 } 392 const InstrItineraryData *getInstrItineraryData() const override { 393 return &InstrItins; 394 } 395 396 protected: 397 // GlobalISel related APIs. 398 std::unique_ptr<CallLowering> CallLoweringInfo; 399 std::unique_ptr<LegalizerInfo> Legalizer; 400 std::unique_ptr<RegisterBankInfo> RegBankInfo; 401 std::unique_ptr<InstructionSelector> InstSelector; 402 403 public: 404 const CallLowering *getCallLowering() const override; 405 const LegalizerInfo *getLegalizerInfo() const override; 406 const RegisterBankInfo *getRegBankInfo() const override; 407 InstructionSelector *getInstructionSelector() const override; 408 }; 409 } // End llvm namespace 410 411 #endif 412