1//==- MipsScheduleP5600.td - P5600 Scheduling Definitions --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9def MipsP5600Model : SchedMachineModel { 10 int IssueWidth = 2; // 2x dispatched per cycle 11 int MicroOpBufferSize = 48; // min(48, 48, 64) 12 int LoadLatency = 4; 13 int MispredictPenalty = 8; // TODO: Estimated 14 15 let CompleteModel = 1; 16 let FullInstRWOverlapCheck = 1; 17 18 list<Predicate> UnsupportedFeatures = [HasMips3, HasMips32r6, HasMips64, 19 HasMips64r2, HasMips64r5, HasMips64r6, 20 IsGP64bit, IsPTR64bit, 21 InMicroMips, InMips16Mode, 22 HasCnMips, HasCnMipsP, 23 HasDSP, HasDSPR2, HasMT, HasCRC]; 24} 25 26let SchedModel = MipsP5600Model in { 27 28// ALQ Pipelines 29// ============= 30 31def P5600ALQ : ProcResource<1> { let BufferSize = 16; } 32def P5600IssueALU : ProcResource<1> { let Super = P5600ALQ; } 33 34// ALU Pipeline 35// ------------ 36 37def P5600WriteALU : SchedWriteRes<[P5600IssueALU]>; 38 39// and, lui, nor, or, slti, sltiu, sub, subu, xor 40def : InstRW<[P5600WriteALU], (instrs AND, LUi, NOR, OR, SLTi, SLTiu, SUB, 41 SUBu, XOR)>; 42 43// AGQ Pipelines 44// ============= 45 46def P5600AGQ : ProcResource<3> { let BufferSize = 16; } 47def P5600IssueAL2 : ProcResource<1> { let Super = P5600AGQ; } 48def P5600IssueCTISTD : ProcResource<1> { let Super = P5600AGQ; } 49def P5600IssueLDST : ProcResource<1> { let Super = P5600AGQ; } 50 51def P5600AL2Div : ProcResource<1>; 52// Pseudo-resource used to block CTISTD when handling multi-pipeline splits. 53def P5600CTISTD : ProcResource<1>; 54 55// CTISTD Pipeline 56// --------------- 57 58def P5600WriteJump : SchedWriteRes<[P5600IssueCTISTD, P5600CTISTD]>; 59def P5600WriteJumpAndLink : SchedWriteRes<[P5600IssueCTISTD, P5600CTISTD]> { 60 let Latency = 2; 61} 62 63def P5600Nop : SchedWriteRes<[P5600IssueCTISTD]> { 64 let Latency = 0; 65} 66 67def : InstRW<[P5600Nop], (instrs SSNOP, NOP)>; 68 69// b, beq, beql, bg[et]z, bl[et]z, bne, bnel, j, syscall, jal, bltzal, 70// jalr, jr.hb, jr 71def : InstRW<[P5600WriteJump], (instrs B, BAL, BAL_BR, BEQ, BEQL, BGEZ, BGEZAL, 72 BGEZALL, BGEZL, BGTZ, BGTZL, BLEZ, BLEZL, BLTZ, 73 BLTZAL, BLTZALL, BLTZL, BNE, BNEL, BREAK, 74 DERET, ERET, ERet, ERETNC, J, JR, JR_HB, 75 PseudoIndirectBranch, 76 PseudoIndirectHazardBranch, PseudoReturn, 77 SDBBP, SYSCALL, RetRA, TAILCALL, TAILCALLREG, 78 TAILCALLREGHB, TEQ, TEQI, TGE, TGEI, TGEIU, 79 TGEU, TLT, TLTI, TLTU, TNE, TNEI, TRAP, 80 TTLTIU, WAIT, PAUSE)>; 81 82def : InstRW<[P5600WriteJumpAndLink], (instrs JAL, JALR, JALRHBPseudo, 83 JALRPseudo, JALR_HB)>; 84 85def : InstRW<[P5600WriteJumpAndLink], (instrs JALX)> { 86 let Unsupported = 1; 87} 88 89def P5600COP0 : SchedWriteRes<[P5600IssueCTISTD, P5600CTISTD]>; 90 91def : InstRW<[P5600COP0], (instrs TLBINV, TLBINVF, TLBP, TLBR, TLBWI, TLBWR, 92 MFC0, MTC0)>; 93 94def P5600COP2 : SchedWriteRes<[P5600IssueCTISTD, P5600CTISTD]>; 95 96def : InstRW<[P5600COP2], (instrs MFC2, MTC2)> { 97 let Unsupported = 1; 98} 99 100// MIPS Virtualization ASE 101// ======================= 102def : InstRW<[P5600COP0], (instrs HYPCALL, MFGC0, MFHGC0, MTGC0, MTHGC0, 103 TLBGINV, TLBGINVF, TLBGP, TLBGR, TLBGWI, TLBGWR)>; 104 105// LDST Pipeline 106// ------------- 107 108def P5600WriteLoad : SchedWriteRes<[P5600IssueLDST]> { 109 let Latency = 4; 110} 111 112def P5600WriteLoadShifted : SchedWriteRes<[P5600IssueLDST, P5600CTISTD]> { 113 let Latency = 4; 114} 115 116def P5600WriteCache : SchedWriteRes<[P5600IssueLDST]>; 117 118def P5600WriteStore : SchedWriteRes<[P5600IssueLDST, P5600CTISTD]> { 119 // FIXME: This is a bit pessimistic. P5600CTISTD is only used during cycle 2 120 // not during 0, 1, and 2. 121 let ResourceCycles = [ 1, 3 ]; 122} 123 124def P5600WriteGPRFromBypass : SchedWriteRes<[P5600IssueLDST]> { 125 let Latency = 2; 126} 127 128def P5600WriteStoreFromOtherUnits : SchedWriteRes<[P5600IssueLDST]>; 129def P5600WriteLoadToOtherUnits : SchedWriteRes<[P5600IssueLDST]> { 130 let Latency = 0; 131} 132 133// l[bhw], l[bh]u, ll 134def : InstRW<[P5600WriteLoad], (instrs LB, LBu, LH, LHu, LW, LL, LWC2, LWC3, 135 LDC2, LDC3, LBE, LBuE, LHE, LHuE, LWE, LLE, 136 LWPC)>; 137 138// lw[lr] 139def : InstRW<[P5600WriteLoadShifted], (instrs LWL, LWR, LWLE, LWRE)>; 140 141// s[bhw], sw[lr] 142def : InstRW<[P5600WriteStore], (instrs SB, SH, SW, SWC2, SWC3, SDC2, SDC3, SC, 143 SBE, SHE, SWE, SCE, SWL, SWR, SWLE, SWRE)>; 144 145// pref, cache, sync, synci 146def : InstRW<[P5600WriteCache], (instrs PREF, PREFE, CACHE, CACHEE, SYNC, 147 SYNCI)>; 148 149// LDST is also used in moves from general purpose registers to floating point 150// and MSA. 151def P5600WriteMoveGPRToOtherUnits : SchedWriteRes<[P5600IssueLDST]> { 152 let Latency = 0; 153} 154 155// AL2 Pipeline 156// ------------ 157 158def P5600WriteAL2 : SchedWriteRes<[P5600IssueAL2]>; 159def P5600WriteAL2BitExt : SchedWriteRes<[P5600IssueAL2]> { let Latency = 2; } 160def P5600WriteAL2ShadowMov : SchedWriteRes<[P5600IssueAL2]> { let Latency = 2; } 161def P5600WriteAL2CondMov : SchedWriteRes<[P5600IssueAL2, P5600CTISTD]> { 162 let Latency = 2; 163} 164def P5600WriteAL2Div : SchedWriteRes<[P5600IssueAL2, P5600AL2Div]> { 165 // Estimated worst case 166 let Latency = 34; 167 let ResourceCycles = [1, 34]; 168} 169def P5600WriteAL2DivU : SchedWriteRes<[P5600IssueAL2, P5600AL2Div]> { 170 // Estimated worst case 171 let Latency = 34; 172 let ResourceCycles = [1, 34]; 173} 174def P5600WriteAL2Mul : SchedWriteRes<[P5600IssueAL2]> { let Latency = 3; } 175def P5600WriteAL2Mult: SchedWriteRes<[P5600IssueAL2]> { let Latency = 5; } 176def P5600WriteAL2MAdd: SchedWriteRes<[P5600IssueAL2, P5600CTISTD]> { 177 let Latency = 5; 178} 179 180// clo, clz, di, ei, mfhi, mflo 181def : InstRW<[P5600WriteAL2], (instrs CLO, CLZ, DI, EI, MFHI, MFLO, 182 PseudoMFHI, PseudoMFLO)>; 183 184// ehb, rdhwr, rdpgpr, wrpgpr, wsbh 185def : InstRW<[P5600WriteAL2ShadowMov], (instrs EHB, RDHWR, WSBH)>; 186 187// mov[nz] 188def : InstRW<[P5600WriteAL2CondMov], (instrs MOVN_I_I, MOVZ_I_I)>; 189 190// divu? 191def : InstRW<[P5600WriteAL2Div], (instrs DIV, PseudoSDIV, SDIV)>; 192def : InstRW<[P5600WriteAL2DivU], (instrs DIVU, PseudoUDIV, UDIV)>; 193 194// mul 195def : InstRW<[P5600WriteAL2Mul], (instrs MUL)>; 196// multu?, multu? 197def : InstRW<[P5600WriteAL2Mult], (instrs MULT, MULTu, PseudoMULT, 198 PseudoMULTu)>; 199// maddu?, msubu?, mthi, mtlo 200def : InstRW<[P5600WriteAL2MAdd], (instrs MADD, MADDU, MSUB, MSUBU, 201 MTHI, MTLO, PseudoMADD, PseudoMADDU, 202 PseudoMSUB, PseudoMSUBU, PseudoMTLOHI)>; 203 204// ext, ins 205def : InstRW<[P5600WriteAL2BitExt], (instrs EXT, INS)>; 206 207// Either ALU or AL2 Pipelines 208// --------------------------- 209// 210// Some instructions can choose between ALU and AL2, but once dispatched to 211// ALQ or AGQ respectively they are committed to that path. 212// The decision is based on the outcome of the most recent selection when the 213// choice was last available. For now, we assume ALU is always chosen. 214 215def P5600WriteEitherALU : SchedWriteVariant< 216 // FIXME: Implement selection predicate 217 [SchedVar<SchedPredicate<[{1}]>, [P5600WriteALU]>, 218 SchedVar<SchedPredicate<[{0}]>, [P5600WriteAL2]> 219 ]>; 220 221// add, addi, addiu, addu, andi, ori, rotr, se[bh], sllv?, sr[al]v?, slt, sltu, 222// xori 223def : InstRW<[P5600WriteEitherALU], (instrs ADD, ADDi, ADDiu, ANDi, ORi, ROTR, 224 SEB, SEH, SLT, SLTu, SLL, SRA, SRL, XORi, 225 ADDu, SLLV, SRAV, SRLV, LSA, COPY)>; 226 227// FPU Pipelines 228// ============= 229 230def P5600FPQ : ProcResource<3> { let BufferSize = 16; } 231def P5600IssueFPUS : ProcResource<1> { let Super = P5600FPQ; } 232def P5600IssueFPUL : ProcResource<1> { let Super = P5600FPQ; } 233def P5600IssueFPULoad : ProcResource<1> { let Super = P5600FPQ; } 234 235def P5600FPUDivSqrt : ProcResource<2>; 236 237def P5600WriteFPUS : SchedWriteRes<[P5600IssueFPUS]>; 238def P5600WriteFPUL : SchedWriteRes<[P5600IssueFPUL]> { let Latency = 4; } 239def P5600WriteFPUL_MADDSUB : SchedWriteRes<[P5600IssueFPUL]> { let Latency = 6; } 240def P5600WriteFPUDivI : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> { 241 // Best/Common/Worst case = 7 / 23 / 27 242 let Latency = 23; // Using common case 243 let ResourceCycles = [ 1, 23 ]; 244} 245def P5600WriteFPUDivS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> { 246 // Best/Common/Worst case = 7 / 23 / 27 247 let Latency = 23; // Using common case 248 let ResourceCycles = [ 1, 23 ]; 249} 250def P5600WriteFPUDivD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> { 251 // Best/Common/Worst case = 7 / 31 / 35 252 let Latency = 31; // Using common case 253 let ResourceCycles = [ 1, 31 ]; 254} 255def P5600WriteFPURcpS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> { 256 // Best/Common/Worst case = 7 / 19 / 23 257 let Latency = 19; // Using common case 258 let ResourceCycles = [ 1, 19 ]; 259} 260def P5600WriteFPURcpD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> { 261 // Best/Common/Worst case = 7 / 27 / 31 262 let Latency = 27; // Using common case 263 let ResourceCycles = [ 1, 27 ]; 264} 265def P5600WriteFPURsqrtS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> { 266 // Best/Common/Worst case = 7 / 27 / 27 267 let Latency = 27; // Using common case 268 let ResourceCycles = [ 1, 27 ]; 269} 270def P5600WriteFPURsqrtD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> { 271 // Best/Common/Worst case = 7 / 27 / 31 272 let Latency = 27; // Using common case 273 let ResourceCycles = [ 1, 27 ]; 274} 275def P5600WriteFPUSqrtS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> { 276 // Best/Common/Worst case = 7 / 27 / 31 277 let Latency = 27; // Using common case 278 let ResourceCycles = [ 1, 27 ]; 279} 280def P5600WriteFPUSqrtD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> { 281 // Best/Common/Worst case = 7 / 35 / 39 282 let Latency = 35; // Using common case 283 let ResourceCycles = [ 1, 35 ]; 284} 285def P5600WriteMSAShortLogic : SchedWriteRes<[P5600IssueFPUS]>; 286def P5600WriteMSAShortInt : SchedWriteRes<[P5600IssueFPUS]> { let Latency = 2; } 287def P5600WriteMoveOtherUnitsToFPU : SchedWriteRes<[P5600IssueFPUS]>; 288def P5600WriteMSAOther3 : SchedWriteRes<[P5600IssueFPUS]> { let Latency = 3; } 289def P5600WriteMSALongInt : SchedWriteRes<[P5600IssueFPUS]> { let Latency = 5; } 290 291// vshf.[bhwd], binsl.[bhwd], binsr.[bhwd], insert.[bhwd], sld?.[bhwd], 292// bset.[bhwd], bclr.[bhwd], bneg.[bhwd], bsel_v, bseli_b 293def : InstRW<[P5600WriteMSAShortInt], (instregex "^VSHF_[BHWD]$")>; 294def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BINSL|BINSLI)_[BHWD]$")>; 295def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BINSR|BINSRI)_[BHWD]$")>; 296def : InstRW<[P5600WriteMSAShortInt], (instregex "^INSERT_[BHWD]$")>; 297def : InstRW<[P5600WriteMSAShortInt], (instregex "^(SLD|SLDI)_[BHWD]$")>; 298def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BSET|BSETI)_[BHWD]$")>; 299def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BCLR|BCLRI)_[BHWD]$")>; 300def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BNEG|BNEGI)_[BHWD]$")>; 301def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BSEL_V|BSELI_B)$")>; 302def : InstRW<[P5600WriteMSAShortInt], (instregex "^BMN*Z.*$")>; 303def : InstRW<[P5600WriteMSAShortInt], 304 (instregex "^BSEL_(H|W|D|FW|FD)_PSEUDO$")>; 305 306// pcnt.[bhwd], sat_s.[bhwd], sat_u.bhwd] 307def : InstRW<[P5600WriteMSAOther3], (instregex "^PCNT_[BHWD]$")>; 308def : InstRW<[P5600WriteMSAOther3], (instregex "^SAT_(S|U)_[BHWD]$")>; 309 310// bnz.[bhwdv], cfcmsa, ctcmsa 311def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(BNZ|BZ)_[BHWDV]$")>; 312def : InstRW<[P5600WriteMSAShortLogic], (instregex "^C(F|T)CMSA$")>; 313 314// FPUS is also used in moves from floating point and MSA registers to general 315// purpose registers. 316def P5600WriteMoveFPUSToOtherUnits : SchedWriteRes<[P5600IssueFPUS]> { 317 let Latency = 0; 318} 319 320// FPUL is also used in moves from floating point and MSA registers to general 321// purpose registers. 322def P5600WriteMoveFPULToOtherUnits : SchedWriteRes<[P5600IssueFPUL]>; 323 324// Short Pipe 325// ---------- 326// 327// abs.[ds], abs.ps, bc1[tf]l?, mov[tf].[ds], mov[tf], mov.[ds], [cm][ft]c1, 328// m[ft]hc1, neg.[ds], neg.ps, nor.v, nori.b, or.v, ori.b, xor.v, xori.b, 329// sdxc1, sdc1, st.[bhwd], swc1, swxc1 330def : InstRW<[P5600WriteFPUS], (instrs FABS_S, FABS_D32, FABS_D64, MOVF_D32, 331 MOVF_D64, MOVF_S, MOVT_D32, MOVT_D64, 332 MOVT_S, FMOV_D32, FMOV_D64, FMOV_S, FNEG_S, 333 FNEG_D32, FNEG_D64)>; 334 335// adds_a.[bhwd], adds_[asu].[bhwd], addvi?.[bhwd], asub_[us].[bhwd], 336// aver?_[us].[bhwd], shf.[bhw], fill[bhwd], splat?.[bhwd] 337def : InstRW<[P5600WriteMSAShortInt], (instregex "^ADD_A_[BHWD]$")>; 338def : InstRW<[P5600WriteMSAShortInt], (instregex "^ADDS_[ASU]_[BHWD]$")>; 339// TODO: ADDVI_[BHW] might be 1 cycle latency rather than 2. Need to confirm it. 340def : InstRW<[P5600WriteMSAShortInt], (instregex "^ADDVI?_[BHWD]$")>; 341def : InstRW<[P5600WriteMSAShortInt], (instregex "^ASUB_[US].[BHWD]$")>; 342def : InstRW<[P5600WriteMSAShortInt], (instregex "^AVER?_[US].[BHWD]$")>; 343def : InstRW<[P5600WriteMSAShortInt], (instregex "^SHF_[BHW]$")>; 344def : InstRW<[P5600WriteMSAShortInt], (instregex "^FILL_[BHWD]$")>; 345def : InstRW<[P5600WriteMSAShortInt], (instregex "^(SPLAT|SPLATI)_[BHWD]$")>; 346 347// and.v, andi.b, move.v, ldi.[bhwd] 348def : InstRW<[P5600WriteMSAShortLogic], (instregex "^MOVE_V$")>; 349def : InstRW<[P5600WriteMSAShortLogic], (instregex "^LDI_[BHWD]$")>; 350def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)_V$")>; 351def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)I_B$")>; 352def : InstRW<[P5600WriteMSAShortLogic], 353 (instregex "^(AND|OR|[XN]OR)_V_[DHW]_PSEUDO$")>; 354def : InstRW<[P5600WriteMSAShortLogic], (instregex "^FILL_F(D|W)_PSEUDO$")>; 355def : InstRW<[P5600WriteMSAShortLogic], (instregex "^INSERT_F(D|W)_PSEUDO$")>; 356 357// fexp2_w, fexp2_d 358def : InstRW<[P5600WriteFPUS], (instregex "^FEXP2_(W|D)$")>; 359 360// compare, converts, round to int, floating point truncate. 361def : InstRW<[P5600WriteFPUS], (instregex "^(CLT|CLTI)_(S|U)_[BHWD]$")>; 362def : InstRW<[P5600WriteFPUS], (instregex "^(CLE|CLEI)_(S|U)_[BHWD]$")>; 363def : InstRW<[P5600WriteFPUS], (instregex "^(CEQ|CEQI)_[BHWD]$")>; 364def : InstRW<[P5600WriteFPUS], (instregex "^CMP_UN_(S|D)$")>; 365def : InstRW<[P5600WriteFPUS], (instregex "^CMP_UEQ_(S|D)$")>; 366def : InstRW<[P5600WriteFPUS], (instregex "^CMP_EQ_(S|D)$")>; 367def : InstRW<[P5600WriteFPUS], (instregex "^CMP_LT_(S|D)$")>; 368def : InstRW<[P5600WriteFPUS], (instregex "^CMP_ULT_(S|D)$")>; 369def : InstRW<[P5600WriteFPUS], (instregex "^CMP_LE_(S|D)$")>; 370def : InstRW<[P5600WriteFPUS], (instregex "^CMP_ULE_(S|D)$")>; 371def : InstRW<[P5600WriteFPUS], (instregex "^FS(AF|EQ|LT|LE|NE|OR)_(W|D)$")>; 372def : InstRW<[P5600WriteFPUS], (instregex "^FSUEQ_(W|D)$")>; 373def : InstRW<[P5600WriteFPUS], (instregex "^FSULE_(W|D)$")>; 374def : InstRW<[P5600WriteFPUS], (instregex "^FSULT_(W|D)$")>; 375def : InstRW<[P5600WriteFPUS], (instregex "^FSUNE_(W|D)$")>; 376def : InstRW<[P5600WriteFPUS], (instregex "^FSUN_(W|D)$")>; 377def : InstRW<[P5600WriteFPUS], (instregex "^FCAF_(W|D)$")>; 378def : InstRW<[P5600WriteFPUS], (instregex "^FCEQ_(W|D)$")>; 379def : InstRW<[P5600WriteFPUS], (instregex "^FCLE_(W|D)$")>; 380def : InstRW<[P5600WriteFPUS], (instregex "^FCLT_(W|D)$")>; 381def : InstRW<[P5600WriteFPUS], (instregex "^FCNE_(W|D)$")>; 382def : InstRW<[P5600WriteFPUS], (instregex "^FCOR_(W|D)$")>; 383def : InstRW<[P5600WriteFPUS], (instregex "^FCUEQ_(W|D)$")>; 384def : InstRW<[P5600WriteFPUS], (instregex "^FCULE_(W|D)$")>; 385def : InstRW<[P5600WriteFPUS], (instregex "^FCULT_(W|D)$")>; 386def : InstRW<[P5600WriteFPUS], (instregex "^FCUNE_(W|D)$")>; 387def : InstRW<[P5600WriteFPUS], (instregex "^FCUN_(W|D)$")>; 388def : InstRW<[P5600WriteFPUS], (instregex "^FABS_(W|D)$")>; 389def : InstRW<[P5600WriteFPUS], (instregex "^FFINT_(U|S)_(W|D)$")>; 390def : InstRW<[P5600WriteFPUS], (instregex "^FFQL_(W|D)$")>; 391def : InstRW<[P5600WriteFPUS], (instregex "^FFQR_(W|D)$")>; 392def : InstRW<[P5600WriteFPUS], (instregex "^FTINT_(U|S)_(W|D)$")>; 393def : InstRW<[P5600WriteFPUS], (instregex "^FRINT_(W|D)$")>; 394def : InstRW<[P5600WriteFPUS], (instregex "^FTQ_(H|W)$")>; 395def : InstRW<[P5600WriteFPUS], (instregex "^FTRUNC_(U|S)_(W|D)$")>; 396 397// fexdo.[hw], fexupl.[wd], fexupr.[wd] 398def : InstRW<[P5600WriteFPUS], (instregex "^FEXDO_(H|W)$")>; 399def : InstRW<[P5600WriteFPUS], (instregex "^FEXUPL_(W|D)$")>; 400def : InstRW<[P5600WriteFPUS], (instregex "^FEXUPR_(W|D)$")>; 401 402// fclass.[wd], fmax.[wd], fmax_a.[wd], fmin.[wd], fmin_a.[wd], flog2.[wd] 403def : InstRW<[P5600WriteFPUS], (instregex "^FCLASS_(W|D)$")>; 404def : InstRW<[P5600WriteFPUS], (instregex "^FMAX_A_(W|D)$")>; 405def : InstRW<[P5600WriteFPUS], (instregex "^FMAX_(W|D)$")>; 406def : InstRW<[P5600WriteFPUS], (instregex "^FMIN_A_(W|D)$")>; 407def : InstRW<[P5600WriteFPUS], (instregex "^FMIN_(W|D)$")>; 408def : InstRW<[P5600WriteFPUS], (instregex "^FLOG2_(W|D)$")>; 409 410// interleave right/left, interleave even/odd, insert 411def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(ILVR|ILVL)_[BHWD]$")>; 412def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(ILVEV|ILVOD)_[BHWD]$")>; 413def : InstRW<[P5600WriteMSAShortLogic], (instregex "^INSVE_[BHWD]$")>; 414 415// subs_?.[bhwd], subsus_?.[bhwd], subsuu_?.[bhwd], subvi.[bhwd], subv.[bhwd], 416def : InstRW<[P5600WriteMSAShortInt], (instregex "^SUBS_(S|U)_[BHWD]$")>; 417def : InstRW<[P5600WriteMSAShortInt], (instregex "^SUBSUS_(S|U)_[BHWD]$")>; 418def : InstRW<[P5600WriteMSAShortInt], (instregex "^SUBSUU_(S|U)_[BHWD]$")>; 419def : InstRW<[P5600WriteMSAShortInt], (instregex "^SUBVI_[BHWD]$")>; 420def : InstRW<[P5600WriteMSAShortInt], (instregex "^SUBV_[BHWD]$")>; 421 422// mod_[su].[bhwd], div_[su].[bhwd] 423def : InstRW<[P5600WriteFPUDivI], (instregex "^MOD_(S|U)_[BHWD]$")>; 424def : InstRW<[P5600WriteFPUDivI], (instregex "^DIV_(S|U)_[BHWD]$")>; 425 426// hadd_[su].[bhwd], hsub_[su].[bhwd], max_[sua].[bhwd], min_[sua].[bhwd], 427// maxi_[su].[bhwd], mini_[su].[bhwd], sra?.[bhwd], srar?.[bhwd], srlr.[bhwd], 428// sll?.[bhwd], pckev.[bhwd], pckod.[bhwd], nloc.[bhwd], nlzc.[bhwd], 429// insve.[bhwd] 430def : InstRW<[P5600WriteMSAShortLogic], (instregex "^HADD_(S|U)_[BHWD]$")>; 431def : InstRW<[P5600WriteMSAShortLogic], (instregex "^HSUB_(S|U)_[BHWD]$")>; 432def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(MAX|MIN)_S_[BHWD]$")>; 433def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(MAX|MIN)_U_[BHWD]$")>; 434def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(MAX|MIN)_A_[BHWD]$")>; 435def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(MAXI|MINI)_(S|U)_[BHWD]$")>; 436def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SRA|SRAI)_[BHWD]$")>; 437def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SRL|SRLI)_[BHWD]$")>; 438def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SRAR|SRARI)_[BHWD]$")>; 439def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SRLR|SRLRI)_[BHWD]$")>; 440def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SLL|SLLI)_[BHWD]$")>; 441def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(PCKEV|PCKOD)_[BHWD]$")>; 442def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(NLOC|NLZC)_[BHWD]$")>; 443 444// Long Pipe 445// ---------- 446// 447// add.[ds], add.ps, cvt.d.[sw], cvt.s.[dw], cvt.w.[sd], cvt.[sw].ps, 448// cvt.ps.[sw], cvt.s.(pl|pu), c.<cc>.[ds], c.<cc>.ps, mul.[ds], mul.ps, 449// pl[lu].ps, sub.[ds], sub.ps, trunc.w.[ds], trunc.w.ps 450def : InstRW<[P5600WriteFPUL], 451 (instrs FADD_D32, FADD_D64, FADD_S, FMUL_D32, FMUL_D64, FMUL_S, 452 FSUB_D32, FSUB_D64, FSUB_S)>; 453def : InstRW<[P5600WriteFPUL], (instregex "^TRUNC_(L|W)_(S|D32|D64)$")>; 454def : InstRW<[P5600WriteFPUL], 455 (instregex "^CVT_(S|D32|D64|L|W)_(S|D32|D64|L|W)$")>; 456def : InstRW<[P5600WriteFPUL], (instrs CVT_PS_S64, CVT_S_PL64, CVT_S_PU64)>; 457def : InstRW<[P5600WriteFPUL], (instregex "^C_[A-Z]+_(S|D32|D64)$")>; 458def : InstRW<[P5600WriteFPUL], (instregex "^FCMP_(S32|D32|D64)$")>; 459def : InstRW<[P5600WriteFPUL], (instregex "^PseudoCVT_(S|D32|D64)_(L|W)$")>; 460def : InstRW<[P5600WriteFPUL], (instrs PLL_PS64, PLU_PS64)>; 461 462// div.[ds], div.ps 463def : InstRW<[P5600WriteFPUDivS], (instrs FDIV_S)>; 464def : InstRW<[P5600WriteFPUDivD], (instrs FDIV_D32, FDIV_D64)>; 465 466// sqrt.[ds], sqrt.ps 467def : InstRW<[P5600WriteFPUSqrtS], (instrs FSQRT_S)>; 468def : InstRW<[P5600WriteFPUSqrtD], (instrs FSQRT_D32, FSQRT_D64)>; 469 470// frcp.[wd], frsqrt.[wd] 471def : InstRW<[P5600WriteFPURsqrtD], (instregex "^FRCP_(W|D)$")>; 472def : InstRW<[P5600WriteFPURsqrtD], (instregex "^FRSQRT_(W|D)$")>; 473 474def : InstRW<[P5600WriteFPURsqrtD], (instrs RECIP_D32, RECIP_D64, RSQRT_D32, 475 RSQRT_D64)>; 476def : InstRW<[P5600WriteFPURsqrtS], (instrs RECIP_S, RSQRT_S)>; 477 478// fmadd.[wd], fmsubb.[wd], fdiv.[wd], fsqrt.[wd], fmul.[wd], fadd.[wd], 479// fsub.[wd] 480def : InstRW<[P5600WriteFPUL_MADDSUB], (instregex "^FMADD_(W|D)$")>; 481def : InstRW<[P5600WriteFPUL_MADDSUB], (instregex "^FMSUB_(W|D)$")>; 482def : InstRW<[P5600WriteFPUDivS], (instregex "^FDIV_W$")>; 483def : InstRW<[P5600WriteFPUDivD], (instregex "^FDIV_D$")>; 484def : InstRW<[P5600WriteFPUSqrtS], (instregex "^FSQRT_W$")>; 485def : InstRW<[P5600WriteFPUSqrtD], (instregex "^FSQRT_D$")>; 486def : InstRW<[P5600WriteFPUL], (instregex "^FMUL_(W|D)$")>; 487def : InstRW<[P5600WriteFPUL], (instregex "^FADD_(W|D)$")>; 488def : InstRW<[P5600WriteFPUL], (instregex "^FSUB_(W|D)$")>; 489 490// dpadd_?.[bhwd], dpsub_?.[bhwd], dotp_?.[bhwd], msubv.[bhwd], maddv.[bhwd] 491// mulv.[bhwd]. 492def : InstRW<[P5600WriteMSALongInt], (instregex "^DPADD_(S|U)_[HWD]$")>; 493def : InstRW<[P5600WriteMSALongInt], (instregex "^DPSUB_(S|U)_[HWD]$")>; 494def : InstRW<[P5600WriteMSALongInt], (instregex "^DOTP_(S|U)_[HWD]$")>; 495def : InstRW<[P5600WriteMSALongInt], (instregex "^MSUBV_[BHWD]$")>; 496def : InstRW<[P5600WriteMSALongInt], (instregex "^MADDV_[BHWD]$")>; 497def : InstRW<[P5600WriteMSALongInt], (instregex "^MULV_[BHWD]$")>; 498 499def : InstRW<[P5600WriteMSALongInt], (instregex "^MADDR_Q_[HW]$")>; 500def : InstRW<[P5600WriteMSALongInt], (instregex "^MADD_Q_[HW]$")>; 501def : InstRW<[P5600WriteMSALongInt], (instregex "^MSUBR_Q_[HW]$")>; 502def : InstRW<[P5600WriteMSALongInt], (instregex "^MSUB_Q_[HW]$")>; 503def : InstRW<[P5600WriteMSALongInt], (instregex "^MULR_Q_[HW]$")>; 504def : InstRW<[P5600WriteMSALongInt], (instregex "^MUL_Q_[HW]$")>; 505 506// madd.[ds], msub.[ds], nmadd.[ds], nmsub.[ds], 507// Operand 0 is read on cycle 5. All other operands are read on operand 0. 508def : InstRW<[SchedReadAdvance<5>, P5600WriteFPUL_MADDSUB], 509 (instrs MADD_D32, MADD_D64, MADD_S, MSUB_D32, MSUB_D64, MSUB_S, 510 NMADD_D32, NMADD_D64, NMADD_S, NMSUB_D32, NMSUB_D64, NMSUB_S)>; 511 512// madd.ps, msub.ps, nmadd.ps, nmsub.ps 513// Operand 0 and 1 are read on cycle 5. All others are read on operand 0. 514// (none of these instructions exist in the backend yet) 515 516// Load Pipe 517// --------- 518// 519// This is typically used in conjunction with the load pipeline under the AGQ 520// All the instructions are in the 'Tricky Instructions' section. 521 522def P5600WriteLoadOtherUnitsToFPU : SchedWriteRes<[P5600IssueFPULoad]> { 523 let Latency = 4; 524} 525 526// Tricky Instructions 527// =================== 528// 529// These instructions are split across multiple uops (in different pipelines) 530// that must cooperate to complete the operation 531 532// FIXME: This isn't quite right since the implementation of WriteSequence 533// current aggregates the resources and ignores the exact cycle they are 534// used. 535def P5600WriteMoveGPRToFPU : WriteSequence<[P5600WriteMoveGPRToOtherUnits, 536 P5600WriteMoveOtherUnitsToFPU]>; 537 538// FIXME: This isn't quite right since the implementation of WriteSequence 539// current aggregates the resources and ignores the exact cycle they are 540// used. 541def P5600WriteMoveFPUToGPR : WriteSequence<[P5600WriteMoveFPUSToOtherUnits, 542 P5600WriteGPRFromBypass]>; 543 544// FIXME: This isn't quite right since the implementation of WriteSequence 545// current aggregates the resources and ignores the exact cycle they are 546// used. 547def P5600WriteStoreFPUS : WriteSequence<[P5600WriteMoveFPUSToOtherUnits, 548 P5600WriteStoreFromOtherUnits]>; 549 550// FIXME: This isn't quite right since the implementation of WriteSequence 551// current aggregates the resources and ignores the exact cycle they are 552// used. 553def P5600WriteStoreFPUL : WriteSequence<[P5600WriteMoveFPULToOtherUnits, 554 P5600WriteStoreFromOtherUnits]>; 555 556// FIXME: This isn't quite right since the implementation of WriteSequence 557// current aggregates the resources and ignores the exact cycle they are 558// used. 559def P5600WriteLoadFPU : WriteSequence<[P5600WriteLoadToOtherUnits, 560 P5600WriteLoadOtherUnitsToFPU]>; 561 562// ctc1, mtc1, mthc1 563def : InstRW<[P5600WriteMoveGPRToFPU], (instrs CTC1, MTC1, MTC1_D64, MTHC1_D32, 564 MTHC1_D64, BuildPairF64, 565 BuildPairF64_64)>; 566 567// copy.[su]_[bhwd] 568def : InstRW<[P5600WriteMoveFPUToGPR], (instregex "^COPY_U_[BHW]$")>; 569def : InstRW<[P5600WriteMoveFPUToGPR], (instregex "^COPY_S_[BHWD]$")>; 570 571// bc1[ft], cfc1, mfc1, mfhc1, movf, movt 572def : InstRW<[P5600WriteMoveFPUToGPR], (instrs BC1F, BC1FL, BC1T, BC1TL, CFC1, 573 MFC1, MFC1_D64, MFHC1_D32, MFHC1_D64, 574 MOVF_I, MOVT_I, ExtractElementF64, 575 ExtractElementF64_64)>; 576 577// swc1, swxc1, st.[bhwd] 578def : InstRW<[P5600WriteStoreFPUS], (instrs SDC1, SDC164, SDXC1, SDXC164, 579 SWC1, SWXC1, SUXC1, SUXC164)>; 580def : InstRW<[P5600WriteStoreFPUS], (instregex "^ST_[BHWD]$")>; 581def : InstRW<[P5600WriteStoreFPUS], (instrs ST_F16)>; 582 583// movn.[ds], movz.[ds] 584def : InstRW<[P5600WriteStoreFPUL], (instrs MOVN_I_D32, MOVN_I_D64, MOVN_I_S, 585 MOVZ_I_D32, MOVZ_I_D64, MOVZ_I_S)>; 586 587// l[dw]x?c1, ld.[bhwd] 588def : InstRW<[P5600WriteLoadFPU], (instrs LDC1, LDC164, LDXC1, LDXC164, 589 LWC1, LWXC1, LUXC1, LUXC164)>; 590def : InstRW<[P5600WriteLoadFPU], (instregex "LD_[BHWD]")>; 591def : InstRW<[P5600WriteLoadFPU], (instrs LD_F16)>; 592 593// Unsupported Instructions 594// ======================== 595// 596// The following instruction classes are never valid on P5600. 597// II_DADDIU, II_DADDU, II_DMFC1, II_DMTC1, II_DMULT, II_DMULTU, II_DROTR, 598// II_DROTR32, II_DROTRV, II_DDIV, II_DSLL, II_DSLL32, II_DSLLV, II_DSRA, 599// II_DSRA32, II_DSRAV, II_DSRL, II_DSRL32, II_DSRLV, II_DSUBU, II_DDIVU, 600// II_JALRC, II_LD, II_LD[LR], II_RESTORE, II_SAVE, II_SD, II_SDC1, II_SD[LR] 601// 602// The following instructions are never valid on P5600. 603// addq.ph, repl.ph, repl.qb, subq.ph, subu_s.qb 604// 605// Guesswork 606// ========= 607// 608// This section is largely temporary guesswork. 609 610// ceil.[lw].[ds], floor.[lw].[ds] 611// Reason behind guess: trunc.[lw].ds and the various cvt's are in FPUL 612def : InstRW<[P5600WriteFPUL], (instregex "^CEIL_(L|W)_(S|D32|D64)$")>; 613def : InstRW<[P5600WriteFPUL], (instregex "^FLOOR_(L|W)_(S|D32|D64)$")>; 614def : InstRW<[P5600WriteFPUL], (instregex "^ROUND_(L|W)_(S|D32|D64)$")>; 615 616// rotrv 617// Reason behind guess: rotr is in the same category and the two register forms 618// generally follow the immediate forms in this category 619def : InstRW<[P5600WriteEitherALU], (instrs ROTRV)>; 620 621// Atomic instructions 622 623// FIXME: Define `WriteAtomic` in the MipsSchedule.td and 624// attach it to the Atomic2OpsPostRA, AtomicCmpSwapPostRA, ... 625// classes. Then just define resources for the `WriteAtomic` in each 626// machine models. 627def P5600Atomic : ProcResource<1> { let BufferSize = 1; } 628def P5600WriteAtomic : SchedWriteRes<[P5600Atomic]> { let Latency = 2; } 629 630def : InstRW<[P5600WriteAtomic], 631 (instregex "^ATOMIC_SWAP_I(8|16|32|64)_POSTRA$")>; 632def : InstRW<[P5600WriteAtomic], 633 (instregex "^ATOMIC_CMP_SWAP_I(8|16|32|64)_POSTRA$")>; 634def : InstRW<[P5600WriteAtomic], 635 (instregex "^ATOMIC_LOAD_(ADD|SUB|AND|OR|XOR|NAND|MIN|MAX|UMIN|UMAX)" 636 "_I(8|16|32|64)_POSTRA$")>; 637} 638