1//==- MipsScheduleP5600.td - P5600 Scheduling Definitions --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9def MipsP5600Model : SchedMachineModel { 10 int IssueWidth = 2; // 2x dispatched per cycle 11 int MicroOpBufferSize = 48; // min(48, 48, 64) 12 int LoadLatency = 4; 13 int MispredictPenalty = 8; // TODO: Estimated 14 15 let CompleteModel = 1; 16 let FullInstRWOverlapCheck = 1; 17 18 list<Predicate> UnsupportedFeatures = [HasMips3, HasMips32r6, HasMips64, 19 HasMips64r2, HasMips64r5, HasMips64r6, 20 IsGP64bit, IsPTR64bit, 21 InMicroMips, InMips16Mode, 22 HasCnMips, HasCnMipsP, 23 HasDSP, HasDSPR2, HasMips3D, HasMT, 24 HasCRC]; 25} 26 27let SchedModel = MipsP5600Model in { 28 29// ALQ Pipelines 30// ============= 31 32def P5600ALQ : ProcResource<1> { let BufferSize = 16; } 33def P5600IssueALU : ProcResource<1> { let Super = P5600ALQ; } 34 35// ALU Pipeline 36// ------------ 37 38def P5600WriteALU : SchedWriteRes<[P5600IssueALU]>; 39 40// and, lui, nor, or, slti, sltiu, sub, subu, xor 41def : InstRW<[P5600WriteALU], (instrs AND, LUi, NOR, OR, SLTi, SLTiu, SUB, 42 SUBu, XOR)>; 43 44// AGQ Pipelines 45// ============= 46 47def P5600AGQ : ProcResource<3> { let BufferSize = 16; } 48def P5600IssueAL2 : ProcResource<1> { let Super = P5600AGQ; } 49def P5600IssueCTISTD : ProcResource<1> { let Super = P5600AGQ; } 50def P5600IssueLDST : ProcResource<1> { let Super = P5600AGQ; } 51 52def P5600AL2Div : ProcResource<1>; 53// Pseudo-resource used to block CTISTD when handling multi-pipeline splits. 54def P5600CTISTD : ProcResource<1>; 55 56// CTISTD Pipeline 57// --------------- 58 59def P5600WriteJump : SchedWriteRes<[P5600IssueCTISTD, P5600CTISTD]>; 60def P5600WriteJumpAndLink : SchedWriteRes<[P5600IssueCTISTD, P5600CTISTD]> { 61 let Latency = 2; 62} 63 64def P5600Nop : SchedWriteRes<[P5600IssueCTISTD]> { 65 let Latency = 0; 66} 67 68def : InstRW<[P5600Nop], (instrs SSNOP, NOP)>; 69 70// b, beq, beql, bg[et]z, bl[et]z, bne, bnel, j, syscall, jal, bltzal, 71// jalr, jr.hb, jr 72def : InstRW<[P5600WriteJump], (instrs B, BAL, BAL_BR, BEQ, BEQL, BGEZ, BGEZAL, 73 BGEZALL, BGEZL, BGTZ, BGTZL, BLEZ, BLEZL, BLTZ, 74 BLTZAL, BLTZALL, BLTZL, BNE, BNEL, BREAK, 75 DERET, ERET, ERet, ERETNC, J, JR, JR_HB, 76 PseudoIndirectBranch, 77 PseudoIndirectHazardBranch, PseudoReturn, 78 SDBBP, SYSCALL, RetRA, TAILCALL, TAILCALLREG, 79 TAILCALLREGHB, TEQ, TEQI, TGE, TGEI, TGEIU, 80 TGEU, TLT, TLTI, TLTU, TNE, TNEI, TRAP, 81 TTLTIU, WAIT, PAUSE)>; 82 83def : InstRW<[P5600WriteJumpAndLink], (instrs JAL, JALR, JALRHBPseudo, 84 JALRPseudo, JALR_HB)>; 85 86def : InstRW<[P5600WriteJumpAndLink], (instrs JALX)> { 87 let Unsupported = 1; 88} 89 90def P5600COP0 : SchedWriteRes<[P5600IssueCTISTD, P5600CTISTD]>; 91 92def : InstRW<[P5600COP0], (instrs TLBINV, TLBINVF, TLBP, TLBR, TLBWI, TLBWR, 93 MFC0, MTC0)>; 94 95def P5600COP2 : SchedWriteRes<[P5600IssueCTISTD, P5600CTISTD]>; 96 97def : InstRW<[P5600COP2], (instrs MFC2, MTC2)> { 98 let Unsupported = 1; 99} 100 101// MIPS Virtualization ASE 102// ======================= 103def : InstRW<[P5600COP0], (instrs HYPCALL, MFGC0, MFHGC0, MTGC0, MTHGC0, 104 TLBGINV, TLBGINVF, TLBGP, TLBGR, TLBGWI, TLBGWR)>; 105 106// LDST Pipeline 107// ------------- 108 109def P5600WriteLoad : SchedWriteRes<[P5600IssueLDST]> { 110 let Latency = 4; 111} 112 113def P5600WriteLoadShifted : SchedWriteRes<[P5600IssueLDST, P5600CTISTD]> { 114 let Latency = 4; 115} 116 117def P5600WriteCache : SchedWriteRes<[P5600IssueLDST]>; 118 119def P5600WriteStore : SchedWriteRes<[P5600IssueLDST, P5600CTISTD]> { 120 // FIXME: This is a bit pessimistic. P5600CTISTD is only used during cycle 2 121 // not during 0, 1, and 2. 122 let ResourceCycles = [ 1, 3 ]; 123} 124 125def P5600WriteGPRFromBypass : SchedWriteRes<[P5600IssueLDST]> { 126 let Latency = 2; 127} 128 129def P5600WriteStoreFromOtherUnits : SchedWriteRes<[P5600IssueLDST]>; 130def P5600WriteLoadToOtherUnits : SchedWriteRes<[P5600IssueLDST]> { 131 let Latency = 0; 132} 133 134// l[bhw], l[bh]u, ll 135def : InstRW<[P5600WriteLoad], (instrs LB, LBu, LH, LHu, LW, LL, LWC2, LWC3, 136 LDC2, LDC3, LBE, LBuE, LHE, LHuE, LWE, LLE, 137 LWPC)>; 138 139// lw[lr] 140def : InstRW<[P5600WriteLoadShifted], (instrs LWL, LWR, LWLE, LWRE)>; 141 142// s[bhw], sw[lr] 143def : InstRW<[P5600WriteStore], (instrs SB, SH, SW, SWC2, SWC3, SDC2, SDC3, SC, 144 SBE, SHE, SWE, SCE, SWL, SWR, SWLE, SWRE)>; 145 146// pref, cache, sync, synci 147def : InstRW<[P5600WriteCache], (instrs PREF, PREFE, CACHE, CACHEE, SYNC, 148 SYNCI)>; 149 150// LDST is also used in moves from general purpose registers to floating point 151// and MSA. 152def P5600WriteMoveGPRToOtherUnits : SchedWriteRes<[P5600IssueLDST]> { 153 let Latency = 0; 154} 155 156// AL2 Pipeline 157// ------------ 158 159def P5600WriteAL2 : SchedWriteRes<[P5600IssueAL2]>; 160def P5600WriteAL2BitExt : SchedWriteRes<[P5600IssueAL2]> { let Latency = 2; } 161def P5600WriteAL2ShadowMov : SchedWriteRes<[P5600IssueAL2]> { let Latency = 2; } 162def P5600WriteAL2CondMov : SchedWriteRes<[P5600IssueAL2, P5600CTISTD]> { 163 let Latency = 2; 164} 165def P5600WriteAL2Div : SchedWriteRes<[P5600IssueAL2, P5600AL2Div]> { 166 // Estimated worst case 167 let Latency = 34; 168 let ResourceCycles = [1, 34]; 169} 170def P5600WriteAL2DivU : SchedWriteRes<[P5600IssueAL2, P5600AL2Div]> { 171 // Estimated worst case 172 let Latency = 34; 173 let ResourceCycles = [1, 34]; 174} 175def P5600WriteAL2Mul : SchedWriteRes<[P5600IssueAL2]> { let Latency = 3; } 176def P5600WriteAL2Mult: SchedWriteRes<[P5600IssueAL2]> { let Latency = 5; } 177def P5600WriteAL2MAdd: SchedWriteRes<[P5600IssueAL2, P5600CTISTD]> { 178 let Latency = 5; 179} 180 181// clo, clz, di, ei, mfhi, mflo 182def : InstRW<[P5600WriteAL2], (instrs CLO, CLZ, DI, EI, MFHI, MFLO, 183 PseudoMFHI, PseudoMFLO)>; 184 185// ehb, rdhwr, rdpgpr, wrpgpr, wsbh 186def : InstRW<[P5600WriteAL2ShadowMov], (instrs EHB, RDHWR, WSBH)>; 187 188// mov[nz] 189def : InstRW<[P5600WriteAL2CondMov], (instrs MOVN_I_I, MOVZ_I_I)>; 190 191// divu? 192def : InstRW<[P5600WriteAL2Div], (instrs DIV, PseudoSDIV, SDIV)>; 193def : InstRW<[P5600WriteAL2DivU], (instrs DIVU, PseudoUDIV, UDIV)>; 194 195// mul 196def : InstRW<[P5600WriteAL2Mul], (instrs MUL)>; 197// multu?, multu? 198def : InstRW<[P5600WriteAL2Mult], (instrs MULT, MULTu, PseudoMULT, 199 PseudoMULTu)>; 200// maddu?, msubu?, mthi, mtlo 201def : InstRW<[P5600WriteAL2MAdd], (instrs MADD, MADDU, MSUB, MSUBU, 202 MTHI, MTLO, PseudoMADD, PseudoMADDU, 203 PseudoMSUB, PseudoMSUBU, PseudoMTLOHI)>; 204 205// ext, ins 206def : InstRW<[P5600WriteAL2BitExt], (instrs EXT, INS)>; 207 208// Either ALU or AL2 Pipelines 209// --------------------------- 210// 211// Some instructions can choose between ALU and AL2, but once dispatched to 212// ALQ or AGQ respectively they are committed to that path. 213// The decision is based on the outcome of the most recent selection when the 214// choice was last available. For now, we assume ALU is always chosen. 215 216def P5600WriteEitherALU : SchedWriteVariant< 217 // FIXME: Implement selection predicate 218 [SchedVar<SchedPredicate<[{1}]>, [P5600WriteALU]>, 219 SchedVar<SchedPredicate<[{0}]>, [P5600WriteAL2]> 220 ]>; 221 222// add, addi, addiu, addu, andi, ori, rotr, se[bh], sllv?, sr[al]v?, slt, sltu, 223// xori 224def : InstRW<[P5600WriteEitherALU], (instrs ADD, ADDi, ADDiu, ANDi, ORi, ROTR, 225 SEB, SEH, SLT, SLTu, SLL, SRA, SRL, XORi, 226 ADDu, SLLV, SRAV, SRLV, LSA, COPY)>; 227 228// FPU Pipelines 229// ============= 230 231def P5600FPQ : ProcResource<3> { let BufferSize = 16; } 232def P5600IssueFPUS : ProcResource<1> { let Super = P5600FPQ; } 233def P5600IssueFPUL : ProcResource<1> { let Super = P5600FPQ; } 234def P5600IssueFPULoad : ProcResource<1> { let Super = P5600FPQ; } 235 236def P5600FPUDivSqrt : ProcResource<2>; 237 238def P5600WriteFPUS : SchedWriteRes<[P5600IssueFPUS]>; 239def P5600WriteFPUL : SchedWriteRes<[P5600IssueFPUL]> { let Latency = 4; } 240def P5600WriteFPUL_MADDSUB : SchedWriteRes<[P5600IssueFPUL]> { let Latency = 6; } 241def P5600WriteFPUDivI : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> { 242 // Best/Common/Worst case = 7 / 23 / 27 243 let Latency = 23; // Using common case 244 let ResourceCycles = [ 1, 23 ]; 245} 246def P5600WriteFPUDivS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> { 247 // Best/Common/Worst case = 7 / 23 / 27 248 let Latency = 23; // Using common case 249 let ResourceCycles = [ 1, 23 ]; 250} 251def P5600WriteFPUDivD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> { 252 // Best/Common/Worst case = 7 / 31 / 35 253 let Latency = 31; // Using common case 254 let ResourceCycles = [ 1, 31 ]; 255} 256def P5600WriteFPURcpS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> { 257 // Best/Common/Worst case = 7 / 19 / 23 258 let Latency = 19; // Using common case 259 let ResourceCycles = [ 1, 19 ]; 260} 261def P5600WriteFPURcpD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> { 262 // Best/Common/Worst case = 7 / 27 / 31 263 let Latency = 27; // Using common case 264 let ResourceCycles = [ 1, 27 ]; 265} 266def P5600WriteFPURsqrtS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> { 267 // Best/Common/Worst case = 7 / 27 / 27 268 let Latency = 27; // Using common case 269 let ResourceCycles = [ 1, 27 ]; 270} 271def P5600WriteFPURsqrtD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> { 272 // Best/Common/Worst case = 7 / 27 / 31 273 let Latency = 27; // Using common case 274 let ResourceCycles = [ 1, 27 ]; 275} 276def P5600WriteFPUSqrtS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> { 277 // Best/Common/Worst case = 7 / 27 / 31 278 let Latency = 27; // Using common case 279 let ResourceCycles = [ 1, 27 ]; 280} 281def P5600WriteFPUSqrtD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> { 282 // Best/Common/Worst case = 7 / 35 / 39 283 let Latency = 35; // Using common case 284 let ResourceCycles = [ 1, 35 ]; 285} 286def P5600WriteMSAShortLogic : SchedWriteRes<[P5600IssueFPUS]>; 287def P5600WriteMSAShortInt : SchedWriteRes<[P5600IssueFPUS]> { let Latency = 2; } 288def P5600WriteMoveOtherUnitsToFPU : SchedWriteRes<[P5600IssueFPUS]>; 289def P5600WriteMSAOther3 : SchedWriteRes<[P5600IssueFPUS]> { let Latency = 3; } 290def P5600WriteMSALongInt : SchedWriteRes<[P5600IssueFPUS]> { let Latency = 5; } 291 292// vshf.[bhwd], binsl.[bhwd], binsr.[bhwd], insert.[bhwd], sld?.[bhwd], 293// bset.[bhwd], bclr.[bhwd], bneg.[bhwd], bsel_v, bseli_b 294def : InstRW<[P5600WriteMSAShortInt], (instregex "^VSHF_[BHWD]$")>; 295def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BINSL|BINSLI)_[BHWD]$")>; 296def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BINSR|BINSRI)_[BHWD]$")>; 297def : InstRW<[P5600WriteMSAShortInt], (instregex "^INSERT_[BHWD]$")>; 298def : InstRW<[P5600WriteMSAShortInt], (instregex "^(SLD|SLDI)_[BHWD]$")>; 299def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BSET|BSETI)_[BHWD]$")>; 300def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BCLR|BCLRI)_[BHWD]$")>; 301def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BNEG|BNEGI)_[BHWD]$")>; 302def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BSEL_V|BSELI_B)$")>; 303def : InstRW<[P5600WriteMSAShortInt], (instregex "^BMN*Z.*$")>; 304def : InstRW<[P5600WriteMSAShortInt], 305 (instregex "^BSEL_(H|W|D|FW|FD)_PSEUDO$")>; 306 307// pcnt.[bhwd], sat_s.[bhwd], sat_u.bhwd] 308def : InstRW<[P5600WriteMSAOther3], (instregex "^PCNT_[BHWD]$")>; 309def : InstRW<[P5600WriteMSAOther3], (instregex "^SAT_(S|U)_[BHWD]$")>; 310 311// bnz.[bhwdv], cfcmsa, ctcmsa 312def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(BNZ|BZ)_[BHWDV]$")>; 313def : InstRW<[P5600WriteMSAShortLogic], (instregex "^C(F|T)CMSA$")>; 314 315// FPUS is also used in moves from floating point and MSA registers to general 316// purpose registers. 317def P5600WriteMoveFPUSToOtherUnits : SchedWriteRes<[P5600IssueFPUS]> { 318 let Latency = 0; 319} 320 321// FPUL is also used in moves from floating point and MSA registers to general 322// purpose registers. 323def P5600WriteMoveFPULToOtherUnits : SchedWriteRes<[P5600IssueFPUL]>; 324 325// Short Pipe 326// ---------- 327// 328// abs.[ds], abs.ps, bc1[tf]l?, mov[tf].[ds], mov[tf], mov.[ds], [cm][ft]c1, 329// m[ft]hc1, neg.[ds], neg.ps, nor.v, nori.b, or.v, ori.b, xor.v, xori.b, 330// sdxc1, sdc1, st.[bhwd], swc1, swxc1 331def : InstRW<[P5600WriteFPUS], (instrs FABS_S, FABS_D32, FABS_D64, MOVF_D32, 332 MOVF_D64, MOVF_S, MOVT_D32, MOVT_D64, 333 MOVT_S, FMOV_D32, FMOV_D64, FMOV_S, FNEG_S, 334 FNEG_D32, FNEG_D64)>; 335 336// adds_a.[bhwd], adds_[asu].[bhwd], addvi?.[bhwd], asub_[us].[bhwd], 337// aver?_[us].[bhwd], shf.[bhw], fill[bhwd], splat?.[bhwd] 338def : InstRW<[P5600WriteMSAShortInt], (instregex "^ADD_A_[BHWD]$")>; 339def : InstRW<[P5600WriteMSAShortInt], (instregex "^ADDS_[ASU]_[BHWD]$")>; 340// TODO: ADDVI_[BHW] might be 1 cycle latency rather than 2. Need to confirm it. 341def : InstRW<[P5600WriteMSAShortInt], (instregex "^ADDVI?_[BHWD]$")>; 342def : InstRW<[P5600WriteMSAShortInt], (instregex "^ASUB_[US].[BHWD]$")>; 343def : InstRW<[P5600WriteMSAShortInt], (instregex "^AVER?_[US].[BHWD]$")>; 344def : InstRW<[P5600WriteMSAShortInt], (instregex "^SHF_[BHW]$")>; 345def : InstRW<[P5600WriteMSAShortInt], (instregex "^FILL_[BHWD]$")>; 346def : InstRW<[P5600WriteMSAShortInt], (instregex "^(SPLAT|SPLATI)_[BHWD]$")>; 347 348// and.v, andi.b, move.v, ldi.[bhwd] 349def : InstRW<[P5600WriteMSAShortLogic], (instregex "^MOVE_V$")>; 350def : InstRW<[P5600WriteMSAShortLogic], (instregex "^LDI_[BHWD]$")>; 351def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)_V$")>; 352def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)I_B$")>; 353def : InstRW<[P5600WriteMSAShortLogic], 354 (instregex "^(AND|OR|[XN]OR)_V_[DHW]_PSEUDO$")>; 355def : InstRW<[P5600WriteMSAShortLogic], (instregex "^FILL_F(D|W)_PSEUDO$")>; 356def : InstRW<[P5600WriteMSAShortLogic], (instregex "^INSERT_F(D|W)_PSEUDO$")>; 357 358// fexp2_w, fexp2_d 359def : InstRW<[P5600WriteFPUS], (instregex "^FEXP2_(W|D)$")>; 360 361// compare, converts, round to int, floating point truncate. 362def : InstRW<[P5600WriteFPUS], (instregex "^(CLT|CLTI)_(S|U)_[BHWD]$")>; 363def : InstRW<[P5600WriteFPUS], (instregex "^(CLE|CLEI)_(S|U)_[BHWD]$")>; 364def : InstRW<[P5600WriteFPUS], (instregex "^(CEQ|CEQI)_[BHWD]$")>; 365def : InstRW<[P5600WriteFPUS], (instregex "^CMP_UN_(S|D)$")>; 366def : InstRW<[P5600WriteFPUS], (instregex "^CMP_UEQ_(S|D)$")>; 367def : InstRW<[P5600WriteFPUS], (instregex "^CMP_EQ_(S|D)$")>; 368def : InstRW<[P5600WriteFPUS], (instregex "^CMP_LT_(S|D)$")>; 369def : InstRW<[P5600WriteFPUS], (instregex "^CMP_ULT_(S|D)$")>; 370def : InstRW<[P5600WriteFPUS], (instregex "^CMP_LE_(S|D)$")>; 371def : InstRW<[P5600WriteFPUS], (instregex "^CMP_ULE_(S|D)$")>; 372def : InstRW<[P5600WriteFPUS], (instregex "^FS(AF|EQ|LT|LE|NE|OR)_(W|D)$")>; 373def : InstRW<[P5600WriteFPUS], (instregex "^FSUEQ_(W|D)$")>; 374def : InstRW<[P5600WriteFPUS], (instregex "^FSULE_(W|D)$")>; 375def : InstRW<[P5600WriteFPUS], (instregex "^FSULT_(W|D)$")>; 376def : InstRW<[P5600WriteFPUS], (instregex "^FSUNE_(W|D)$")>; 377def : InstRW<[P5600WriteFPUS], (instregex "^FSUN_(W|D)$")>; 378def : InstRW<[P5600WriteFPUS], (instregex "^FCAF_(W|D)$")>; 379def : InstRW<[P5600WriteFPUS], (instregex "^FCEQ_(W|D)$")>; 380def : InstRW<[P5600WriteFPUS], (instregex "^FCLE_(W|D)$")>; 381def : InstRW<[P5600WriteFPUS], (instregex "^FCLT_(W|D)$")>; 382def : InstRW<[P5600WriteFPUS], (instregex "^FCNE_(W|D)$")>; 383def : InstRW<[P5600WriteFPUS], (instregex "^FCOR_(W|D)$")>; 384def : InstRW<[P5600WriteFPUS], (instregex "^FCUEQ_(W|D)$")>; 385def : InstRW<[P5600WriteFPUS], (instregex "^FCULE_(W|D)$")>; 386def : InstRW<[P5600WriteFPUS], (instregex "^FCULT_(W|D)$")>; 387def : InstRW<[P5600WriteFPUS], (instregex "^FCUNE_(W|D)$")>; 388def : InstRW<[P5600WriteFPUS], (instregex "^FCUN_(W|D)$")>; 389def : InstRW<[P5600WriteFPUS], (instregex "^FABS_(W|D)$")>; 390def : InstRW<[P5600WriteFPUS], (instregex "^FFINT_(U|S)_(W|D)$")>; 391def : InstRW<[P5600WriteFPUS], (instregex "^FFQL_(W|D)$")>; 392def : InstRW<[P5600WriteFPUS], (instregex "^FFQR_(W|D)$")>; 393def : InstRW<[P5600WriteFPUS], (instregex "^FTINT_(U|S)_(W|D)$")>; 394def : InstRW<[P5600WriteFPUS], (instregex "^FRINT_(W|D)$")>; 395def : InstRW<[P5600WriteFPUS], (instregex "^FTQ_(H|W)$")>; 396def : InstRW<[P5600WriteFPUS], (instregex "^FTRUNC_(U|S)_(W|D)$")>; 397 398// fexdo.[hw], fexupl.[wd], fexupr.[wd] 399def : InstRW<[P5600WriteFPUS], (instregex "^FEXDO_(H|W)$")>; 400def : InstRW<[P5600WriteFPUS], (instregex "^FEXUPL_(W|D)$")>; 401def : InstRW<[P5600WriteFPUS], (instregex "^FEXUPR_(W|D)$")>; 402 403// fclass.[wd], fmax.[wd], fmax_a.[wd], fmin.[wd], fmin_a.[wd], flog2.[wd] 404def : InstRW<[P5600WriteFPUS], (instregex "^FCLASS_(W|D)$")>; 405def : InstRW<[P5600WriteFPUS], (instregex "^FMAX_A_(W|D)$")>; 406def : InstRW<[P5600WriteFPUS], (instregex "^FMAX_(W|D)$")>; 407def : InstRW<[P5600WriteFPUS], (instregex "^FMIN_A_(W|D)$")>; 408def : InstRW<[P5600WriteFPUS], (instregex "^FMIN_(W|D)$")>; 409def : InstRW<[P5600WriteFPUS], (instregex "^FLOG2_(W|D)$")>; 410 411// interleave right/left, interleave even/odd, insert 412def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(ILVR|ILVL)_[BHWD]$")>; 413def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(ILVEV|ILVOD)_[BHWD]$")>; 414def : InstRW<[P5600WriteMSAShortLogic], (instregex "^INSVE_[BHWD]$")>; 415 416// subs_?.[bhwd], subsus_?.[bhwd], subsuu_?.[bhwd], subvi.[bhwd], subv.[bhwd], 417def : InstRW<[P5600WriteMSAShortInt], (instregex "^SUBS_(S|U)_[BHWD]$")>; 418def : InstRW<[P5600WriteMSAShortInt], (instregex "^SUBSUS_(S|U)_[BHWD]$")>; 419def : InstRW<[P5600WriteMSAShortInt], (instregex "^SUBSUU_(S|U)_[BHWD]$")>; 420def : InstRW<[P5600WriteMSAShortInt], (instregex "^SUBVI_[BHWD]$")>; 421def : InstRW<[P5600WriteMSAShortInt], (instregex "^SUBV_[BHWD]$")>; 422 423// mod_[su].[bhwd], div_[su].[bhwd] 424def : InstRW<[P5600WriteFPUDivI], (instregex "^MOD_(S|U)_[BHWD]$")>; 425def : InstRW<[P5600WriteFPUDivI], (instregex "^DIV_(S|U)_[BHWD]$")>; 426 427// hadd_[su].[bhwd], hsub_[su].[bhwd], max_[sua].[bhwd], min_[sua].[bhwd], 428// maxi_[su].[bhwd], mini_[su].[bhwd], sra?.[bhwd], srar?.[bhwd], srlr.[bhwd], 429// sll?.[bhwd], pckev.[bhwd], pckod.[bhwd], nloc.[bhwd], nlzc.[bhwd], 430// insve.[bhwd] 431def : InstRW<[P5600WriteMSAShortLogic], (instregex "^HADD_(S|U)_[BHWD]$")>; 432def : InstRW<[P5600WriteMSAShortLogic], (instregex "^HSUB_(S|U)_[BHWD]$")>; 433def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(MAX|MIN)_S_[BHWD]$")>; 434def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(MAX|MIN)_U_[BHWD]$")>; 435def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(MAX|MIN)_A_[BHWD]$")>; 436def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(MAXI|MINI)_(S|U)_[BHWD]$")>; 437def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SRA|SRAI)_[BHWD]$")>; 438def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SRL|SRLI)_[BHWD]$")>; 439def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SRAR|SRARI)_[BHWD]$")>; 440def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SRLR|SRLRI)_[BHWD]$")>; 441def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SLL|SLLI)_[BHWD]$")>; 442def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(PCKEV|PCKOD)_[BHWD]$")>; 443def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(NLOC|NLZC)_[BHWD]$")>; 444 445// Long Pipe 446// ---------- 447// 448// add.[ds], add.ps, cvt.d.[sw], cvt.s.[dw], cvt.w.[sd], cvt.[sw].ps, 449// cvt.ps.[sw], cvt.s.(pl|pu), c.<cc>.[ds], c.<cc>.ps, mul.[ds], mul.ps, 450// pl[lu].ps, sub.[ds], sub.ps, trunc.w.[ds], trunc.w.ps 451def : InstRW<[P5600WriteFPUL], 452 (instrs FADD_D32, FADD_D64, FADD_S, FMUL_D32, FMUL_D64, FMUL_S, 453 FSUB_D32, FSUB_D64, FSUB_S)>; 454def : InstRW<[P5600WriteFPUL], (instregex "^TRUNC_(L|W)_(S|D32|D64)$")>; 455def : InstRW<[P5600WriteFPUL], 456 (instregex "^CVT_(S|D32|D64|L|W)_(S|D32|D64|L|W)$")>; 457def : InstRW<[P5600WriteFPUL], (instrs CVT_PS_S64, CVT_S_PL64, CVT_S_PU64)>; 458def : InstRW<[P5600WriteFPUL], (instregex "^C_[A-Z]+_(S|D32|D64)$")>; 459def : InstRW<[P5600WriteFPUL], (instregex "^FCMP_(S32|D32|D64)$")>; 460def : InstRW<[P5600WriteFPUL], (instregex "^PseudoCVT_(S|D32|D64)_(L|W)$")>; 461def : InstRW<[P5600WriteFPUL], (instrs PLL_PS64, PLU_PS64, PUL_PS64, PUU_PS64)>; 462 463// div.[ds], div.ps 464def : InstRW<[P5600WriteFPUDivS], (instrs FDIV_S)>; 465def : InstRW<[P5600WriteFPUDivD], (instrs FDIV_D32, FDIV_D64)>; 466 467// sqrt.[ds], sqrt.ps 468def : InstRW<[P5600WriteFPUSqrtS], (instrs FSQRT_S)>; 469def : InstRW<[P5600WriteFPUSqrtD], (instrs FSQRT_D32, FSQRT_D64)>; 470 471// frcp.[wd], frsqrt.[wd] 472def : InstRW<[P5600WriteFPURsqrtD], (instregex "^FRCP_(W|D)$")>; 473def : InstRW<[P5600WriteFPURsqrtD], (instregex "^FRSQRT_(W|D)$")>; 474 475def : InstRW<[P5600WriteFPURsqrtD], (instrs RECIP_D32, RECIP_D64, RSQRT_D32, 476 RSQRT_D64)>; 477def : InstRW<[P5600WriteFPURsqrtS], (instrs RECIP_S, RSQRT_S)>; 478 479// fmadd.[wd], fmsubb.[wd], fdiv.[wd], fsqrt.[wd], fmul.[wd], fadd.[wd], 480// fsub.[wd] 481def : InstRW<[P5600WriteFPUL_MADDSUB], (instregex "^FMADD_(W|D)$")>; 482def : InstRW<[P5600WriteFPUL_MADDSUB], (instregex "^FMSUB_(W|D)$")>; 483def : InstRW<[P5600WriteFPUDivS], (instregex "^FDIV_W$")>; 484def : InstRW<[P5600WriteFPUDivD], (instregex "^FDIV_D$")>; 485def : InstRW<[P5600WriteFPUSqrtS], (instregex "^FSQRT_W$")>; 486def : InstRW<[P5600WriteFPUSqrtD], (instregex "^FSQRT_D$")>; 487def : InstRW<[P5600WriteFPUL], (instregex "^FMUL_(W|D)$")>; 488def : InstRW<[P5600WriteFPUL], (instregex "^FADD_(W|D)$")>; 489def : InstRW<[P5600WriteFPUL], (instregex "^FSUB_(W|D)$")>; 490 491// dpadd_?.[bhwd], dpsub_?.[bhwd], dotp_?.[bhwd], msubv.[bhwd], maddv.[bhwd] 492// mulv.[bhwd]. 493def : InstRW<[P5600WriteMSALongInt], (instregex "^DPADD_(S|U)_[HWD]$")>; 494def : InstRW<[P5600WriteMSALongInt], (instregex "^DPSUB_(S|U)_[HWD]$")>; 495def : InstRW<[P5600WriteMSALongInt], (instregex "^DOTP_(S|U)_[HWD]$")>; 496def : InstRW<[P5600WriteMSALongInt], (instregex "^MSUBV_[BHWD]$")>; 497def : InstRW<[P5600WriteMSALongInt], (instregex "^MADDV_[BHWD]$")>; 498def : InstRW<[P5600WriteMSALongInt], (instregex "^MULV_[BHWD]$")>; 499 500def : InstRW<[P5600WriteMSALongInt], (instregex "^MADDR_Q_[HW]$")>; 501def : InstRW<[P5600WriteMSALongInt], (instregex "^MADD_Q_[HW]$")>; 502def : InstRW<[P5600WriteMSALongInt], (instregex "^MSUBR_Q_[HW]$")>; 503def : InstRW<[P5600WriteMSALongInt], (instregex "^MSUB_Q_[HW]$")>; 504def : InstRW<[P5600WriteMSALongInt], (instregex "^MULR_Q_[HW]$")>; 505def : InstRW<[P5600WriteMSALongInt], (instregex "^MUL_Q_[HW]$")>; 506 507// madd.[ds], msub.[ds], nmadd.[ds], nmsub.[ds], 508// Operand 0 is read on cycle 5. All other operands are read on operand 0. 509def : InstRW<[SchedReadAdvance<5>, P5600WriteFPUL_MADDSUB], 510 (instrs MADD_D32, MADD_D64, MADD_S, MSUB_D32, MSUB_D64, MSUB_S, 511 NMADD_D32, NMADD_D64, NMADD_S, NMSUB_D32, NMSUB_D64, NMSUB_S)>; 512 513// madd.ps, msub.ps, nmadd.ps, nmsub.ps 514// Operand 0 and 1 are read on cycle 5. All others are read on operand 0. 515// (none of these instructions exist in the backend yet) 516 517// Load Pipe 518// --------- 519// 520// This is typically used in conjunction with the load pipeline under the AGQ 521// All the instructions are in the 'Tricky Instructions' section. 522 523def P5600WriteLoadOtherUnitsToFPU : SchedWriteRes<[P5600IssueFPULoad]> { 524 let Latency = 4; 525} 526 527// Tricky Instructions 528// =================== 529// 530// These instructions are split across multiple uops (in different pipelines) 531// that must cooperate to complete the operation 532 533// FIXME: This isn't quite right since the implementation of WriteSequence 534// current aggregates the resources and ignores the exact cycle they are 535// used. 536def P5600WriteMoveGPRToFPU : WriteSequence<[P5600WriteMoveGPRToOtherUnits, 537 P5600WriteMoveOtherUnitsToFPU]>; 538 539// FIXME: This isn't quite right since the implementation of WriteSequence 540// current aggregates the resources and ignores the exact cycle they are 541// used. 542def P5600WriteMoveFPUToGPR : WriteSequence<[P5600WriteMoveFPUSToOtherUnits, 543 P5600WriteGPRFromBypass]>; 544 545// FIXME: This isn't quite right since the implementation of WriteSequence 546// current aggregates the resources and ignores the exact cycle they are 547// used. 548def P5600WriteStoreFPUS : WriteSequence<[P5600WriteMoveFPUSToOtherUnits, 549 P5600WriteStoreFromOtherUnits]>; 550 551// FIXME: This isn't quite right since the implementation of WriteSequence 552// current aggregates the resources and ignores the exact cycle they are 553// used. 554def P5600WriteStoreFPUL : WriteSequence<[P5600WriteMoveFPULToOtherUnits, 555 P5600WriteStoreFromOtherUnits]>; 556 557// FIXME: This isn't quite right since the implementation of WriteSequence 558// current aggregates the resources and ignores the exact cycle they are 559// used. 560def P5600WriteLoadFPU : WriteSequence<[P5600WriteLoadToOtherUnits, 561 P5600WriteLoadOtherUnitsToFPU]>; 562 563// ctc1, mtc1, mthc1 564def : InstRW<[P5600WriteMoveGPRToFPU], (instrs CTC1, MTC1, MTC1_D64, MTHC1_D32, 565 MTHC1_D64, BuildPairF64, 566 BuildPairF64_64)>; 567 568// copy.[su]_[bhwd] 569def : InstRW<[P5600WriteMoveFPUToGPR], (instregex "^COPY_U_[BHW]$")>; 570def : InstRW<[P5600WriteMoveFPUToGPR], (instregex "^COPY_S_[BHWD]$")>; 571 572// bc1[ft], cfc1, mfc1, mfhc1, movf, movt 573def : InstRW<[P5600WriteMoveFPUToGPR], (instrs BC1F, BC1FL, BC1T, BC1TL, CFC1, 574 MFC1, MFC1_D64, MFHC1_D32, MFHC1_D64, 575 MOVF_I, MOVT_I, ExtractElementF64, 576 ExtractElementF64_64)>; 577 578// swc1, swxc1, st.[bhwd] 579def : InstRW<[P5600WriteStoreFPUS], (instrs SDC1, SDC164, SDXC1, SDXC164, 580 SWC1, SWXC1, SUXC1, SUXC164)>; 581def : InstRW<[P5600WriteStoreFPUS], (instregex "^ST_[BHWD]$")>; 582def : InstRW<[P5600WriteStoreFPUS], (instrs ST_F16)>; 583 584// movn.[ds], movz.[ds] 585def : InstRW<[P5600WriteStoreFPUL], (instrs MOVN_I_D32, MOVN_I_D64, MOVN_I_S, 586 MOVZ_I_D32, MOVZ_I_D64, MOVZ_I_S)>; 587 588// l[dw]x?c1, ld.[bhwd] 589def : InstRW<[P5600WriteLoadFPU], (instrs LDC1, LDC164, LDXC1, LDXC164, 590 LWC1, LWXC1, LUXC1, LUXC164)>; 591def : InstRW<[P5600WriteLoadFPU], (instregex "LD_[BHWD]")>; 592def : InstRW<[P5600WriteLoadFPU], (instrs LD_F16)>; 593 594// Unsupported Instructions 595// ======================== 596// 597// The following instruction classes are never valid on P5600. 598// II_DADDIU, II_DADDU, II_DMFC1, II_DMTC1, II_DMULT, II_DMULTU, II_DROTR, 599// II_DROTR32, II_DROTRV, II_DDIV, II_DSLL, II_DSLL32, II_DSLLV, II_DSRA, 600// II_DSRA32, II_DSRAV, II_DSRL, II_DSRL32, II_DSRLV, II_DSUBU, II_DDIVU, 601// II_JALRC, II_LD, II_LD[LR], II_RESTORE, II_SAVE, II_SD, II_SDC1, II_SD[LR] 602// 603// The following instructions are never valid on P5600. 604// addq.ph, repl.ph, repl.qb, subq.ph, subu_s.qb 605// 606// Guesswork 607// ========= 608// 609// This section is largely temporary guesswork. 610 611// ceil.[lw].[ds], floor.[lw].[ds] 612// Reason behind guess: trunc.[lw].ds and the various cvt's are in FPUL 613def : InstRW<[P5600WriteFPUL], (instregex "^CEIL_(L|W)_(S|D32|D64)$")>; 614def : InstRW<[P5600WriteFPUL], (instregex "^FLOOR_(L|W)_(S|D32|D64)$")>; 615def : InstRW<[P5600WriteFPUL], (instregex "^ROUND_(L|W)_(S|D32|D64)$")>; 616 617// rotrv 618// Reason behind guess: rotr is in the same category and the two register forms 619// generally follow the immediate forms in this category 620def : InstRW<[P5600WriteEitherALU], (instrs ROTRV)>; 621 622// Atomic instructions 623 624// FIXME: Define `WriteAtomic` in the MipsSchedule.td and 625// attach it to the Atomic2OpsPostRA, AtomicCmpSwapPostRA, ... 626// classes. Then just define resources for the `WriteAtomic` in each 627// machine models. 628def P5600Atomic : ProcResource<1> { let BufferSize = 1; } 629def P5600WriteAtomic : SchedWriteRes<[P5600Atomic]> { let Latency = 2; } 630 631def : InstRW<[P5600WriteAtomic], 632 (instregex "^ATOMIC_SWAP_I(8|16|32|64)_POSTRA$")>; 633def : InstRW<[P5600WriteAtomic], 634 (instregex "^ATOMIC_CMP_SWAP_I(8|16|32|64)_POSTRA$")>; 635def : InstRW<[P5600WriteAtomic], 636 (instregex "^ATOMIC_LOAD_(ADD|SUB|AND|OR|XOR|NAND|MIN|MAX|UMIN|UMAX)" 637 "_I(8|16|32|64)_POSTRA$")>; 638} 639