1//=- MipsScheduleGeneric.td - Generic Scheduling Definitions -*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the interAptiv processor in a manner of speaking. It 10// describes a hypothetical version of the in-order MIPS32R2 interAptiv with all 11// branches of the MIPS ISAs, ASEs and ISA variants. The itinerary lists are 12// broken down into per ISA lists, so that this file can be used to rapidly 13// develop new schedule models. 14// 15//===----------------------------------------------------------------------===// 16def MipsGenericModel : SchedMachineModel { 17 int IssueWidth = 1; 18 int MicroOpBufferSize = 0; 19 20 // These figures assume an L1 hit. 21 int LoadLatency = 2; 22 int MispredictPenalty = 4; 23 24 int HighLatency = 37; 25 list<Predicate> UnsupportedFeatures = []; 26 27 let CompleteModel = 1; 28 let PostRAScheduler = 1; 29 30 // FIXME: Remove when all errors have been fixed. 31 let FullInstRWOverlapCheck = 1; 32} 33 34let SchedModel = MipsGenericModel in { 35 36// ALU Pipeline 37// ============ 38 39def GenericALU : ProcResource<1> { let BufferSize = 1; } 40def GenericIssueALU : ProcResource<1> { let Super = GenericALU; } 41 42def GenericWriteALU : SchedWriteRes<[GenericIssueALU]>; 43 44// add, addi, addiu, addu, and, andi, clo, clz, ext, ins, lui, nor, or, ori, 45// rotr, rotrv, seb, seh, sll, sllv, slt, slti, sltiu, sltu, sra, srav, srl, 46// srlv, ssnop, sub, subu, wsbh, xor, xori 47def : InstRW<[GenericWriteALU], (instrs ADD, ADDi, ADDiu, ADDu, AND, ANDi, 48 CLO, CLZ, EXT, INS, LEA_ADDiu, LUi, NOP, 49 NOR, OR, ORi, ROTR, ROTRV, SEB, SEH, SLL, 50 SLLV, SLT, SLTi, SLTiu, SLTu, SRA, SRAV, SRL, 51 SRLV, SSNOP, SUB, SUBu, WSBH, XOR, XORi)>; 52 53def : InstRW<[GenericWriteALU], (instrs COPY)>; 54 55// MIPSR6 56// ====== 57 58// addiupc, align, aluipc, aui, auipc, bitswap, clo, clz, lsa, seleqz, selnez 59def : InstRW<[GenericWriteALU], (instrs ADDIUPC, ALIGN, ALUIPC, AUI, 60 AUIPC, BITSWAP, CLO_R6, CLZ_R6, LSA_R6, 61 SELEQZ, SELNEZ)>; 62 63// MIPS16e 64// ======= 65 66def : InstRW<[GenericWriteALU], (instrs AddiuRxImmX16, AddiuRxRxImm16, 67 AddiuRxRxImmX16, AddiuRxRyOffMemX16, 68 AddiuRxPcImmX16, AddiuSpImm16, AddiuSpImmX16, 69 AdduRxRyRz16, AndRxRxRy16, CmpRxRy16, 70 CmpiRxImm16, CmpiRxImmX16, LiRxImm16, 71 LiRxImmX16, LiRxImmAlignX16, Move32R16, 72 MoveR3216, Mfhi16, Mflo16, NegRxRy16, 73 NotRxRy16, OrRxRxRy16, SebRx16, SehRx16, 74 SllX16, SllvRxRy16, SltiRxImm16, 75 SltiRxImmX16, SltiCCRxImmX16, 76 SltiuRxImm16, SltiuRxImmX16, SltiuCCRxImmX16, 77 SltRxRy16, SltCCRxRy16, SltuRxRy16, 78 SltuRxRyRz16, SltuCCRxRy16, SravRxRy16, 79 SraX16, SrlvRxRy16, SrlX16, SubuRxRyRz16, 80 XorRxRxRy16)>; 81 82def : InstRW<[GenericWriteALU], (instrs Constant32, LwConstant32, 83 GotPrologue16, CONSTPOOL_ENTRY)>; 84 85// microMIPS 86// ========= 87 88def : InstRW<[GenericWriteALU], (instrs ADDIUPC_MM, ADDIUR1SP_MM, ADDIUR2_MM, 89 ADDIUS5_MM, ADDIUSP_MM, ADDU16_MM, ADD_MM, 90 ADDi_MM, ADDiu_MM, ADDu_MM, AND16_MM, 91 ANDI16_MM, AND_MM, ANDi_MM, CLO_MM, CLZ_MM, 92 EXT_MM, INS_MM, LEA_ADDiu_MM, LI16_MM, 93 LUi_MM, MOVE16_MM, MOVEP_MM, NOR_MM, 94 NOT16_MM, OR16_MM, OR_MM, ORi_MM, ROTRV_MM, 95 ROTR_MM, SEB_MM, SEH_MM, SLL16_MM, SLLV_MM, 96 SLL_MM, SLT_MM, SLTi_MM, SLTiu_MM, SLTu_MM, 97 SRAV_MM, SRA_MM, SRL16_MM, SRLV_MM, SRL_MM, 98 SSNOP_MM, SUBU16_MM, SUB_MM, SUBu_MM, 99 WSBH_MM, XOR16_MM, XOR_MM, XORi_MM)>; 100 101// microMIPS32r6 102// ============= 103 104def : InstRW<[GenericWriteALU], (instrs ADDIUPC_MMR6, ADDIU_MMR6, ADDU16_MMR6, 105 ADDU_MMR6, ADD_MMR6, ALIGN_MMR6, ALUIPC_MMR6, 106 AND16_MMR6, ANDI16_MMR6, ANDI_MMR6, AND_MMR6, 107 AUIPC_MMR6, AUI_MMR6, BITSWAP_MMR6, CLO_MMR6, 108 CLZ_MMR6, EXT_MMR6, INS_MMR6, LI16_MMR6, 109 LSA_MMR6, LUI_MMR6, MOVE16_MMR6, NOR_MMR6, 110 NOT16_MMR6, OR16_MMR6, ORI_MMR6, OR_MMR6, 111 SELEQZ_MMR6, SELNEZ_MMR6, SLL16_MMR6, 112 SLL_MMR6, SRL16_MMR6, SSNOP_MMR6, SUBU16_MMR6, 113 SUBU_MMR6, SUB_MMR6, WSBH_MMR6, XOR16_MMR6, 114 XORI_MMR6, XOR_MMR6)>; 115 116// MIPS64 117// ====== 118 119def : InstRW<[GenericWriteALU], (instrs AND64, ANDi64, DEXT64_32, DSLL64_32, 120 ORi64, SEB64, SEH64, SLL64_32, SLL64_64, 121 SLT64, SLTi64, SLTiu64, SLTu64, XOR64, 122 XORi64)>; 123 124def : InstRW<[GenericWriteALU], (instrs DADD, DADDi, DADDiu, DADDu, DCLO, 125 DCLZ, DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, 126 DROTR, DROTR32, DROTRV, DSBH, DSHD, DSLL, 127 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, 128 DSRL32, DSRLV, DSUB, DSUBu, LEA_ADDiu64, 129 LUi64, NOR64, OR64)>; 130 131// MIPS64R6 132// ======== 133 134def : InstRW<[GenericWriteALU], (instrs DALIGN, DAHI, DATI, DAUI, DCLO_R6, 135 DCLZ_R6, DBITSWAP, DLSA, DLSA_R6, SELEQZ64, 136 SELNEZ64)>; 137 138 139def GenericMDU : ProcResource<1> { let BufferSize = 1; } 140def GenericIssueMDU : ProcResource<1> { let Super = GenericALU; } 141def GenericIssueDIV : ProcResource<1> { let Super = GenericMDU; } 142def GenericWriteHILO : SchedWriteRes<[GenericIssueMDU]>; 143def GenericWriteALULong : SchedWriteRes<[GenericIssueALU]> { let Latency = 5; } 144def GenericWriteMove : SchedWriteRes<[GenericIssueALU]> { let Latency = 2; } 145def GenericWriteMul : SchedWriteRes<[GenericIssueMDU]> { let Latency = 4; } 146 147def : InstRW<[GenericWriteHILO], (instrs MADD, MADDU, MSUB, MSUBU)>; 148 149def : InstRW<[GenericWriteHILO], (instrs PseudoMADD_MM, PseudoMADDU_MM, 150 PseudoMSUB_MM, PseudoMSUBU_MM, 151 PseudoMULT_MM, PseudoMULTu_MM)>; 152 153def : InstRW<[GenericWriteHILO], (instrs PseudoMADD, PseudoMADDU, PseudoMSUB, 154 PseudoMSUBU, PseudoMULT, PseudoMULTu)>; 155 156def GenericWriteMDUtoGPR : SchedWriteRes<[GenericIssueMDU]> { 157 let Latency = 5; 158} 159 160def GenericWriteDIV : SchedWriteRes<[GenericIssueDIV]> { 161 // Estimated worst case 162 let Latency = 33; 163 let ResourceCycles = [33]; 164} 165def GenericWriteDIVU : SchedWriteRes<[GenericIssueDIV]> { 166 // Estimated worst case 167 let Latency = 31; 168 let ResourceCycles = [31]; 169} 170 171// mul 172def : InstRW<[GenericWriteMDUtoGPR], (instrs MUL)>; 173 174// mult, multu 175def : InstRW<[GenericWriteMul], (instrs MULT, MULTu)>; 176 177// div, sdiv 178def : InstRW<[GenericWriteDIV], (instrs PseudoSDIV, SDIV)>; 179 180def : InstRW<[GenericWriteDIVU], (instrs PseudoUDIV, UDIV)>; 181 182// mfhi, mflo, movn, mthi, mtlo, rdwhr 183def : InstRW<[GenericWriteALULong], (instrs MFHI, MFLO, PseudoMFHI, 184 PseudoMFLO)>; 185 186def : InstRW<[GenericWriteALULong], (instrs PseudoMFHI_MM, PseudoMFLO_MM)>; 187 188def : InstRW<[GenericWriteMove], (instrs MTHI, MTLO, RDHWR, PseudoMTLOHI)>; 189def : InstRW<[GenericWriteMove], (instrs PseudoMTLOHI_MM)>; 190 191def : InstRW<[GenericWriteALU], (instrs MOVN_I_I, MOVZ_I_I)>; 192 193// MIPSR6 194// ====== 195 196// muh, muhu, mulu, mul 197def : InstRW<[GenericWriteMul], (instrs MUH, MUHU, MULU, MUL_R6)>; 198 199// divu, udiv 200def : InstRW<[GenericWriteDIV], (instrs MOD, MODU, DIV, DIVU)>; 201 202 203// MIPS16e 204// ======= 205 206def : InstRW<[GenericWriteHILO], (instrs MultRxRy16, MultuRxRy16, 207 MultRxRyRz16, MultuRxRyRz16)>; 208 209def : InstRW<[GenericWriteDIV], (instrs DivRxRy16)>; 210 211def : InstRW<[GenericWriteDIVU], (instrs DivuRxRy16)>; 212 213// microMIPS 214// ========= 215 216def : InstRW<[GenericWriteMul], (instrs MULT_MM, MULTu_MM, MADD_MM, MADDU_MM, 217 MSUB_MM, MSUBU_MM)>; 218 219def : InstRW<[GenericWriteALULong], (instrs MUL_MM)>; 220 221def : InstRW<[GenericWriteDIV], (instrs SDIV_MM, SDIV_MM_Pseudo)>; 222 223def : InstRW<[GenericWriteDIVU], (instrs UDIV_MM, UDIV_MM_Pseudo)>; 224 225def : InstRW<[GenericWriteMove], (instrs MFHI16_MM, MFLO16_MM, MOVF_I_MM, 226 MOVT_I_MM, MFHI_MM, MFLO_MM, MTHI_MM, 227 MTLO_MM)>; 228 229def : InstRW<[GenericWriteMove], (instrs RDHWR_MM)>; 230 231// microMIPS32r6 232// ============= 233 234def : InstRW<[GenericWriteMul], (instrs MUHU_MMR6, MUH_MMR6, MULU_MMR6, 235 MUL_MMR6)>; 236 237def : InstRW<[GenericWriteDIV], (instrs MODU_MMR6, MOD_MMR6, DIVU_MMR6, 238 DIV_MMR6)>; 239 240def : InstRW<[GenericWriteMove], (instrs RDHWR_MMR6)>; 241 242// MIPS64 243// ====== 244 245def : InstRW<[GenericWriteHILO], (instrs DMULU, DMULT, DMULTu, PseudoDMULT, 246 PseudoDMULTu)>; 247 248def : InstRW<[GenericWriteDIV], (instrs DSDIV, PseudoDSDIV)>; 249 250def : InstRW<[GenericWriteDIVU], (instrs DUDIV, PseudoDUDIV)>; 251 252def : InstRW<[GenericWriteALULong], (instrs MFHI64, MFLO64, PseudoMFHI64, 253 PseudoMFLO64, PseudoMTLOHI64)>; 254 255def : InstRW<[GenericWriteMove], (instrs MTHI64, MTLO64, RDHWR64)>; 256 257// mov[zn] 258def : InstRW<[GenericWriteALU], (instrs MOVN_I_I64, MOVN_I64_I, MOVN_I64_I64, 259 MOVZ_I_I64, MOVZ_I64_I, MOVZ_I64_I64)>; 260 261 262// MIPS64R6 263// ======== 264 265def : InstRW<[GenericWriteMDUtoGPR], (instrs DMUH, DMUHU, DMUL_R6)>; 266 267def : InstRW<[GenericWriteDIV], (instrs DDIV, DMOD)>; 268 269def : InstRW<[GenericWriteDIVU], (instrs DDIVU, DMODU)>; 270 271// CTISTD Pipeline 272// --------------- 273 274def GenericIssueCTISTD : ProcResource<1> { let Super = GenericALU; } 275 276def GenericLDST : ProcResource<1> { let BufferSize = 1; } 277def GenericIssueLDST : ProcResource<1> { let Super = GenericLDST; } 278 279def GenericWriteJump : SchedWriteRes<[GenericIssueCTISTD]>; 280def GenericWriteJumpAndLink : SchedWriteRes<[GenericIssueCTISTD]> { 281 let Latency = 2; 282} 283 284// b, beq, beql, bg[et]z, bl[et]z, bne, bnel, j, syscall, jal, bltzal, jalx, 285// jalr, jr.hb, jr, jalr.hb, jarlc, jialc 286def : InstRW<[GenericWriteJump], (instrs B, BAL, BAL_BR, BEQ, BNE, BGTZ, BGEZ, 287 BLEZ, BLTZ, BLTZAL, J, JALX, JR, JR_HB, ERET, 288 ERet, ERETNC, DERET)>; 289 290def : InstRW<[GenericWriteJump], (instrs BEQL, BNEL, BGEZL, BGTZL, BLEZL, 291 BLTZL)>; 292 293def : InstRW<[GenericWriteJump], (instrs TAILCALL, TAILCALLREG, 294 TAILCALLREGHB, PseudoIndirectBranch, 295 PseudoIndirectHazardBranch, PseudoReturn, 296 RetRA)>; 297 298def : InstRW<[GenericWriteJumpAndLink], (instrs BGEZAL, JAL, JALR, JALR_HB, 299 JALRHBPseudo, JALRPseudo)>; 300 301def : InstRW<[GenericWriteJumpAndLink], (instrs BGEZALL, BLTZALL)>; 302 303def GenericWriteTrap : SchedWriteRes<[GenericIssueCTISTD]>; 304 305def : InstRW<[GenericWriteTrap], (instrs BREAK, SYSCALL, TEQ, TEQI, 306 TGE, TGEI, TGEIU, TGEU, TNE, 307 TNEI, TLT, TLTI, TLTU, TTLTIU, 308 TRAP, SDBBP)>; 309 310// MIPSR6 311// ====== 312 313def : InstRW<[GenericWriteJumpAndLink], (instrs BALC, BEQZALC, BGEZALC, 314 BGTZALC, BLEZALC, BLTZALC, 315 BNEZALC, 316 JIALC)>; 317 318def : InstRW<[GenericWriteJump], (instrs BC, BC2EQZ, BC2NEZ, BEQC, BEQZC, BGEC, 319 BGEUC, BGEZC, BGTZC, BLEZC, BLTC, BLTUC, 320 BLTZC, BNEC, BNEZC, BNVC, BOVC, JIC, JR_HB_R6, 321 SIGRIE, PseudoIndirectBranchR6, 322 PseudoIndrectHazardBranchR6)>; 323 324def : InstRW<[GenericWriteJump], (instrs TAILCALLR6REG, TAILCALLHBR6REG)>; 325 326def : InstRW<[GenericWriteTrap], (instrs SDBBP_R6)>; 327 328// MIPS16e 329// ======= 330 331def : InstRW<[GenericWriteJump], (instrs Bimm16, BimmX16, BeqzRxImm16, 332 BeqzRxImmX16, BnezRxImm16, BnezRxImmX16, 333 Bteqz16, BteqzX16, BteqzT8CmpX16, 334 BteqzT8CmpiX16, BteqzT8SltX16, 335 BteqzT8SltuX16, BteqzT8SltiX16, 336 BteqzT8SltiuX16, Btnez16, BtnezX16, 337 BtnezT8CmpX16, BtnezT8CmpiX16, 338 BtnezT8SltX16, BtnezT8SltuX16, 339 BtnezT8SltiX16, BtnezT8SltiuX16, JrRa16, 340 JrcRa16, JrcRx16, RetRA16)>; 341 342def : InstRW<[GenericWriteJumpAndLink], (instrs Jal16, JalB16, JumpLinkReg16)>; 343 344def : InstRW<[GenericWriteTrap], (instrs Break16)>; 345 346def : InstRW<[GenericWriteALULong], (instrs SelBeqZ, SelTBteqZCmp, 347 SelTBteqZCmpi, SelTBteqZSlt, 348 SelTBteqZSlti, SelTBteqZSltu, 349 SelTBteqZSltiu, SelBneZ, SelTBtneZCmp, 350 SelTBtneZCmpi, SelTBtneZSlt, 351 SelTBtneZSlti, SelTBtneZSltu, 352 SelTBtneZSltiu)>; 353 354// microMIPS 355// ========= 356 357def : InstRW<[GenericWriteJump], (instrs B16_MM, BAL_BR_MM, BC1F_MM, BC1T_MM, 358 BEQZ16_MM, BEQZC_MM, BEQ_MM, BGEZ_MM, 359 BGTZ_MM, BLEZ_MM, BLTZ_MM, BNEZ16_MM, 360 BNEZC_MM, BNE_MM, B_MM, DERET_MM, ERET_MM, 361 JR16_MM, JR_MM, J_MM, B_MM_Pseudo)>; 362 363def : InstRW<[GenericWriteJumpAndLink], (instrs BGEZALS_MM, BGEZAL_MM, 364 BLTZALS_MM, BLTZAL_MM, JALR16_MM, 365 JALRS16_MM, JALRS_MM, JALR_MM, 366 JALS_MM, JALX_MM, JAL_MM)>; 367 368def : InstRW<[GenericWriteJump], (instrs TAILCALLREG_MM, TAILCALL_MM, 369 PseudoIndirectBranch_MM)>; 370 371def : InstRW<[GenericWriteTrap], (instrs BREAK16_MM, BREAK_MM, SDBBP16_MM, 372 SDBBP_MM, SYSCALL_MM, TEQI_MM, TEQ_MM, 373 TGEIU_MM, TGEI_MM, TGEU_MM, TGE_MM, TLTIU_MM, 374 TLTI_MM, TLTU_MM, TLT_MM, TNEI_MM, TNE_MM, 375 TRAP_MM)>; 376 377// microMIPS32r6 378// ============= 379 380def : InstRW<[GenericWriteJump], (instrs BC16_MMR6, BC1EQZC_MMR6, BC1NEZC_MMR6, 381 BC2EQZC_MMR6, BC2NEZC_MMR6, BC_MMR6, 382 BEQC_MMR6, BEQZC16_MMR6, BEQZC_MMR6, 383 BGEC_MMR6, BGEUC_MMR6, BGEZC_MMR6, 384 BGTZC_MMR6, BLEZC_MMR6, BLTC_MMR6, 385 BLTUC_MMR6, BLTZC_MMR6, BNEC_MMR6, 386 BNEZC16_MMR6, BNEZC_MMR6, BNVC_MMR6, 387 BOVC_MMR6, DERET_MMR6, ERETNC_MMR6, JAL_MMR6, 388 ERET_MMR6, JIC_MMR6, JRADDIUSP, JRC16_MM, 389 JRC16_MMR6, JRCADDIUSP_MMR6, SIGRIE_MMR6, 390 B_MMR6_Pseudo, PseudoIndirectBranch_MMR6)>; 391 392def : InstRW<[GenericWriteJumpAndLink], (instrs BALC_MMR6, BEQZALC_MMR6, 393 BGEZALC_MMR6, BGTZALC_MMR6, 394 BLEZALC_MMR6, BLTZALC_MMR6, 395 BNEZALC_MMR6, JALRC16_MMR6, 396 JALRC_HB_MMR6, JALRC_MMR6, 397 JIALC_MMR6)>; 398 399def : InstRW<[GenericWriteJump], (instrs TAILCALLREG_MMR6, TAILCALL_MMR6)>; 400 401def : InstRW<[GenericWriteTrap], (instrs BREAK16_MMR6, BREAK_MMR6, SDBBP_MMR6, 402 SDBBP16_MMR6)>; 403 404// MIPS64 405// ====== 406 407def : InstRW<[GenericWriteJump], (instrs BEQ64, BGEZ64, BGTZ64, BLEZ64, 408 BLTZ64, BNE64, JR64)>; 409 410def : InstRW<[GenericWriteJumpAndLink], (instrs JALR64, JALR64Pseudo, 411 JALRHB64Pseudo, JALR_HB64)>; 412 413def : InstRW<[GenericWriteJump], (instrs JR_HB64, TAILCALLREG64, 414 TAILCALLREGHB64, PseudoReturn64)>; 415 416// MIPS64R6 417// ======== 418 419def : InstRW<[GenericWriteJump], (instrs BEQC64, BEQZC64, BGEC64, BGEUC64, 420 BGEZC64, BGTZC64, BLEZC64, BLTC64, BLTUC64, 421 BLTZC64, BNEC64, BNEZC64, JIC64, 422 PseudoIndirectBranch64, 423 PseudoIndirectHazardBranch64)>; 424 425def : InstRW<[GenericWriteJumpAndLink], (instrs JIALC64)>; 426 427def : InstRW<[GenericWriteJump], (instrs JR_HB64_R6, TAILCALL64R6REG, 428 TAILCALLHB64R6REG, PseudoIndirectBranch64R6, 429 PseudoIndrectHazardBranch64R6)>; 430 431// COP0 Pipeline 432// ============= 433 434def GenericCOP0 : ProcResource<1> { let BufferSize = 1; } 435 436def GenericIssueCOP0 : ProcResource<1> { let Super = GenericCOP0; } 437def GenericWriteCOP0TLB : SchedWriteRes<[GenericIssueCOP0]> { let Latency = 4; } 438def GenericWriteCOP0 : SchedWriteRes<[GenericIssueCOP0]> { let Latency = 3; } 439def GenericReadCOP0 : SchedWriteRes<[GenericIssueCOP0]> { let Latency = 2; } 440def GenericReadWritePGPR : SchedWriteRes<[GenericIssueCOP0]>; 441def GenericReadWriteCOP0Long : SchedWriteRes<[GenericIssueCOP0]> { 442 let Latency = 5; 443} 444def GenericWriteCOP0Short : SchedWriteRes<[GenericIssueCOP0]>; 445 446def : InstRW<[GenericWriteCOP0TLB], (instrs TLBP, TLBR, TLBWI, TLBWR)>; 447def : InstRW<[GenericWriteCOP0TLB], (instrs TLBINV, TLBINVF)>; 448 449def : InstRW<[GenericReadCOP0], (instrs MFC0)>; 450def : InstRW<[GenericWriteCOP0], (instrs MTC0)>; 451 452def : InstRW<[GenericWriteCOP0], (instrs EVP, DVP)>; 453 454def : InstRW<[GenericWriteCOP0], (instrs DI, EI)>; 455 456def : InstRW<[GenericWriteCOP0], (instrs EHB, PAUSE, WAIT)>; 457 458// microMIPS 459// ========= 460 461def : InstRW<[GenericWriteCOP0TLB], (instrs TLBP_MM, TLBR_MM, TLBWI_MM, 462 TLBWR_MM)>; 463 464def : InstRW<[GenericWriteCOP0], (instrs DI_MM, EI_MM)>; 465 466def : InstRW<[GenericWriteCOP0], (instrs EHB_MM, PAUSE_MM, WAIT_MM)>; 467 468 469// microMIPS32R6 470// ============= 471 472def : InstRW<[GenericWriteCOP0], (instrs RDPGPR_MMR6, WRPGPR_MMR6)>; 473 474def : InstRW<[GenericWriteCOP0TLB], (instrs TLBINV_MMR6, TLBINVF_MMR6)>; 475 476def : InstRW<[GenericReadCOP0], (instrs MFHC0_MMR6, MFC0_MMR6, MFHC2_MMR6, 477 MFC2_MMR6)>; 478 479def : InstRW<[GenericWriteCOP0], (instrs MTHC0_MMR6, MTC0_MMR6, MTHC2_MMR6, 480 MTC2_MMR6)>; 481 482def : InstRW<[GenericWriteCOP0], (instrs EVP_MMR6, DVP_MMR6)>; 483 484def : InstRW<[GenericWriteCOP0], (instrs DI_MMR6, EI_MMR6)>; 485 486def : InstRW<[GenericWriteCOP0], (instrs EHB_MMR6, PAUSE_MMR6, WAIT_MMR6)>; 487 488// MIPS64 489// ====== 490 491def : InstRW<[GenericReadCOP0], (instrs DMFC0)>; 492 493def : InstRW<[GenericWriteCOP0], (instrs DMTC0)>; 494 495 496def GenericCOP2 : ProcResource<1> { let BufferSize = 1; } 497def GenericWriteCOPOther : SchedWriteRes<[GenericCOP2]>; 498 499def : InstRW<[GenericWriteCOPOther], (instrs MFC2, MTC2)>; 500 501def : InstRW<[GenericWriteCOPOther], (instrs DMFC2, DMTC2)>; 502 503// microMIPS32R6 504// ============= 505 506// The latency and repeat rate of these instructions are implementation 507// dependant. 508def : InstRW<[GenericWriteMove], (instrs CFC2_MM, CTC2_MM)>; 509 510 511// MIPS MT ASE - hasMT 512// ==================== 513 514def : InstRW<[GenericWriteMove], (instrs DMT, DVPE, EMT, EVPE, MFTR, 515 MTTR)>; 516 517def : InstRW<[GenericReadWriteCOP0Long], (instrs YIELD)>; 518 519def : InstRW<[GenericWriteCOP0Short], (instrs FORK)>; 520 521// MIPS Virtualization ASE 522// ======================= 523 524def : InstRW<[GenericWriteCOP0Short], (instrs HYPCALL, TLBGINV, TLBGINVF, TLBGP, 525 TLBGR, TLBGWI, TLBGWR, MFGC0, MFHGC0, 526 MTGC0, MTHGC0)>; 527 528// MIPS64 Virtualization ASE 529// ========================= 530 531def : InstRW<[GenericWriteCOP0Short], (instrs DMFGC0, DMTGC0)>; 532 533// microMIPS virtualization ASE 534// ============================ 535 536def : InstRW<[GenericWriteCOP0Short], (instrs HYPCALL_MM, TLBGINVF_MM, 537 TLBGINV_MM, TLBGP_MM, TLBGR_MM, 538 TLBGWI_MM, TLBGWR_MM, MFGC0_MM, 539 MFHGC0_MM, MTGC0_MM, MTHGC0_MM)>; 540 541// LDST Pipeline 542// ------------- 543 544def GenericWriteLoad : SchedWriteRes<[GenericIssueLDST]> { 545 let Latency = 2; 546} 547 548def GenericWritePref : SchedWriteRes<[GenericIssueLDST]>; 549def GenericWriteSync : SchedWriteRes<[GenericIssueLDST]>; 550def GenericWriteCache : SchedWriteRes<[GenericIssueLDST]> { let Latency = 5; } 551 552def GenericWriteStore : SchedWriteRes<[GenericIssueLDST]>; 553def GenericWriteStoreSC : SchedWriteRes<[GenericIssueLDST]> { let Latency = 2; } 554 555def GenericWriteGPRFromBypass : SchedWriteRes<[GenericIssueLDST]> { 556 let Latency = 2; 557} 558 559def GenericWriteStoreFromOtherUnits : SchedWriteRes<[GenericIssueLDST]>; 560def GenericWriteLoadToOtherUnits : SchedWriteRes<[GenericIssueLDST]> { 561 let Latency = 0; 562} 563 564// l[bhw], l[bh]u, ll 565def : InstRW<[GenericWriteLoad], (instrs LB, LBu, LH, LHu, LW, LL, 566 LWC2, LWC3, LDC2, LDC3)>; 567 568// lw[lr] 569def : InstRW<[GenericWriteLoad], (instrs LWL, LWR)>; 570 571// s[bhw], sc, s[dw]c[23] 572def : InstRW<[GenericWriteStore], (instrs SB, SH, SW, SWC2, SWC3, 573 SDC2, SDC3)>; 574 575// PreMIPSR6 sw[lr] 576def : InstRW<[GenericWriteStore], (instrs SWL, SWR)>; 577 578def : InstRW<[GenericWriteStoreSC], (instrs SC, SC_MMR6)>; 579 580// pref 581def : InstRW<[GenericWritePref], (instrs PREF)>; 582// cache 583def : InstRW<[GenericWriteCache], (instrs CACHE)>; 584 585// sync 586def : InstRW<[GenericWriteSync], (instrs SYNC, SYNCI)>; 587 588// MIPSR6 589// ====== 590 591def : InstRW<[GenericWriteLoad], (instrs LDC2_R6, LL_R6, LWC2_R6, LWPC)>; 592 593def : InstRW<[GenericWriteStore], (instrs SWC2_R6, SDC2_R6)>; 594 595def : InstRW<[GenericWriteStoreSC], (instrs SC_R6)>; 596 597def : InstRW<[GenericWritePref], (instrs PREF_R6)>; 598 599def : InstRW<[GenericWriteCache], (instrs CACHE_R6)>; 600 601def : InstRW<[GenericWriteSync], (instrs GINVI, GINVT)>; 602 603// MIPS32 EVA 604// ========== 605 606def : InstRW<[GenericWriteLoad], (instrs LBE, LBuE, LHE, LHuE, LWE, 607 LLE)>; 608 609def : InstRW<[GenericWriteStore], (instrs SBE, SHE, SWE, SCE)>; 610 611def : InstRW<[GenericWriteLoad], (instrs LWLE, LWRE)>; 612 613def : InstRW<[GenericWriteStore], (instrs SWLE, SWRE)>; 614 615def : InstRW<[GenericWritePref], (instrs PREFE)>; 616 617def : InstRW<[GenericWriteCache], (instrs CACHEE)>; 618 619// microMIPS EVA ASE - InMicroMipsMode, hasEVA 620// =========================================== 621 622def : InstRW<[GenericWriteLoad], (instrs LBE_MM, LBuE_MM, LHE_MM, LHuE_MM, 623 LWE_MM, LWLE_MM, LWRE_MM, LLE_MM)>; 624 625def : InstRW<[GenericWriteStore], (instrs SBE_MM, SB_MM, SHE_MM, SWE_MM, 626 SWLE_MM, SWRE_MM, SCE_MM)>; 627 628def : InstRW<[GenericWritePref], (instrs PREFE_MM)>; 629def : InstRW<[GenericWriteCache], (instrs CACHEE_MM)>; 630 631 632// MIPS16e 633// ======= 634 635def : InstRW<[GenericWriteLoad], (instrs Restore16, RestoreX16, 636 LbRxRyOffMemX16, 637 LbuRxRyOffMemX16, LhRxRyOffMemX16, 638 LhuRxRyOffMemX16, LwRxRyOffMemX16, 639 LwRxSpImmX16, LwRxPcTcp16, LwRxPcTcpX16)>; 640 641def : InstRW<[GenericWriteStore], (instrs Save16, SaveX16, SbRxRyOffMemX16, 642 ShRxRyOffMemX16, SwRxRyOffMemX16, 643 SwRxSpImmX16)>; 644 645// microMIPS 646// ========= 647 648def : InstRW<[GenericWriteLoad], (instrs LBU16_MM, LB_MM, LBu_MM, LHU16_MM, 649 LH_MM, LHu_MM, LL_MM, LW16_MM, LWGP_MM, 650 LWL_MM, LWM16_MM, LWM32_MM, LWP_MM, LWR_MM, 651 LWSP_MM, LWU_MM, LWXS_MM, LW_MM)>; 652 653def : InstRW<[GenericWriteStore], (instrs SB16_MM, SC_MM, SH16_MM, SH_MM, 654 SW16_MM, SWL_MM, SWM16_MM, SWM32_MM, SWM_MM, 655 SWP_MM, SWR_MM, SWSP_MM, SW_MM)>; 656 657 658def : InstRW<[GenericWritePref], (instrs PREF_MM, PREFX_MM)>; 659 660def : InstRW<[GenericWriteCache], (instrs CACHE_MM)>; 661 662def : InstRW<[GenericWriteSync], (instrs SYNC_MM, SYNCI_MM)>; 663def : InstRW<[GenericWriteSync], (instrs GINVI_MMR6, GINVT_MMR6)>; 664 665// microMIPS32r6 666// ============= 667 668def : InstRW<[GenericWriteLoad], (instrs LBU_MMR6, LB_MMR6, LDC2_MMR6, LL_MMR6, 669 LWM16_MMR6, LWC2_MMR6, LWPC_MMR6, LW_MMR6)>; 670 671def : InstRW<[GenericWriteStore], (instrs SB16_MMR6, SB_MMR6, SDC2_MMR6, 672 SH16_MMR6, SH_MMR6, SW16_MMR6, SWC2_MMR6, 673 SWM16_MMR6, SWSP_MMR6, SW_MMR6)>; 674 675def : InstRW<[GenericWriteSync], (instrs SYNC_MMR6, SYNCI_MMR6)>; 676 677def : InstRW<[GenericWritePref], (instrs PREF_MMR6)>; 678 679def : InstRW<[GenericWriteCache], (instrs CACHE_MMR6)>; 680 681// MIPS64 682// ====== 683 684def : InstRW<[GenericWriteLoad], (instrs LD, LL64, LLD, LWu, LB64, LBu64, 685 LH64, LHu64, LW64)>; 686 687// l[dw][lr] 688def : InstRW<[GenericWriteLoad], (instrs LWL64, LWR64, LDL, LDR)>; 689 690def : InstRW<[GenericWriteStore], (instrs SD, SC64, SCD, SB64, SH64, SW64, 691 SWL64, SWR64)>; 692 693def : InstRW<[GenericWriteStore], (instrs SDL, SDR)>; 694 695// MIPS64R6 696// ======== 697 698def : InstRW<[GenericWriteLoad], (instrs LWUPC, LDPC)>; 699 700def : InstRW<[GenericWriteLoad], (instrs LLD_R6, LL64_R6)>; 701 702def : InstRW<[GenericWriteStoreSC], (instrs SC64_R6, SCD_R6)>; 703 704// MIPSR6 CRC ASE - hasCRC 705// ======================= 706 707def : InstRW<[GenericWriteALU], (instrs CRC32B, CRC32H, CRC32W, CRC32CB, 708 CRC32CH, CRC32CW)>; 709 710// MIPS64R6 CRC ASE - hasCRC 711// ------------------------- 712 713def : InstRW<[GenericWriteALU], (instrs CRC32D, CRC32CD)>; 714 715 716// Cavium Networks MIPS (cnMIPS) - Octeon, HasCnMips 717// ================================================= 718 719def : InstRW<[GenericWriteALU], (instrs BADDu, BBIT0, BBIT032, BBIT1, BBIT132, 720 CINS, CINS32, CINS64_32, CINS_i32, 721 DMFC2_OCTEON, DMTC2_OCTEON, DPOP, EXTS, 722 EXTS32, MTM0, MTM1, MTM2, MTP0, MTP1, MTP2, 723 POP, SEQ, SEQi, SNE, SNEi, 724 V3MULU, VMM0, VMULU)>; 725 726def : InstRW<[GenericWriteMDUtoGPR], (instrs DMUL)>; 727 728// Cavium Networks MIPS (cnMIPSP) - Octeon+, HasCnMipsP 729// ================================================= 730 731def : InstRW<[GenericWriteALU], (instrs SAA, SAAD)>; 732 733// FPU Pipelines 734// ============= 735 736def GenericFPQ : ProcResource<1> { let BufferSize = 1; } 737def GenericIssueFPUS : ProcResource<1> { let Super = GenericFPQ; } 738def GenericIssueFPUL : ProcResource<1> { let Super = GenericFPQ; } 739def GenericIssueFPULoad : ProcResource<1> { let Super = GenericFPQ; } 740def GenericIssueFPUStore : ProcResource<1> { let Super = GenericFPQ; } 741def GenericIssueFPUMove : ProcResource<1> { let Super = GenericFPQ; } 742def GenericFPUDivSqrt : ProcResource<1> { let Super = GenericFPQ; } 743 744// The floating point compare of the 24k series including interAptiv has a 745// listed latency of 1-2. Using the higher latency here. 746 747def GenericWriteFPUCmp : SchedWriteRes<[GenericIssueFPUS]> { let Latency = 2; } 748def GenericWriteFPUS : SchedWriteRes<[GenericIssueFPUS]> { let Latency = 4; } 749def GenericWriteFPUL : SchedWriteRes<[GenericIssueFPUL]> { let Latency = 5; } 750def GenericWriteFPUStore : SchedWriteRes<[GenericIssueFPUStore]> { let 751 Latency = 1; 752} 753def GenericWriteFPULoad : SchedWriteRes<[GenericIssueFPULoad]> { 754 let Latency = 2; 755} 756def GenericWriteFPUMoveFP : SchedWriteRes<[GenericIssueFPUMove]> { 757 let Latency = 4; 758} 759def GenericWriteFPUMoveGPRFPU : SchedWriteRes<[GenericIssueFPUMove]> { 760 let Latency = 2; 761} 762def GenericWriteFPUDivS : SchedWriteRes<[GenericFPUDivSqrt]> { 763 let Latency = 17; 764 let ResourceCycles = [ 14 ]; 765} 766def GenericWriteFPUDivD : SchedWriteRes<[GenericFPUDivSqrt]> { 767 let Latency = 32; 768 let ResourceCycles = [ 29 ]; 769} 770def GenericWriteFPURcpS : SchedWriteRes<[GenericFPUDivSqrt]> { 771 let Latency = 13; 772 let ResourceCycles = [ 10 ]; 773} 774def GenericWriteFPURcpD : SchedWriteRes<[GenericFPUDivSqrt]> { 775 let Latency = 25; 776 let ResourceCycles = [ 21 ]; 777} 778def GenericWriteFPURsqrtS : SchedWriteRes<[GenericFPUDivSqrt]> { 779 let Latency = 17; 780 let ResourceCycles = [ 14 ]; 781} 782def GenericWriteFPURsqrtD : SchedWriteRes<[GenericFPUDivSqrt]> { 783 let Latency = 32; 784 let ResourceCycles = [ 29 ]; 785} 786def GenericWriteFPUSqrtS : SchedWriteRes<[GenericFPUDivSqrt]> { 787 let Latency = 17; 788 let ResourceCycles = [ 14 ]; 789} 790def GenericWriteFPUSqrtD : SchedWriteRes<[GenericFPUDivSqrt]> { 791 let Latency = 29; 792 let ResourceCycles = [ 29 ]; 793} 794 795// Floating point compare and branch 796// --------------------------------- 797// 798// c.<cc>.[ds], bc1[tf], bc1[tf]l 799def : InstRW<[GenericWriteFPUCmp], (instrs FCMP_D32, FCMP_D64, FCMP_S32, BC1F, 800 BC1T, BC1FL, BC1TL)>; 801 802def : InstRW<[GenericWriteFPUCmp], (instregex "C_[A-Z]+_(S|D32|D64)$")>; 803 804// Short Pipe 805// ---------- 806// 807// abs.[ds], abs.ps, add.[ds], neg.[ds], neg.ps, madd.s, msub.s, nmadd,s 808// nmsub.s, sub.[ds], mul.s 809 810def : InstRW<[GenericWriteFPUS], (instrs FABS_S, FABS_D32, FABS_D64, FADD_D32, 811 FADD_D64, FADD_S, MADD_S, MSUB_S, FMUL_S, 812 FNEG_S, FNEG_D32, FNEG_D64, NMADD_S, NMSUB_S, 813 FSUB_S, FSUB_D32, FSUB_D64)>; 814 815// Long Pipe 816// ---------- 817// 818// nmadd.d, nmsub.d, mul.[ds], mul.ps, ceil.[wl].[sd], cvt.d.[sw], cvt.s.[dw], 819// cvt.w.[sd], cvt.[sw].ps, trunc.w.[ds], trunc.w.ps, floor.[ds], 820// round.[lw].[ds], floor.[lw].ds 821 822// madd.d, msub.dm mul.d, mul.ps, nmadd.d, nmsub.d, ceil.[wl].[sd], cvt.d.[sw], 823// cvt.s.[dw], cvt.w.[sd], cvt.[sw].ps, round.[lw].[ds], floor.[lw].ds, 824// trunc.w.[ds], trunc.w.ps, 825def : InstRW<[GenericWriteFPUL], (instrs ADDR_PS64, 826 CEIL_L_D64, CEIL_L_S, CEIL_W_D32, 827 CEIL_W_D64, CEIL_W_S, CVT_D32_S, CVT_D32_W, 828 CVT_D64_L, CVT_D64_S, CVT_D64_W, CVT_L_D64, 829 CVT_L_S, CVT_S_D32, CVT_S_D64, CVT_S_L, 830 CVT_S_W, CVT_W_D32, CVT_W_D64, CVT_W_S, 831 CVT_PS_S64, CVT_S_PL64, CVT_S_PU64, 832 CVT_PS_PW64, CVT_PW_PS64, 833 FLOOR_L_D64, FLOOR_L_S, FLOOR_W_D32, 834 FLOOR_W_D64, FLOOR_W_S, FMUL_D32, FMUL_D64, 835 MADD_D32, MADD_D64, MSUB_D32, MSUB_D64, MULR_PS64, 836 NMADD_D32, NMADD_D64, NMSUB_D32, NMSUB_D64, 837 PLL_PS64, PLU_PS64, PUL_PS64, PUU_PS64, 838 ROUND_L_D64, ROUND_L_S, ROUND_W_D32, 839 ROUND_W_D64, ROUND_W_S, TRUNC_L_D64, 840 TRUNC_L_S, TRUNC_W_D32, TRUNC_W_D64, 841 TRUNC_W_S, PseudoTRUNC_W_D, 842 PseudoTRUNC_W_D32, PseudoTRUNC_W_S)>; 843 844// Pseudo convert instruction 845def : InstRW<[GenericWriteFPUL], (instrs PseudoCVT_D32_W, PseudoCVT_D64_L, 846 PseudoCVT_D64_W, PseudoCVT_S_L, 847 PseudoCVT_S_W)>; 848 849// div.[ds], div.ps 850def : InstRW<[GenericWriteFPUDivS], (instrs FDIV_S)>; 851def : InstRW<[GenericWriteFPUDivD], (instrs FDIV_D32, FDIV_D64)>; 852 853// sqrt.[ds], sqrt.ps 854def : InstRW<[GenericWriteFPUSqrtS], (instrs FSQRT_S)>; 855def : InstRW<[GenericWriteFPUSqrtD], (instrs FSQRT_D32, FSQRT_D64)>; 856 857// rsqrt.[ds], recip.[ds] 858def : InstRW<[GenericWriteFPURcpS], (instrs RECIP_S, RSQRT_S)>; 859def : InstRW<[GenericWriteFPURcpD], (instrs RECIP_D32, RECIP_D64, 860 RSQRT_D32, RSQRT_D64)>; 861 862 863// Load Pipe 864// --------- 865 866// ctc1, mtc1, mthc1, cfc1, mfc1, mfhc1 867def : InstRW<[GenericWriteFPUMoveGPRFPU], (instrs BuildPairF64, 868 BuildPairF64_64, ExtractElementF64, 869 ExtractElementF64_64, CFC1, CTC1, 870 MFC1, MFC1_D64, MFHC1_D32, 871 MFHC1_D64, MTC1, MTC1_D64, 872 MTHC1_D32, MTHC1_D64)>; 873 874// swc1, swxc1 875def : InstRW<[GenericWriteFPUStore], (instrs SDC1, SDC164, SDXC1, SDXC164, 876 SUXC1, SUXC164, SWC1, SWXC1)>; 877 878def : InstRW<[GenericWriteFPUMoveFP], (instrs FMOV_D32, FMOV_D64, FMOV_S)>; 879 880 881// movn.[ds], movz.[ds] 882def : InstRW<[GenericWriteFPUMoveFP], (instrs MOVF_I, MOVF_D32, MOVF_D64, 883 MOVF_S, MOVT_I, MOVT_D32, MOVT_D64, 884 MOVT_S, MOVN_I_D32, MOVN_I_D64, 885 MOVN_I_S, MOVZ_I_D32, MOVZ_I_D64, 886 MOVZ_I_S)>; 887 888def : InstRW<[GenericWriteFPUMoveFP], (instrs MOVT_I64, MOVF_I64, MOVZ_I64_S, 889 MOVN_I64_D64, MOVN_I64_S, 890 MOVZ_I64_D64)>; 891 892// l[dw]x?c1 893def : InstRW<[GenericWriteFPULoad], (instrs LDC1, LDC164, LDXC1, LDXC164, 894 LUXC1, LUXC164, LWC1, LWXC1)>; 895 896// MIPSR6 897// ====== 898 899// sel(eq|ne).[ds], max.[ds], maxa.[ds], min.[ds], mina.[ds], class.[ds] 900def : InstRW<[GenericWriteFPUS], (instrs SELEQZ_S, SELNEZ_S, SELEQZ_D, SELNEZ_D, 901 MAX_S, MAX_D, MAXA_S, MAXA_D, MIN_S, MIN_D, 902 MINA_S, MINA_D, CLASS_S, CLASS_D)>; 903 904def : InstRW<[GenericWriteFPUL], (instrs RINT_S, RINT_D)>; 905 906def : InstRW<[GenericWriteFPUCmp], (instrs BC1EQZ, BC1NEZ, SEL_D, SEL_S)>; 907 908def : InstRW<[GenericWriteFPUS], (instrs MADDF_S, MSUBF_S, MADDF_D, MSUBF_D)>; 909 910 911// microMIPS 912// ========= 913 914def : InstRW<[GenericWriteFPUMoveFP], (instrs MOVF_D32_MM, MOVF_S_MM, 915 MOVN_I_D32_MM, MOVN_I_S_MM, 916 MOVT_D32_MM, MOVT_S_MM, MOVZ_I_D32_MM, 917 MOVZ_I_S_MM)>; 918 919 920// cvt.?.?, ceil.?, floor.?, round.?, trunc.? (n)madd.? (n)msub.? 921def : InstRW<[GenericWriteFPUL], (instrs CVT_D32_S_MM, CVT_D32_W_MM, 922 CVT_D64_S_MM, CVT_D64_W_MM, CVT_L_D64_MM, 923 CVT_L_S_MM, CVT_S_D32_MM, CVT_S_D64_MM, 924 CVT_S_W_MM, CVT_W_D32_MM, CVT_W_D64_MM, 925 CVT_W_S_MM, CEIL_W_MM, CEIL_W_S_MM, 926 FLOOR_W_MM, FLOOR_W_S_MM, NMADD_S_MM, 927 NMADD_D32_MM, NMSUB_S_MM, NMSUB_D32_MM, 928 MADD_S_MM, MADD_D32_MM, ROUND_W_MM, 929 ROUND_W_S_MM, TRUNC_W_MM, TRUNC_W_S_MM)>; 930 931def : InstRW<[GenericWriteFPUCmp], (instregex "^C_[A-Z]_(S|D32|D64)_MM$")>; 932def : InstRW<[GenericWriteFPUCmp], (instregex "^C_[A-Z][A-Z]_(S|D32|D64)_MM$")>; 933def : InstRW<[GenericWriteFPUCmp], (instregex "^C_[A-Z][A-Z][A-Z]_(S|D32|D64)_MM$")>; 934def : InstRW<[GenericWriteFPUCmp], (instregex "^C_NGLE_(S|D32|D64)_MM$")>; 935def : InstRW<[GenericWriteFPUCmp], (instrs FCMP_S32_MM, FCMP_D32_MM)>; 936 937def : InstRW<[GenericWriteFPUS], (instrs MFC1_MM, MFHC1_D32_MM, MFHC1_D64_MM, 938 MTC1_MM, MTC1_D64_MM, 939 MTHC1_D32_MM, MTHC1_D64_MM)>; 940 941def : InstRW<[GenericWriteFPUS], (instrs FABS_D32_MM, FABS_D64_MM, FABS_S_MM, 942 FNEG_D32_MM, FNEG_D64_MM, FNEG_S_MM, 943 FADD_D32_MM, FADD_D64_MM, FADD_S_MM, 944 FMOV_D32_MM, FMOV_D64_MM, FMOV_S_MM, 945 FMUL_D32_MM, FMUL_D64_MM, FMUL_S_MM, 946 FSUB_D32_MM, FSUB_D64_MM, FSUB_S_MM, 947 MSUB_S_MM, MSUB_D32_MM)>; 948 949def : InstRW<[GenericWriteFPUDivS], (instrs FDIV_S_MM)>; 950def : InstRW<[GenericWriteFPUDivD], (instrs FDIV_D32_MM, FDIV_D64_MM)>; 951 952def : InstRW<[GenericWriteFPUSqrtS], (instrs FSQRT_S_MM)>; 953def : InstRW<[GenericWriteFPUSqrtD], (instrs FSQRT_D32_MM, FSQRT_D64_MM)>; 954 955def : InstRW<[GenericWriteFPURcpS], (instrs RECIP_S_MM, RSQRT_S_MM)>; 956def : InstRW<[GenericWriteFPURcpD], (instrs RECIP_D32_MM, RECIP_D64_MM, 957 RSQRT_D32_MM, RSQRT_D64_MM)>; 958 959def : InstRW<[GenericWriteFPUStore], (instrs SDC1_MM, SWC1_MM, SUXC1_MM, 960 SWXC1_MM)>; 961 962def : InstRW<[GenericWriteFPUMoveGPRFPU], (instrs CFC1_MM, CTC1_MM)>; 963 964def : InstRW<[GenericWriteFPULoad], (instrs LDC1_MM, LUXC1_MM, LWC1_MM, 965 LWXC1_MM)>; 966 967// microMIPS32r6 968// ============= 969 970def : InstRW<[GenericWriteFPUS], (instrs FNEG_S_MMR6)>; 971 972def : InstRW<[GenericWriteFPUCmp], (instregex "CMP_[A-Z][A-Z]_(S|D)_MMR6")>; 973def : InstRW<[GenericWriteFPUCmp], 974 (instregex "CMP_[A-Z][A-Z][A-Z]_(S|D)_MMR6")>; 975def : InstRW<[GenericWriteFPUCmp], 976 (instregex "CMP_[A-Z][A-Z][A-Z][A-Z]_(S|D)_MMR6")>; 977 978def : InstRW<[GenericWriteFPUL], 979 (instregex "CVT_(L|D|S|W)_(L|D|S|L|W)_MMR6")>; 980 981def : InstRW<[GenericWriteFPUL], 982 (instregex "TRUNC_(L|W)_(D|S)_MMR6")>; 983 984def : InstRW<[GenericWriteFPUL], 985 (instregex "ROUND_(L|W)_(D|S)_MMR6")>; 986 987def : InstRW<[GenericWriteFPUL], 988 (instregex "FLOOR_(L|W)_(D|S)_MMR6")>; 989 990def : InstRW<[GenericWriteFPUL], 991 (instregex "CEIL_(L|W)_(S|D)_MMR6")>; 992 993def : InstRW<[GenericWriteFPUS], 994 (instrs MFC1_MMR6, MTC1_MMR6, CLASS_S_MMR6, CLASS_D_MMR6, 995 FADD_S_MMR6)>; 996 997def : InstRW<[GenericWriteFPUS], (instregex "M(IN|AX)_(S|D)_MMR6")>; 998 999def : InstRW<[GenericWriteFPUS], (instregex "M(IN|AX)A_(S|D)_MMR6")>; 1000 1001def : InstRW<[GenericWriteFPUS], (instregex "SEL(EQ|NE)Z_(S|D)_MMR6")>; 1002 1003def : InstRW<[GenericWriteFPUS], (instregex "SEL_(S|D)_MMR6")>; 1004 1005def : InstRW<[GenericWriteFPUL], (instrs RINT_S_MMR6, RINT_D_MMR6)>; 1006 1007def : InstRW<[GenericWriteFPUS], (instregex "M(ADD|SUB)F_(S|D)_MMR6")>; 1008 1009def : InstRW<[GenericWriteFPUS], (instrs FMOV_S_MMR6, FMUL_S_MMR6, 1010 FSUB_S_MMR6, FMOV_D_MMR6)>; 1011 1012def : InstRW<[GenericWriteFPUL], (instrs FDIV_S_MMR6)>; 1013 1014def : InstRW<[GenericWriteFPUStore], (instrs SDC1_D64_MMR6)>; 1015 1016def : InstRW<[GenericWriteFPULoad], (instrs LDC1_D64_MMR6)>; 1017 1018// MIPS64 1019// ====== 1020 1021def : InstRW<[GenericWriteFPUMoveGPRFPU], (instrs DMFC1, DMTC1)>; 1022 1023// MIPS DSP ASE, HasDSP 1024// ==================== 1025 1026def : InstRW<[GenericWriteStore], (instrs SWDSP)>; 1027 1028def : InstRW<[GenericWriteLoad], (instrs LWDSP)>; 1029 1030def : InstRW<[GenericWriteMove], (instrs PseudoMTLOHI_DSP)>; 1031 1032def GenericDSP : ProcResource<1> { let BufferSize = 1; } 1033def GenericDSPShort : SchedWriteRes<[GenericDSP]> { let Latency = 2; } 1034def GenericDSPLong : SchedWriteRes<[GenericDSP]> { let Latency = 6; } 1035def GenericDSPBypass : SchedWriteRes<[GenericDSP]> { let Latency = 1; } 1036def GenericDSPMTHILO : SchedWriteRes<[GenericDSP]> { let Latency = 5; } 1037def GenericDSPLoad : SchedWriteRes<[GenericDSP]> { let Latency = 4; } 1038def GenericDSPMTHLIP : SchedWriteRes<[GenericDSP]> { let Latency = 5; } 1039 1040def : InstRW<[GenericDSPLong], (instregex "^EXTRV_RS_W$")>; 1041def : InstRW<[GenericDSPLong], (instregex "^EXTRV_R_W$")>; 1042def : InstRW<[GenericDSPLong], (instregex "^EXTRV_S_H$")>; 1043def : InstRW<[GenericDSPLong], (instregex "^EXTRV_W$")>; 1044def : InstRW<[GenericDSPLong], (instregex "^EXTR_RS_W$")>; 1045def : InstRW<[GenericDSPLong], (instregex "^EXTR_R_W$")>; 1046def : InstRW<[GenericDSPLong], (instregex "^EXTR_S_H$")>; 1047def : InstRW<[GenericDSPLong], (instregex "^EXTR_W$")>; 1048def : InstRW<[GenericDSPLong], (instregex "^INSV$")>; 1049 1050def : InstRW<[GenericDSPMTHLIP], (instregex "^MTHLIP$")>; 1051def : InstRW<[GenericDSPMTHILO], (instregex "^MTHI_DSP$")>; 1052def : InstRW<[GenericDSPMTHILO], (instregex "^MTLO_DSP$")>; 1053 1054def : InstRW<[GenericDSPShort], (instregex "^ABSQ_S_PH$")>; 1055def : InstRW<[GenericDSPShort], (instregex "^ABSQ_S_W$")>; 1056def : InstRW<[GenericDSPShort], (instregex "^ADDQ_PH$")>; 1057def : InstRW<[GenericDSPShort], (instregex "^ADDQ_S_PH$")>; 1058def : InstRW<[GenericDSPShort], (instregex "^ADDQ_S_W$")>; 1059def : InstRW<[GenericDSPShort], (instregex "^ADDSC$")>; 1060def : InstRW<[GenericDSPShort], (instregex "^ADDU_QB$")>; 1061def : InstRW<[GenericDSPShort], (instregex "^ADDU_S_QB$")>; 1062def : InstRW<[GenericDSPShort], (instregex "^ADDWC$")>; 1063def : InstRW<[GenericDSPShort], (instregex "^BITREV$")>; 1064def : InstRW<[GenericDSPShort], (instregex "^BPOSGE32$")>; 1065def : InstRW<[GenericDSPShort], (instregex "^CMPGU_EQ_QB$")>; 1066def : InstRW<[GenericDSPShort], (instregex "^CMPGU_LE_QB$")>; 1067def : InstRW<[GenericDSPShort], (instregex "^CMPGU_LT_QB$")>; 1068def : InstRW<[GenericDSPShort], (instregex "^CMPU_EQ_QB$")>; 1069def : InstRW<[GenericDSPShort], (instregex "^CMPU_LE_QB$")>; 1070def : InstRW<[GenericDSPShort], (instregex "^CMPU_LT_QB$")>; 1071def : InstRW<[GenericDSPShort], (instregex "^CMP_EQ_PH$")>; 1072def : InstRW<[GenericDSPShort], (instregex "^CMP_LE_PH$")>; 1073def : InstRW<[GenericDSPShort], (instregex "^CMP_LT_PH$")>; 1074def : InstRW<[GenericDSPShort], (instregex "^DPAQ_SA_L_W$")>; 1075def : InstRW<[GenericDSPShort], (instregex "^DPAQ_S_W_PH$")>; 1076def : InstRW<[GenericDSPShort], (instregex "^DPAU_H_QBL$")>; 1077def : InstRW<[GenericDSPShort], (instregex "^DPAU_H_QBR$")>; 1078def : InstRW<[GenericDSPShort], (instregex "^DPSQ_SA_L_W$")>; 1079def : InstRW<[GenericDSPShort], (instregex "^DPSQ_S_W_PH$")>; 1080def : InstRW<[GenericDSPShort], (instregex "^DPSU_H_QBL$")>; 1081def : InstRW<[GenericDSPShort], (instregex "^DPSU_H_QBR$")>; 1082def : InstRW<[GenericDSPShort], (instregex "^EXTPDPV$")>; 1083def : InstRW<[GenericDSPShort], (instregex "^EXTPDP$")>; 1084def : InstRW<[GenericDSPShort], (instregex "^EXTPV$")>; 1085def : InstRW<[GenericDSPShort], (instregex "^EXTP$")>; 1086def : InstRW<[GenericDSPShort], (instregex "^LBUX$")>; 1087def : InstRW<[GenericDSPShort], (instregex "^LHX$")>; 1088def : InstRW<[GenericDSPShort], (instregex "^LWX$")>; 1089def : InstRW<[GenericDSPShort], (instregex "^MADDU_DSP$")>; 1090def : InstRW<[GenericDSPShort], (instregex "^MADD_DSP$")>; 1091def : InstRW<[GenericDSPShort], (instregex "^MAQ_SA_W_PHL$")>; 1092def : InstRW<[GenericDSPShort], (instregex "^MAQ_SA_W_PHR$")>; 1093def : InstRW<[GenericDSPShort], (instregex "^MAQ_S_W_PHL$")>; 1094def : InstRW<[GenericDSPShort], (instregex "^MAQ_S_W_PHR$")>; 1095def : InstRW<[GenericDSPShort], (instregex "^MFHI_DSP$")>; 1096def : InstRW<[GenericDSPShort], (instregex "^MFLO_DSP$")>; 1097def : InstRW<[GenericDSPShort], (instregex "^MODSUB$")>; 1098def : InstRW<[GenericDSPShort], (instregex "^MSUBU_DSP$")>; 1099def : InstRW<[GenericDSPShort], (instregex "^MSUB_DSP$")>; 1100def : InstRW<[GenericDSPShort], (instregex "^MULEQ_S_W_PHL$")>; 1101def : InstRW<[GenericDSPShort], (instregex "^MULEQ_S_W_PHR$")>; 1102def : InstRW<[GenericDSPShort], (instregex "^MULEU_S_PH_QBL$")>; 1103def : InstRW<[GenericDSPShort], (instregex "^MULEU_S_PH_QBR$")>; 1104def : InstRW<[GenericDSPShort], (instregex "^MULQ_RS_PH$")>; 1105def : InstRW<[GenericDSPShort], (instregex "^MULSAQ_S_W_PH$")>; 1106def : InstRW<[GenericDSPShort], (instregex "^MULTU_DSP$")>; 1107def : InstRW<[GenericDSPShort], (instregex "^MULT_DSP$")>; 1108def : InstRW<[GenericDSPShort], (instregex "^PACKRL_PH$")>; 1109def : InstRW<[GenericDSPShort], (instregex "^PICK_PH$")>; 1110def : InstRW<[GenericDSPShort], (instregex "^PICK_QB$")>; 1111def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBLA$")>; 1112def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBL$")>; 1113def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBRA$")>; 1114def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBR$")>; 1115def : InstRW<[GenericDSPShort], (instregex "^PRECEQ_W_PHL$")>; 1116def : InstRW<[GenericDSPShort], (instregex "^PRECEQ_W_PHR$")>; 1117def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBLA$")>; 1118def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBL$")>; 1119def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBRA$")>; 1120def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBR$")>; 1121def : InstRW<[GenericDSPShort], (instregex "^PRECRQU_S_QB_PH$")>; 1122def : InstRW<[GenericDSPShort], (instregex "^PRECRQ_PH_W$")>; 1123def : InstRW<[GenericDSPShort], (instregex "^PRECRQ_QB_PH$")>; 1124def : InstRW<[GenericDSPShort], (instregex "^PRECRQ_RS_PH_W$")>; 1125def : InstRW<[GenericDSPShort], (instregex "^RADDU_W_QB$")>; 1126def : InstRW<[GenericDSPShort], (instregex "^RDDSP$")>; 1127def : InstRW<[GenericDSPShort], (instregex "^REPLV_PH$")>; 1128def : InstRW<[GenericDSPShort], (instregex "^REPLV_QB$")>; 1129def : InstRW<[GenericDSPShort], (instregex "^REPL_PH$")>; 1130def : InstRW<[GenericDSPShort], (instregex "^REPL_QB$")>; 1131def : InstRW<[GenericDSPShort], (instregex "^SHILOV$")>; 1132def : InstRW<[GenericDSPShort], (instregex "^SHILO$")>; 1133def : InstRW<[GenericDSPShort], (instregex "^SHLLV_PH$")>; 1134def : InstRW<[GenericDSPShort], (instregex "^SHLLV_QB$")>; 1135def : InstRW<[GenericDSPShort], (instregex "^SHLLV_S_PH$")>; 1136def : InstRW<[GenericDSPShort], (instregex "^SHLLV_S_W$")>; 1137def : InstRW<[GenericDSPShort], (instregex "^SHLL_PH$")>; 1138def : InstRW<[GenericDSPShort], (instregex "^SHLL_QB$")>; 1139def : InstRW<[GenericDSPShort], (instregex "^SHLL_S_PH$")>; 1140def : InstRW<[GenericDSPShort], (instregex "^SHLL_S_W$")>; 1141def : InstRW<[GenericDSPShort], (instregex "^SHRAV_PH$")>; 1142def : InstRW<[GenericDSPShort], (instregex "^SHRAV_R_PH$")>; 1143def : InstRW<[GenericDSPShort], (instregex "^SHRAV_R_W$")>; 1144def : InstRW<[GenericDSPShort], (instregex "^SHRA_PH$")>; 1145def : InstRW<[GenericDSPShort], (instregex "^SHRA_R_PH$")>; 1146def : InstRW<[GenericDSPShort], (instregex "^SHRA_R_W$")>; 1147def : InstRW<[GenericDSPShort], (instregex "^SHRLV_QB$")>; 1148def : InstRW<[GenericDSPShort], (instregex "^SHRL_QB$")>; 1149def : InstRW<[GenericDSPShort], (instregex "^SUBQ_PH$")>; 1150def : InstRW<[GenericDSPShort], (instregex "^SUBQ_S_PH$")>; 1151def : InstRW<[GenericDSPShort], (instregex "^SUBQ_S_W$")>; 1152def : InstRW<[GenericDSPShort], (instregex "^SUBU_QB$")>; 1153def : InstRW<[GenericDSPShort], (instregex "^SUBU_S_QB$")>; 1154def : InstRW<[GenericDSPShort], (instregex "^WRDSP$")>; 1155 1156def : InstRW<[GenericDSPShort], 1157 (instregex "^Pseudo(CMP|CMPU)_(EQ|LE|LT)_(PH|QB)$")>; 1158def : InstRW<[GenericDSPShort], 1159 (instregex "^PseudoPICK_(PH|QB)$")>; 1160 1161// MIPS DSP R2 - hasDSP, HasDSPR2, InMicroMips 1162// =========================================== 1163 1164def : InstRW<[GenericDSPShort], (instregex "^ABSQ_S_QB$")>; 1165def : InstRW<[GenericDSPShort], (instregex "^ADDQH_PH$")>; 1166def : InstRW<[GenericDSPShort], (instregex "^ADDQH_R_PH$")>; 1167def : InstRW<[GenericDSPShort], (instregex "^ADDQH_R_W$")>; 1168def : InstRW<[GenericDSPShort], (instregex "^ADDQH_W$")>; 1169def : InstRW<[GenericDSPShort], (instregex "^ADDUH_QB$")>; 1170def : InstRW<[GenericDSPShort], (instregex "^ADDUH_R_QB$")>; 1171def : InstRW<[GenericDSPShort], (instregex "^ADDU_PH$")>; 1172def : InstRW<[GenericDSPShort], (instregex "^ADDU_S_PH$")>; 1173def : InstRW<[GenericDSPShort], (instregex "^APPEND$")>; 1174def : InstRW<[GenericDSPShort], (instregex "^BALIGN$")>; 1175def : InstRW<[GenericDSPShort], (instregex "^CMPGDU_EQ_QB$")>; 1176def : InstRW<[GenericDSPShort], (instregex "^CMPGDU_LE_QB$")>; 1177def : InstRW<[GenericDSPShort], (instregex "^CMPGDU_LT_QB$")>; 1178def : InstRW<[GenericDSPShort], (instregex "^DPA_W_PH$")>; 1179def : InstRW<[GenericDSPShort], (instregex "^DPAQX_SA_W_PH$")>; 1180def : InstRW<[GenericDSPShort], (instregex "^DPAQX_S_W_PH$")>; 1181def : InstRW<[GenericDSPShort], (instregex "^DPAX_W_PH$")>; 1182def : InstRW<[GenericDSPShort], (instregex "^DPS_W_PH$")>; 1183def : InstRW<[GenericDSPShort], (instregex "^DPSQX_S_W_PH$")>; 1184def : InstRW<[GenericDSPShort], (instregex "^DPSQX_SA_W_PH$")>; 1185def : InstRW<[GenericDSPShort], (instregex "^DPSX_W_PH$")>; 1186def : InstRW<[GenericDSPShort], (instregex "^MUL_PH$")>; 1187def : InstRW<[GenericDSPShort], (instregex "^MUL_S_PH$")>; 1188def : InstRW<[GenericDSPShort], (instregex "^MULQ_RS_W$")>; 1189def : InstRW<[GenericDSPShort], (instregex "^MULQ_S_PH$")>; 1190def : InstRW<[GenericDSPShort], (instregex "^MULQ_S_W$")>; 1191def : InstRW<[GenericDSPShort], (instregex "^MULSA_W_PH$")>; 1192def : InstRW<[GenericDSPShort], (instregex "^PRECR_QB_PH$")>; 1193def : InstRW<[GenericDSPShort], (instregex "^PRECR_SRA_PH_W$")>; 1194def : InstRW<[GenericDSPShort], (instregex "^PRECR_SRA_R_PH_W$")>; 1195def : InstRW<[GenericDSPShort], (instregex "^PREPEND$")>; 1196def : InstRW<[GenericDSPShort], (instregex "^SHRA_QB$")>; 1197def : InstRW<[GenericDSPShort], (instregex "^SHRA_R_QB$")>; 1198def : InstRW<[GenericDSPShort], (instregex "^SHRAV_QB$")>; 1199def : InstRW<[GenericDSPShort], (instregex "^SHRAV_R_QB$")>; 1200def : InstRW<[GenericDSPShort], (instregex "^SHRL_PH$")>; 1201def : InstRW<[GenericDSPShort], (instregex "^SHRLV_PH$")>; 1202def : InstRW<[GenericDSPShort], (instregex "^SUBQH_PH$")>; 1203def : InstRW<[GenericDSPShort], (instregex "^SUBQH_R_PH$")>; 1204def : InstRW<[GenericDSPShort], (instregex "^SUBQH_W$")>; 1205def : InstRW<[GenericDSPShort], (instregex "^SUBQH_R_W$")>; 1206def : InstRW<[GenericDSPShort], (instregex "^SUBU_PH$")>; 1207def : InstRW<[GenericDSPShort], (instregex "^SUBU_S_PH$")>; 1208def : InstRW<[GenericDSPShort], (instregex "^SUBUH_QB$")>; 1209def : InstRW<[GenericDSPShort], (instregex "^SUBUH_R_QB$")>; 1210 1211// microMIPS DSP R1 - HasDSP, InMicroMips 1212// ====================================== 1213 1214def : InstRW<[GenericWriteLoad], (instrs LWDSP_MM)>; 1215 1216def : InstRW<[GenericWriteStore], (instrs SWDSP_MM)>; 1217 1218def : InstRW<[GenericDSPShort], (instregex "^ABSQ_S_PH_MM$")>; 1219def : InstRW<[GenericDSPShort], (instregex "^ABSQ_S_W_MM$")>; 1220def : InstRW<[GenericDSPShort], (instregex "^ADDQ_PH_MM$")>; 1221def : InstRW<[GenericDSPShort], (instregex "^ADDQ_S_PH_MM$")>; 1222def : InstRW<[GenericDSPShort], (instregex "^ADDQ_S_W_MM$")>; 1223def : InstRW<[GenericDSPShort], (instregex "^ADDSC_MM$")>; 1224def : InstRW<[GenericDSPShort], (instregex "^ADDU_QB_MM$")>; 1225def : InstRW<[GenericDSPShort], (instregex "^ADDU_S_QB_MM$")>; 1226def : InstRW<[GenericDSPShort], (instregex "^ADDWC_MM$")>; 1227def : InstRW<[GenericDSPShort], (instregex "^BITREV_MM$")>; 1228def : InstRW<[GenericDSPShort], (instregex "^BPOSGE32_MM$")>; 1229def : InstRW<[GenericDSPShort], (instregex "^CMPGU_EQ_QB_MM$")>; 1230def : InstRW<[GenericDSPShort], (instregex "^CMPGU_LE_QB_MM$")>; 1231def : InstRW<[GenericDSPShort], (instregex "^CMPGU_LT_QB_MM$")>; 1232def : InstRW<[GenericDSPShort], (instregex "^CMPU_EQ_QB_MM$")>; 1233def : InstRW<[GenericDSPShort], (instregex "^CMPU_LE_QB_MM$")>; 1234def : InstRW<[GenericDSPShort], (instregex "^CMPU_LT_QB_MM$")>; 1235def : InstRW<[GenericDSPShort], (instregex "^CMP_EQ_PH_MM$")>; 1236def : InstRW<[GenericDSPShort], (instregex "^CMP_LE_PH_MM$")>; 1237def : InstRW<[GenericDSPShort], (instregex "^CMP_LT_PH_MM$")>; 1238def : InstRW<[GenericDSPShort], (instregex "^DPAQ_SA_L_W_MM$")>; 1239def : InstRW<[GenericDSPShort], (instregex "^DPAQ_S_W_PH_MM$")>; 1240def : InstRW<[GenericDSPShort], (instregex "^DPAU_H_QBL_MM$")>; 1241def : InstRW<[GenericDSPShort], (instregex "^DPAU_H_QBR_MM$")>; 1242def : InstRW<[GenericDSPShort], (instregex "^DPSQ_SA_L_W_MM$")>; 1243def : InstRW<[GenericDSPShort], (instregex "^DPSQ_S_W_PH_MM$")>; 1244def : InstRW<[GenericDSPShort], (instregex "^DPSU_H_QBL_MM$")>; 1245def : InstRW<[GenericDSPShort], (instregex "^DPSU_H_QBR_MM$")>; 1246def : InstRW<[GenericDSPShort], (instregex "^EXTPDPV_MM$")>; 1247def : InstRW<[GenericDSPShort], (instregex "^EXTPDP_MM$")>; 1248def : InstRW<[GenericDSPShort], (instregex "^EXTPV_MM$")>; 1249def : InstRW<[GenericDSPShort], (instregex "^EXTP_MM$")>; 1250def : InstRW<[GenericDSPShort], (instregex "^EXTRV_RS_W_MM$")>; 1251def : InstRW<[GenericDSPShort], (instregex "^EXTRV_R_W_MM$")>; 1252def : InstRW<[GenericDSPShort], (instregex "^EXTRV_S_H_MM$")>; 1253def : InstRW<[GenericDSPShort], (instregex "^EXTRV_W_MM$")>; 1254def : InstRW<[GenericDSPShort], (instregex "^EXTR_RS_W_MM$")>; 1255def : InstRW<[GenericDSPShort], (instregex "^EXTR_R_W_MM$")>; 1256def : InstRW<[GenericDSPShort], (instregex "^EXTR_S_H_MM$")>; 1257def : InstRW<[GenericDSPShort], (instregex "^EXTR_W_MM$")>; 1258def : InstRW<[GenericDSPShort], (instregex "^INSV_MM$")>; 1259def : InstRW<[GenericDSPShort], (instregex "^LBUX_MM$")>; 1260def : InstRW<[GenericDSPShort], (instregex "^LHX_MM$")>; 1261def : InstRW<[GenericDSPShort], (instregex "^LWX_MM$")>; 1262def : InstRW<[GenericDSPShort], (instregex "^MADDU_DSP_MM$")>; 1263def : InstRW<[GenericDSPShort], (instregex "^MADD_DSP_MM$")>; 1264def : InstRW<[GenericDSPShort], (instregex "^MAQ_SA_W_PHL_MM$")>; 1265def : InstRW<[GenericDSPShort], (instregex "^MAQ_SA_W_PHR_MM$")>; 1266def : InstRW<[GenericDSPShort], (instregex "^MAQ_S_W_PHL_MM$")>; 1267def : InstRW<[GenericDSPShort], (instregex "^MAQ_S_W_PHR_MM$")>; 1268def : InstRW<[GenericDSPShort], (instregex "^MFHI_DSP_MM$")>; 1269def : InstRW<[GenericDSPShort], (instregex "^MFLO_DSP_MM$")>; 1270def : InstRW<[GenericDSPShort], (instregex "^MODSUB_MM$")>; 1271def : InstRW<[GenericDSPShort], (instregex "^MOVEP_MMR6$")>; 1272def : InstRW<[GenericDSPShort], (instregex "^MOVN_I_MM$")>; 1273def : InstRW<[GenericDSPShort], (instregex "^MOVZ_I_MM$")>; 1274def : InstRW<[GenericDSPShort], (instregex "^MSUBU_DSP_MM$")>; 1275def : InstRW<[GenericDSPShort], (instregex "^MSUB_DSP_MM$")>; 1276def : InstRW<[GenericDSPShort], (instregex "^MTHI_DSP_MM$")>; 1277def : InstRW<[GenericDSPShort], (instregex "^MTHLIP_MM$")>; 1278def : InstRW<[GenericDSPShort], (instregex "^MTLO_DSP_MM$")>; 1279def : InstRW<[GenericDSPShort], (instregex "^MULEQ_S_W_PHL_MM$")>; 1280def : InstRW<[GenericDSPShort], (instregex "^MULEQ_S_W_PHR_MM$")>; 1281def : InstRW<[GenericDSPShort], (instregex "^MULEU_S_PH_QBL_MM$")>; 1282def : InstRW<[GenericDSPShort], (instregex "^MULEU_S_PH_QBR_MM$")>; 1283def : InstRW<[GenericDSPShort], (instregex "^MULQ_RS_PH_MM$")>; 1284def : InstRW<[GenericDSPShort], (instregex "^MULSAQ_S_W_PH_MM$")>; 1285def : InstRW<[GenericDSPShort], (instregex "^MULTU_DSP_MM$")>; 1286def : InstRW<[GenericDSPShort], (instregex "^MULT_DSP_MM$")>; 1287def : InstRW<[GenericDSPShort], (instregex "^PACKRL_PH_MM$")>; 1288def : InstRW<[GenericDSPShort], (instregex "^PICK_PH_MM$")>; 1289def : InstRW<[GenericDSPShort], (instregex "^PICK_QB_MM$")>; 1290def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBLA_MM$")>; 1291def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBL_MM$")>; 1292def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBRA_MM$")>; 1293def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBR_MM$")>; 1294def : InstRW<[GenericDSPShort], (instregex "^PRECEQ_W_PHL_MM$")>; 1295def : InstRW<[GenericDSPShort], (instregex "^PRECEQ_W_PHR_MM$")>; 1296def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBLA_MM$")>; 1297def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBL_MM$")>; 1298def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBRA_MM$")>; 1299def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBR_MM$")>; 1300def : InstRW<[GenericDSPShort], (instregex "^PRECRQU_S_QB_PH_MM$")>; 1301def : InstRW<[GenericDSPShort], (instregex "^PRECRQ_PH_W_MM$")>; 1302def : InstRW<[GenericDSPShort], (instregex "^PRECRQ_QB_PH_MM$")>; 1303def : InstRW<[GenericDSPShort], (instregex "^PRECRQ_RS_PH_W_MM$")>; 1304def : InstRW<[GenericDSPShort], (instregex "^RADDU_W_QB_MM$")>; 1305def : InstRW<[GenericDSPShort], (instregex "^RDDSP_MM$")>; 1306def : InstRW<[GenericDSPShort], (instregex "^REPLV_PH_MM$")>; 1307def : InstRW<[GenericDSPShort], (instregex "^REPLV_QB_MM$")>; 1308def : InstRW<[GenericDSPShort], (instregex "^REPL_PH_MM$")>; 1309def : InstRW<[GenericDSPShort], (instregex "^REPL_QB_MM$")>; 1310def : InstRW<[GenericDSPShort], (instregex "^SHILOV_MM$")>; 1311def : InstRW<[GenericDSPShort], (instregex "^SHILO_MM$")>; 1312def : InstRW<[GenericDSPShort], (instregex "^SHLLV_PH_MM$")>; 1313def : InstRW<[GenericDSPShort], (instregex "^SHLLV_QB_MM$")>; 1314def : InstRW<[GenericDSPShort], (instregex "^SHLLV_S_PH_MM$")>; 1315def : InstRW<[GenericDSPShort], (instregex "^SHLLV_S_W_MM$")>; 1316def : InstRW<[GenericDSPShort], (instregex "^SHLL_PH_MM$")>; 1317def : InstRW<[GenericDSPShort], (instregex "^SHLL_QB_MM$")>; 1318def : InstRW<[GenericDSPShort], (instregex "^SHLL_S_PH_MM$")>; 1319def : InstRW<[GenericDSPShort], (instregex "^SHLL_S_W_MM$")>; 1320def : InstRW<[GenericDSPShort], (instregex "^SHRAV_PH_MM$")>; 1321def : InstRW<[GenericDSPShort], (instregex "^SHRAV_R_PH_MM$")>; 1322def : InstRW<[GenericDSPShort], (instregex "^SHRAV_R_W_MM$")>; 1323def : InstRW<[GenericDSPShort], (instregex "^SHRA_PH_MM$")>; 1324def : InstRW<[GenericDSPShort], (instregex "^SHRA_R_PH_MM$")>; 1325def : InstRW<[GenericDSPShort], (instregex "^SHRA_R_W_MM$")>; 1326def : InstRW<[GenericDSPShort], (instregex "^SHRLV_QB_MM$")>; 1327def : InstRW<[GenericDSPShort], (instregex "^SHRL_QB_MM$")>; 1328def : InstRW<[GenericDSPShort], (instregex "^SUBQ_PH_MM$")>; 1329def : InstRW<[GenericDSPShort], (instregex "^SUBQ_S_PH_MM$")>; 1330def : InstRW<[GenericDSPShort], (instregex "^SUBQ_S_W_MM$")>; 1331def : InstRW<[GenericDSPShort], (instregex "^SUBU_QB_MM$")>; 1332def : InstRW<[GenericDSPShort], (instregex "^SUBU_S_QB_MM$")>; 1333def : InstRW<[GenericDSPShort], (instregex "^WRDSP_MM$")>; 1334 1335 1336// microMIPS DSP R2 - hasDSP, HasDSPR2, InMicroMips 1337// ================================================ 1338 1339def : InstRW<[GenericDSPShort], (instregex "^ABSQ_S_QB_MMR2$")>; 1340def : InstRW<[GenericDSPShort], (instregex "^ADDQH_PH_MMR2$")>; 1341def : InstRW<[GenericDSPShort], (instregex "^ADDQH_R_PH_MMR2$")>; 1342def : InstRW<[GenericDSPShort], (instregex "^ADDQH_R_W_MMR2$")>; 1343def : InstRW<[GenericDSPShort], (instregex "^ADDQH_W_MMR2$")>; 1344def : InstRW<[GenericDSPShort], (instregex "^ADDUH_QB_MMR2$")>; 1345def : InstRW<[GenericDSPShort], (instregex "^ADDUH_R_QB_MMR2$")>; 1346def : InstRW<[GenericDSPShort], (instregex "^ADDU_PH_MMR2$")>; 1347def : InstRW<[GenericDSPShort], (instregex "^ADDU_S_PH_MMR2$")>; 1348def : InstRW<[GenericDSPShort], (instregex "^APPEND_MMR2$")>; 1349def : InstRW<[GenericDSPShort], (instregex "^BALIGN_MMR2$")>; 1350def : InstRW<[GenericDSPShort], (instregex "^CMPGDU_EQ_QB_MMR2$")>; 1351def : InstRW<[GenericDSPShort], (instregex "^CMPGDU_LE_QB_MMR2$")>; 1352def : InstRW<[GenericDSPShort], (instregex "^CMPGDU_LT_QB_MMR2$")>; 1353def : InstRW<[GenericDSPShort], (instregex "^DPA_W_PH_MMR2$")>; 1354def : InstRW<[GenericDSPShort], (instregex "^DPAQX_SA_W_PH_MMR2$")>; 1355def : InstRW<[GenericDSPShort], (instregex "^DPAQX_S_W_PH_MMR2$")>; 1356def : InstRW<[GenericDSPShort], (instregex "^DPAX_W_PH_MMR2$")>; 1357def : InstRW<[GenericDSPShort], (instregex "^DPS_W_PH_MMR2$")>; 1358def : InstRW<[GenericDSPShort], (instregex "^DPSQX_S_W_PH_MMR2$")>; 1359def : InstRW<[GenericDSPShort], (instregex "^DPSQX_SA_W_PH_MMR2$")>; 1360def : InstRW<[GenericDSPShort], (instregex "^DPSX_W_PH_MMR2$")>; 1361def : InstRW<[GenericDSPShort], (instregex "^MUL_PH_MMR2$")>; 1362def : InstRW<[GenericDSPShort], (instregex "^MUL_S_PH_MMR2$")>; 1363def : InstRW<[GenericDSPShort], (instregex "^MULQ_RS_W_MMR2$")>; 1364def : InstRW<[GenericDSPShort], (instregex "^MULQ_S_PH_MMR2$")>; 1365def : InstRW<[GenericDSPShort], (instregex "^MULQ_S_W_MMR2$")>; 1366def : InstRW<[GenericDSPShort], (instregex "^MULSA_W_PH_MMR2$")>; 1367def : InstRW<[GenericDSPShort], (instregex "^PRECR_QB_PH_MMR2$")>; 1368def : InstRW<[GenericDSPShort], (instregex "^PRECR_SRA_PH_W_MMR2$")>; 1369def : InstRW<[GenericDSPShort], (instregex "^PRECR_SRA_R_PH_W_MMR2$")>; 1370def : InstRW<[GenericDSPShort], (instregex "^PREPEND_MMR2$")>; 1371def : InstRW<[GenericDSPShort], (instregex "^SHRA_QB_MMR2$")>; 1372def : InstRW<[GenericDSPShort], (instregex "^SHRA_R_QB_MMR2$")>; 1373def : InstRW<[GenericDSPShort], (instregex "^SHRAV_QB_MMR2$")>; 1374def : InstRW<[GenericDSPShort], (instregex "^SHRAV_R_QB_MMR2$")>; 1375def : InstRW<[GenericDSPShort], (instregex "^SHRL_PH_MMR2$")>; 1376def : InstRW<[GenericDSPShort], (instregex "^SHRLV_PH_MMR2$")>; 1377def : InstRW<[GenericDSPShort], (instregex "^SUBQH_PH_MMR2$")>; 1378def : InstRW<[GenericDSPShort], (instregex "^SUBQH_R_PH_MMR2$")>; 1379def : InstRW<[GenericDSPShort], (instregex "^SUBQH_W_MMR2$")>; 1380def : InstRW<[GenericDSPShort], (instregex "^SUBQH_R_W_MMR2$")>; 1381def : InstRW<[GenericDSPShort], (instregex "^SUBU_PH_MMR2$")>; 1382def : InstRW<[GenericDSPShort], (instregex "^SUBU_S_PH_MMR2$")>; 1383def : InstRW<[GenericDSPShort], (instregex "^SUBUH_QB_MMR2$")>; 1384def : InstRW<[GenericDSPShort], (instregex "^SUBUH_R_QB_MMR2$")>; 1385 1386// microMIPS DSP R3 - hasDSP, hasDSPR2, hasDSPR3, InMicroMips 1387// ========================================================== 1388 1389def : InstRW<[GenericDSPShort], (instregex "^BPOSGE32C_MMR3$")>; 1390 1391// MIPS MSA ASE - hasMSA 1392// ===================== 1393 1394def GenericWriteMSAShortLogic : SchedWriteRes<[GenericIssueFPUS]>; 1395def GenericWriteMSAShortInt : SchedWriteRes<[GenericIssueFPUS]> { 1396let Latency = 2; 1397} 1398def GenericWriteMoveOtherUnitsToFPU : SchedWriteRes<[GenericIssueFPUS]>; 1399def GenericWriteMSAOther3 : SchedWriteRes<[GenericIssueFPUS]> { 1400let Latency = 3; 1401} 1402def GenericWriteMSALongInt : SchedWriteRes<[GenericIssueFPUS]> { 1403let Latency = 5; 1404} 1405def GenericWriteFPUDivI : SchedWriteRes<[GenericFPQ]> { 1406 let Latency = 33; 1407 let ResourceCycles = [ 33 ]; 1408} 1409 1410// FPUS is also used in moves from floating point and MSA registers to general 1411// purpose registers. 1412def GenericWriteMoveFPUSToOtherUnits : SchedWriteRes<[GenericIssueFPUS]> { 1413 let Latency = 0; 1414} 1415 1416// FPUL is also used in moves from floating point and MSA registers to general 1417// purpose registers. 1418def GenericWriteMoveFPULToOtherUnits : SchedWriteRes<[GenericIssueFPUL]>; 1419 1420 1421// adds_a.[bhwd], adds_[asu].[bhwd], addvi?.[bhwd], asub_[us].[bhwd], 1422// aver?_[us].[bhwd] 1423def : InstRW<[GenericWriteMSAShortInt], (instregex "^ADD_A_[BHWD]$")>; 1424def : InstRW<[GenericWriteMSAShortInt], (instregex "^ADDS_[ASU]_[BHWD]$")>; 1425 1426// TODO: ADDVI_[BHW] might be 1 cycle latency rather than 2. Need to confirm it. 1427// add.[bhwd], addvi.[bhwd], asub_[us].[bhwd], ave.[bhwd], aver.[bhwd] 1428def : InstRW<[GenericWriteMSAShortInt], (instregex "^ADDVI?_[BHWD]$")>; 1429def : InstRW<[GenericWriteMSAShortInt], (instregex "^ASUB_[US].[BHWD]$")>; 1430def : InstRW<[GenericWriteMSAShortInt], (instregex "^AVER?_[US].[BHWD]$")>; 1431 1432// and.v, andi.b, move.v, ldi.[bhwd], xor.v, nor.v, xori.b, nori.b, lsa 1433def : InstRW<[GenericWriteMSAShortLogic], (instregex "^MOVE_V$")>; 1434def : InstRW<[GenericWriteMSAShortLogic], (instregex "^LDI_[BHWD]$")>; 1435def : InstRW<[GenericWriteMSAShortLogic], (instrs LSA)>; 1436def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)_V$")>; 1437def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)I_B$")>; 1438def : InstRW<[GenericWriteMSAShortLogic], 1439 (instregex "^(AND|OR|[XN]OR)_V_[DHW]_PSEUDO$")>; 1440 1441// vshf.[bhwd], binsl.[bhwd], binsr.[bhwd], insert.[bhwd], sld?.[bhwd], 1442// bset.[bhwd], bclr.[bhwd], bneg.[bhwd], bsel_v, bseli_b 1443def : InstRW<[GenericWriteMSAShortInt], (instregex "^VSHF_[BHWD]$")>; 1444def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BINSL|BINSLI)_[BHWD]$")>; 1445def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BINSR|BINSRI)_[BHWD]$")>; 1446def : InstRW<[GenericWriteMSAShortInt], (instregex "^INSERT_[BHWD]$")>; 1447def : InstRW<[GenericWriteMSAShortInt], (instregex "^(SLD|SLDI)_[BHWD]$")>; 1448def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BSET|BSETI)_[BHWD]$")>; 1449def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BCLR|BCLRI)_[BHWD]$")>; 1450def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BNEG|BNEGI)_[BHWD]$")>; 1451def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BSEL_V|BSELI_B)$")>; 1452def : InstRW<[GenericWriteMSAShortInt], (instregex "^BMN*Z.*$")>; 1453def : InstRW<[GenericWriteMSAShortInt], 1454 (instregex "^BSEL_(H|W|D|FW|FD)_PSEUDO$")>; 1455 1456// pcnt.[bhwd], sat_s.[bhwd], sat_u.[bhwd] 1457def : InstRW<[GenericWriteMSAOther3], (instregex "^PCNT_[BHWD]$")>; 1458def : InstRW<[GenericWriteMSAOther3], (instregex "^SAT_(S|U)_[BHWD]$")>; 1459 1460// bnz.[bhwdv], cfcmsa, ctcmsa 1461def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(BNZ|BZ)_[BHWDV]$")>; 1462def : InstRW<[GenericWriteMSAShortLogic], (instregex "^C(F|T)CMSA$")>; 1463 1464// shf.[bhw], fill[bhwd], splat?.[bhwd] 1465def : InstRW<[GenericWriteMSAShortInt], (instregex "^SHF_[BHW]$")>; 1466def : InstRW<[GenericWriteMSAShortInt], (instregex "^FILL_[BHWD]$")>; 1467def : InstRW<[GenericWriteMSAShortInt], (instregex "^(SPLAT|SPLATI)_[BHWD]$")>; 1468 1469// fexp2_w, fexp2_d 1470def : InstRW<[GenericWriteFPUS], (instregex "^FEXP2_(W|D)$")>; 1471 1472// compare, converts, round to int, floating point truncate. 1473def : InstRW<[GenericWriteFPUS], (instregex "^(CLT|CLTI)_(S|U)_[BHWD]$")>; 1474def : InstRW<[GenericWriteFPUS], (instregex "^(CLE|CLEI)_(S|U)_[BHWD]$")>; 1475def : InstRW<[GenericWriteFPUS], (instregex "^(CEQ|CEQI)_[BHWD]$")>; 1476def : InstRW<[GenericWriteFPUS], (instregex "^CMP_UN_(S|D)$")>; 1477def : InstRW<[GenericWriteFPUS], (instregex "^CMP_UEQ_(S|D)$")>; 1478def : InstRW<[GenericWriteFPUS], (instregex "^CMP_EQ_(S|D)$")>; 1479def : InstRW<[GenericWriteFPUS], (instregex "^CMP_LT_(S|D)$")>; 1480def : InstRW<[GenericWriteFPUS], (instregex "^CMP_ULT_(S|D)$")>; 1481def : InstRW<[GenericWriteFPUS], (instregex "^CMP_LE_(S|D)$")>; 1482def : InstRW<[GenericWriteFPUS], (instregex "^CMP_ULE_(S|D)$")>; 1483def : InstRW<[GenericWriteFPUS], (instregex "^CMP_F_(D|S)$")>; 1484def : InstRW<[GenericWriteFPUS], (instregex "^CMP_SAF_(D|S)$")>; 1485def : InstRW<[GenericWriteFPUS], (instregex "^CMP_SEQ_(D|S)$")>; 1486def : InstRW<[GenericWriteFPUS], (instregex "^CMP_SLE_(D|S)$")>; 1487def : InstRW<[GenericWriteFPUS], (instregex "^CMP_SLT_(D|S)$")>; 1488def : InstRW<[GenericWriteFPUS], (instregex "^CMP_SUEQ_(D|S)$")>; 1489def : InstRW<[GenericWriteFPUS], (instregex "^CMP_SULE_(D|S)$")>; 1490def : InstRW<[GenericWriteFPUS], (instregex "^CMP_SULT_(D|S)$")>; 1491def : InstRW<[GenericWriteFPUS], (instregex "^CMP_SUN_(D|S)$")>; 1492def : InstRW<[GenericWriteFPUS], (instregex "^FS(AF|EQ|LT|LE|NE|OR)_(W|D)$")>; 1493def : InstRW<[GenericWriteFPUS], (instregex "^FSUEQ_(W|D)$")>; 1494def : InstRW<[GenericWriteFPUS], (instregex "^FSULE_(W|D)$")>; 1495def : InstRW<[GenericWriteFPUS], (instregex "^FSULT_(W|D)$")>; 1496def : InstRW<[GenericWriteFPUS], (instregex "^FSUNE_(W|D)$")>; 1497def : InstRW<[GenericWriteFPUS], (instregex "^FSUN_(W|D)$")>; 1498def : InstRW<[GenericWriteFPUS], (instregex "^FCAF_(W|D)$")>; 1499def : InstRW<[GenericWriteFPUS], (instregex "^FCEQ_(W|D)$")>; 1500def : InstRW<[GenericWriteFPUS], (instregex "^FCLE_(W|D)$")>; 1501def : InstRW<[GenericWriteFPUS], (instregex "^FCLT_(W|D)$")>; 1502def : InstRW<[GenericWriteFPUS], (instregex "^FCNE_(W|D)$")>; 1503def : InstRW<[GenericWriteFPUS], (instregex "^FCOR_(W|D)$")>; 1504def : InstRW<[GenericWriteFPUS], (instregex "^FCUEQ_(W|D)$")>; 1505def : InstRW<[GenericWriteFPUS], (instregex "^FCULE_(W|D)$")>; 1506def : InstRW<[GenericWriteFPUS], (instregex "^FCULT_(W|D)$")>; 1507def : InstRW<[GenericWriteFPUS], (instregex "^FCUNE_(W|D)$")>; 1508def : InstRW<[GenericWriteFPUS], (instregex "^FCUN_(W|D)$")>; 1509def : InstRW<[GenericWriteFPUS], (instregex "^FABS_(W|D)$")>; 1510def : InstRW<[GenericWriteFPUS], (instregex "^FFINT_(U|S)_(W|D)$")>; 1511def : InstRW<[GenericWriteFPUS], (instregex "^FFQL_(W|D)$")>; 1512def : InstRW<[GenericWriteFPUS], (instregex "^FFQR_(W|D)$")>; 1513def : InstRW<[GenericWriteFPUS], (instregex "^FTINT_(U|S)_(W|D)$")>; 1514def : InstRW<[GenericWriteFPUS], (instregex "^FRINT_(W|D)$")>; 1515def : InstRW<[GenericWriteFPUS], (instregex "^FTQ_(H|W)$")>; 1516def : InstRW<[GenericWriteFPUS], (instregex "^FTRUNC_(U|S)_(W|D)$")>; 1517 1518// fexdo.[hw], fexupl.[wd], fexupr.[wd] 1519def : InstRW<[GenericWriteFPUS], (instregex "^FEXDO_(H|W)$")>; 1520def : InstRW<[GenericWriteFPUS], (instregex "^FEXUPL_(W|D)$")>; 1521def : InstRW<[GenericWriteFPUS], (instregex "^FEXUPR_(W|D)$")>; 1522 1523// fclass.[wd], fmax.[wd], fmax_a.[wd], fmin.[wd], fmin_a.[wd], flog2.[wd] 1524def : InstRW<[GenericWriteFPUS], (instregex "^FCLASS_(W|D)$")>; 1525def : InstRW<[GenericWriteFPUS], (instregex "^FMAX_A_(W|D)$")>; 1526def : InstRW<[GenericWriteFPUS], (instregex "^FMAX_(W|D)$")>; 1527def : InstRW<[GenericWriteFPUS], (instregex "^FMIN_A_(W|D)$")>; 1528def : InstRW<[GenericWriteFPUS], (instregex "^FMIN_(W|D)$")>; 1529def : InstRW<[GenericWriteFPUS], (instregex "^FLOG2_(W|D)$")>; 1530 1531// interleave right/left, interleave even/odd, insert 1532def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(ILVR|ILVL)_[BHWD]$")>; 1533def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(ILVEV|ILVOD)_[BHWD]$")>; 1534 1535// subs_?.[bhwd], subsus_?.[bhwd], subsuu_?.[bhwd], subvi.[bhwd], subv.[bhwd], 1536def : InstRW<[GenericWriteMSAShortInt], (instregex "^SUBS_(S|U)_[BHWD]$")>; 1537def : InstRW<[GenericWriteMSAShortInt], (instregex "^SUBSUS_(S|U)_[BHWD]$")>; 1538def : InstRW<[GenericWriteMSAShortInt], (instregex "^SUBSUU_(S|U)_[BHWD]$")>; 1539def : InstRW<[GenericWriteMSAShortInt], (instregex "^SUBVI_[BHWD]$")>; 1540def : InstRW<[GenericWriteMSAShortInt], (instregex "^SUBV_[BHWD]$")>; 1541 1542// mod_[su].[bhwd], div_[su].[bhwd] 1543def : InstRW<[GenericWriteFPUDivI], (instregex "^MOD_(S|U)_[BHWD]$")>; 1544def : InstRW<[GenericWriteFPUDivI], (instregex "^DIV_(S|U)_[BHWD]$")>; 1545 1546// hadd_[su].[bhwd], hsub_[su].[bhwd], max_[sua].[bhwd], min_[sua].[bhwd], 1547// maxi_[su].[bhwd], mini_[su].[bhwd], sra?.[bhwd], srar?.[bhwd], srlr.[bhwd], 1548// sll?.[bhwd], pckev.[bhwd], pckod.[bhwd], nloc.[bhwd], nlzc.[bhwd], 1549// insve.[bhwd] 1550def : InstRW<[GenericWriteMSAShortLogic], (instregex "^HADD_(S|U)_[BHWD]$")>; 1551def : InstRW<[GenericWriteMSAShortLogic], (instregex "^HSUB_(S|U)_[BHWD]$")>; 1552def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(MAX|MIN)_S_[BHWD]$")>; 1553def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(MAX|MIN)_U_[BHWD]$")>; 1554def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(MAX|MIN)_A_[BHWD]$")>; 1555def : InstRW<[GenericWriteMSAShortLogic], 1556 (instregex "^(MAXI|MINI)_(S|U)_[BHWD]$")>; 1557def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SRA|SRAI)_[BHWD]$")>; 1558def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SRL|SRLI)_[BHWD]$")>; 1559def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SRAR|SRARI)_[BHWD]$")>; 1560def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SRLR|SRLRI)_[BHWD]$")>; 1561def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SLL|SLLI)_[BHWD]$")>; 1562def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(PCKEV|PCKOD)_[BHWD]$")>; 1563def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(NLOC|NLZC)_[BHWD]$")>; 1564def : InstRW<[GenericWriteMSAShortLogic], (instregex "^INSVE_[BHWD]$")>; 1565def : InstRW<[GenericWriteMSAShortLogic], (instregex "^INSERT_F(D|W)_PSEUDO$")>; 1566def : InstRW<[GenericWriteMSAShortLogic], (instregex "^FILL_F(D|W)_PSEUDO$")>; 1567 1568// dpadd_?.[bhwd], dpsub_?.[bhwd], dotp_?.[bhwd], msubv.[bhwd], maddv.[bhwd] 1569// mulv.[bhwd]. 1570def : InstRW<[GenericWriteMSALongInt], (instregex "^DPADD_(S|U)_[HWD]$")>; 1571def : InstRW<[GenericWriteMSALongInt], (instregex "^DPSUB_(S|U)_[HWD]$")>; 1572def : InstRW<[GenericWriteMSALongInt], (instregex "^DOTP_(S|U)_[HWD]$")>; 1573def : InstRW<[GenericWriteMSALongInt], (instregex "^MSUBV_[BHWD]$")>; 1574def : InstRW<[GenericWriteMSALongInt], (instregex "^MADDV_[BHWD]$")>; 1575def : InstRW<[GenericWriteMSALongInt], (instregex "^MULV_[BHWD]$")>; 1576 1577// madd?.q.[hw], msub?.q.[hw], mul?.q.[hw] 1578def : InstRW<[GenericWriteMSALongInt], (instregex "^MADDR_Q_[HW]$")>; 1579def : InstRW<[GenericWriteMSALongInt], (instregex "^MADD_Q_[HW]$")>; 1580def : InstRW<[GenericWriteMSALongInt], (instregex "^MSUBR_Q_[HW]$")>; 1581def : InstRW<[GenericWriteMSALongInt], (instregex "^MSUB_Q_[HW]$")>; 1582def : InstRW<[GenericWriteMSALongInt], (instregex "^MULR_Q_[HW]$")>; 1583def : InstRW<[GenericWriteMSALongInt], (instregex "^MUL_Q_[HW]$")>; 1584 1585// fadd.[dw], fmadd.[dw], fmul.[dw], frcp.[dw], frsqrt.[dw], fsqrt.[dw] 1586// fsub.[dw], fdiv.[dw] 1587def : InstRW<[GenericWriteFPUL], (instregex "^FADD_[DW]$")>; 1588def : InstRW<[GenericWriteFPUL], (instregex "^FMADD_[DW]$")>; 1589def : InstRW<[GenericWriteFPUL], (instregex "^FMSUB_[DW]$")>; 1590def : InstRW<[GenericWriteFPUL], (instregex "^FMUL_[DW]$")>; 1591def : InstRW<[GenericWriteFPUL], (instregex "^FRCP_[DW]$")>; 1592def : InstRW<[GenericWriteFPUL], (instregex "^FRSQRT_[DW]$")>; 1593def : InstRW<[GenericWriteFPUL], (instregex "^FSQRT_[DW]$")>; 1594def : InstRW<[GenericWriteFPUL], (instregex "^FSUB_[DW]$")>; 1595def : InstRW<[GenericWriteFPUL], (instregex "^FDIV_[DW]$")>; 1596 1597// copy.[su]_[bhwd] 1598def : InstRW<[GenericWriteFPUMoveGPRFPU], (instregex "^COPY_U_[BHW]$")>; 1599def : InstRW<[GenericWriteFPUMoveGPRFPU], (instregex "^COPY_S_[BHWD]$")>; 1600 1601def : InstRW<[GenericWriteFPUStore], (instregex "^ST_[BHWD]$")>; 1602def : InstRW<[GenericWriteFPUStore], (instrs ST_F16)>; 1603def : InstRW<[GenericWriteFPULoad], (instregex "^LD_[BHWD]$")>; 1604def : InstRW<[GenericWriteFPULoad], (instrs LD_F16)>; 1605 1606// Atomic instructions 1607 1608// FIXME: Define `WriteAtomic` in the MipsSchedule.td and 1609// attach it to the Atomic2OpsPostRA, AtomicCmpSwapPostRA, ... 1610// classes. Then just define resources for the `WriteAtomic` in each 1611// machine models. 1612def GenericAtomic : ProcResource<1> { let BufferSize = 1; } 1613def GenericWriteAtomic : SchedWriteRes<[GenericAtomic]> { let Latency = 2; } 1614 1615def : InstRW<[GenericWriteAtomic], 1616 (instregex "^ATOMIC_SWAP_I(8|16|32|64)_POSTRA$")>; 1617def : InstRW<[GenericWriteAtomic], 1618 (instregex "^ATOMIC_CMP_SWAP_I(8|16|32|64)_POSTRA$")>; 1619def : InstRW<[GenericWriteAtomic], 1620 (instregex "^ATOMIC_LOAD_(ADD|SUB|AND|OR|XOR|NAND|MIN|MAX|UMIN|UMAX)" 1621 "_I(8|16|32|64)_POSTRA$")>; 1622} 1623