xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp (revision c66ec88fed842fbaad62c30d510644ceb7bd2d71)
1 //===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Mips32/64 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsSEInstrInfo.h"
14 #include "MCTargetDesc/MipsInstPrinter.h"
15 #include "MipsAnalyzeImmediate.h"
16 #include "MipsMachineFunction.h"
17 #include "MipsTargetMachine.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/TargetRegistry.h"
24 
25 using namespace llvm;
26 
27 static unsigned getUnconditionalBranch(const MipsSubtarget &STI) {
28   if (STI.inMicroMipsMode())
29     return STI.isPositionIndependent() ? Mips::B_MM : Mips::J_MM;
30   return STI.isPositionIndependent() ? Mips::B : Mips::J;
31 }
32 
33 MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI)
34     : MipsInstrInfo(STI, getUnconditionalBranch(STI)), RI() {}
35 
36 const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
37   return RI;
38 }
39 
40 /// isLoadFromStackSlot - If the specified machine instruction is a direct
41 /// load from a stack slot, return the virtual or physical register number of
42 /// the destination along with the FrameIndex of the loaded stack slot.  If
43 /// not, return 0.  This predicate must return 0 if the instruction has
44 /// any side effects other than loading from the stack slot.
45 unsigned MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
46                                               int &FrameIndex) const {
47   unsigned Opc = MI.getOpcode();
48 
49   if ((Opc == Mips::LW)   || (Opc == Mips::LD)   ||
50       (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
51     if ((MI.getOperand(1).isFI()) &&  // is a stack slot
52         (MI.getOperand(2).isImm()) && // the imm is zero
53         (isZeroImm(MI.getOperand(2)))) {
54       FrameIndex = MI.getOperand(1).getIndex();
55       return MI.getOperand(0).getReg();
56     }
57   }
58 
59   return 0;
60 }
61 
62 /// isStoreToStackSlot - If the specified machine instruction is a direct
63 /// store to a stack slot, return the virtual or physical register number of
64 /// the source reg along with the FrameIndex of the loaded stack slot.  If
65 /// not, return 0.  This predicate must return 0 if the instruction has
66 /// any side effects other than storing to the stack slot.
67 unsigned MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
68                                              int &FrameIndex) const {
69   unsigned Opc = MI.getOpcode();
70 
71   if ((Opc == Mips::SW)   || (Opc == Mips::SD)   ||
72       (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
73     if ((MI.getOperand(1).isFI()) &&  // is a stack slot
74         (MI.getOperand(2).isImm()) && // the imm is zero
75         (isZeroImm(MI.getOperand(2)))) {
76       FrameIndex = MI.getOperand(1).getIndex();
77       return MI.getOperand(0).getReg();
78     }
79   }
80   return 0;
81 }
82 
83 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
84                                   MachineBasicBlock::iterator I,
85                                   const DebugLoc &DL, MCRegister DestReg,
86                                   MCRegister SrcReg, bool KillSrc) const {
87   unsigned Opc = 0, ZeroReg = 0;
88   bool isMicroMips = Subtarget.inMicroMipsMode();
89 
90   if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
91     if (Mips::GPR32RegClass.contains(SrcReg)) {
92       if (isMicroMips)
93         Opc = Mips::MOVE16_MM;
94       else
95         Opc = Mips::OR, ZeroReg = Mips::ZERO;
96     } else if (Mips::CCRRegClass.contains(SrcReg))
97       Opc = Mips::CFC1;
98     else if (Mips::FGR32RegClass.contains(SrcReg))
99       Opc = Mips::MFC1;
100     else if (Mips::HI32RegClass.contains(SrcReg)) {
101       Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
102       SrcReg = 0;
103     } else if (Mips::LO32RegClass.contains(SrcReg)) {
104       Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
105       SrcReg = 0;
106     } else if (Mips::HI32DSPRegClass.contains(SrcReg))
107       Opc = Mips::MFHI_DSP;
108     else if (Mips::LO32DSPRegClass.contains(SrcReg))
109       Opc = Mips::MFLO_DSP;
110     else if (Mips::DSPCCRegClass.contains(SrcReg)) {
111       BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
112         .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
113       return;
114     }
115     else if (Mips::MSACtrlRegClass.contains(SrcReg))
116       Opc = Mips::CFCMSA;
117   }
118   else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
119     if (Mips::CCRRegClass.contains(DestReg))
120       Opc = Mips::CTC1;
121     else if (Mips::FGR32RegClass.contains(DestReg))
122       Opc = Mips::MTC1;
123     else if (Mips::HI32RegClass.contains(DestReg))
124       Opc = Mips::MTHI, DestReg = 0;
125     else if (Mips::LO32RegClass.contains(DestReg))
126       Opc = Mips::MTLO, DestReg = 0;
127     else if (Mips::HI32DSPRegClass.contains(DestReg))
128       Opc = Mips::MTHI_DSP;
129     else if (Mips::LO32DSPRegClass.contains(DestReg))
130       Opc = Mips::MTLO_DSP;
131     else if (Mips::DSPCCRegClass.contains(DestReg)) {
132       BuildMI(MBB, I, DL, get(Mips::WRDSP))
133         .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
134         .addReg(DestReg, RegState::ImplicitDefine);
135       return;
136     } else if (Mips::MSACtrlRegClass.contains(DestReg)) {
137       BuildMI(MBB, I, DL, get(Mips::CTCMSA))
138           .addReg(DestReg)
139           .addReg(SrcReg, getKillRegState(KillSrc));
140       return;
141     }
142   }
143   else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
144     Opc = Mips::FMOV_S;
145   else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
146     Opc = Mips::FMOV_D32;
147   else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
148     Opc = Mips::FMOV_D64;
149   else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
150     if (Mips::GPR64RegClass.contains(SrcReg))
151       Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
152     else if (Mips::HI64RegClass.contains(SrcReg))
153       Opc = Mips::MFHI64, SrcReg = 0;
154     else if (Mips::LO64RegClass.contains(SrcReg))
155       Opc = Mips::MFLO64, SrcReg = 0;
156     else if (Mips::FGR64RegClass.contains(SrcReg))
157       Opc = Mips::DMFC1;
158   }
159   else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
160     if (Mips::HI64RegClass.contains(DestReg))
161       Opc = Mips::MTHI64, DestReg = 0;
162     else if (Mips::LO64RegClass.contains(DestReg))
163       Opc = Mips::MTLO64, DestReg = 0;
164     else if (Mips::FGR64RegClass.contains(DestReg))
165       Opc = Mips::DMTC1;
166   }
167   else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
168     if (Mips::MSA128BRegClass.contains(SrcReg))
169       Opc = Mips::MOVE_V;
170   }
171 
172   assert(Opc && "Cannot copy registers");
173 
174   MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
175 
176   if (DestReg)
177     MIB.addReg(DestReg, RegState::Define);
178 
179   if (SrcReg)
180     MIB.addReg(SrcReg, getKillRegState(KillSrc));
181 
182   if (ZeroReg)
183     MIB.addReg(ZeroReg);
184 }
185 
186 static bool isORCopyInst(const MachineInstr &MI) {
187   switch (MI.getOpcode()) {
188   default:
189     break;
190   case Mips::OR_MM:
191   case Mips::OR:
192     if (MI.getOperand(2).getReg() == Mips::ZERO)
193       return true;
194     break;
195   case Mips::OR64:
196     if (MI.getOperand(2).getReg() == Mips::ZERO_64)
197       return true;
198     break;
199   }
200   return false;
201 }
202 
203 /// If @MI is WRDSP/RRDSP instruction return true with @isWrite set to true
204 /// if it is WRDSP instruction.
205 static bool isReadOrWriteToDSPReg(const MachineInstr &MI, bool &isWrite) {
206   switch (MI.getOpcode()) {
207   default:
208    return false;
209   case Mips::WRDSP:
210   case Mips::WRDSP_MM:
211     isWrite = true;
212     break;
213   case Mips::RDDSP:
214   case Mips::RDDSP_MM:
215     isWrite = false;
216     break;
217   }
218   return true;
219 }
220 
221 /// We check for the common case of 'or', as it's MIPS' preferred instruction
222 /// for GPRs but we have to check the operands to ensure that is the case.
223 /// Other move instructions for MIPS are directly identifiable.
224 Optional<DestSourcePair>
225 MipsSEInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
226   bool isDSPControlWrite = false;
227   // Condition is made to match the creation of WRDSP/RDDSP copy instruction
228   // from copyPhysReg function.
229   if (isReadOrWriteToDSPReg(MI, isDSPControlWrite)) {
230     if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != (1 << 4))
231       return None;
232     else if (isDSPControlWrite) {
233       return DestSourcePair{MI.getOperand(2), MI.getOperand(0)};
234 
235     } else {
236       return DestSourcePair{MI.getOperand(0), MI.getOperand(2)};
237     }
238   } else if (MI.isMoveReg() || isORCopyInst(MI)) {
239     return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
240   }
241   return None;
242 }
243 
244 void MipsSEInstrInfo::
245 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
246                 Register SrcReg, bool isKill, int FI,
247                 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
248                 int64_t Offset) const {
249   DebugLoc DL;
250   MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
251 
252   unsigned Opc = 0;
253 
254   if (Mips::GPR32RegClass.hasSubClassEq(RC))
255     Opc = Mips::SW;
256   else if (Mips::GPR64RegClass.hasSubClassEq(RC))
257     Opc = Mips::SD;
258   else if (Mips::ACC64RegClass.hasSubClassEq(RC))
259     Opc = Mips::STORE_ACC64;
260   else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
261     Opc = Mips::STORE_ACC64DSP;
262   else if (Mips::ACC128RegClass.hasSubClassEq(RC))
263     Opc = Mips::STORE_ACC128;
264   else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
265     Opc = Mips::STORE_CCOND_DSP;
266   else if (Mips::FGR32RegClass.hasSubClassEq(RC))
267     Opc = Mips::SWC1;
268   else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
269     Opc = Mips::SDC1;
270   else if (Mips::FGR64RegClass.hasSubClassEq(RC))
271     Opc = Mips::SDC164;
272   else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
273     Opc = Mips::ST_B;
274   else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
275            TRI->isTypeLegalForClass(*RC, MVT::v8f16))
276     Opc = Mips::ST_H;
277   else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
278            TRI->isTypeLegalForClass(*RC, MVT::v4f32))
279     Opc = Mips::ST_W;
280   else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
281            TRI->isTypeLegalForClass(*RC, MVT::v2f64))
282     Opc = Mips::ST_D;
283   else if (Mips::LO32RegClass.hasSubClassEq(RC))
284     Opc = Mips::SW;
285   else if (Mips::LO64RegClass.hasSubClassEq(RC))
286     Opc = Mips::SD;
287   else if (Mips::HI32RegClass.hasSubClassEq(RC))
288     Opc = Mips::SW;
289   else if (Mips::HI64RegClass.hasSubClassEq(RC))
290     Opc = Mips::SD;
291   else if (Mips::DSPRRegClass.hasSubClassEq(RC))
292     Opc = Mips::SWDSP;
293 
294   // Hi, Lo are normally caller save but they are callee save
295   // for interrupt handling.
296   const Function &Func = MBB.getParent()->getFunction();
297   if (Func.hasFnAttribute("interrupt")) {
298     if (Mips::HI32RegClass.hasSubClassEq(RC)) {
299       BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);
300       SrcReg = Mips::K0;
301     } else if (Mips::HI64RegClass.hasSubClassEq(RC)) {
302       BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64);
303       SrcReg = Mips::K0_64;
304     } else if (Mips::LO32RegClass.hasSubClassEq(RC)) {
305       BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0);
306       SrcReg = Mips::K0;
307     } else if (Mips::LO64RegClass.hasSubClassEq(RC)) {
308       BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64);
309       SrcReg = Mips::K0_64;
310     }
311   }
312 
313   assert(Opc && "Register class not handled!");
314   BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
315     .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
316 }
317 
318 void MipsSEInstrInfo::
319 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
320                  Register DestReg, int FI, const TargetRegisterClass *RC,
321                  const TargetRegisterInfo *TRI, int64_t Offset) const {
322   DebugLoc DL;
323   if (I != MBB.end()) DL = I->getDebugLoc();
324   MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
325   unsigned Opc = 0;
326 
327   const Function &Func = MBB.getParent()->getFunction();
328   bool ReqIndirectLoad = Func.hasFnAttribute("interrupt") &&
329                          (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 ||
330                           DestReg == Mips::HI0 || DestReg == Mips::HI0_64);
331 
332   if (Mips::GPR32RegClass.hasSubClassEq(RC))
333     Opc = Mips::LW;
334   else if (Mips::GPR64RegClass.hasSubClassEq(RC))
335     Opc = Mips::LD;
336   else if (Mips::ACC64RegClass.hasSubClassEq(RC))
337     Opc = Mips::LOAD_ACC64;
338   else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
339     Opc = Mips::LOAD_ACC64DSP;
340   else if (Mips::ACC128RegClass.hasSubClassEq(RC))
341     Opc = Mips::LOAD_ACC128;
342   else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
343     Opc = Mips::LOAD_CCOND_DSP;
344   else if (Mips::FGR32RegClass.hasSubClassEq(RC))
345     Opc = Mips::LWC1;
346   else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
347     Opc = Mips::LDC1;
348   else if (Mips::FGR64RegClass.hasSubClassEq(RC))
349     Opc = Mips::LDC164;
350   else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
351     Opc = Mips::LD_B;
352   else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
353            TRI->isTypeLegalForClass(*RC, MVT::v8f16))
354     Opc = Mips::LD_H;
355   else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
356            TRI->isTypeLegalForClass(*RC, MVT::v4f32))
357     Opc = Mips::LD_W;
358   else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
359            TRI->isTypeLegalForClass(*RC, MVT::v2f64))
360     Opc = Mips::LD_D;
361   else if (Mips::HI32RegClass.hasSubClassEq(RC))
362     Opc = Mips::LW;
363   else if (Mips::HI64RegClass.hasSubClassEq(RC))
364     Opc = Mips::LD;
365   else if (Mips::LO32RegClass.hasSubClassEq(RC))
366     Opc = Mips::LW;
367   else if (Mips::LO64RegClass.hasSubClassEq(RC))
368     Opc = Mips::LD;
369   else if (Mips::DSPRRegClass.hasSubClassEq(RC))
370     Opc = Mips::LWDSP;
371 
372   assert(Opc && "Register class not handled!");
373 
374   if (!ReqIndirectLoad)
375     BuildMI(MBB, I, DL, get(Opc), DestReg)
376         .addFrameIndex(FI)
377         .addImm(Offset)
378         .addMemOperand(MMO);
379   else {
380     // Load HI/LO through K0. Notably the DestReg is encoded into the
381     // instruction itself.
382     unsigned Reg = Mips::K0;
383     unsigned LdOp = Mips::MTLO;
384     if (DestReg == Mips::HI0)
385       LdOp = Mips::MTHI;
386 
387     if (Subtarget.getABI().ArePtrs64bit()) {
388       Reg = Mips::K0_64;
389       if (DestReg == Mips::HI0_64)
390         LdOp = Mips::MTHI64;
391       else
392         LdOp = Mips::MTLO64;
393     }
394 
395     BuildMI(MBB, I, DL, get(Opc), Reg)
396         .addFrameIndex(FI)
397         .addImm(Offset)
398         .addMemOperand(MMO);
399     BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg);
400   }
401 }
402 
403 bool MipsSEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
404   MachineBasicBlock &MBB = *MI.getParent();
405   bool isMicroMips = Subtarget.inMicroMipsMode();
406   unsigned Opc;
407 
408   switch (MI.getDesc().getOpcode()) {
409   default:
410     return false;
411   case Mips::RetRA:
412     expandRetRA(MBB, MI);
413     break;
414   case Mips::ERet:
415     expandERet(MBB, MI);
416     break;
417   case Mips::PseudoMFHI:
418     expandPseudoMFHiLo(MBB, MI, Mips::MFHI);
419     break;
420   case Mips::PseudoMFHI_MM:
421     expandPseudoMFHiLo(MBB, MI, Mips::MFHI16_MM);
422     break;
423   case Mips::PseudoMFLO:
424     expandPseudoMFHiLo(MBB, MI, Mips::MFLO);
425     break;
426   case Mips::PseudoMFLO_MM:
427     expandPseudoMFHiLo(MBB, MI, Mips::MFLO16_MM);
428     break;
429   case Mips::PseudoMFHI64:
430     expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);
431     break;
432   case Mips::PseudoMFLO64:
433     expandPseudoMFHiLo(MBB, MI, Mips::MFLO64);
434     break;
435   case Mips::PseudoMTLOHI:
436     expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false);
437     break;
438   case Mips::PseudoMTLOHI64:
439     expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false);
440     break;
441   case Mips::PseudoMTLOHI_DSP:
442     expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true);
443     break;
444   case Mips::PseudoMTLOHI_MM:
445     expandPseudoMTLoHi(MBB, MI, Mips::MTLO_MM, Mips::MTHI_MM, false);
446     break;
447   case Mips::PseudoCVT_S_W:
448     expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
449     break;
450   case Mips::PseudoCVT_D32_W:
451     Opc = isMicroMips ? Mips::CVT_D32_W_MM : Mips::CVT_D32_W;
452     expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false);
453     break;
454   case Mips::PseudoCVT_S_L:
455     expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
456     break;
457   case Mips::PseudoCVT_D64_W:
458     Opc = isMicroMips ? Mips::CVT_D64_W_MM : Mips::CVT_D64_W;
459     expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true);
460     break;
461   case Mips::PseudoCVT_D64_L:
462     expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
463     break;
464   case Mips::BuildPairF64:
465     expandBuildPairF64(MBB, MI, isMicroMips, false);
466     break;
467   case Mips::BuildPairF64_64:
468     expandBuildPairF64(MBB, MI, isMicroMips, true);
469     break;
470   case Mips::ExtractElementF64:
471     expandExtractElementF64(MBB, MI, isMicroMips, false);
472     break;
473   case Mips::ExtractElementF64_64:
474     expandExtractElementF64(MBB, MI, isMicroMips, true);
475     break;
476   case Mips::MIPSeh_return32:
477   case Mips::MIPSeh_return64:
478     expandEhReturn(MBB, MI);
479     break;
480   }
481 
482   MBB.erase(MI);
483   return true;
484 }
485 
486 /// isBranchWithImm - Return true if the branch contains an immediate
487 /// operand (\see lib/Target/Mips/MipsBranchExpansion.cpp).
488 bool MipsSEInstrInfo::isBranchWithImm(unsigned Opc) const {
489   switch (Opc) {
490   default:
491     return false;
492   case Mips::BBIT0:
493   case Mips::BBIT1:
494   case Mips::BBIT032:
495   case Mips::BBIT132:
496     return true;
497   }
498 }
499 
500 /// getOppositeBranchOpc - Return the inverse of the specified
501 /// opcode, e.g. turning BEQ to BNE.
502 unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
503   switch (Opc) {
504   default:           llvm_unreachable("Illegal opcode!");
505   case Mips::BEQ:    return Mips::BNE;
506   case Mips::BEQ_MM: return Mips::BNE_MM;
507   case Mips::BNE:    return Mips::BEQ;
508   case Mips::BNE_MM: return Mips::BEQ_MM;
509   case Mips::BGTZ:   return Mips::BLEZ;
510   case Mips::BGEZ:   return Mips::BLTZ;
511   case Mips::BLTZ:   return Mips::BGEZ;
512   case Mips::BLEZ:   return Mips::BGTZ;
513   case Mips::BGTZ_MM:   return Mips::BLEZ_MM;
514   case Mips::BGEZ_MM:   return Mips::BLTZ_MM;
515   case Mips::BLTZ_MM:   return Mips::BGEZ_MM;
516   case Mips::BLEZ_MM:   return Mips::BGTZ_MM;
517   case Mips::BEQ64:  return Mips::BNE64;
518   case Mips::BNE64:  return Mips::BEQ64;
519   case Mips::BGTZ64: return Mips::BLEZ64;
520   case Mips::BGEZ64: return Mips::BLTZ64;
521   case Mips::BLTZ64: return Mips::BGEZ64;
522   case Mips::BLEZ64: return Mips::BGTZ64;
523   case Mips::BC1T:   return Mips::BC1F;
524   case Mips::BC1F:   return Mips::BC1T;
525   case Mips::BC1T_MM:   return Mips::BC1F_MM;
526   case Mips::BC1F_MM:   return Mips::BC1T_MM;
527   case Mips::BEQZ16_MM: return Mips::BNEZ16_MM;
528   case Mips::BNEZ16_MM: return Mips::BEQZ16_MM;
529   case Mips::BEQZC_MM:  return Mips::BNEZC_MM;
530   case Mips::BNEZC_MM:  return Mips::BEQZC_MM;
531   case Mips::BEQZC:  return Mips::BNEZC;
532   case Mips::BNEZC:  return Mips::BEQZC;
533   case Mips::BLEZC:  return Mips::BGTZC;
534   case Mips::BGEZC:  return Mips::BLTZC;
535   case Mips::BGEC:   return Mips::BLTC;
536   case Mips::BGTZC:  return Mips::BLEZC;
537   case Mips::BLTZC:  return Mips::BGEZC;
538   case Mips::BLTC:   return Mips::BGEC;
539   case Mips::BGEUC:  return Mips::BLTUC;
540   case Mips::BLTUC:  return Mips::BGEUC;
541   case Mips::BEQC:   return Mips::BNEC;
542   case Mips::BNEC:   return Mips::BEQC;
543   case Mips::BC1EQZ: return Mips::BC1NEZ;
544   case Mips::BC1NEZ: return Mips::BC1EQZ;
545   case Mips::BEQZC_MMR6:  return Mips::BNEZC_MMR6;
546   case Mips::BNEZC_MMR6:  return Mips::BEQZC_MMR6;
547   case Mips::BLEZC_MMR6:  return Mips::BGTZC_MMR6;
548   case Mips::BGEZC_MMR6:  return Mips::BLTZC_MMR6;
549   case Mips::BGEC_MMR6:   return Mips::BLTC_MMR6;
550   case Mips::BGTZC_MMR6:  return Mips::BLEZC_MMR6;
551   case Mips::BLTZC_MMR6:  return Mips::BGEZC_MMR6;
552   case Mips::BLTC_MMR6:   return Mips::BGEC_MMR6;
553   case Mips::BGEUC_MMR6:  return Mips::BLTUC_MMR6;
554   case Mips::BLTUC_MMR6:  return Mips::BGEUC_MMR6;
555   case Mips::BEQC_MMR6:   return Mips::BNEC_MMR6;
556   case Mips::BNEC_MMR6:   return Mips::BEQC_MMR6;
557   case Mips::BC1EQZC_MMR6: return Mips::BC1NEZC_MMR6;
558   case Mips::BC1NEZC_MMR6: return Mips::BC1EQZC_MMR6;
559   case Mips::BEQZC64:  return Mips::BNEZC64;
560   case Mips::BNEZC64:  return Mips::BEQZC64;
561   case Mips::BEQC64:   return Mips::BNEC64;
562   case Mips::BNEC64:   return Mips::BEQC64;
563   case Mips::BGEC64:   return Mips::BLTC64;
564   case Mips::BGEUC64:  return Mips::BLTUC64;
565   case Mips::BLTC64:   return Mips::BGEC64;
566   case Mips::BLTUC64:  return Mips::BGEUC64;
567   case Mips::BGTZC64:  return Mips::BLEZC64;
568   case Mips::BGEZC64:  return Mips::BLTZC64;
569   case Mips::BLTZC64:  return Mips::BGEZC64;
570   case Mips::BLEZC64:  return Mips::BGTZC64;
571   case Mips::BBIT0:  return Mips::BBIT1;
572   case Mips::BBIT1:  return Mips::BBIT0;
573   case Mips::BBIT032:  return Mips::BBIT132;
574   case Mips::BBIT132:  return Mips::BBIT032;
575   case Mips::BZ_B:   return Mips::BNZ_B;
576   case Mips::BZ_H:   return Mips::BNZ_H;
577   case Mips::BZ_W:   return Mips::BNZ_W;
578   case Mips::BZ_D:   return Mips::BNZ_D;
579   case Mips::BZ_V:   return Mips::BNZ_V;
580   case Mips::BNZ_B:  return Mips::BZ_B;
581   case Mips::BNZ_H:  return Mips::BZ_H;
582   case Mips::BNZ_W:  return Mips::BZ_W;
583   case Mips::BNZ_D:  return Mips::BZ_D;
584   case Mips::BNZ_V:  return Mips::BZ_V;
585   }
586 }
587 
588 /// Adjust SP by Amount bytes.
589 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
590                                      MachineBasicBlock &MBB,
591                                      MachineBasicBlock::iterator I) const {
592   MipsABIInfo ABI = Subtarget.getABI();
593   DebugLoc DL;
594   unsigned ADDiu = ABI.GetPtrAddiuOp();
595 
596   if (Amount == 0)
597     return;
598 
599   if (isInt<16>(Amount)) {
600     // addi sp, sp, amount
601     BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
602   } else {
603     // For numbers which are not 16bit integers we synthesize Amount inline
604     // then add or subtract it from sp.
605     unsigned Opc = ABI.GetPtrAdduOp();
606     if (Amount < 0) {
607       Opc = ABI.GetPtrSubuOp();
608       Amount = -Amount;
609     }
610     unsigned Reg = loadImmediate(Amount, MBB, I, DL, nullptr);
611     BuildMI(MBB, I, DL, get(Opc), SP).addReg(SP).addReg(Reg, RegState::Kill);
612   }
613 }
614 
615 /// This function generates the sequence of instructions needed to get the
616 /// result of adding register REG and immediate IMM.
617 unsigned MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
618                                         MachineBasicBlock::iterator II,
619                                         const DebugLoc &DL,
620                                         unsigned *NewImm) const {
621   MipsAnalyzeImmediate AnalyzeImm;
622   const MipsSubtarget &STI = Subtarget;
623   MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
624   unsigned Size = STI.isABI_N64() ? 64 : 32;
625   unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
626   unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
627   const TargetRegisterClass *RC = STI.isABI_N64() ?
628     &Mips::GPR64RegClass : &Mips::GPR32RegClass;
629   bool LastInstrIsADDiu = NewImm;
630 
631   const MipsAnalyzeImmediate::InstSeq &Seq =
632     AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
633   MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
634 
635   assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
636 
637   // The first instruction can be a LUi, which is different from other
638   // instructions (ADDiu, ORI and SLL) in that it does not have a register
639   // operand.
640   Register Reg = RegInfo.createVirtualRegister(RC);
641 
642   if (Inst->Opc == LUi)
643     BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
644   else
645     BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
646       .addImm(SignExtend64<16>(Inst->ImmOpnd));
647 
648   // Build the remaining instructions in Seq.
649   for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
650     BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
651       .addImm(SignExtend64<16>(Inst->ImmOpnd));
652 
653   if (LastInstrIsADDiu)
654     *NewImm = Inst->ImmOpnd;
655 
656   return Reg;
657 }
658 
659 unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
660   return (Opc == Mips::BEQ    || Opc == Mips::BEQ_MM || Opc == Mips::BNE    ||
661           Opc == Mips::BNE_MM || Opc == Mips::BGTZ   || Opc == Mips::BGEZ   ||
662           Opc == Mips::BLTZ   || Opc == Mips::BLEZ   || Opc == Mips::BEQ64  ||
663           Opc == Mips::BNE64  || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 ||
664           Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T   ||
665           Opc == Mips::BC1F   || Opc == Mips::B      || Opc == Mips::J      ||
666           Opc == Mips::J_MM   || Opc == Mips::B_MM   || Opc == Mips::BEQZC_MM ||
667           Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || Opc == Mips::BNEC   ||
668           Opc == Mips::BLTC   || Opc == Mips::BGEC   || Opc == Mips::BLTUC  ||
669           Opc == Mips::BGEUC  || Opc == Mips::BGTZC  || Opc == Mips::BLEZC  ||
670           Opc == Mips::BGEZC  || Opc == Mips::BLTZC  || Opc == Mips::BEQZC  ||
671           Opc == Mips::BNEZC  || Opc == Mips::BEQZC64 || Opc == Mips::BNEZC64 ||
672           Opc == Mips::BEQC64 || Opc == Mips::BNEC64 || Opc == Mips::BGEC64 ||
673           Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 || Opc == Mips::BLTUC64 ||
674           Opc == Mips::BGTZC64 || Opc == Mips::BGEZC64 ||
675           Opc == Mips::BLTZC64 || Opc == Mips::BLEZC64 || Opc == Mips::BC ||
676           Opc == Mips::BBIT0 || Opc == Mips::BBIT1 || Opc == Mips::BBIT032 ||
677           Opc == Mips::BBIT132 ||  Opc == Mips::BC_MMR6 ||
678           Opc == Mips::BEQC_MMR6 || Opc == Mips::BNEC_MMR6 ||
679           Opc == Mips::BLTC_MMR6 || Opc == Mips::BGEC_MMR6 ||
680           Opc == Mips::BLTUC_MMR6 || Opc == Mips::BGEUC_MMR6 ||
681           Opc == Mips::BGTZC_MMR6 || Opc == Mips::BLEZC_MMR6 ||
682           Opc == Mips::BGEZC_MMR6 || Opc == Mips::BLTZC_MMR6 ||
683           Opc == Mips::BEQZC_MMR6 || Opc == Mips::BNEZC_MMR6) ? Opc : 0;
684 }
685 
686 void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
687                                   MachineBasicBlock::iterator I) const {
688 
689   MachineInstrBuilder MIB;
690   if (Subtarget.isGP64bit())
691     MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
692               .addReg(Mips::RA_64, RegState::Undef);
693   else
694     MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn))
695               .addReg(Mips::RA, RegState::Undef);
696 
697   // Retain any imp-use flags.
698   for (auto & MO : I->operands()) {
699     if (MO.isImplicit())
700       MIB.add(MO);
701   }
702 }
703 
704 void MipsSEInstrInfo::expandERet(MachineBasicBlock &MBB,
705                                  MachineBasicBlock::iterator I) const {
706   BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET));
707 }
708 
709 std::pair<bool, bool>
710 MipsSEInstrInfo::compareOpndSize(unsigned Opc,
711                                  const MachineFunction &MF) const {
712   const MCInstrDesc &Desc = get(Opc);
713   assert(Desc.NumOperands == 2 && "Unary instruction expected.");
714   const MipsRegisterInfo *RI = &getRegisterInfo();
715   unsigned DstRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 0, RI, MF));
716   unsigned SrcRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 1, RI, MF));
717 
718   return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
719 }
720 
721 void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB,
722                                          MachineBasicBlock::iterator I,
723                                          unsigned NewOpc) const {
724   BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
725 }
726 
727 void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB,
728                                          MachineBasicBlock::iterator I,
729                                          unsigned LoOpc,
730                                          unsigned HiOpc,
731                                          bool HasExplicitDef) const {
732   // Expand
733   //  lo_hi pseudomtlohi $gpr0, $gpr1
734   // to these two instructions:
735   //  mtlo $gpr0
736   //  mthi $gpr1
737 
738   DebugLoc DL = I->getDebugLoc();
739   const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
740   MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc));
741   MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc));
742 
743   // Add lo/hi registers if the mtlo/hi instructions created have explicit
744   // def registers.
745   if (HasExplicitDef) {
746     Register DstReg = I->getOperand(0).getReg();
747     Register DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
748     Register DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
749     LoInst.addReg(DstLo, RegState::Define);
750     HiInst.addReg(DstHi, RegState::Define);
751   }
752 
753   LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
754   HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
755 }
756 
757 void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
758                                      MachineBasicBlock::iterator I,
759                                      unsigned CvtOpc, unsigned MovOpc,
760                                      bool IsI64) const {
761   const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
762   const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
763   unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
764   unsigned KillSrc =  getKillRegState(Src.isKill());
765   DebugLoc DL = I->getDebugLoc();
766   bool DstIsLarger, SrcIsLarger;
767 
768   std::tie(DstIsLarger, SrcIsLarger) =
769       compareOpndSize(CvtOpc, *MBB.getParent());
770 
771   if (DstIsLarger)
772     TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
773 
774   if (SrcIsLarger)
775     DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
776 
777   BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
778   BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
779 }
780 
781 void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
782                                               MachineBasicBlock::iterator I,
783                                               bool isMicroMips,
784                                               bool FP64) const {
785   Register DstReg = I->getOperand(0).getReg();
786   Register SrcReg = I->getOperand(1).getReg();
787   unsigned N = I->getOperand(2).getImm();
788   DebugLoc dl = I->getDebugLoc();
789 
790   assert(N < 2 && "Invalid immediate");
791   unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
792   Register SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
793 
794   // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
795   // in MipsSEFrameLowering.cpp.
796   assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
797 
798   // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
799   // in MipsSEFrameLowering.cpp.
800   assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg()));
801 
802   if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) {
803     // FIXME: Strictly speaking MFHC1 only reads the top 32-bits however, we
804     //        claim to read the whole 64-bits as part of a white lie used to
805     //        temporarily work around a widespread bug in the -mfp64 support.
806     //        The problem is that none of the 32-bit fpu ops mention the fact
807     //        that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
808     //        requires a major overhaul of the FPU implementation which can't
809     //        be done right now due to time constraints.
810     //        MFHC1 is one of two instructions that are affected since they are
811     //        the only instructions that don't read the lower 32-bits.
812     //        We therefore pretend that it reads the bottom 32-bits to
813     //        artificially create a dependency and prevent the scheduler
814     //        changing the behaviour of the code.
815     BuildMI(MBB, I, dl,
816             get(isMicroMips ? (FP64 ? Mips::MFHC1_D64_MM : Mips::MFHC1_D32_MM)
817                             : (FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32)),
818             DstReg)
819         .addReg(SrcReg);
820   } else
821     BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
822 }
823 
824 void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
825                                          MachineBasicBlock::iterator I,
826                                          bool isMicroMips, bool FP64) const {
827   Register DstReg = I->getOperand(0).getReg();
828   unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
829   const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
830   DebugLoc dl = I->getDebugLoc();
831   const TargetRegisterInfo &TRI = getRegisterInfo();
832 
833   // When mthc1 is available, use:
834   //   mtc1 Lo, $fp
835   //   mthc1 Hi, $fp
836   //
837   // Otherwise, for O32 FPXX ABI:
838   //   spill + reload via ldc1
839   // This case is handled by the frame lowering code.
840   //
841   // Otherwise, for FP32:
842   //   mtc1 Lo, $fp
843   //   mtc1 Hi, $fp + 1
844   //
845   // The case where dmtc1 is available doesn't need to be handled here
846   // because it never creates a BuildPairF64 node.
847 
848   // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
849   // in MipsSEFrameLowering.cpp.
850   assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
851 
852   // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
853   // in MipsSEFrameLowering.cpp.
854   assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg()));
855 
856   BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
857     .addReg(LoReg);
858 
859   if (Subtarget.hasMTHC1()) {
860     // FIXME: The .addReg(DstReg) is a white lie used to temporarily work
861     //        around a widespread bug in the -mfp64 support.
862     //        The problem is that none of the 32-bit fpu ops mention the fact
863     //        that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
864     //        requires a major overhaul of the FPU implementation which can't
865     //        be done right now due to time constraints.
866     //        MTHC1 is one of two instructions that are affected since they are
867     //        the only instructions that don't read the lower 32-bits.
868     //        We therefore pretend that it reads the bottom 32-bits to
869     //        artificially create a dependency and prevent the scheduler
870     //        changing the behaviour of the code.
871     BuildMI(MBB, I, dl,
872             get(isMicroMips ? (FP64 ? Mips::MTHC1_D64_MM : Mips::MTHC1_D32_MM)
873                             : (FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32)),
874             DstReg)
875         .addReg(DstReg)
876         .addReg(HiReg);
877   } else if (Subtarget.isABI_FPXX())
878     llvm_unreachable("BuildPairF64 not expanded in frame lowering code!");
879   else
880     BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
881       .addReg(HiReg);
882 }
883 
884 void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
885                                      MachineBasicBlock::iterator I) const {
886   // This pseudo instruction is generated as part of the lowering of
887   // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
888   // indirect jump to TargetReg
889   MipsABIInfo ABI = Subtarget.getABI();
890   unsigned ADDU = ABI.GetPtrAdduOp();
891   unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP;
892   unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA;
893   unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9;
894   unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
895   Register OffsetReg = I->getOperand(0).getReg();
896   Register TargetReg = I->getOperand(1).getReg();
897 
898   // addu $ra, $v0, $zero
899   // addu $sp, $sp, $v1
900   // jr   $ra (via RetRA)
901   const TargetMachine &TM = MBB.getParent()->getTarget();
902   if (TM.isPositionIndependent())
903     BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), T9)
904         .addReg(TargetReg)
905         .addReg(ZERO);
906   BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA)
907       .addReg(TargetReg)
908       .addReg(ZERO);
909   BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg);
910   expandRetRA(MBB, I);
911 }
912 
913 const MipsInstrInfo *llvm::createMipsSEInstrInfo(const MipsSubtarget &STI) {
914   return new MipsSEInstrInfo(STI);
915 }
916