1*0b57cec5SDimitry Andric //===- MipsSEISelLowering.h - MipsSE DAG Lowering Interface -----*- C++ -*-===// 2*0b57cec5SDimitry Andric // 3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric // 7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric // 9*0b57cec5SDimitry Andric // Subclass of MipsTargetLowering specialized for mips32/64. 10*0b57cec5SDimitry Andric // 11*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 12*0b57cec5SDimitry Andric 13*0b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H 14*0b57cec5SDimitry Andric #define LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H 15*0b57cec5SDimitry Andric 16*0b57cec5SDimitry Andric #include "MipsISelLowering.h" 17*0b57cec5SDimitry Andric #include "llvm/CodeGen/SelectionDAGNodes.h" 18*0b57cec5SDimitry Andric #include "llvm/Support/MachineValueType.h" 19*0b57cec5SDimitry Andric 20*0b57cec5SDimitry Andric namespace llvm { 21*0b57cec5SDimitry Andric 22*0b57cec5SDimitry Andric class MachineBasicBlock; 23*0b57cec5SDimitry Andric class MachineInstr; 24*0b57cec5SDimitry Andric class MipsSubtarget; 25*0b57cec5SDimitry Andric class MipsTargetMachine; 26*0b57cec5SDimitry Andric class SelectionDAG; 27*0b57cec5SDimitry Andric class TargetRegisterClass; 28*0b57cec5SDimitry Andric 29*0b57cec5SDimitry Andric class MipsSETargetLowering : public MipsTargetLowering { 30*0b57cec5SDimitry Andric public: 31*0b57cec5SDimitry Andric explicit MipsSETargetLowering(const MipsTargetMachine &TM, 32*0b57cec5SDimitry Andric const MipsSubtarget &STI); 33*0b57cec5SDimitry Andric 34*0b57cec5SDimitry Andric /// Enable MSA support for the given integer type and Register 35*0b57cec5SDimitry Andric /// class. 36*0b57cec5SDimitry Andric void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC); 37*0b57cec5SDimitry Andric 38*0b57cec5SDimitry Andric /// Enable MSA support for the given floating-point type and 39*0b57cec5SDimitry Andric /// Register class. 40*0b57cec5SDimitry Andric void addMSAFloatType(MVT::SimpleValueType Ty, 41*0b57cec5SDimitry Andric const TargetRegisterClass *RC); 42*0b57cec5SDimitry Andric 43*0b57cec5SDimitry Andric bool allowsMisalignedMemoryAccesses( 44*0b57cec5SDimitry Andric EVT VT, unsigned AS = 0, unsigned Align = 1, 45*0b57cec5SDimitry Andric MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 46*0b57cec5SDimitry Andric bool *Fast = nullptr) const override; 47*0b57cec5SDimitry Andric 48*0b57cec5SDimitry Andric SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 49*0b57cec5SDimitry Andric 50*0b57cec5SDimitry Andric SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 51*0b57cec5SDimitry Andric 52*0b57cec5SDimitry Andric MachineBasicBlock * 53*0b57cec5SDimitry Andric EmitInstrWithCustomInserter(MachineInstr &MI, 54*0b57cec5SDimitry Andric MachineBasicBlock *MBB) const override; 55*0b57cec5SDimitry Andric 56*0b57cec5SDimitry Andric bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override { 57*0b57cec5SDimitry Andric return false; 58*0b57cec5SDimitry Andric } 59*0b57cec5SDimitry Andric 60*0b57cec5SDimitry Andric const TargetRegisterClass *getRepRegClassFor(MVT VT) const override; 61*0b57cec5SDimitry Andric 62*0b57cec5SDimitry Andric private: 63*0b57cec5SDimitry Andric bool isEligibleForTailCallOptimization( 64*0b57cec5SDimitry Andric const CCState &CCInfo, unsigned NextStackOffset, 65*0b57cec5SDimitry Andric const MipsFunctionInfo &FI) const override; 66*0b57cec5SDimitry Andric 67*0b57cec5SDimitry Andric void 68*0b57cec5SDimitry Andric getOpndList(SmallVectorImpl<SDValue> &Ops, 69*0b57cec5SDimitry Andric std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 70*0b57cec5SDimitry Andric bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 71*0b57cec5SDimitry Andric bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 72*0b57cec5SDimitry Andric SDValue Chain) const override; 73*0b57cec5SDimitry Andric 74*0b57cec5SDimitry Andric SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; 75*0b57cec5SDimitry Andric SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; 76*0b57cec5SDimitry Andric SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const; 77*0b57cec5SDimitry Andric 78*0b57cec5SDimitry Andric SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi, 79*0b57cec5SDimitry Andric SelectionDAG &DAG) const; 80*0b57cec5SDimitry Andric 81*0b57cec5SDimitry Andric SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 82*0b57cec5SDimitry Andric SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 83*0b57cec5SDimitry Andric SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 84*0b57cec5SDimitry Andric SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 85*0b57cec5SDimitry Andric SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 86*0b57cec5SDimitry Andric /// Lower VECTOR_SHUFFLE into one of a number of instructions 87*0b57cec5SDimitry Andric /// depending on the indices in the shuffle. 88*0b57cec5SDimitry Andric SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 89*0b57cec5SDimitry Andric SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; 90*0b57cec5SDimitry Andric 91*0b57cec5SDimitry Andric MachineBasicBlock *emitBPOSGE32(MachineInstr &MI, 92*0b57cec5SDimitry Andric MachineBasicBlock *BB) const; 93*0b57cec5SDimitry Andric MachineBasicBlock *emitMSACBranchPseudo(MachineInstr &MI, 94*0b57cec5SDimitry Andric MachineBasicBlock *BB, 95*0b57cec5SDimitry Andric unsigned BranchOp) const; 96*0b57cec5SDimitry Andric /// Emit the COPY_FW pseudo instruction 97*0b57cec5SDimitry Andric MachineBasicBlock *emitCOPY_FW(MachineInstr &MI, 98*0b57cec5SDimitry Andric MachineBasicBlock *BB) const; 99*0b57cec5SDimitry Andric /// Emit the COPY_FD pseudo instruction 100*0b57cec5SDimitry Andric MachineBasicBlock *emitCOPY_FD(MachineInstr &MI, 101*0b57cec5SDimitry Andric MachineBasicBlock *BB) const; 102*0b57cec5SDimitry Andric /// Emit the INSERT_FW pseudo instruction 103*0b57cec5SDimitry Andric MachineBasicBlock *emitINSERT_FW(MachineInstr &MI, 104*0b57cec5SDimitry Andric MachineBasicBlock *BB) const; 105*0b57cec5SDimitry Andric /// Emit the INSERT_FD pseudo instruction 106*0b57cec5SDimitry Andric MachineBasicBlock *emitINSERT_FD(MachineInstr &MI, 107*0b57cec5SDimitry Andric MachineBasicBlock *BB) const; 108*0b57cec5SDimitry Andric /// Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction 109*0b57cec5SDimitry Andric MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr &MI, 110*0b57cec5SDimitry Andric MachineBasicBlock *BB, 111*0b57cec5SDimitry Andric unsigned EltSizeInBytes, 112*0b57cec5SDimitry Andric bool IsFP) const; 113*0b57cec5SDimitry Andric /// Emit the FILL_FW pseudo instruction 114*0b57cec5SDimitry Andric MachineBasicBlock *emitFILL_FW(MachineInstr &MI, 115*0b57cec5SDimitry Andric MachineBasicBlock *BB) const; 116*0b57cec5SDimitry Andric /// Emit the FILL_FD pseudo instruction 117*0b57cec5SDimitry Andric MachineBasicBlock *emitFILL_FD(MachineInstr &MI, 118*0b57cec5SDimitry Andric MachineBasicBlock *BB) const; 119*0b57cec5SDimitry Andric /// Emit the FEXP2_W_1 pseudo instructions. 120*0b57cec5SDimitry Andric MachineBasicBlock *emitFEXP2_W_1(MachineInstr &MI, 121*0b57cec5SDimitry Andric MachineBasicBlock *BB) const; 122*0b57cec5SDimitry Andric /// Emit the FEXP2_D_1 pseudo instructions. 123*0b57cec5SDimitry Andric MachineBasicBlock *emitFEXP2_D_1(MachineInstr &MI, 124*0b57cec5SDimitry Andric MachineBasicBlock *BB) const; 125*0b57cec5SDimitry Andric /// Emit the FILL_FW pseudo instruction 126*0b57cec5SDimitry Andric MachineBasicBlock *emitLD_F16_PSEUDO(MachineInstr &MI, 127*0b57cec5SDimitry Andric MachineBasicBlock *BB) const; 128*0b57cec5SDimitry Andric /// Emit the FILL_FD pseudo instruction 129*0b57cec5SDimitry Andric MachineBasicBlock *emitST_F16_PSEUDO(MachineInstr &MI, 130*0b57cec5SDimitry Andric MachineBasicBlock *BB) const; 131*0b57cec5SDimitry Andric /// Emit the FEXP2_W_1 pseudo instructions. 132*0b57cec5SDimitry Andric MachineBasicBlock *emitFPEXTEND_PSEUDO(MachineInstr &MI, 133*0b57cec5SDimitry Andric MachineBasicBlock *BB, 134*0b57cec5SDimitry Andric bool IsFGR64) const; 135*0b57cec5SDimitry Andric /// Emit the FEXP2_D_1 pseudo instructions. 136*0b57cec5SDimitry Andric MachineBasicBlock *emitFPROUND_PSEUDO(MachineInstr &MI, 137*0b57cec5SDimitry Andric MachineBasicBlock *BBi, 138*0b57cec5SDimitry Andric bool IsFGR64) const; 139*0b57cec5SDimitry Andric }; 140*0b57cec5SDimitry Andric 141*0b57cec5SDimitry Andric } // end namespace llvm 142*0b57cec5SDimitry Andric 143*0b57cec5SDimitry Andric #endif // LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H 144