1 //===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // Subclass of MipsDAGToDAGISel specialized for mips32/64. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MipsSEISelDAGToDAG.h" 14 #include "MCTargetDesc/MipsBaseInfo.h" 15 #include "Mips.h" 16 #include "MipsAnalyzeImmediate.h" 17 #include "MipsMachineFunction.h" 18 #include "MipsRegisterInfo.h" 19 #include "llvm/CodeGen/MachineConstantPool.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineRegisterInfo.h" 24 #include "llvm/CodeGen/SelectionDAGNodes.h" 25 #include "llvm/IR/CFG.h" 26 #include "llvm/IR/Dominators.h" 27 #include "llvm/IR/GlobalValue.h" 28 #include "llvm/IR/Instructions.h" 29 #include "llvm/IR/Intrinsics.h" 30 #include "llvm/IR/IntrinsicsMips.h" 31 #include "llvm/IR/Type.h" 32 #include "llvm/Support/Debug.h" 33 #include "llvm/Support/ErrorHandling.h" 34 #include "llvm/Support/raw_ostream.h" 35 #include "llvm/Target/TargetMachine.h" 36 using namespace llvm; 37 38 #define DEBUG_TYPE "mips-isel" 39 40 bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { 41 Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget()); 42 if (Subtarget->inMips16Mode()) 43 return false; 44 return MipsDAGToDAGISel::runOnMachineFunction(MF); 45 } 46 47 void MipsSEDAGToDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 48 AU.addRequired<DominatorTreeWrapperPass>(); 49 SelectionDAGISel::getAnalysisUsage(AU); 50 } 51 52 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI, 53 MachineFunction &MF) { 54 MachineInstrBuilder MIB(MF, &MI); 55 unsigned Mask = MI.getOperand(1).getImm(); 56 unsigned Flag = 57 IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef; 58 59 if (Mask & 1) 60 MIB.addReg(Mips::DSPPos, Flag); 61 62 if (Mask & 2) 63 MIB.addReg(Mips::DSPSCount, Flag); 64 65 if (Mask & 4) 66 MIB.addReg(Mips::DSPCarry, Flag); 67 68 if (Mask & 8) 69 MIB.addReg(Mips::DSPOutFlag, Flag); 70 71 if (Mask & 16) 72 MIB.addReg(Mips::DSPCCond, Flag); 73 74 if (Mask & 32) 75 MIB.addReg(Mips::DSPEFI, Flag); 76 } 77 78 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const { 79 uint64_t RegNum = cast<ConstantSDNode>(RegIdx)->getZExtValue(); 80 return Mips::MSACtrlRegClass.getRegister(RegNum); 81 } 82 83 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI, 84 const MachineInstr& MI) { 85 unsigned DstReg = 0, ZeroReg = 0; 86 87 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0". 88 if ((MI.getOpcode() == Mips::ADDiu) && 89 (MI.getOperand(1).getReg() == Mips::ZERO) && 90 (MI.getOperand(2).isImm()) && 91 (MI.getOperand(2).getImm() == 0)) { 92 DstReg = MI.getOperand(0).getReg(); 93 ZeroReg = Mips::ZERO; 94 } else if ((MI.getOpcode() == Mips::DADDiu) && 95 (MI.getOperand(1).getReg() == Mips::ZERO_64) && 96 (MI.getOperand(2).isImm()) && 97 (MI.getOperand(2).getImm() == 0)) { 98 DstReg = MI.getOperand(0).getReg(); 99 ZeroReg = Mips::ZERO_64; 100 } 101 102 if (!DstReg) 103 return false; 104 105 // Replace uses with ZeroReg. 106 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg), 107 E = MRI->use_end(); U != E;) { 108 MachineOperand &MO = *U; 109 unsigned OpNo = U.getOperandNo(); 110 MachineInstr *MI = MO.getParent(); 111 ++U; 112 113 // Do not replace if it is a phi's operand or is tied to def operand. 114 if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo()) 115 continue; 116 117 // Also, we have to check that the register class of the operand 118 // contains the zero register. 119 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg)) 120 continue; 121 122 MO.setReg(ZeroReg); 123 } 124 125 return true; 126 } 127 128 void MipsSEDAGToDAGISel::emitMCountABI(MachineInstr &MI, MachineBasicBlock &MBB, 129 MachineFunction &MF) { 130 MachineInstrBuilder MIB(MF, &MI); 131 if (!Subtarget->isABI_O32()) { // N32, N64 132 // Save current return address. 133 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::OR64)) 134 .addDef(Mips::AT_64) 135 .addUse(Mips::RA_64, RegState::Undef) 136 .addUse(Mips::ZERO_64); 137 // Stops instruction above from being removed later on. 138 MIB.addUse(Mips::AT_64, RegState::Implicit); 139 } else { // O32 140 // Save current return address. 141 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::OR)) 142 .addDef(Mips::AT) 143 .addUse(Mips::RA, RegState::Undef) 144 .addUse(Mips::ZERO); 145 // _mcount pops 2 words from stack. 146 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::ADDiu)) 147 .addDef(Mips::SP) 148 .addUse(Mips::SP) 149 .addImm(-8); 150 // Stops first instruction above from being removed later on. 151 MIB.addUse(Mips::AT, RegState::Implicit); 152 } 153 } 154 155 void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) { 156 MF.getInfo<MipsFunctionInfo>()->initGlobalBaseReg(); 157 158 MachineRegisterInfo *MRI = &MF.getRegInfo(); 159 160 for (auto &MBB: MF) { 161 for (auto &MI: MBB) { 162 switch (MI.getOpcode()) { 163 case Mips::RDDSP: 164 addDSPCtrlRegOperands(false, MI, MF); 165 break; 166 case Mips::WRDSP: 167 addDSPCtrlRegOperands(true, MI, MF); 168 break; 169 case Mips::BuildPairF64_64: 170 case Mips::ExtractElementF64_64: 171 if (!Subtarget->useOddSPReg()) { 172 MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true)); 173 break; 174 } 175 LLVM_FALLTHROUGH; 176 case Mips::BuildPairF64: 177 case Mips::ExtractElementF64: 178 if (Subtarget->isABI_FPXX() && !Subtarget->hasMTHC1()) 179 MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true)); 180 break; 181 case Mips::JAL: 182 case Mips::JAL_MM: 183 if (MI.getOperand(0).isGlobal() && 184 MI.getOperand(0).getGlobal()->getGlobalIdentifier() == "_mcount") 185 emitMCountABI(MI, MBB, MF); 186 break; 187 case Mips::JALRPseudo: 188 case Mips::JALR64Pseudo: 189 case Mips::JALR16_MM: 190 if (MI.getOperand(2).isMCSymbol() && 191 MI.getOperand(2).getMCSymbol()->getName() == "_mcount") 192 emitMCountABI(MI, MBB, MF); 193 break; 194 case Mips::JALR: 195 if (MI.getOperand(3).isMCSymbol() && 196 MI.getOperand(3).getMCSymbol()->getName() == "_mcount") 197 emitMCountABI(MI, MBB, MF); 198 break; 199 default: 200 replaceUsesWithZeroReg(MRI, MI); 201 } 202 } 203 } 204 } 205 206 void MipsSEDAGToDAGISel::selectAddE(SDNode *Node, const SDLoc &DL) const { 207 SDValue InFlag = Node->getOperand(2); 208 unsigned Opc = InFlag.getOpcode(); 209 SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1); 210 EVT VT = LHS.getValueType(); 211 212 // In the base case, we can rely on the carry bit from the addsc 213 // instruction. 214 if (Opc == ISD::ADDC) { 215 SDValue Ops[3] = {LHS, RHS, InFlag}; 216 CurDAG->SelectNodeTo(Node, Mips::ADDWC, VT, MVT::Glue, Ops); 217 return; 218 } 219 220 assert(Opc == ISD::ADDE && "ISD::ADDE not in a chain of ADDE nodes!"); 221 222 // The more complex case is when there is a chain of ISD::ADDE nodes like: 223 // (adde (adde (adde (addc a b) c) d) e). 224 // 225 // The addwc instruction does not write to the carry bit, instead it writes 226 // to bit 20 of the dsp control register. To match this series of nodes, each 227 // intermediate adde node must be expanded to write the carry bit before the 228 // addition. 229 230 // Start by reading the overflow field for addsc and moving the value to the 231 // carry field. The usage of 1 here with MipsISD::RDDSP / Mips::WRDSP 232 // corresponds to reading/writing the entire control register to/from a GPR. 233 234 SDValue CstOne = CurDAG->getTargetConstant(1, DL, MVT::i32); 235 236 SDValue OuFlag = CurDAG->getTargetConstant(20, DL, MVT::i32); 237 238 SDNode *DSPCtrlField = CurDAG->getMachineNode(Mips::RDDSP, DL, MVT::i32, 239 MVT::Glue, CstOne, InFlag); 240 241 SDNode *Carry = CurDAG->getMachineNode( 242 Mips::EXT, DL, MVT::i32, SDValue(DSPCtrlField, 0), OuFlag, CstOne); 243 244 SDValue Ops[4] = {SDValue(DSPCtrlField, 0), 245 CurDAG->getTargetConstant(6, DL, MVT::i32), CstOne, 246 SDValue(Carry, 0)}; 247 SDNode *DSPCFWithCarry = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, Ops); 248 249 // My reading of the MIPS DSP 3.01 specification isn't as clear as I 250 // would like about whether bit 20 always gets overwritten by addwc. 251 // Hence take an extremely conservative view and presume it's sticky. We 252 // therefore need to clear it. 253 254 SDValue Zero = CurDAG->getRegister(Mips::ZERO, MVT::i32); 255 256 SDValue InsOps[4] = {Zero, OuFlag, CstOne, SDValue(DSPCFWithCarry, 0)}; 257 SDNode *DSPCtrlFinal = 258 CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, InsOps); 259 260 SDNode *WrDSP = CurDAG->getMachineNode(Mips::WRDSP, DL, MVT::Glue, 261 SDValue(DSPCtrlFinal, 0), CstOne); 262 263 SDValue Operands[3] = {LHS, RHS, SDValue(WrDSP, 0)}; 264 CurDAG->SelectNodeTo(Node, Mips::ADDWC, VT, MVT::Glue, Operands); 265 } 266 267 /// Match frameindex 268 bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base, 269 SDValue &Offset) const { 270 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 271 EVT ValTy = Addr.getValueType(); 272 273 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); 274 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), ValTy); 275 return true; 276 } 277 return false; 278 } 279 280 /// Match frameindex+offset and frameindex|offset 281 bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset( 282 SDValue Addr, SDValue &Base, SDValue &Offset, unsigned OffsetBits, 283 unsigned ShiftAmount = 0) const { 284 if (CurDAG->isBaseWithConstantOffset(Addr)) { 285 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)); 286 if (isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) { 287 EVT ValTy = Addr.getValueType(); 288 289 // If the first operand is a FI, get the TargetFI Node 290 if (FrameIndexSDNode *FIN = 291 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) 292 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); 293 else { 294 Base = Addr.getOperand(0); 295 // If base is a FI, additional offset calculation is done in 296 // eliminateFrameIndex, otherwise we need to check the alignment 297 const Align Alignment(1ULL << ShiftAmount); 298 if (!isAligned(Alignment, CN->getZExtValue())) 299 return false; 300 } 301 302 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr), 303 ValTy); 304 return true; 305 } 306 } 307 return false; 308 } 309 310 /// ComplexPattern used on MipsInstrInfo 311 /// Used on Mips Load/Store instructions 312 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base, 313 SDValue &Offset) const { 314 // if Address is FI, get the TargetFrameIndex. 315 if (selectAddrFrameIndex(Addr, Base, Offset)) 316 return true; 317 318 // on PIC code Load GA 319 if (Addr.getOpcode() == MipsISD::Wrapper) { 320 Base = Addr.getOperand(0); 321 Offset = Addr.getOperand(1); 322 return true; 323 } 324 325 if (!TM.isPositionIndependent()) { 326 if ((Addr.getOpcode() == ISD::TargetExternalSymbol || 327 Addr.getOpcode() == ISD::TargetGlobalAddress)) 328 return false; 329 } 330 331 // Addresses of the form FI+const or FI|const 332 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16)) 333 return true; 334 335 // Operand is a result from an ADD. 336 if (Addr.getOpcode() == ISD::ADD) { 337 // When loading from constant pools, load the lower address part in 338 // the instruction itself. Example, instead of: 339 // lui $2, %hi($CPI1_0) 340 // addiu $2, $2, %lo($CPI1_0) 341 // lwc1 $f0, 0($2) 342 // Generate: 343 // lui $2, %hi($CPI1_0) 344 // lwc1 $f0, %lo($CPI1_0)($2) 345 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo || 346 Addr.getOperand(1).getOpcode() == MipsISD::GPRel) { 347 SDValue Opnd0 = Addr.getOperand(1).getOperand(0); 348 if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) || 349 isa<JumpTableSDNode>(Opnd0)) { 350 Base = Addr.getOperand(0); 351 Offset = Opnd0; 352 return true; 353 } 354 } 355 } 356 357 return false; 358 } 359 360 /// ComplexPattern used on MipsInstrInfo 361 /// Used on Mips Load/Store instructions 362 bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base, 363 SDValue &Offset) const { 364 Base = Addr; 365 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Addr.getValueType()); 366 return true; 367 } 368 369 bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base, 370 SDValue &Offset) const { 371 return selectAddrRegImm(Addr, Base, Offset) || 372 selectAddrDefault(Addr, Base, Offset); 373 } 374 375 bool MipsSEDAGToDAGISel::selectAddrRegImm9(SDValue Addr, SDValue &Base, 376 SDValue &Offset) const { 377 if (selectAddrFrameIndex(Addr, Base, Offset)) 378 return true; 379 380 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 9)) 381 return true; 382 383 return false; 384 } 385 386 /// Used on microMIPS LWC2, LDC2, SWC2 and SDC2 instructions (11-bit offset) 387 bool MipsSEDAGToDAGISel::selectAddrRegImm11(SDValue Addr, SDValue &Base, 388 SDValue &Offset) const { 389 if (selectAddrFrameIndex(Addr, Base, Offset)) 390 return true; 391 392 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 11)) 393 return true; 394 395 return false; 396 } 397 398 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset) 399 bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base, 400 SDValue &Offset) const { 401 if (selectAddrFrameIndex(Addr, Base, Offset)) 402 return true; 403 404 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12)) 405 return true; 406 407 return false; 408 } 409 410 bool MipsSEDAGToDAGISel::selectAddrRegImm16(SDValue Addr, SDValue &Base, 411 SDValue &Offset) const { 412 if (selectAddrFrameIndex(Addr, Base, Offset)) 413 return true; 414 415 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16)) 416 return true; 417 418 return false; 419 } 420 421 bool MipsSEDAGToDAGISel::selectIntAddr11MM(SDValue Addr, SDValue &Base, 422 SDValue &Offset) const { 423 return selectAddrRegImm11(Addr, Base, Offset) || 424 selectAddrDefault(Addr, Base, Offset); 425 } 426 427 bool MipsSEDAGToDAGISel::selectIntAddr12MM(SDValue Addr, SDValue &Base, 428 SDValue &Offset) const { 429 return selectAddrRegImm12(Addr, Base, Offset) || 430 selectAddrDefault(Addr, Base, Offset); 431 } 432 433 bool MipsSEDAGToDAGISel::selectIntAddr16MM(SDValue Addr, SDValue &Base, 434 SDValue &Offset) const { 435 return selectAddrRegImm16(Addr, Base, Offset) || 436 selectAddrDefault(Addr, Base, Offset); 437 } 438 439 bool MipsSEDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base, 440 SDValue &Offset) const { 441 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 7)) { 442 if (isa<FrameIndexSDNode>(Base)) 443 return false; 444 445 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Offset)) { 446 unsigned CnstOff = CN->getZExtValue(); 447 return (CnstOff == (CnstOff & 0x3c)); 448 } 449 450 return false; 451 } 452 453 // For all other cases where "lw" would be selected, don't select "lw16" 454 // because it would result in additional instructions to prepare operands. 455 if (selectAddrRegImm(Addr, Base, Offset)) 456 return false; 457 458 return selectAddrDefault(Addr, Base, Offset); 459 } 460 461 bool MipsSEDAGToDAGISel::selectIntAddrSImm10(SDValue Addr, SDValue &Base, 462 SDValue &Offset) const { 463 464 if (selectAddrFrameIndex(Addr, Base, Offset)) 465 return true; 466 467 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10)) 468 return true; 469 470 return selectAddrDefault(Addr, Base, Offset); 471 } 472 473 bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base, 474 SDValue &Offset) const { 475 if (selectAddrFrameIndex(Addr, Base, Offset)) 476 return true; 477 478 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 1)) 479 return true; 480 481 return selectAddrDefault(Addr, Base, Offset); 482 } 483 484 bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base, 485 SDValue &Offset) const { 486 if (selectAddrFrameIndex(Addr, Base, Offset)) 487 return true; 488 489 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 2)) 490 return true; 491 492 return selectAddrDefault(Addr, Base, Offset); 493 } 494 495 bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base, 496 SDValue &Offset) const { 497 if (selectAddrFrameIndex(Addr, Base, Offset)) 498 return true; 499 500 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 3)) 501 return true; 502 503 return selectAddrDefault(Addr, Base, Offset); 504 } 505 506 // Select constant vector splats. 507 // 508 // Returns true and sets Imm if: 509 // * MSA is enabled 510 // * N is a ISD::BUILD_VECTOR representing a constant splat 511 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm, 512 unsigned MinSizeInBits) const { 513 if (!Subtarget->hasMSA()) 514 return false; 515 516 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N); 517 518 if (!Node) 519 return false; 520 521 APInt SplatValue, SplatUndef; 522 unsigned SplatBitSize; 523 bool HasAnyUndefs; 524 525 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, 526 MinSizeInBits, !Subtarget->isLittle())) 527 return false; 528 529 Imm = SplatValue; 530 531 return true; 532 } 533 534 // Select constant vector splats. 535 // 536 // In addition to the requirements of selectVSplat(), this function returns 537 // true and sets Imm if: 538 // * The splat value is the same width as the elements of the vector 539 // * The splat value fits in an integer with the specified signed-ness and 540 // width. 541 // 542 // This function looks through ISD::BITCAST nodes. 543 // TODO: This might not be appropriate for big-endian MSA since BITCAST is 544 // sometimes a shuffle in big-endian mode. 545 // 546 // It's worth noting that this function is not used as part of the selection 547 // of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd] 548 // instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in 549 // MipsSEDAGToDAGISel::selectNode. 550 bool MipsSEDAGToDAGISel:: 551 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed, 552 unsigned ImmBitSize) const { 553 APInt ImmValue; 554 EVT EltTy = N->getValueType(0).getVectorElementType(); 555 556 if (N->getOpcode() == ISD::BITCAST) 557 N = N->getOperand(0); 558 559 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) && 560 ImmValue.getBitWidth() == EltTy.getSizeInBits()) { 561 562 if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) || 563 (!Signed && ImmValue.isIntN(ImmBitSize))) { 564 Imm = CurDAG->getTargetConstant(ImmValue, SDLoc(N), EltTy); 565 return true; 566 } 567 } 568 569 return false; 570 } 571 572 // Select constant vector splats. 573 bool MipsSEDAGToDAGISel:: 574 selectVSplatUimm1(SDValue N, SDValue &Imm) const { 575 return selectVSplatCommon(N, Imm, false, 1); 576 } 577 578 bool MipsSEDAGToDAGISel:: 579 selectVSplatUimm2(SDValue N, SDValue &Imm) const { 580 return selectVSplatCommon(N, Imm, false, 2); 581 } 582 583 bool MipsSEDAGToDAGISel:: 584 selectVSplatUimm3(SDValue N, SDValue &Imm) const { 585 return selectVSplatCommon(N, Imm, false, 3); 586 } 587 588 // Select constant vector splats. 589 bool MipsSEDAGToDAGISel:: 590 selectVSplatUimm4(SDValue N, SDValue &Imm) const { 591 return selectVSplatCommon(N, Imm, false, 4); 592 } 593 594 // Select constant vector splats. 595 bool MipsSEDAGToDAGISel:: 596 selectVSplatUimm5(SDValue N, SDValue &Imm) const { 597 return selectVSplatCommon(N, Imm, false, 5); 598 } 599 600 // Select constant vector splats. 601 bool MipsSEDAGToDAGISel:: 602 selectVSplatUimm6(SDValue N, SDValue &Imm) const { 603 return selectVSplatCommon(N, Imm, false, 6); 604 } 605 606 // Select constant vector splats. 607 bool MipsSEDAGToDAGISel:: 608 selectVSplatUimm8(SDValue N, SDValue &Imm) const { 609 return selectVSplatCommon(N, Imm, false, 8); 610 } 611 612 // Select constant vector splats. 613 bool MipsSEDAGToDAGISel:: 614 selectVSplatSimm5(SDValue N, SDValue &Imm) const { 615 return selectVSplatCommon(N, Imm, true, 5); 616 } 617 618 // Select constant vector splats whose value is a power of 2. 619 // 620 // In addition to the requirements of selectVSplat(), this function returns 621 // true and sets Imm if: 622 // * The splat value is the same width as the elements of the vector 623 // * The splat value is a power of two. 624 // 625 // This function looks through ISD::BITCAST nodes. 626 // TODO: This might not be appropriate for big-endian MSA since BITCAST is 627 // sometimes a shuffle in big-endian mode. 628 bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const { 629 APInt ImmValue; 630 EVT EltTy = N->getValueType(0).getVectorElementType(); 631 632 if (N->getOpcode() == ISD::BITCAST) 633 N = N->getOperand(0); 634 635 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) && 636 ImmValue.getBitWidth() == EltTy.getSizeInBits()) { 637 int32_t Log2 = ImmValue.exactLogBase2(); 638 639 if (Log2 != -1) { 640 Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy); 641 return true; 642 } 643 } 644 645 return false; 646 } 647 648 // Select constant vector splats whose value only has a consecutive sequence 649 // of left-most bits set (e.g. 0b11...1100...00). 650 // 651 // In addition to the requirements of selectVSplat(), this function returns 652 // true and sets Imm if: 653 // * The splat value is the same width as the elements of the vector 654 // * The splat value is a consecutive sequence of left-most bits. 655 // 656 // This function looks through ISD::BITCAST nodes. 657 // TODO: This might not be appropriate for big-endian MSA since BITCAST is 658 // sometimes a shuffle in big-endian mode. 659 bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const { 660 APInt ImmValue; 661 EVT EltTy = N->getValueType(0).getVectorElementType(); 662 663 if (N->getOpcode() == ISD::BITCAST) 664 N = N->getOperand(0); 665 666 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) && 667 ImmValue.getBitWidth() == EltTy.getSizeInBits()) { 668 // Extract the run of set bits starting with bit zero from the bitwise 669 // inverse of ImmValue, and test that the inverse of this is the same 670 // as the original value. 671 if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) { 672 673 Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N), 674 EltTy); 675 return true; 676 } 677 } 678 679 return false; 680 } 681 682 // Select constant vector splats whose value only has a consecutive sequence 683 // of right-most bits set (e.g. 0b00...0011...11). 684 // 685 // In addition to the requirements of selectVSplat(), this function returns 686 // true and sets Imm if: 687 // * The splat value is the same width as the elements of the vector 688 // * The splat value is a consecutive sequence of right-most bits. 689 // 690 // This function looks through ISD::BITCAST nodes. 691 // TODO: This might not be appropriate for big-endian MSA since BITCAST is 692 // sometimes a shuffle in big-endian mode. 693 bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const { 694 APInt ImmValue; 695 EVT EltTy = N->getValueType(0).getVectorElementType(); 696 697 if (N->getOpcode() == ISD::BITCAST) 698 N = N->getOperand(0); 699 700 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) && 701 ImmValue.getBitWidth() == EltTy.getSizeInBits()) { 702 // Extract the run of set bits starting with bit zero, and test that the 703 // result is the same as the original value 704 if (ImmValue == (ImmValue & ~(ImmValue + 1))) { 705 Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N), 706 EltTy); 707 return true; 708 } 709 } 710 711 return false; 712 } 713 714 bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N, 715 SDValue &Imm) const { 716 APInt ImmValue; 717 EVT EltTy = N->getValueType(0).getVectorElementType(); 718 719 if (N->getOpcode() == ISD::BITCAST) 720 N = N->getOperand(0); 721 722 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) && 723 ImmValue.getBitWidth() == EltTy.getSizeInBits()) { 724 int32_t Log2 = (~ImmValue).exactLogBase2(); 725 726 if (Log2 != -1) { 727 Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy); 728 return true; 729 } 730 } 731 732 return false; 733 } 734 735 bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) { 736 unsigned Opcode = Node->getOpcode(); 737 SDLoc DL(Node); 738 739 /// 740 // Instruction Selection not handled by the auto-generated 741 // tablegen selection should be handled here. 742 /// 743 switch(Opcode) { 744 default: break; 745 746 case Mips::PseudoD_SELECT_I: 747 case Mips::PseudoD_SELECT_I64: { 748 MVT VT = Subtarget->isGP64bit() ? MVT::i64 : MVT::i32; 749 SDValue cond = Node->getOperand(0); 750 SDValue Hi1 = Node->getOperand(1); 751 SDValue Lo1 = Node->getOperand(2); 752 SDValue Hi2 = Node->getOperand(3); 753 SDValue Lo2 = Node->getOperand(4); 754 755 SDValue ops[] = {cond, Hi1, Lo1, Hi2, Lo2}; 756 EVT NodeTys[] = {VT, VT}; 757 ReplaceNode(Node, CurDAG->getMachineNode(Subtarget->isGP64bit() 758 ? Mips::PseudoD_SELECT_I64 759 : Mips::PseudoD_SELECT_I, 760 DL, NodeTys, ops)); 761 return true; 762 } 763 764 case ISD::ADDE: { 765 selectAddE(Node, DL); 766 return true; 767 } 768 769 case ISD::ConstantFP: { 770 auto *CN = cast<ConstantFPSDNode>(Node); 771 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) { 772 if (Subtarget->isGP64bit()) { 773 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, 774 Mips::ZERO_64, MVT::i64); 775 ReplaceNode(Node, 776 CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero)); 777 } else if (Subtarget->isFP64bit()) { 778 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, 779 Mips::ZERO, MVT::i32); 780 ReplaceNode(Node, CurDAG->getMachineNode(Mips::BuildPairF64_64, DL, 781 MVT::f64, Zero, Zero)); 782 } else { 783 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, 784 Mips::ZERO, MVT::i32); 785 ReplaceNode(Node, CurDAG->getMachineNode(Mips::BuildPairF64, DL, 786 MVT::f64, Zero, Zero)); 787 } 788 return true; 789 } 790 break; 791 } 792 793 case ISD::Constant: { 794 auto *CN = cast<ConstantSDNode>(Node); 795 int64_t Imm = CN->getSExtValue(); 796 unsigned Size = CN->getValueSizeInBits(0); 797 798 if (isInt<32>(Imm)) 799 break; 800 801 MipsAnalyzeImmediate AnalyzeImm; 802 803 const MipsAnalyzeImmediate::InstSeq &Seq = 804 AnalyzeImm.Analyze(Imm, Size, false); 805 806 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin(); 807 SDLoc DL(CN); 808 SDNode *RegOpnd; 809 SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), 810 DL, MVT::i64); 811 812 // The first instruction can be a LUi which is different from other 813 // instructions (ADDiu, ORI and SLL) in that it does not have a register 814 // operand. 815 if (Inst->Opc == Mips::LUi64) 816 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd); 817 else 818 RegOpnd = 819 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, 820 CurDAG->getRegister(Mips::ZERO_64, MVT::i64), 821 ImmOpnd); 822 823 // The remaining instructions in the sequence are handled here. 824 for (++Inst; Inst != Seq.end(); ++Inst) { 825 ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), DL, 826 MVT::i64); 827 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, 828 SDValue(RegOpnd, 0), ImmOpnd); 829 } 830 831 ReplaceNode(Node, RegOpnd); 832 return true; 833 } 834 835 case ISD::INTRINSIC_W_CHAIN: { 836 switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 837 default: 838 break; 839 840 case Intrinsic::mips_cfcmsa: { 841 SDValue ChainIn = Node->getOperand(0); 842 SDValue RegIdx = Node->getOperand(2); 843 SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL, 844 getMSACtrlReg(RegIdx), MVT::i32); 845 ReplaceNode(Node, Reg.getNode()); 846 return true; 847 } 848 } 849 break; 850 } 851 852 case ISD::INTRINSIC_WO_CHAIN: { 853 switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) { 854 default: 855 break; 856 857 case Intrinsic::mips_move_v: 858 // Like an assignment but will always produce a move.v even if 859 // unnecessary. 860 ReplaceNode(Node, CurDAG->getMachineNode(Mips::MOVE_V, DL, 861 Node->getValueType(0), 862 Node->getOperand(1))); 863 return true; 864 } 865 break; 866 } 867 868 case ISD::INTRINSIC_VOID: { 869 switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 870 default: 871 break; 872 873 case Intrinsic::mips_ctcmsa: { 874 SDValue ChainIn = Node->getOperand(0); 875 SDValue RegIdx = Node->getOperand(2); 876 SDValue Value = Node->getOperand(3); 877 SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL, 878 getMSACtrlReg(RegIdx), Value); 879 ReplaceNode(Node, ChainOut.getNode()); 880 return true; 881 } 882 } 883 break; 884 } 885 886 // Manually match MipsISD::Ins nodes to get the correct instruction. It has 887 // to be done in this fashion so that we respect the differences between 888 // dins and dinsm, as the difference is that the size operand has the range 889 // 0 < size <= 32 for dins while dinsm has the range 2 <= size <= 64 which 890 // means SelectionDAGISel would have to test all the operands at once to 891 // match the instruction. 892 case MipsISD::Ins: { 893 894 // Sanity checking for the node operands. 895 if (Node->getValueType(0) != MVT::i32 && Node->getValueType(0) != MVT::i64) 896 return false; 897 898 if (Node->getNumOperands() != 4) 899 return false; 900 901 if (Node->getOperand(1)->getOpcode() != ISD::Constant || 902 Node->getOperand(2)->getOpcode() != ISD::Constant) 903 return false; 904 905 MVT ResTy = Node->getSimpleValueType(0); 906 uint64_t Pos = Node->getConstantOperandVal(1); 907 uint64_t Size = Node->getConstantOperandVal(2); 908 909 // Size has to be >0 for 'ins', 'dins' and 'dinsu'. 910 if (!Size) 911 return false; 912 913 if (Pos + Size > 64) 914 return false; 915 916 if (ResTy != MVT::i32 && ResTy != MVT::i64) 917 return false; 918 919 unsigned Opcode = 0; 920 if (ResTy == MVT::i32) { 921 if (Pos + Size <= 32) 922 Opcode = Mips::INS; 923 } else { 924 if (Pos + Size <= 32) 925 Opcode = Mips::DINS; 926 else if (Pos < 32 && 1 < Size) 927 Opcode = Mips::DINSM; 928 else 929 Opcode = Mips::DINSU; 930 } 931 932 if (Opcode) { 933 SDValue Ops[4] = { 934 Node->getOperand(0), CurDAG->getTargetConstant(Pos, DL, MVT::i32), 935 CurDAG->getTargetConstant(Size, DL, MVT::i32), Node->getOperand(3)}; 936 937 ReplaceNode(Node, CurDAG->getMachineNode(Opcode, DL, ResTy, Ops)); 938 return true; 939 } 940 941 return false; 942 } 943 944 case MipsISD::ThreadPointer: { 945 EVT PtrVT = getTargetLowering()->getPointerTy(CurDAG->getDataLayout()); 946 unsigned RdhwrOpc, DestReg; 947 948 if (PtrVT == MVT::i32) { 949 RdhwrOpc = Mips::RDHWR; 950 DestReg = Mips::V1; 951 } else { 952 RdhwrOpc = Mips::RDHWR64; 953 DestReg = Mips::V1_64; 954 } 955 956 SDNode *Rdhwr = 957 CurDAG->getMachineNode(RdhwrOpc, DL, Node->getValueType(0), 958 CurDAG->getRegister(Mips::HWR29, MVT::i32), 959 CurDAG->getTargetConstant(0, DL, MVT::i32)); 960 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg, 961 SDValue(Rdhwr, 0)); 962 SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT); 963 ReplaceNode(Node, ResNode.getNode()); 964 return true; 965 } 966 967 case ISD::BUILD_VECTOR: { 968 // Select appropriate ldi.[bhwd] instructions for constant splats of 969 // 128-bit when MSA is enabled. Fixup any register class mismatches that 970 // occur as a result. 971 // 972 // This allows the compiler to use a wider range of immediates than would 973 // otherwise be allowed. If, for example, v4i32 could only use ldi.h then 974 // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101, 975 // 0x01010101 } without using a constant pool. This would be sub-optimal 976 // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the 977 // same set/ of registers. Similarly, ldi.h isn't capable of producing { 978 // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can. 979 980 const MipsABIInfo &ABI = 981 static_cast<const MipsTargetMachine &>(TM).getABI(); 982 983 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node); 984 APInt SplatValue, SplatUndef; 985 unsigned SplatBitSize; 986 bool HasAnyUndefs; 987 unsigned LdiOp; 988 EVT ResVecTy = BVN->getValueType(0); 989 EVT ViaVecTy; 990 991 if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector()) 992 return false; 993 994 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, 995 HasAnyUndefs, 8, 996 !Subtarget->isLittle())) 997 return false; 998 999 switch (SplatBitSize) { 1000 default: 1001 return false; 1002 case 8: 1003 LdiOp = Mips::LDI_B; 1004 ViaVecTy = MVT::v16i8; 1005 break; 1006 case 16: 1007 LdiOp = Mips::LDI_H; 1008 ViaVecTy = MVT::v8i16; 1009 break; 1010 case 32: 1011 LdiOp = Mips::LDI_W; 1012 ViaVecTy = MVT::v4i32; 1013 break; 1014 case 64: 1015 LdiOp = Mips::LDI_D; 1016 ViaVecTy = MVT::v2i64; 1017 break; 1018 } 1019 1020 SDNode *Res = nullptr; 1021 1022 // If we have a signed 10 bit integer, we can splat it directly. 1023 // 1024 // If we have something bigger we can synthesize the value into a GPR and 1025 // splat from there. 1026 if (SplatValue.isSignedIntN(10)) { 1027 SDValue Imm = CurDAG->getTargetConstant(SplatValue, DL, 1028 ViaVecTy.getVectorElementType()); 1029 1030 Res = CurDAG->getMachineNode(LdiOp, DL, ViaVecTy, Imm); 1031 } else if (SplatValue.isSignedIntN(16) && 1032 ((ABI.IsO32() && SplatBitSize < 64) || 1033 (ABI.IsN32() || ABI.IsN64()))) { 1034 // Only handle signed 16 bit values when the element size is GPR width. 1035 // MIPS64 can handle all the cases but MIPS32 would need to handle 1036 // negative cases specifically here. Instead, handle those cases as 1037 // 64bit values. 1038 1039 bool Is32BitSplat = ABI.IsO32() || SplatBitSize < 64; 1040 const unsigned ADDiuOp = Is32BitSplat ? Mips::ADDiu : Mips::DADDiu; 1041 const MVT SplatMVT = Is32BitSplat ? MVT::i32 : MVT::i64; 1042 SDValue ZeroVal = CurDAG->getRegister( 1043 Is32BitSplat ? Mips::ZERO : Mips::ZERO_64, SplatMVT); 1044 1045 const unsigned FILLOp = 1046 SplatBitSize == 16 1047 ? Mips::FILL_H 1048 : (SplatBitSize == 32 ? Mips::FILL_W 1049 : (SplatBitSize == 64 ? Mips::FILL_D : 0)); 1050 1051 assert(FILLOp != 0 && "Unknown FILL Op for splat synthesis!"); 1052 assert((!ABI.IsO32() || (FILLOp != Mips::FILL_D)) && 1053 "Attempting to use fill.d on MIPS32!"); 1054 1055 const unsigned Lo = SplatValue.getLoBits(16).getZExtValue(); 1056 SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, SplatMVT); 1057 1058 Res = CurDAG->getMachineNode(ADDiuOp, DL, SplatMVT, ZeroVal, LoVal); 1059 Res = CurDAG->getMachineNode(FILLOp, DL, ViaVecTy, SDValue(Res, 0)); 1060 1061 } else if (SplatValue.isSignedIntN(32) && SplatBitSize == 32) { 1062 // Only handle the cases where the splat size agrees with the size 1063 // of the SplatValue here. 1064 const unsigned Lo = SplatValue.getLoBits(16).getZExtValue(); 1065 const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue(); 1066 SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32); 1067 1068 SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32); 1069 SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32); 1070 1071 if (Hi) 1072 Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal); 1073 1074 if (Lo) 1075 Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32, 1076 Hi ? SDValue(Res, 0) : ZeroVal, LoVal); 1077 1078 assert((Hi || Lo) && "Zero case reached 32 bit case splat synthesis!"); 1079 Res = 1080 CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32, SDValue(Res, 0)); 1081 1082 } else if (SplatValue.isSignedIntN(32) && SplatBitSize == 64 && 1083 (ABI.IsN32() || ABI.IsN64())) { 1084 // N32 and N64 can perform some tricks that O32 can't for signed 32 bit 1085 // integers due to having 64bit registers. lui will cause the necessary 1086 // zero/sign extension. 1087 const unsigned Lo = SplatValue.getLoBits(16).getZExtValue(); 1088 const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue(); 1089 SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32); 1090 1091 SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32); 1092 SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32); 1093 1094 if (Hi) 1095 Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal); 1096 1097 if (Lo) 1098 Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32, 1099 Hi ? SDValue(Res, 0) : ZeroVal, LoVal); 1100 1101 Res = CurDAG->getMachineNode( 1102 Mips::SUBREG_TO_REG, DL, MVT::i64, 1103 CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64), 1104 SDValue(Res, 0), 1105 CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64)); 1106 1107 Res = 1108 CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, SDValue(Res, 0)); 1109 1110 } else if (SplatValue.isSignedIntN(64)) { 1111 // If we have a 64 bit Splat value, we perform a similar sequence to the 1112 // above: 1113 // 1114 // MIPS32: MIPS64: 1115 // lui $res, %highest(val) lui $res, %highest(val) 1116 // ori $res, $res, %higher(val) ori $res, $res, %higher(val) 1117 // lui $res2, %hi(val) lui $res2, %hi(val) 1118 // ori $res2, %res2, %lo(val) ori $res2, %res2, %lo(val) 1119 // $res3 = fill $res2 dinsu $res, $res2, 0, 32 1120 // $res4 = insert.w $res3[1], $res fill.d $res 1121 // splat.d $res4, 0 1122 // 1123 // The ability to use dinsu is guaranteed as MSA requires MIPSR5. 1124 // This saves having to materialize the value by shifts and ors. 1125 // 1126 // FIXME: Implement the preferred sequence for MIPS64R6: 1127 // 1128 // MIPS64R6: 1129 // ori $res, $zero, %lo(val) 1130 // daui $res, $res, %hi(val) 1131 // dahi $res, $res, %higher(val) 1132 // dati $res, $res, %highest(cal) 1133 // fill.d $res 1134 // 1135 1136 const unsigned Lo = SplatValue.getLoBits(16).getZExtValue(); 1137 const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue(); 1138 const unsigned Higher = SplatValue.lshr(32).getLoBits(16).getZExtValue(); 1139 const unsigned Highest = SplatValue.lshr(48).getLoBits(16).getZExtValue(); 1140 1141 SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32); 1142 SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32); 1143 SDValue HigherVal = CurDAG->getTargetConstant(Higher, DL, MVT::i32); 1144 SDValue HighestVal = CurDAG->getTargetConstant(Highest, DL, MVT::i32); 1145 SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32); 1146 1147 // Independent of whether we're targeting MIPS64 or not, the basic 1148 // operations are the same. Also, directly use the $zero register if 1149 // the 16 bit chunk is zero. 1150 // 1151 // For optimization purposes we always synthesize the splat value as 1152 // an i32 value, then if we're targetting MIPS64, use SUBREG_TO_REG 1153 // just before combining the values with dinsu to produce an i64. This 1154 // enables SelectionDAG to aggressively share components of splat values 1155 // where possible. 1156 // 1157 // FIXME: This is the general constant synthesis problem. This code 1158 // should be factored out into a class shared between all the 1159 // classes that need it. Specifically, for a splat size of 64 1160 // bits that's a negative number we can do better than LUi/ORi 1161 // for the upper 32bits. 1162 1163 if (Hi) 1164 Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal); 1165 1166 if (Lo) 1167 Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32, 1168 Hi ? SDValue(Res, 0) : ZeroVal, LoVal); 1169 1170 SDNode *HiRes; 1171 if (Highest) 1172 HiRes = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HighestVal); 1173 1174 if (Higher) 1175 HiRes = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32, 1176 Highest ? SDValue(HiRes, 0) : ZeroVal, 1177 HigherVal); 1178 1179 1180 if (ABI.IsO32()) { 1181 Res = CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32, 1182 (Hi || Lo) ? SDValue(Res, 0) : ZeroVal); 1183 1184 Res = CurDAG->getMachineNode( 1185 Mips::INSERT_W, DL, MVT::v4i32, SDValue(Res, 0), 1186 (Highest || Higher) ? SDValue(HiRes, 0) : ZeroVal, 1187 CurDAG->getTargetConstant(1, DL, MVT::i32)); 1188 1189 const TargetLowering *TLI = getTargetLowering(); 1190 const TargetRegisterClass *RC = 1191 TLI->getRegClassFor(ViaVecTy.getSimpleVT()); 1192 1193 Res = CurDAG->getMachineNode( 1194 Mips::COPY_TO_REGCLASS, DL, ViaVecTy, SDValue(Res, 0), 1195 CurDAG->getTargetConstant(RC->getID(), DL, MVT::i32)); 1196 1197 Res = CurDAG->getMachineNode( 1198 Mips::SPLATI_D, DL, MVT::v2i64, SDValue(Res, 0), 1199 CurDAG->getTargetConstant(0, DL, MVT::i32)); 1200 } else if (ABI.IsN64() || ABI.IsN32()) { 1201 1202 SDValue Zero64Val = CurDAG->getRegister(Mips::ZERO_64, MVT::i64); 1203 const bool HiResNonZero = Highest || Higher; 1204 const bool ResNonZero = Hi || Lo; 1205 1206 if (HiResNonZero) 1207 HiRes = CurDAG->getMachineNode( 1208 Mips::SUBREG_TO_REG, DL, MVT::i64, 1209 CurDAG->getTargetConstant(((Highest >> 15) & 0x1), DL, MVT::i64), 1210 SDValue(HiRes, 0), 1211 CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64)); 1212 1213 if (ResNonZero) 1214 Res = CurDAG->getMachineNode( 1215 Mips::SUBREG_TO_REG, DL, MVT::i64, 1216 CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64), 1217 SDValue(Res, 0), 1218 CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64)); 1219 1220 // We have 3 cases: 1221 // The HiRes is nonzero but Res is $zero => dsll32 HiRes, 0 1222 // The Res is nonzero but HiRes is $zero => dinsu Res, $zero, 32, 32 1223 // Both are non zero => dinsu Res, HiRes, 32, 32 1224 // 1225 // The obvious "missing" case is when both are zero, but that case is 1226 // handled by the ldi case. 1227 if (ResNonZero) { 1228 IntegerType *Int32Ty = 1229 IntegerType::get(MF->getFunction().getContext(), 32); 1230 const ConstantInt *Const32 = ConstantInt::get(Int32Ty, 32); 1231 SDValue Ops[4] = {HiResNonZero ? SDValue(HiRes, 0) : Zero64Val, 1232 CurDAG->getConstant(*Const32, DL, MVT::i32), 1233 CurDAG->getConstant(*Const32, DL, MVT::i32), 1234 SDValue(Res, 0)}; 1235 1236 Res = CurDAG->getMachineNode(Mips::DINSU, DL, MVT::i64, Ops); 1237 } else if (HiResNonZero) { 1238 Res = CurDAG->getMachineNode( 1239 Mips::DSLL32, DL, MVT::i64, SDValue(HiRes, 0), 1240 CurDAG->getTargetConstant(0, DL, MVT::i32)); 1241 } else 1242 llvm_unreachable( 1243 "Zero splat value handled by non-zero 64bit splat synthesis!"); 1244 1245 Res = CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, 1246 SDValue(Res, 0)); 1247 } else 1248 llvm_unreachable("Unknown ABI in MipsISelDAGToDAG!"); 1249 1250 } else 1251 return false; 1252 1253 if (ResVecTy != ViaVecTy) { 1254 // If LdiOp is writing to a different register class to ResVecTy, then 1255 // fix it up here. This COPY_TO_REGCLASS should never cause a move.v 1256 // since the source and destination register sets contain the same 1257 // registers. 1258 const TargetLowering *TLI = getTargetLowering(); 1259 MVT ResVecTySimple = ResVecTy.getSimpleVT(); 1260 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple); 1261 Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, DL, 1262 ResVecTy, SDValue(Res, 0), 1263 CurDAG->getTargetConstant(RC->getID(), DL, 1264 MVT::i32)); 1265 } 1266 1267 ReplaceNode(Node, Res); 1268 return true; 1269 } 1270 1271 } 1272 1273 return false; 1274 } 1275 1276 bool MipsSEDAGToDAGISel:: 1277 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, 1278 std::vector<SDValue> &OutOps) { 1279 SDValue Base, Offset; 1280 1281 switch(ConstraintID) { 1282 default: 1283 llvm_unreachable("Unexpected asm memory constraint"); 1284 // All memory constraints can at least accept raw pointers. 1285 case InlineAsm::Constraint_m: 1286 case InlineAsm::Constraint_o: 1287 if (selectAddrRegImm16(Op, Base, Offset)) { 1288 OutOps.push_back(Base); 1289 OutOps.push_back(Offset); 1290 return false; 1291 } 1292 OutOps.push_back(Op); 1293 OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32)); 1294 return false; 1295 case InlineAsm::Constraint_R: 1296 // The 'R' constraint is supposed to be much more complicated than this. 1297 // However, it's becoming less useful due to architectural changes and 1298 // ought to be replaced by other constraints such as 'ZC'. 1299 // For now, support 9-bit signed offsets which is supportable by all 1300 // subtargets for all instructions. 1301 if (selectAddrRegImm9(Op, Base, Offset)) { 1302 OutOps.push_back(Base); 1303 OutOps.push_back(Offset); 1304 return false; 1305 } 1306 OutOps.push_back(Op); 1307 OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32)); 1308 return false; 1309 case InlineAsm::Constraint_ZC: 1310 // ZC matches whatever the pref, ll, and sc instructions can handle for the 1311 // given subtarget. 1312 if (Subtarget->inMicroMipsMode()) { 1313 // On microMIPS, they can handle 12-bit offsets. 1314 if (selectAddrRegImm12(Op, Base, Offset)) { 1315 OutOps.push_back(Base); 1316 OutOps.push_back(Offset); 1317 return false; 1318 } 1319 } else if (Subtarget->hasMips32r6()) { 1320 // On MIPS32r6/MIPS64r6, they can only handle 9-bit offsets. 1321 if (selectAddrRegImm9(Op, Base, Offset)) { 1322 OutOps.push_back(Base); 1323 OutOps.push_back(Offset); 1324 return false; 1325 } 1326 } else if (selectAddrRegImm16(Op, Base, Offset)) { 1327 // Prior to MIPS32r6/MIPS64r6, they can handle 16-bit offsets. 1328 OutOps.push_back(Base); 1329 OutOps.push_back(Offset); 1330 return false; 1331 } 1332 // In all cases, 0-bit offsets are acceptable. 1333 OutOps.push_back(Op); 1334 OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32)); 1335 return false; 1336 } 1337 return true; 1338 } 1339 1340 FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM, 1341 CodeGenOpt::Level OptLevel) { 1342 return new MipsSEDAGToDAGISel(TM, OptLevel); 1343 } 1344