1*0b57cec5SDimitry Andric //===- MipsRegisterInfo.h - Mips Register Information Impl ------*- C++ -*-===// 2*0b57cec5SDimitry Andric // 3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric // 7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric // 9*0b57cec5SDimitry Andric // This file contains the Mips implementation of the TargetRegisterInfo class. 10*0b57cec5SDimitry Andric // 11*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 12*0b57cec5SDimitry Andric 13*0b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_MIPS_MIPSREGISTERINFO_H 14*0b57cec5SDimitry Andric #define LLVM_LIB_TARGET_MIPS_MIPSREGISTERINFO_H 15*0b57cec5SDimitry Andric 16*0b57cec5SDimitry Andric #include "Mips.h" 17*0b57cec5SDimitry Andric #include "llvm/CodeGen/MachineBasicBlock.h" 18*0b57cec5SDimitry Andric #include <cstdint> 19*0b57cec5SDimitry Andric 20*0b57cec5SDimitry Andric #define GET_REGINFO_HEADER 21*0b57cec5SDimitry Andric #include "MipsGenRegisterInfo.inc" 22*0b57cec5SDimitry Andric 23*0b57cec5SDimitry Andric namespace llvm { 24*0b57cec5SDimitry Andric 25*0b57cec5SDimitry Andric class TargetRegisterClass; 26*0b57cec5SDimitry Andric 27*0b57cec5SDimitry Andric class MipsRegisterInfo : public MipsGenRegisterInfo { 28*0b57cec5SDimitry Andric public: 29*0b57cec5SDimitry Andric enum class MipsPtrClass { 30*0b57cec5SDimitry Andric /// The default register class for integer values. 31*0b57cec5SDimitry Andric Default = 0, 32*0b57cec5SDimitry Andric /// The subset of registers permitted in certain microMIPS instructions 33*0b57cec5SDimitry Andric /// such as lw16. 34*0b57cec5SDimitry Andric GPR16MM = 1, 35*0b57cec5SDimitry Andric /// The stack pointer only. 36*0b57cec5SDimitry Andric StackPointer = 2, 37*0b57cec5SDimitry Andric /// The global pointer only. 38*0b57cec5SDimitry Andric GlobalPointer = 3, 39*0b57cec5SDimitry Andric }; 40*0b57cec5SDimitry Andric 41*0b57cec5SDimitry Andric MipsRegisterInfo(); 42*0b57cec5SDimitry Andric 43*0b57cec5SDimitry Andric /// Get PIC indirect call register 44*0b57cec5SDimitry Andric static unsigned getPICCallReg(); 45*0b57cec5SDimitry Andric 46*0b57cec5SDimitry Andric /// Code Generation virtual methods... 47*0b57cec5SDimitry Andric const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF, 48*0b57cec5SDimitry Andric unsigned Kind) const override; 49*0b57cec5SDimitry Andric 50*0b57cec5SDimitry Andric unsigned getRegPressureLimit(const TargetRegisterClass *RC, 51*0b57cec5SDimitry Andric MachineFunction &MF) const override; 52*0b57cec5SDimitry Andric const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override; 53*0b57cec5SDimitry Andric const uint32_t *getCallPreservedMask(const MachineFunction &MF, 54*0b57cec5SDimitry Andric CallingConv::ID) const override; 55*0b57cec5SDimitry Andric static const uint32_t *getMips16RetHelperMask(); 56*0b57cec5SDimitry Andric 57*0b57cec5SDimitry Andric BitVector getReservedRegs(const MachineFunction &MF) const override; 58*0b57cec5SDimitry Andric 59*0b57cec5SDimitry Andric bool requiresRegisterScavenging(const MachineFunction &MF) const override; 60*0b57cec5SDimitry Andric 61*0b57cec5SDimitry Andric bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override; 62*0b57cec5SDimitry Andric 63*0b57cec5SDimitry Andric /// Stack Frame Processing Methods 64*0b57cec5SDimitry Andric void eliminateFrameIndex(MachineBasicBlock::iterator II, 65*0b57cec5SDimitry Andric int SPAdj, unsigned FIOperandNum, 66*0b57cec5SDimitry Andric RegScavenger *RS = nullptr) const override; 67*0b57cec5SDimitry Andric 68*0b57cec5SDimitry Andric // Stack realignment queries. 69*0b57cec5SDimitry Andric bool canRealignStack(const MachineFunction &MF) const override; 70*0b57cec5SDimitry Andric 71*0b57cec5SDimitry Andric /// Debug information queries. 72*0b57cec5SDimitry Andric Register getFrameRegister(const MachineFunction &MF) const override; 73*0b57cec5SDimitry Andric 74*0b57cec5SDimitry Andric /// Return GPR register class. 75*0b57cec5SDimitry Andric virtual const TargetRegisterClass *intRegClass(unsigned Size) const = 0; 76*0b57cec5SDimitry Andric 77*0b57cec5SDimitry Andric private: 78*0b57cec5SDimitry Andric virtual void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo, 79*0b57cec5SDimitry Andric int FrameIndex, uint64_t StackSize, 80*0b57cec5SDimitry Andric int64_t SPOffset) const = 0; 81*0b57cec5SDimitry Andric }; 82*0b57cec5SDimitry Andric 83*0b57cec5SDimitry Andric } // end namespace llvm 84*0b57cec5SDimitry Andric 85*0b57cec5SDimitry Andric #endif // LLVM_LIB_TARGET_MIPS_MIPSREGISTERINFO_H 86