xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MipsMTInstrFormats.td (revision d0b2dbfa0ecf2bbc9709efc5e20baf8e4b44bbbf) 
1//===-- MipsMTInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10//  Describe the MIPS MT instructions format
11//
12//  opcode - operation code.
13//  rt     - destination register
14//
15//===----------------------------------------------------------------------===//
16
17class MipsMTInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
18  let DecoderNamespace = "Mips";
19  let EncodingPredicates = [HasStdEnc];
20}
21
22class OPCODE1<bits<1> Val> {
23  bits<1> Value = Val;
24}
25
26def OPCODE_SC_D : OPCODE1<0b0>;
27def OPCODE_SC_E : OPCODE1<0b1>;
28
29class FIELD5<bits<5> Val> {
30  bits<5> Value = Val;
31}
32
33def FIELD5_1_DMT_EMT  : FIELD5<0b00001>;
34def FIELD5_2_DMT_EMT  : FIELD5<0b01111>;
35def FIELD5_1_2_DVPE_EVPE : FIELD5<0b00000>;
36def FIELD5_MFTR : FIELD5<0b01000>;
37def FIELD5_MTTR : FIELD5<0b01100>;
38
39class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
40  bits<32> Inst;
41
42  bits<5> rt;
43  let Inst{31-26} = 0b010000; // COP0
44  let Inst{25-21} = 0b01011;  // MFMC0
45  let Inst{20-16} = rt;
46  let Inst{15-11} = Op1.Value;
47  let Inst{10-6}  = Op2.Value;
48  let Inst{5}     = sc.Value;
49  let Inst{4-3}   = 0b00;
50  let Inst{2-0}   = 0b001;
51}
52
53class COP0_MFTTR_MT<FIELD5 Op> : MipsMTInst {
54  bits<32> Inst;
55
56  bits<5> rt;
57  bits<5> rd;
58  bits<1> u;
59  bits<1> h;
60  bits<3> sel;
61  let Inst{31-26} = 0b010000; // COP0
62  let Inst{25-21} = Op.Value; // MFMC0
63  let Inst{20-16} = rt;
64  let Inst{15-11} = rd;
65  let Inst{10-6}  = 0b00000;  // rx - currently unsupported.
66  let Inst{5}     = u;
67  let Inst{4}     = h;
68  let Inst{3}     = 0b0;
69  let Inst{2-0}   = sel;
70}
71
72class SPECIAL3_MT_FORK : MipsMTInst {
73  bits<32> Inst;
74
75  bits<5> rs;
76  bits<5> rt;
77  bits<5> rd;
78  let Inst{31-26} = 0b011111; // SPECIAL3
79  let Inst{25-21} = rs;
80  let Inst{20-16} = rt;
81  let Inst{15-11} = rd;
82  let Inst{10-6}  = 0b00000;
83  let Inst{5-0}   = 0b001000; // FORK
84}
85
86class SPECIAL3_MT_YIELD : MipsMTInst {
87  bits<32> Inst;
88
89  bits<5> rs;
90  bits<5> rd;
91  let Inst{31-26} = 0b011111; // SPECIAL3
92  let Inst{25-21} = rs;
93  let Inst{20-16} = 0b00000;
94  let Inst{15-11} = rd;
95  let Inst{10-6}  = 0b00000;
96  let Inst{5-0}   = 0b001001; // FORK
97}
98