1//===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes Mips MSA ASE instructions. 10// 11//===----------------------------------------------------------------------===// 12 13def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>; 14def SDT_VSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>, 15 SDTCisInt<1>, 16 SDTCisSameAs<1, 2>, 17 SDTCisVT<3, OtherVT>]>; 18def SDT_VFSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>, 19 SDTCisFP<1>, 20 SDTCisSameAs<1, 2>, 21 SDTCisVT<3, OtherVT>]>; 22def SDT_VSHF : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>, 23 SDTCisInt<1>, SDTCisVec<1>, 24 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>; 25def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>, 26 SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>; 27def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>, 28 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>; 29def SDT_INSVE : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0, 1>, 30 SDTCisVT<2, i32>, SDTCisSameAs<0, 3>, 31 SDTCisVT<4, i32>]>; 32 33def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>; 34def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>; 35def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>; 36def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>; 37def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp, 38 [SDNPCommutative, SDNPAssociative]>; 39def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>; 40def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>; 41def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>; 42def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>; 43def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>; 44def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>; 45def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>; 46def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>; 47def MipsINSVE : SDNode<"MipsISD::INSVE", SDT_INSVE>; 48def MipsFMS : SDNode<"MipsISD::FMS", SDTFPTernaryOp>; 49 50def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>; 51def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>; 52 53def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT", 54 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>; 55def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT", 56 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>; 57 58def immZExt1Ptr : ImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>; 59def immZExt2Ptr : ImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>; 60def immZExt3Ptr : ImmLeaf<iPTR, [{return isUInt<3>(Imm);}]>; 61def immZExt4Ptr : ImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>; 62 63// Operands 64 65def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>; 66 67// Pattern fragments 68def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx), 69 (MipsVExtractSExt node:$vec, node:$idx, i8)>; 70def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx), 71 (MipsVExtractSExt node:$vec, node:$idx, i16)>; 72def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx), 73 (MipsVExtractSExt node:$vec, node:$idx, i32)>; 74def vextract_sext_i64 : PatFrag<(ops node:$vec, node:$idx), 75 (MipsVExtractSExt node:$vec, node:$idx, i64)>; 76 77def vextract_zext_i8 : PatFrag<(ops node:$vec, node:$idx), 78 (MipsVExtractZExt node:$vec, node:$idx, i8)>; 79def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx), 80 (MipsVExtractZExt node:$vec, node:$idx, i16)>; 81def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx), 82 (MipsVExtractZExt node:$vec, node:$idx, i32)>; 83def vextract_zext_i64 : PatFrag<(ops node:$vec, node:$idx), 84 (MipsVExtractZExt node:$vec, node:$idx, i64)>; 85 86def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx), 87 (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>; 88def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx), 89 (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>; 90def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx), 91 (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>; 92def vinsert_v2i64 : PatFrag<(ops node:$vec, node:$val, node:$idx), 93 (v2i64 (vector_insert node:$vec, node:$val, node:$idx))>; 94 95def insve_v16i8 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 96 (v16i8 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 97def insve_v8i16 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 98 (v8i16 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 99def insve_v4i32 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 100 (v4i32 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 101def insve_v2i64 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 102 (v2i64 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 103 104class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> : 105 PatFrag<(ops node:$lhs, node:$rhs), 106 (ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>; 107 108// ISD::SETFALSE cannot occur 109def vfseteq_v4f32 : vfsetcc_type<v4i32, v4f32, SETEQ>; 110def vfseteq_v2f64 : vfsetcc_type<v2i64, v2f64, SETEQ>; 111def vfsetge_v4f32 : vfsetcc_type<v4i32, v4f32, SETGE>; 112def vfsetge_v2f64 : vfsetcc_type<v2i64, v2f64, SETGE>; 113def vfsetgt_v4f32 : vfsetcc_type<v4i32, v4f32, SETGT>; 114def vfsetgt_v2f64 : vfsetcc_type<v2i64, v2f64, SETGT>; 115def vfsetle_v4f32 : vfsetcc_type<v4i32, v4f32, SETLE>; 116def vfsetle_v2f64 : vfsetcc_type<v2i64, v2f64, SETLE>; 117def vfsetlt_v4f32 : vfsetcc_type<v4i32, v4f32, SETLT>; 118def vfsetlt_v2f64 : vfsetcc_type<v2i64, v2f64, SETLT>; 119def vfsetne_v4f32 : vfsetcc_type<v4i32, v4f32, SETNE>; 120def vfsetne_v2f64 : vfsetcc_type<v2i64, v2f64, SETNE>; 121def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>; 122def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>; 123def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>; 124def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>; 125def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>; 126def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>; 127def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>; 128def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>; 129def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>; 130def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>; 131def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>; 132def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>; 133def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>; 134def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>; 135def vfsetun_v4f32 : vfsetcc_type<v4i32, v4f32, SETUO>; 136def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>; 137def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>; 138def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>; 139def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>; 140def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>; 141def vfsetugt_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGT>; 142def vfsetugt_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGT>; 143def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>; 144def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>; 145def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>; 146def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>; 147def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>; 148def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>; 149// ISD::SETTRUE cannot occur 150// ISD::SETFALSE2 cannot occur 151// ISD::SETTRUE2 cannot occur 152 153class vsetcc_type<ValueType ResTy, CondCode CC> : 154 PatFrag<(ops node:$lhs, node:$rhs), 155 (ResTy (vsetcc node:$lhs, node:$rhs, CC))>; 156 157def vseteq_v16i8 : vsetcc_type<v16i8, SETEQ>; 158def vseteq_v8i16 : vsetcc_type<v8i16, SETEQ>; 159def vseteq_v4i32 : vsetcc_type<v4i32, SETEQ>; 160def vseteq_v2i64 : vsetcc_type<v2i64, SETEQ>; 161def vsetle_v16i8 : vsetcc_type<v16i8, SETLE>; 162def vsetle_v8i16 : vsetcc_type<v8i16, SETLE>; 163def vsetle_v4i32 : vsetcc_type<v4i32, SETLE>; 164def vsetle_v2i64 : vsetcc_type<v2i64, SETLE>; 165def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>; 166def vsetlt_v8i16 : vsetcc_type<v8i16, SETLT>; 167def vsetlt_v4i32 : vsetcc_type<v4i32, SETLT>; 168def vsetlt_v2i64 : vsetcc_type<v2i64, SETLT>; 169def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>; 170def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>; 171def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>; 172def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>; 173def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>; 174def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>; 175def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>; 176def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>; 177 178def vsplati8 : PatFrag<(ops node:$e0), 179 (v16i8 (build_vector node:$e0, node:$e0, 180 node:$e0, node:$e0, 181 node:$e0, node:$e0, 182 node:$e0, node:$e0, 183 node:$e0, node:$e0, 184 node:$e0, node:$e0, 185 node:$e0, node:$e0, 186 node:$e0, node:$e0))>; 187def vsplati16 : PatFrag<(ops node:$e0), 188 (v8i16 (build_vector node:$e0, node:$e0, 189 node:$e0, node:$e0, 190 node:$e0, node:$e0, 191 node:$e0, node:$e0))>; 192def vsplati32 : PatFrag<(ops node:$e0), 193 (v4i32 (build_vector node:$e0, node:$e0, 194 node:$e0, node:$e0))>; 195 196def vsplati64_imm_eq_1 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{ 197 APInt Imm; 198 SDNode *BV = N->getOperand(0).getNode(); 199 EVT EltTy = N->getValueType(0).getVectorElementType(); 200 201 return selectVSplat(BV, Imm, EltTy.getSizeInBits()) && 202 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; 203}]>; 204 205def vsplati64 : PatFrag<(ops node:$e0), 206 (v2i64 (build_vector node:$e0, node:$e0))>; 207 208def vsplati64_splat_d : PatFrag<(ops node:$e0), 209 (v2i64 (bitconvert 210 (v4i32 (and 211 (v4i32 (build_vector node:$e0, 212 node:$e0, 213 node:$e0, 214 node:$e0)), 215 vsplati64_imm_eq_1))))>; 216 217def vsplatf32 : PatFrag<(ops node:$e0), 218 (v4f32 (build_vector node:$e0, node:$e0, 219 node:$e0, node:$e0))>; 220def vsplatf64 : PatFrag<(ops node:$e0), 221 (v2f64 (build_vector node:$e0, node:$e0))>; 222 223def vsplati8_elt : PatFrag<(ops node:$v, node:$i), 224 (MipsVSHF (vsplati8 node:$i), node:$v, node:$v)>; 225def vsplati16_elt : PatFrag<(ops node:$v, node:$i), 226 (MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>; 227def vsplati32_elt : PatFrag<(ops node:$v, node:$i), 228 (MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>; 229def vsplati64_elt : PatFrag<(ops node:$v, node:$i), 230 (MipsVSHF (vsplati64_splat_d node:$i), 231 node:$v, node:$v)>; 232 233class SplatPatLeaf<Operand opclass, dag frag, code pred = [{}], 234 SDNodeXForm xform = NOOP_SDNodeXForm> 235 : PatLeaf<frag, pred, xform> { 236 Operand OpClass = opclass; 237} 238 239class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn, 240 list<SDNode> roots = [], 241 list<SDNodeProperty> props = []> : 242 ComplexPattern<ty, numops, fn, roots, props> { 243 Operand OpClass = opclass; 244} 245 246def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1, 247 "selectVSplatUimm3", 248 [build_vector, bitconvert]>; 249 250def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1, 251 "selectVSplatUimm4", 252 [build_vector, bitconvert]>; 253 254def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1, 255 "selectVSplatUimm5", 256 [build_vector, bitconvert]>; 257 258def vsplati8_uimm8 : SplatComplexPattern<vsplat_uimm8, v16i8, 1, 259 "selectVSplatUimm8", 260 [build_vector, bitconvert]>; 261 262def vsplati8_simm5 : SplatComplexPattern<vsplat_simm5, v16i8, 1, 263 "selectVSplatSimm5", 264 [build_vector, bitconvert]>; 265 266def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1, 267 "selectVSplatUimm3", 268 [build_vector, bitconvert]>; 269 270def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1, 271 "selectVSplatUimm4", 272 [build_vector, bitconvert]>; 273 274def vsplati16_uimm5 : SplatComplexPattern<vsplat_uimm5, v8i16, 1, 275 "selectVSplatUimm5", 276 [build_vector, bitconvert]>; 277 278def vsplati16_simm5 : SplatComplexPattern<vsplat_simm5, v8i16, 1, 279 "selectVSplatSimm5", 280 [build_vector, bitconvert]>; 281 282def vsplati32_uimm2 : SplatComplexPattern<vsplat_uimm2, v4i32, 1, 283 "selectVSplatUimm2", 284 [build_vector, bitconvert]>; 285 286def vsplati32_uimm5 : SplatComplexPattern<vsplat_uimm5, v4i32, 1, 287 "selectVSplatUimm5", 288 [build_vector, bitconvert]>; 289 290def vsplati32_simm5 : SplatComplexPattern<vsplat_simm5, v4i32, 1, 291 "selectVSplatSimm5", 292 [build_vector, bitconvert]>; 293 294def vsplati64_uimm1 : SplatComplexPattern<vsplat_uimm1, v2i64, 1, 295 "selectVSplatUimm1", 296 [build_vector, bitconvert]>; 297 298def vsplati64_uimm5 : SplatComplexPattern<vsplat_uimm5, v2i64, 1, 299 "selectVSplatUimm5", 300 [build_vector, bitconvert]>; 301 302def vsplati64_uimm6 : SplatComplexPattern<vsplat_uimm6, v2i64, 1, 303 "selectVSplatUimm6", 304 [build_vector, bitconvert]>; 305 306def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1, 307 "selectVSplatSimm5", 308 [build_vector, bitconvert]>; 309 310// Any build_vector that is a constant splat with a value that is an exact 311// power of 2 312def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2", 313 [build_vector, bitconvert]>; 314 315// Any build_vector that is a constant splat with a value that is the bitwise 316// inverse of an exact power of 2 317def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2", 318 [build_vector, bitconvert]>; 319 320// Any build_vector that is a constant splat with only a consecutive sequence 321// of left-most bits set. 322def vsplat_maskl_bits_uimm3 323 : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskL", 324 [build_vector, bitconvert]>; 325def vsplat_maskl_bits_uimm4 326 : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskL", 327 [build_vector, bitconvert]>; 328def vsplat_maskl_bits_uimm5 329 : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskL", 330 [build_vector, bitconvert]>; 331def vsplat_maskl_bits_uimm6 332 : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskL", 333 [build_vector, bitconvert]>; 334 335// Any build_vector that is a constant splat with only a consecutive sequence 336// of right-most bits set. 337def vsplat_maskr_bits_uimm3 338 : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskR", 339 [build_vector, bitconvert]>; 340def vsplat_maskr_bits_uimm4 341 : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskR", 342 [build_vector, bitconvert]>; 343def vsplat_maskr_bits_uimm5 344 : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskR", 345 [build_vector, bitconvert]>; 346def vsplat_maskr_bits_uimm6 347 : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskR", 348 [build_vector, bitconvert]>; 349 350// Any build_vector that is a constant splat with a value that equals 1 351// FIXME: These should be a ComplexPattern but we can't use them because the 352// ISel generator requires the uses to have a name, but providing a name 353// causes other errors ("used in pattern but not operand list") 354def vsplat_imm_eq_1 : PatLeaf<(build_vector), [{ 355 APInt Imm; 356 EVT EltTy = N->getValueType(0).getVectorElementType(); 357 358 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 359 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; 360}]>; 361 362def vbclr_b : PatFrag<(ops node:$ws, node:$wt), 363 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 364 immAllOnesV))>; 365def vbclr_h : PatFrag<(ops node:$ws, node:$wt), 366 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 367 immAllOnesV))>; 368def vbclr_w : PatFrag<(ops node:$ws, node:$wt), 369 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 370 immAllOnesV))>; 371def vbclr_d : PatFrag<(ops node:$ws, node:$wt), 372 (and node:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1), 373 node:$wt), 374 (bitconvert (v4i32 immAllOnesV))))>; 375 376def vbneg_b : PatFrag<(ops node:$ws, node:$wt), 377 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 378def vbneg_h : PatFrag<(ops node:$ws, node:$wt), 379 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 380def vbneg_w : PatFrag<(ops node:$ws, node:$wt), 381 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 382def vbneg_d : PatFrag<(ops node:$ws, node:$wt), 383 (xor node:$ws, (shl (v2i64 vsplati64_imm_eq_1), 384 node:$wt))>; 385 386def vbset_b : PatFrag<(ops node:$ws, node:$wt), 387 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 388def vbset_h : PatFrag<(ops node:$ws, node:$wt), 389 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 390def vbset_w : PatFrag<(ops node:$ws, node:$wt), 391 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 392def vbset_d : PatFrag<(ops node:$ws, node:$wt), 393 (or node:$ws, (shl (v2i64 vsplati64_imm_eq_1), 394 node:$wt))>; 395 396def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt), 397 (add node:$wd, (mul node:$ws, node:$wt))>; 398 399def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt), 400 (sub node:$wd, (mul node:$ws, node:$wt))>; 401 402def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt), 403 (fmul node:$ws, (fexp2 node:$wt))>; 404 405// Instruction encoding. 406class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>; 407class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>; 408class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>; 409class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>; 410 411class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>; 412class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>; 413class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>; 414class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>; 415 416class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>; 417class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>; 418class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>; 419class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>; 420 421class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>; 422class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>; 423class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>; 424class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>; 425 426class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>; 427class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>; 428class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>; 429class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>; 430 431class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>; 432class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>; 433class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>; 434class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>; 435 436class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>; 437 438class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>; 439 440class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>; 441class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>; 442class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>; 443class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>; 444 445class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>; 446class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>; 447class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>; 448class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>; 449 450class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>; 451class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>; 452class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>; 453class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>; 454 455class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>; 456class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>; 457class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>; 458class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>; 459 460class AVER_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010000>; 461class AVER_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010000>; 462class AVER_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010000>; 463class AVER_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010000>; 464 465class AVER_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010000>; 466class AVER_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010000>; 467class AVER_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010000>; 468class AVER_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010000>; 469 470class BCLR_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001101>; 471class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>; 472class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>; 473class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>; 474 475class BCLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001001>; 476class BCLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001001>; 477class BCLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001001>; 478class BCLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001001>; 479 480class BINSL_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001101>; 481class BINSL_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001101>; 482class BINSL_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001101>; 483class BINSL_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001101>; 484 485class BINSLI_B_ENC : MSA_BIT_B_FMT<0b110, 0b001001>; 486class BINSLI_H_ENC : MSA_BIT_H_FMT<0b110, 0b001001>; 487class BINSLI_W_ENC : MSA_BIT_W_FMT<0b110, 0b001001>; 488class BINSLI_D_ENC : MSA_BIT_D_FMT<0b110, 0b001001>; 489 490class BINSR_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001101>; 491class BINSR_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001101>; 492class BINSR_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001101>; 493class BINSR_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001101>; 494 495class BINSRI_B_ENC : MSA_BIT_B_FMT<0b111, 0b001001>; 496class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>; 497class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>; 498class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>; 499 500class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>; 501 502class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>; 503 504class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>; 505 506class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>; 507 508class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>; 509class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>; 510class BNEG_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001101>; 511class BNEG_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001101>; 512 513class BNEGI_B_ENC : MSA_BIT_B_FMT<0b101, 0b001001>; 514class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>; 515class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>; 516class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>; 517 518class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>; 519class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>; 520class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>; 521class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>; 522 523class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01111>; 524 525class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>; 526 527class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>; 528 529class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>; 530class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>; 531class BSET_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001101>; 532class BSET_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001101>; 533 534class BSETI_B_ENC : MSA_BIT_B_FMT<0b100, 0b001001>; 535class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>; 536class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>; 537class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>; 538 539class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>; 540class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>; 541class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>; 542class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>; 543 544class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>; 545 546class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>; 547class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>; 548class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>; 549class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>; 550 551class CEQI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000111>; 552class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>; 553class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>; 554class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>; 555 556class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>; 557 558class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>; 559class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>; 560class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>; 561class CLE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001111>; 562 563class CLE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001111>; 564class CLE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001111>; 565class CLE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001111>; 566class CLE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001111>; 567 568class CLEI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000111>; 569class CLEI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000111>; 570class CLEI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000111>; 571class CLEI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000111>; 572 573class CLEI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000111>; 574class CLEI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000111>; 575class CLEI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000111>; 576class CLEI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000111>; 577 578class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>; 579class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>; 580class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>; 581class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>; 582 583class CLT_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001111>; 584class CLT_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001111>; 585class CLT_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001111>; 586class CLT_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001111>; 587 588class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>; 589class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>; 590class CLTI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000111>; 591class CLTI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000111>; 592 593class CLTI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000111>; 594class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>; 595class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>; 596class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>; 597 598class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>; 599class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>; 600class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>; 601class COPY_S_D_ENC : MSA_ELM_COPY_D_FMT<0b0010, 0b011001>; 602 603class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>; 604class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>; 605class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>; 606 607class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>; 608 609class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>; 610class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>; 611class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>; 612class DIV_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010010>; 613 614class DIV_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010010>; 615class DIV_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010010>; 616class DIV_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010010>; 617class DIV_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010010>; 618 619class DOTP_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010011>; 620class DOTP_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010011>; 621class DOTP_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010011>; 622 623class DOTP_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010011>; 624class DOTP_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010011>; 625class DOTP_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010011>; 626 627class DPADD_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010011>; 628class DPADD_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010011>; 629class DPADD_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010011>; 630 631class DPADD_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010011>; 632class DPADD_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010011>; 633class DPADD_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010011>; 634 635class DPSUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010011>; 636class DPSUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010011>; 637class DPSUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010011>; 638 639class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>; 640class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>; 641class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>; 642 643class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>; 644class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>; 645 646class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>; 647class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>; 648 649class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>; 650class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>; 651 652class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>; 653class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>; 654 655class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>; 656class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>; 657 658class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>; 659class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>; 660 661class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>; 662class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>; 663 664class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>; 665class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>; 666 667class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>; 668class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>; 669 670class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>; 671class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>; 672 673class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>; 674class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>; 675 676class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>; 677class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>; 678 679class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>; 680class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>; 681 682class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>; 683class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>; 684 685class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>; 686class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>; 687 688class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>; 689class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>; 690 691class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>; 692class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>; 693 694class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>; 695class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>; 696 697class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>; 698class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>; 699 700class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>; 701class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>; 702 703class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>; 704class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>; 705 706class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>; 707class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>; 708 709class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>; 710class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>; 711class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>; 712class FILL_D_ENC : MSA_2R_FILL_D_FMT<0b11000000, 0b11, 0b011110>; 713 714class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>; 715class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>; 716 717class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>; 718class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>; 719 720class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>; 721class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>; 722 723class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>; 724class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>; 725 726class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>; 727class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>; 728 729class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>; 730class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>; 731 732class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>; 733class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>; 734 735class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>; 736class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>; 737 738class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>; 739class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>; 740 741class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>; 742class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>; 743 744class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>; 745class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>; 746 747class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>; 748class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>; 749 750class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>; 751class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>; 752 753class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>; 754class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>; 755 756class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>; 757class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>; 758 759class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>; 760class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>; 761 762class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>; 763class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>; 764 765class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>; 766class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>; 767 768class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>; 769class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>; 770 771class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>; 772class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>; 773 774class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>; 775class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>; 776 777class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>; 778class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>; 779 780class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>; 781class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>; 782 783class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>; 784class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>; 785 786class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>; 787class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>; 788 789class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>; 790class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>; 791 792class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>; 793class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>; 794 795class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>; 796class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>; 797 798class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>; 799class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>; 800 801class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>; 802class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>; 803class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>; 804 805class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>; 806class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>; 807class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>; 808 809class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>; 810class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>; 811class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>; 812 813class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>; 814class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>; 815class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>; 816 817class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>; 818class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>; 819class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>; 820class ILVEV_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010100>; 821 822class ILVL_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010100>; 823class ILVL_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010100>; 824class ILVL_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010100>; 825class ILVL_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010100>; 826 827class ILVOD_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010100>; 828class ILVOD_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010100>; 829class ILVOD_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010100>; 830class ILVOD_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010100>; 831 832class ILVR_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010100>; 833class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>; 834class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>; 835class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>; 836 837class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>; 838class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>; 839class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>; 840class INSERT_D_ENC : MSA_ELM_INSERT_D_FMT<0b0100, 0b011001>; 841 842class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>; 843class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>; 844class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>; 845class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>; 846 847class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>; 848class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>; 849class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>; 850class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>; 851 852class LDI_B_ENC : MSA_I10_FMT<0b110, 0b00, 0b000111>; 853class LDI_H_ENC : MSA_I10_FMT<0b110, 0b01, 0b000111>; 854class LDI_W_ENC : MSA_I10_FMT<0b110, 0b10, 0b000111>; 855class LDI_D_ENC : MSA_I10_FMT<0b110, 0b11, 0b000111>; 856 857class LSA_ENC : SPECIAL_LSA_FMT<0b000101>; 858class DLSA_ENC : SPECIAL_DLSA_FMT<0b010101>; 859 860class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>; 861class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>; 862 863class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>; 864class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>; 865 866class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>; 867class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>; 868class MADDV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010010>; 869class MADDV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010010>; 870 871class MAX_A_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001110>; 872class MAX_A_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001110>; 873class MAX_A_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001110>; 874class MAX_A_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001110>; 875 876class MAX_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001110>; 877class MAX_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001110>; 878class MAX_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001110>; 879class MAX_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001110>; 880 881class MAX_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001110>; 882class MAX_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001110>; 883class MAX_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001110>; 884class MAX_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001110>; 885 886class MAXI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000110>; 887class MAXI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000110>; 888class MAXI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000110>; 889class MAXI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000110>; 890 891class MAXI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000110>; 892class MAXI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000110>; 893class MAXI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000110>; 894class MAXI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000110>; 895 896class MIN_A_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001110>; 897class MIN_A_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001110>; 898class MIN_A_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001110>; 899class MIN_A_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001110>; 900 901class MIN_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001110>; 902class MIN_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001110>; 903class MIN_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001110>; 904class MIN_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001110>; 905 906class MIN_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001110>; 907class MIN_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001110>; 908class MIN_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001110>; 909class MIN_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001110>; 910 911class MINI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000110>; 912class MINI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000110>; 913class MINI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000110>; 914class MINI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000110>; 915 916class MINI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000110>; 917class MINI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000110>; 918class MINI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000110>; 919class MINI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000110>; 920 921class MOD_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010010>; 922class MOD_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010010>; 923class MOD_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010010>; 924class MOD_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010010>; 925 926class MOD_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010010>; 927class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>; 928class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>; 929class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>; 930 931class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>; 932 933class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>; 934class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>; 935 936class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>; 937class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>; 938 939class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>; 940class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>; 941class MSUBV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010010>; 942class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>; 943 944class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>; 945class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>; 946 947class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>; 948class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>; 949 950class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>; 951class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>; 952class MULV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010010>; 953class MULV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010010>; 954 955class NLOC_B_ENC : MSA_2R_FMT<0b11000010, 0b00, 0b011110>; 956class NLOC_H_ENC : MSA_2R_FMT<0b11000010, 0b01, 0b011110>; 957class NLOC_W_ENC : MSA_2R_FMT<0b11000010, 0b10, 0b011110>; 958class NLOC_D_ENC : MSA_2R_FMT<0b11000010, 0b11, 0b011110>; 959 960class NLZC_B_ENC : MSA_2R_FMT<0b11000011, 0b00, 0b011110>; 961class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>; 962class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>; 963class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>; 964 965class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>; 966 967class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>; 968 969class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>; 970 971class ORI_B_ENC : MSA_I8_FMT<0b01, 0b000000>; 972 973class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>; 974class PCKEV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010100>; 975class PCKEV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010100>; 976class PCKEV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010100>; 977 978class PCKOD_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010100>; 979class PCKOD_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010100>; 980class PCKOD_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010100>; 981class PCKOD_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010100>; 982 983class PCNT_B_ENC : MSA_2R_FMT<0b11000001, 0b00, 0b011110>; 984class PCNT_H_ENC : MSA_2R_FMT<0b11000001, 0b01, 0b011110>; 985class PCNT_W_ENC : MSA_2R_FMT<0b11000001, 0b10, 0b011110>; 986class PCNT_D_ENC : MSA_2R_FMT<0b11000001, 0b11, 0b011110>; 987 988class SAT_S_B_ENC : MSA_BIT_B_FMT<0b000, 0b001010>; 989class SAT_S_H_ENC : MSA_BIT_H_FMT<0b000, 0b001010>; 990class SAT_S_W_ENC : MSA_BIT_W_FMT<0b000, 0b001010>; 991class SAT_S_D_ENC : MSA_BIT_D_FMT<0b000, 0b001010>; 992 993class SAT_U_B_ENC : MSA_BIT_B_FMT<0b001, 0b001010>; 994class SAT_U_H_ENC : MSA_BIT_H_FMT<0b001, 0b001010>; 995class SAT_U_W_ENC : MSA_BIT_W_FMT<0b001, 0b001010>; 996class SAT_U_D_ENC : MSA_BIT_D_FMT<0b001, 0b001010>; 997 998class SHF_B_ENC : MSA_I8_FMT<0b00, 0b000010>; 999class SHF_H_ENC : MSA_I8_FMT<0b01, 0b000010>; 1000class SHF_W_ENC : MSA_I8_FMT<0b10, 0b000010>; 1001 1002class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>; 1003class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>; 1004class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>; 1005class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>; 1006 1007class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>; 1008class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>; 1009class SLDI_W_ENC : MSA_ELM_W_FMT<0b0000, 0b011001>; 1010class SLDI_D_ENC : MSA_ELM_D_FMT<0b0000, 0b011001>; 1011 1012class SLL_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001101>; 1013class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>; 1014class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>; 1015class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>; 1016 1017class SLLI_B_ENC : MSA_BIT_B_FMT<0b000, 0b001001>; 1018class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>; 1019class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>; 1020class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>; 1021 1022class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>; 1023class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>; 1024class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>; 1025class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>; 1026 1027class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>; 1028class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>; 1029class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>; 1030class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>; 1031 1032class SRA_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001101>; 1033class SRA_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001101>; 1034class SRA_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001101>; 1035class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>; 1036 1037class SRAI_B_ENC : MSA_BIT_B_FMT<0b001, 0b001001>; 1038class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>; 1039class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>; 1040class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>; 1041 1042class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>; 1043class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>; 1044class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>; 1045class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>; 1046 1047class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>; 1048class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>; 1049class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>; 1050class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>; 1051 1052class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>; 1053class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>; 1054class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>; 1055class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>; 1056 1057class SRLI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001001>; 1058class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>; 1059class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>; 1060class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>; 1061 1062class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>; 1063class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>; 1064class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>; 1065class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>; 1066 1067class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>; 1068class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>; 1069class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>; 1070class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>; 1071 1072class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>; 1073class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>; 1074class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>; 1075class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>; 1076 1077class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>; 1078class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>; 1079class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>; 1080class SUBS_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010001>; 1081 1082class SUBS_U_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010001>; 1083class SUBS_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010001>; 1084class SUBS_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010001>; 1085class SUBS_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010001>; 1086 1087class SUBSUS_U_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010001>; 1088class SUBSUS_U_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010001>; 1089class SUBSUS_U_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010001>; 1090class SUBSUS_U_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010001>; 1091 1092class SUBSUU_S_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010001>; 1093class SUBSUU_S_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010001>; 1094class SUBSUU_S_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010001>; 1095class SUBSUU_S_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010001>; 1096 1097class SUBV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001110>; 1098class SUBV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001110>; 1099class SUBV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001110>; 1100class SUBV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001110>; 1101 1102class SUBVI_B_ENC : MSA_I5_FMT<0b001, 0b00, 0b000110>; 1103class SUBVI_H_ENC : MSA_I5_FMT<0b001, 0b01, 0b000110>; 1104class SUBVI_W_ENC : MSA_I5_FMT<0b001, 0b10, 0b000110>; 1105class SUBVI_D_ENC : MSA_I5_FMT<0b001, 0b11, 0b000110>; 1106 1107class VSHF_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010101>; 1108class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>; 1109class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>; 1110class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>; 1111 1112class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>; 1113 1114class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>; 1115 1116// Instruction desc. 1117class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1118 ComplexPattern Imm, RegisterOperand ROWD, 1119 RegisterOperand ROWS = ROWD, 1120 InstrItinClass itin = NoItinerary> { 1121 dag OutOperandList = (outs ROWD:$wd); 1122 dag InOperandList = (ins ROWS:$ws, vsplat_uimm3:$m); 1123 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1124 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1125 InstrItinClass Itinerary = itin; 1126} 1127 1128class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1129 ComplexPattern Imm, RegisterOperand ROWD, 1130 RegisterOperand ROWS = ROWD, 1131 InstrItinClass itin = NoItinerary> { 1132 dag OutOperandList = (outs ROWD:$wd); 1133 dag InOperandList = (ins ROWS:$ws, vsplat_uimm4:$m); 1134 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1135 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1136 InstrItinClass Itinerary = itin; 1137} 1138 1139class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1140 ComplexPattern Imm, RegisterOperand ROWD, 1141 RegisterOperand ROWS = ROWD, 1142 InstrItinClass itin = NoItinerary> { 1143 dag OutOperandList = (outs ROWD:$wd); 1144 dag InOperandList = (ins ROWS:$ws, vsplat_uimm5:$m); 1145 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1146 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1147 InstrItinClass Itinerary = itin; 1148} 1149 1150class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1151 ComplexPattern Imm, RegisterOperand ROWD, 1152 RegisterOperand ROWS = ROWD, 1153 InstrItinClass itin = NoItinerary> { 1154 dag OutOperandList = (outs ROWD:$wd); 1155 dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m); 1156 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1157 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1158 InstrItinClass Itinerary = itin; 1159} 1160 1161class MSA_BIT_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1162 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1163 RegisterOperand ROWS = ROWD, 1164 InstrItinClass itin = NoItinerary> { 1165 dag OutOperandList = (outs ROWD:$wd); 1166 dag InOperandList = (ins ROWS:$ws, ImmOp:$m); 1167 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1168 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1169 InstrItinClass Itinerary = itin; 1170} 1171 1172class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty, 1173 SplatComplexPattern Mask, RegisterOperand ROWD, 1174 RegisterOperand ROWS = ROWD, 1175 InstrItinClass itin = NoItinerary> { 1176 dag OutOperandList = (outs ROWD:$wd); 1177 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, Mask.OpClass:$m); 1178 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1179 // Note that binsxi and vselect treat the condition operand the opposite 1180 // way to each other. 1181 // (vselect cond, if_set, if_clear) 1182 // (BSEL_V cond, if_clear, if_set) 1183 list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$ws), 1184 ROWS:$wd_in))]; 1185 InstrItinClass Itinerary = itin; 1186 string Constraints = "$wd = $wd_in"; 1187} 1188 1189class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty, 1190 SplatComplexPattern ImmOp, RegisterOperand ROWD, 1191 RegisterOperand ROWS = ROWD, 1192 InstrItinClass itin = NoItinerary> : 1193 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>; 1194 1195class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty, 1196 SplatComplexPattern ImmOp, RegisterOperand ROWD, 1197 RegisterOperand ROWS = ROWD, 1198 InstrItinClass itin = NoItinerary> : 1199 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>; 1200 1201class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1202 SplatComplexPattern SplatImm, 1203 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1204 InstrItinClass itin = NoItinerary> { 1205 dag OutOperandList = (outs ROWD:$wd); 1206 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m); 1207 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1208 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))]; 1209 InstrItinClass Itinerary = itin; 1210} 1211 1212class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1213 ValueType VecTy, Operand ImmOp, ImmLeaf Imm, 1214 RegisterOperand ROD, RegisterOperand ROWS, 1215 InstrItinClass itin = NoItinerary> { 1216 dag OutOperandList = (outs ROD:$rd); 1217 dag InOperandList = (ins ROWS:$ws, ImmOp:$n); 1218 string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]"); 1219 list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), Imm:$n))]; 1220 InstrItinClass Itinerary = itin; 1221} 1222 1223class MSA_ELM_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1224 RegisterOperand ROWD, RegisterOperand ROWS, 1225 Operand ImmOp, ImmLeaf Imm, 1226 InstrItinClass itin = NoItinerary> { 1227 dag OutOperandList = (outs ROWD:$wd); 1228 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ImmOp:$n); 1229 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]"); 1230 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1231 Imm:$n))]; 1232 string Constraints = "$wd = $wd_in"; 1233 InstrItinClass Itinerary = itin; 1234} 1235 1236class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy, 1237 Operand ImmOp, ImmLeaf Imm, RegisterClass RCD, 1238 RegisterClass RCWS> : 1239 MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, ImmOp:$n), 1240 [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), Imm:$n))]> { 1241 bit usesCustomInserter = 1; 1242 bit hasNoSchedulingInfo = 1; 1243} 1244 1245class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1246 SplatComplexPattern SplatImm, RegisterOperand ROWD, 1247 RegisterOperand ROWS = ROWD, 1248 InstrItinClass itin = NoItinerary> { 1249 dag OutOperandList = (outs ROWD:$wd); 1250 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm); 1251 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm"); 1252 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))]; 1253 InstrItinClass Itinerary = itin; 1254} 1255 1256class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1257 SplatComplexPattern SplatImm, RegisterOperand ROWD, 1258 RegisterOperand ROWS = ROWD, 1259 InstrItinClass itin = NoItinerary> { 1260 dag OutOperandList = (outs ROWD:$wd); 1261 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8); 1262 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8"); 1263 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))]; 1264 InstrItinClass Itinerary = itin; 1265} 1266 1267class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1268 RegisterOperand ROWS = ROWD, 1269 InstrItinClass itin = NoItinerary> { 1270 dag OutOperandList = (outs ROWD:$wd); 1271 dag InOperandList = (ins ROWS:$ws, uimm8:$u8); 1272 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8"); 1273 list<dag> Pattern = [(set ROWD:$wd, (MipsSHF immZExt8:$u8, ROWS:$ws))]; 1274 InstrItinClass Itinerary = itin; 1275} 1276 1277class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1278 InstrItinClass itin = NoItinerary> { 1279 dag OutOperandList = (outs ROWD:$wd); 1280 dag InOperandList = (ins vsplat_simm10:$s10); 1281 string AsmString = !strconcat(instr_asm, "\t$wd, $s10"); 1282 // LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp 1283 list<dag> Pattern = []; 1284 bit hasSideEffects = 0; 1285 InstrItinClass Itinerary = itin; 1286} 1287 1288class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1289 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1290 InstrItinClass itin = NoItinerary> { 1291 dag OutOperandList = (outs ROWD:$wd); 1292 dag InOperandList = (ins ROWS:$ws); 1293 string AsmString = !strconcat(instr_asm, "\t$wd, $ws"); 1294 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))]; 1295 InstrItinClass Itinerary = itin; 1296} 1297 1298class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT, 1299 SDPatternOperator OpNode, RegisterOperand ROWD, 1300 RegisterOperand ROS = ROWD, 1301 InstrItinClass itin = NoItinerary> { 1302 dag OutOperandList = (outs ROWD:$wd); 1303 dag InOperandList = (ins ROS:$rs); 1304 string AsmString = !strconcat(instr_asm, "\t$wd, $rs"); 1305 list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))]; 1306 InstrItinClass Itinerary = itin; 1307} 1308 1309class MSA_2R_FILL_PSEUDO_BASE<ValueType VT, SDPatternOperator OpNode, 1310 RegisterClass RCWD, RegisterClass RCWS = RCWD> : 1311 MSAPseudo<(outs RCWD:$wd), (ins RCWS:$fs), 1312 [(set RCWD:$wd, (OpNode RCWS:$fs))]> { 1313 let usesCustomInserter = 1; 1314} 1315 1316class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1317 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1318 InstrItinClass itin = NoItinerary> { 1319 dag OutOperandList = (outs ROWD:$wd); 1320 dag InOperandList = (ins ROWS:$ws); 1321 string AsmString = !strconcat(instr_asm, "\t$wd, $ws"); 1322 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))]; 1323 InstrItinClass Itinerary = itin; 1324} 1325 1326class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1327 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1328 RegisterOperand ROWT = ROWD, 1329 InstrItinClass itin = NoItinerary> { 1330 dag OutOperandList = (outs ROWD:$wd); 1331 dag InOperandList = (ins ROWS:$ws, ROWT:$wt); 1332 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1333 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]; 1334 InstrItinClass Itinerary = itin; 1335} 1336 1337class MSA_3R_BINSX_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1338 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1339 RegisterOperand ROWT = ROWD, 1340 InstrItinClass itin = NoItinerary> { 1341 dag OutOperandList = (outs ROWD:$wd); 1342 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1343 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1344 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1345 ROWT:$wt))]; 1346 string Constraints = "$wd = $wd_in"; 1347 InstrItinClass Itinerary = itin; 1348} 1349 1350class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1351 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1352 InstrItinClass itin = NoItinerary> { 1353 dag OutOperandList = (outs ROWD:$wd); 1354 dag InOperandList = (ins ROWS:$ws, GPR32Opnd:$rt); 1355 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]"); 1356 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32Opnd:$rt))]; 1357 InstrItinClass Itinerary = itin; 1358} 1359 1360class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1361 RegisterOperand ROWS = ROWD, 1362 RegisterOperand ROWT = ROWD, 1363 InstrItinClass itin = NoItinerary> { 1364 dag OutOperandList = (outs ROWD:$wd); 1365 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1366 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1367 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws, 1368 ROWT:$wt))]; 1369 string Constraints = "$wd = $wd_in"; 1370 InstrItinClass Itinerary = itin; 1371} 1372 1373class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1374 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1375 InstrItinClass itin = NoItinerary> { 1376 dag OutOperandList = (outs ROWD:$wd); 1377 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, GPR32Opnd:$rt); 1378 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]"); 1379 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1380 GPR32Opnd:$rt))]; 1381 InstrItinClass Itinerary = itin; 1382 string Constraints = "$wd = $wd_in"; 1383} 1384 1385class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1386 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1387 RegisterOperand ROWT = ROWD, 1388 InstrItinClass itin = NoItinerary> { 1389 dag OutOperandList = (outs ROWD:$wd); 1390 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1391 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1392 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1393 ROWT:$wt))]; 1394 InstrItinClass Itinerary = itin; 1395 string Constraints = "$wd = $wd_in"; 1396} 1397 1398class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1399 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1400 RegisterOperand ROWT = ROWD, 1401 InstrItinClass itin = NoItinerary> : 1402 MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>; 1403 1404class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1405 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1406 RegisterOperand ROWT = ROWD, 1407 InstrItinClass itin = NoItinerary> : 1408 MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>; 1409 1410class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> { 1411 dag OutOperandList = (outs); 1412 dag InOperandList = (ins ROWD:$wt, brtarget:$offset); 1413 string AsmString = !strconcat(instr_asm, "\t$wt, $offset"); 1414 list<dag> Pattern = []; 1415 InstrItinClass Itinerary = NoItinerary; 1416 bit isBranch = 1; 1417 bit isTerminator = 1; 1418 bit hasDelaySlot = 1; 1419 list<Register> Defs = [AT]; 1420} 1421 1422class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1423 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1424 RegisterOperand ROS, 1425 InstrItinClass itin = NoItinerary> { 1426 dag OutOperandList = (outs ROWD:$wd); 1427 dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, ImmOp:$n); 1428 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs"); 1429 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROS:$rs, Imm:$n))]; 1430 InstrItinClass Itinerary = itin; 1431 string Constraints = "$wd = $wd_in"; 1432} 1433 1434class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty, 1435 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1436 RegisterOperand ROFS> : 1437 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ImmOp:$n, ROFS:$fs), 1438 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, Imm:$n))]> { 1439 bit usesCustomInserter = 1; 1440 string Constraints = "$wd = $wd_in"; 1441} 1442 1443class MSA_INSERT_VIDX_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty, 1444 RegisterOperand ROWD, RegisterOperand ROFS, 1445 RegisterOperand ROIdx> : 1446 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ROIdx:$n, ROFS:$fs), 1447 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, 1448 ROIdx:$n))]> { 1449 bit usesCustomInserter = 1; 1450 bit hasNoSchedulingInfo = 1; 1451 string Constraints = "$wd = $wd_in"; 1452} 1453 1454class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1455 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1456 RegisterOperand ROWS = ROWD, 1457 InstrItinClass itin = NoItinerary> { 1458 dag OutOperandList = (outs ROWD:$wd); 1459 dag InOperandList = (ins ROWD:$wd_in, ImmOp:$n, ROWS:$ws, uimmz:$n2); 1460 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[$n2]"); 1461 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, 1462 Imm:$n, 1463 ROWS:$ws, 1464 immz:$n2))]; 1465 InstrItinClass Itinerary = itin; 1466 string Constraints = "$wd = $wd_in"; 1467} 1468 1469class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1470 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1471 RegisterOperand ROWT = ROWD, 1472 InstrItinClass itin = NoItinerary> { 1473 dag OutOperandList = (outs ROWD:$wd); 1474 dag InOperandList = (ins ROWS:$ws, ROWT:$wt); 1475 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1476 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]; 1477 InstrItinClass Itinerary = itin; 1478} 1479 1480class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm, 1481 RegisterOperand ROWD, 1482 RegisterOperand ROWS = ROWD, 1483 InstrItinClass itin = NoItinerary> { 1484 dag OutOperandList = (outs ROWD:$wd); 1485 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n); 1486 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]"); 1487 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws, 1488 ROWS:$ws))]; 1489 InstrItinClass Itinerary = itin; 1490} 1491 1492class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD, 1493 RegisterOperand ROWS = ROWD, 1494 RegisterOperand ROWT = ROWD> : 1495 MSAPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt), 1496 [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>; 1497 1498class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>, 1499 IsCommutable; 1500class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>, 1501 IsCommutable; 1502class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>, 1503 IsCommutable; 1504class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>, 1505 IsCommutable; 1506 1507class ADDS_A_B_DESC : MSA_3R_DESC_BASE<"adds_a.b", int_mips_adds_a_b, 1508 MSA128BOpnd>, IsCommutable; 1509class ADDS_A_H_DESC : MSA_3R_DESC_BASE<"adds_a.h", int_mips_adds_a_h, 1510 MSA128HOpnd>, IsCommutable; 1511class ADDS_A_W_DESC : MSA_3R_DESC_BASE<"adds_a.w", int_mips_adds_a_w, 1512 MSA128WOpnd>, IsCommutable; 1513class ADDS_A_D_DESC : MSA_3R_DESC_BASE<"adds_a.d", int_mips_adds_a_d, 1514 MSA128DOpnd>, IsCommutable; 1515 1516class ADDS_S_B_DESC : MSA_3R_DESC_BASE<"adds_s.b", int_mips_adds_s_b, 1517 MSA128BOpnd>, IsCommutable; 1518class ADDS_S_H_DESC : MSA_3R_DESC_BASE<"adds_s.h", int_mips_adds_s_h, 1519 MSA128HOpnd>, IsCommutable; 1520class ADDS_S_W_DESC : MSA_3R_DESC_BASE<"adds_s.w", int_mips_adds_s_w, 1521 MSA128WOpnd>, IsCommutable; 1522class ADDS_S_D_DESC : MSA_3R_DESC_BASE<"adds_s.d", int_mips_adds_s_d, 1523 MSA128DOpnd>, IsCommutable; 1524 1525class ADDS_U_B_DESC : MSA_3R_DESC_BASE<"adds_u.b", int_mips_adds_u_b, 1526 MSA128BOpnd>, IsCommutable; 1527class ADDS_U_H_DESC : MSA_3R_DESC_BASE<"adds_u.h", int_mips_adds_u_h, 1528 MSA128HOpnd>, IsCommutable; 1529class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w, 1530 MSA128WOpnd>, IsCommutable; 1531class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d, 1532 MSA128DOpnd>, IsCommutable; 1533 1534class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable; 1535class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable; 1536class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable; 1537class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable; 1538 1539class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5, 1540 MSA128BOpnd>; 1541class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5, 1542 MSA128HOpnd>; 1543class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5, 1544 MSA128WOpnd>; 1545class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5, 1546 MSA128DOpnd>; 1547 1548class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>; 1549class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128HOpnd>; 1550class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128WOpnd>; 1551class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128DOpnd>; 1552 1553class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8, 1554 MSA128BOpnd>; 1555 1556class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b, 1557 MSA128BOpnd>; 1558class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h, 1559 MSA128HOpnd>; 1560class ASUB_S_W_DESC : MSA_3R_DESC_BASE<"asub_s.w", int_mips_asub_s_w, 1561 MSA128WOpnd>; 1562class ASUB_S_D_DESC : MSA_3R_DESC_BASE<"asub_s.d", int_mips_asub_s_d, 1563 MSA128DOpnd>; 1564 1565class ASUB_U_B_DESC : MSA_3R_DESC_BASE<"asub_u.b", int_mips_asub_u_b, 1566 MSA128BOpnd>; 1567class ASUB_U_H_DESC : MSA_3R_DESC_BASE<"asub_u.h", int_mips_asub_u_h, 1568 MSA128HOpnd>; 1569class ASUB_U_W_DESC : MSA_3R_DESC_BASE<"asub_u.w", int_mips_asub_u_w, 1570 MSA128WOpnd>; 1571class ASUB_U_D_DESC : MSA_3R_DESC_BASE<"asub_u.d", int_mips_asub_u_d, 1572 MSA128DOpnd>; 1573 1574class AVE_S_B_DESC : MSA_3R_DESC_BASE<"ave_s.b", int_mips_ave_s_b, MSA128BOpnd>, 1575 IsCommutable; 1576class AVE_S_H_DESC : MSA_3R_DESC_BASE<"ave_s.h", int_mips_ave_s_h, MSA128HOpnd>, 1577 IsCommutable; 1578class AVE_S_W_DESC : MSA_3R_DESC_BASE<"ave_s.w", int_mips_ave_s_w, MSA128WOpnd>, 1579 IsCommutable; 1580class AVE_S_D_DESC : MSA_3R_DESC_BASE<"ave_s.d", int_mips_ave_s_d, MSA128DOpnd>, 1581 IsCommutable; 1582 1583class AVE_U_B_DESC : MSA_3R_DESC_BASE<"ave_u.b", int_mips_ave_u_b, MSA128BOpnd>, 1584 IsCommutable; 1585class AVE_U_H_DESC : MSA_3R_DESC_BASE<"ave_u.h", int_mips_ave_u_h, MSA128HOpnd>, 1586 IsCommutable; 1587class AVE_U_W_DESC : MSA_3R_DESC_BASE<"ave_u.w", int_mips_ave_u_w, MSA128WOpnd>, 1588 IsCommutable; 1589class AVE_U_D_DESC : MSA_3R_DESC_BASE<"ave_u.d", int_mips_ave_u_d, MSA128DOpnd>, 1590 IsCommutable; 1591 1592class AVER_S_B_DESC : MSA_3R_DESC_BASE<"aver_s.b", int_mips_aver_s_b, 1593 MSA128BOpnd>, IsCommutable; 1594class AVER_S_H_DESC : MSA_3R_DESC_BASE<"aver_s.h", int_mips_aver_s_h, 1595 MSA128HOpnd>, IsCommutable; 1596class AVER_S_W_DESC : MSA_3R_DESC_BASE<"aver_s.w", int_mips_aver_s_w, 1597 MSA128WOpnd>, IsCommutable; 1598class AVER_S_D_DESC : MSA_3R_DESC_BASE<"aver_s.d", int_mips_aver_s_d, 1599 MSA128DOpnd>, IsCommutable; 1600 1601class AVER_U_B_DESC : MSA_3R_DESC_BASE<"aver_u.b", int_mips_aver_u_b, 1602 MSA128BOpnd>, IsCommutable; 1603class AVER_U_H_DESC : MSA_3R_DESC_BASE<"aver_u.h", int_mips_aver_u_h, 1604 MSA128HOpnd>, IsCommutable; 1605class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w, 1606 MSA128WOpnd>, IsCommutable; 1607class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d, 1608 MSA128DOpnd>, IsCommutable; 1609 1610class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", vbclr_b, MSA128BOpnd>; 1611class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", vbclr_h, MSA128HOpnd>; 1612class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", vbclr_w, MSA128WOpnd>; 1613class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", vbclr_d, MSA128DOpnd>; 1614 1615class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", and, vsplat_uimm_inv_pow2, 1616 MSA128BOpnd>; 1617class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", and, vsplat_uimm_inv_pow2, 1618 MSA128HOpnd>; 1619class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", and, vsplat_uimm_inv_pow2, 1620 MSA128WOpnd>; 1621class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", and, vsplat_uimm_inv_pow2, 1622 MSA128DOpnd>; 1623 1624class BINSL_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.b", int_mips_binsl_b, 1625 MSA128BOpnd>; 1626class BINSL_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.h", int_mips_binsl_h, 1627 MSA128HOpnd>; 1628class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w, 1629 MSA128WOpnd>; 1630class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d, 1631 MSA128DOpnd>; 1632 1633class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, vsplat_maskl_bits_uimm3, MSA128BOpnd>; 1634class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, vsplat_maskl_bits_uimm4, MSA128HOpnd>; 1635class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, vsplat_maskl_bits_uimm5, MSA128WOpnd>; 1636class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, vsplat_maskl_bits_uimm6, MSA128DOpnd>; 1637 1638class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b, 1639 MSA128BOpnd>; 1640class BINSR_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.h", int_mips_binsr_h, 1641 MSA128HOpnd>; 1642class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w, 1643 MSA128WOpnd>; 1644class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d, 1645 MSA128DOpnd>; 1646 1647class BINSRI_B_DESC 1648 : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, vsplat_maskr_bits_uimm3, 1649 MSA128BOpnd>; 1650class BINSRI_H_DESC 1651 : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, vsplat_maskr_bits_uimm4, 1652 MSA128HOpnd>; 1653class BINSRI_W_DESC 1654 : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, vsplat_maskr_bits_uimm5, 1655 MSA128WOpnd>; 1656class BINSRI_D_DESC 1657 : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, vsplat_maskr_bits_uimm6, 1658 MSA128DOpnd>; 1659 1660class BMNZ_V_DESC { 1661 dag OutOperandList = (outs MSA128BOpnd:$wd); 1662 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1663 MSA128BOpnd:$wt); 1664 string AsmString = "bmnz.v\t$wd, $ws, $wt"; 1665 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt, 1666 MSA128BOpnd:$ws, 1667 MSA128BOpnd:$wd_in))]; 1668 InstrItinClass Itinerary = NoItinerary; 1669 string Constraints = "$wd = $wd_in"; 1670} 1671 1672class BMNZI_B_DESC { 1673 dag OutOperandList = (outs MSA128BOpnd:$wd); 1674 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1675 vsplat_uimm8:$u8); 1676 string AsmString = "bmnzi.b\t$wd, $ws, $u8"; 1677 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8, 1678 MSA128BOpnd:$ws, 1679 MSA128BOpnd:$wd_in))]; 1680 InstrItinClass Itinerary = NoItinerary; 1681 string Constraints = "$wd = $wd_in"; 1682} 1683 1684class BMZ_V_DESC { 1685 dag OutOperandList = (outs MSA128BOpnd:$wd); 1686 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1687 MSA128BOpnd:$wt); 1688 string AsmString = "bmz.v\t$wd, $ws, $wt"; 1689 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt, 1690 MSA128BOpnd:$wd_in, 1691 MSA128BOpnd:$ws))]; 1692 InstrItinClass Itinerary = NoItinerary; 1693 string Constraints = "$wd = $wd_in"; 1694} 1695 1696class BMZI_B_DESC { 1697 dag OutOperandList = (outs MSA128BOpnd:$wd); 1698 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1699 vsplat_uimm8:$u8); 1700 string AsmString = "bmzi.b\t$wd, $ws, $u8"; 1701 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8, 1702 MSA128BOpnd:$wd_in, 1703 MSA128BOpnd:$ws))]; 1704 InstrItinClass Itinerary = NoItinerary; 1705 string Constraints = "$wd = $wd_in"; 1706} 1707 1708class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg_b, MSA128BOpnd>; 1709class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg_h, MSA128HOpnd>; 1710class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg_w, MSA128WOpnd>; 1711class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg_d, MSA128DOpnd>; 1712 1713class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", xor, vsplat_uimm_pow2, 1714 MSA128BOpnd>; 1715class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", xor, vsplat_uimm_pow2, 1716 MSA128HOpnd>; 1717class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", xor, vsplat_uimm_pow2, 1718 MSA128WOpnd>; 1719class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", xor, vsplat_uimm_pow2, 1720 MSA128DOpnd>; 1721 1722class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>; 1723class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>; 1724class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>; 1725class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>; 1726 1727class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>; 1728 1729class BSEL_V_DESC { 1730 dag OutOperandList = (outs MSA128BOpnd:$wd); 1731 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1732 MSA128BOpnd:$wt); 1733 string AsmString = "bsel.v\t$wd, $ws, $wt"; 1734 // Note that vselect and BSEL_V treat the condition operand the opposite way 1735 // from each other. 1736 // (vselect cond, if_set, if_clear) 1737 // (BSEL_V cond, if_clear, if_set) 1738 list<dag> Pattern = [(set MSA128BOpnd:$wd, 1739 (vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$wt, 1740 MSA128BOpnd:$ws))]; 1741 InstrItinClass Itinerary = NoItinerary; 1742 string Constraints = "$wd = $wd_in"; 1743} 1744 1745class BSELI_B_DESC { 1746 dag OutOperandList = (outs MSA128BOpnd:$wd); 1747 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1748 vsplat_uimm8:$u8); 1749 string AsmString = "bseli.b\t$wd, $ws, $u8"; 1750 // Note that vselect and BSEL_V treat the condition operand the opposite way 1751 // from each other. 1752 // (vselect cond, if_set, if_clear) 1753 // (BSEL_V cond, if_clear, if_set) 1754 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in, 1755 vsplati8_uimm8:$u8, 1756 MSA128BOpnd:$ws))]; 1757 InstrItinClass Itinerary = NoItinerary; 1758 string Constraints = "$wd = $wd_in"; 1759} 1760 1761class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", vbset_b, MSA128BOpnd>; 1762class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", vbset_h, MSA128HOpnd>; 1763class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", vbset_w, MSA128WOpnd>; 1764class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", vbset_d, MSA128DOpnd>; 1765 1766class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", or, vsplat_uimm_pow2, 1767 MSA128BOpnd>; 1768class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", or, vsplat_uimm_pow2, 1769 MSA128HOpnd>; 1770class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", or, vsplat_uimm_pow2, 1771 MSA128WOpnd>; 1772class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", or, vsplat_uimm_pow2, 1773 MSA128DOpnd>; 1774 1775class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>; 1776class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>; 1777class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>; 1778class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>; 1779 1780class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>; 1781 1782class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>, 1783 IsCommutable; 1784class CEQ_H_DESC : MSA_3R_DESC_BASE<"ceq.h", vseteq_v8i16, MSA128HOpnd>, 1785 IsCommutable; 1786class CEQ_W_DESC : MSA_3R_DESC_BASE<"ceq.w", vseteq_v4i32, MSA128WOpnd>, 1787 IsCommutable; 1788class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq.d", vseteq_v2i64, MSA128DOpnd>, 1789 IsCommutable; 1790 1791class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5, 1792 MSA128BOpnd>; 1793class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5, 1794 MSA128HOpnd>; 1795class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5, 1796 MSA128WOpnd>; 1797class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5, 1798 MSA128DOpnd>; 1799 1800class CFCMSA_DESC { 1801 dag OutOperandList = (outs GPR32Opnd:$rd); 1802 dag InOperandList = (ins MSA128CROpnd:$cs); 1803 string AsmString = "cfcmsa\t$rd, $cs"; 1804 InstrItinClass Itinerary = NoItinerary; 1805 bit hasSideEffects = 1; 1806 bit isMoveReg = 1; 1807} 1808 1809class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>; 1810class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", vsetle_v8i16, MSA128HOpnd>; 1811class CLE_S_W_DESC : MSA_3R_DESC_BASE<"cle_s.w", vsetle_v4i32, MSA128WOpnd>; 1812class CLE_S_D_DESC : MSA_3R_DESC_BASE<"cle_s.d", vsetle_v2i64, MSA128DOpnd>; 1813 1814class CLE_U_B_DESC : MSA_3R_DESC_BASE<"cle_u.b", vsetule_v16i8, MSA128BOpnd>; 1815class CLE_U_H_DESC : MSA_3R_DESC_BASE<"cle_u.h", vsetule_v8i16, MSA128HOpnd>; 1816class CLE_U_W_DESC : MSA_3R_DESC_BASE<"cle_u.w", vsetule_v4i32, MSA128WOpnd>; 1817class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>; 1818 1819class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8, 1820 vsplati8_simm5, MSA128BOpnd>; 1821class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16, 1822 vsplati16_simm5, MSA128HOpnd>; 1823class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32, 1824 vsplati32_simm5, MSA128WOpnd>; 1825class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64, 1826 vsplati64_simm5, MSA128DOpnd>; 1827 1828class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8, 1829 vsplati8_uimm5, MSA128BOpnd>; 1830class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16, 1831 vsplati16_uimm5, MSA128HOpnd>; 1832class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32, 1833 vsplati32_uimm5, MSA128WOpnd>; 1834class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64, 1835 vsplati64_uimm5, MSA128DOpnd>; 1836 1837class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>; 1838class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>; 1839class CLT_S_W_DESC : MSA_3R_DESC_BASE<"clt_s.w", vsetlt_v4i32, MSA128WOpnd>; 1840class CLT_S_D_DESC : MSA_3R_DESC_BASE<"clt_s.d", vsetlt_v2i64, MSA128DOpnd>; 1841 1842class CLT_U_B_DESC : MSA_3R_DESC_BASE<"clt_u.b", vsetult_v16i8, MSA128BOpnd>; 1843class CLT_U_H_DESC : MSA_3R_DESC_BASE<"clt_u.h", vsetult_v8i16, MSA128HOpnd>; 1844class CLT_U_W_DESC : MSA_3R_DESC_BASE<"clt_u.w", vsetult_v4i32, MSA128WOpnd>; 1845class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>; 1846 1847class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8, 1848 vsplati8_simm5, MSA128BOpnd>; 1849class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16, 1850 vsplati16_simm5, MSA128HOpnd>; 1851class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32, 1852 vsplati32_simm5, MSA128WOpnd>; 1853class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64, 1854 vsplati64_simm5, MSA128DOpnd>; 1855 1856class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8, 1857 vsplati8_uimm5, MSA128BOpnd>; 1858class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16, 1859 vsplati16_uimm5, MSA128HOpnd>; 1860class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32, 1861 vsplati32_uimm5, MSA128WOpnd>; 1862class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64, 1863 vsplati64_uimm5, MSA128DOpnd>; 1864 1865class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8, 1866 uimm4_ptr, immZExt4Ptr, GPR32Opnd, 1867 MSA128BOpnd>; 1868class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16, 1869 uimm3_ptr, immZExt3Ptr, GPR32Opnd, 1870 MSA128HOpnd>; 1871class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32, 1872 uimm2_ptr, immZExt2Ptr, GPR32Opnd, 1873 MSA128WOpnd>; 1874class COPY_S_D_DESC : MSA_COPY_DESC_BASE<"copy_s.d", vextract_sext_i64, v2i64, 1875 uimm1_ptr, immZExt1Ptr, GPR64Opnd, 1876 MSA128DOpnd>; 1877 1878class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8, 1879 uimm4_ptr, immZExt4Ptr, GPR32Opnd, 1880 MSA128BOpnd>; 1881class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16, 1882 uimm3_ptr, immZExt3Ptr, GPR32Opnd, 1883 MSA128HOpnd>; 1884class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32, 1885 uimm2_ptr, immZExt2Ptr, GPR32Opnd, 1886 MSA128WOpnd>; 1887 1888class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, 1889 uimm2_ptr, immZExt2Ptr, FGR32, 1890 MSA128W>; 1891class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64, 1892 uimm1_ptr, immZExt1Ptr, FGR64, 1893 MSA128D>; 1894 1895class CTCMSA_DESC { 1896 dag OutOperandList = (outs); 1897 dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs); 1898 string AsmString = "ctcmsa\t$cd, $rs"; 1899 InstrItinClass Itinerary = NoItinerary; 1900 bit hasSideEffects = 1; 1901 bit isMoveReg = 1; 1902} 1903 1904class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>; 1905class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128HOpnd>; 1906class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128WOpnd>; 1907class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128DOpnd>; 1908 1909class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128BOpnd>; 1910class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128HOpnd>; 1911class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128WOpnd>; 1912class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128DOpnd>; 1913 1914class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h, 1915 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>, 1916 IsCommutable; 1917class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w, 1918 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>, 1919 IsCommutable; 1920class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d, 1921 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>, 1922 IsCommutable; 1923 1924class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h, 1925 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>, 1926 IsCommutable; 1927class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w, 1928 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>, 1929 IsCommutable; 1930class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d, 1931 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>, 1932 IsCommutable; 1933 1934class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h, 1935 MSA128HOpnd, MSA128BOpnd, 1936 MSA128BOpnd>, IsCommutable; 1937class DPADD_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.w", int_mips_dpadd_s_w, 1938 MSA128WOpnd, MSA128HOpnd, 1939 MSA128HOpnd>, IsCommutable; 1940class DPADD_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.d", int_mips_dpadd_s_d, 1941 MSA128DOpnd, MSA128WOpnd, 1942 MSA128WOpnd>, IsCommutable; 1943 1944class DPADD_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.h", int_mips_dpadd_u_h, 1945 MSA128HOpnd, MSA128BOpnd, 1946 MSA128BOpnd>, IsCommutable; 1947class DPADD_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.w", int_mips_dpadd_u_w, 1948 MSA128WOpnd, MSA128HOpnd, 1949 MSA128HOpnd>, IsCommutable; 1950class DPADD_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.d", int_mips_dpadd_u_d, 1951 MSA128DOpnd, MSA128WOpnd, 1952 MSA128WOpnd>, IsCommutable; 1953 1954class DPSUB_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.h", int_mips_dpsub_s_h, 1955 MSA128HOpnd, MSA128BOpnd, 1956 MSA128BOpnd>; 1957class DPSUB_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.w", int_mips_dpsub_s_w, 1958 MSA128WOpnd, MSA128HOpnd, 1959 MSA128HOpnd>; 1960class DPSUB_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.d", int_mips_dpsub_s_d, 1961 MSA128DOpnd, MSA128WOpnd, 1962 MSA128WOpnd>; 1963 1964class DPSUB_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.h", int_mips_dpsub_u_h, 1965 MSA128HOpnd, MSA128BOpnd, 1966 MSA128BOpnd>; 1967class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w, 1968 MSA128WOpnd, MSA128HOpnd, 1969 MSA128HOpnd>; 1970class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d, 1971 MSA128DOpnd, MSA128WOpnd, 1972 MSA128WOpnd>; 1973 1974class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>, 1975 IsCommutable; 1976class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>, 1977 IsCommutable; 1978 1979class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>, 1980 IsCommutable; 1981class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>, 1982 IsCommutable; 1983 1984class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>, 1985 IsCommutable; 1986class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>, 1987 IsCommutable; 1988 1989class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w, 1990 MSA128WOpnd>; 1991class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d, 1992 MSA128DOpnd>; 1993 1994class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>; 1995class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>; 1996 1997class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>; 1998class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>; 1999 2000class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>, 2001 IsCommutable; 2002class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>, 2003 IsCommutable; 2004 2005class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>, 2006 IsCommutable; 2007class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>, 2008 IsCommutable; 2009 2010class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>, 2011 IsCommutable; 2012class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>, 2013 IsCommutable; 2014 2015class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>, 2016 IsCommutable; 2017class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>, 2018 IsCommutable; 2019 2020class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>, 2021 IsCommutable; 2022class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>, 2023 IsCommutable; 2024 2025class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>, 2026 IsCommutable; 2027class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>, 2028 IsCommutable; 2029 2030class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>, 2031 IsCommutable; 2032class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>, 2033 IsCommutable; 2034 2035class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>; 2036class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>; 2037 2038class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h, 2039 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>; 2040class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w, 2041 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>; 2042 2043// The fexp2.df instruction multiplies the first operand by 2 to the power of 2044// the second operand. We therefore need a pseudo-insn in order to invent the 2045// 1.0 when we only need to match ISD::FEXP2. 2046class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>; 2047class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>; 2048let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in { 2049 class FEXP2_W_1_PSEUDO_DESC : 2050 MSAPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws), 2051 [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>; 2052 class FEXP2_D_1_PSEUDO_DESC : 2053 MSAPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws), 2054 [(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>; 2055} 2056 2057class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w, 2058 MSA128WOpnd, MSA128HOpnd>; 2059class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d, 2060 MSA128DOpnd, MSA128WOpnd>; 2061 2062class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w, 2063 MSA128WOpnd, MSA128HOpnd>; 2064class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d, 2065 MSA128DOpnd, MSA128WOpnd>; 2066 2067class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>; 2068class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>; 2069 2070class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>; 2071class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>; 2072 2073class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w, 2074 MSA128WOpnd, MSA128HOpnd>; 2075class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d, 2076 MSA128DOpnd, MSA128WOpnd>; 2077 2078class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w, 2079 MSA128WOpnd, MSA128HOpnd>; 2080class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d, 2081 MSA128DOpnd, MSA128WOpnd>; 2082 2083class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8, 2084 MSA128BOpnd, GPR32Opnd>; 2085class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16, 2086 MSA128HOpnd, GPR32Opnd>; 2087class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32, 2088 MSA128WOpnd, GPR32Opnd>; 2089class FILL_D_DESC : MSA_2R_FILL_DESC_BASE<"fill.d", v2i64, vsplati64, 2090 MSA128DOpnd, GPR64Opnd>; 2091 2092class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v4f32, vsplatf32, MSA128W, 2093 FGR32>; 2094class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v2f64, vsplatf64, MSA128D, 2095 FGR64>; 2096 2097class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>; 2098class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>; 2099 2100class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>; 2101class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>; 2102 2103class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>; 2104class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>; 2105 2106class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w, 2107 MSA128WOpnd>; 2108class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d, 2109 MSA128DOpnd>; 2110 2111class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>; 2112class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>; 2113 2114class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w, 2115 MSA128WOpnd>; 2116class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d, 2117 MSA128DOpnd>; 2118 2119class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", MipsFMS, MSA128WOpnd>; 2120class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", MipsFMS, MSA128DOpnd>; 2121 2122class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>; 2123class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>; 2124 2125class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>; 2126class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>; 2127 2128class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>; 2129class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>; 2130 2131class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w, 2132 MSA128WOpnd>; 2133class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d, 2134 MSA128DOpnd>; 2135 2136class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>; 2137class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>; 2138 2139class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>; 2140class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>; 2141 2142class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>; 2143class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>; 2144 2145class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>; 2146class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>; 2147 2148class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>; 2149class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>; 2150 2151class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>; 2152class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>; 2153 2154class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>; 2155class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>; 2156 2157class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>; 2158class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>; 2159 2160class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w, 2161 MSA128WOpnd>; 2162class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d, 2163 MSA128DOpnd>; 2164 2165class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w, 2166 MSA128WOpnd>; 2167class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d, 2168 MSA128DOpnd>; 2169 2170class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w, 2171 MSA128WOpnd>; 2172class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d, 2173 MSA128DOpnd>; 2174 2175class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w, 2176 MSA128WOpnd>; 2177class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d, 2178 MSA128DOpnd>; 2179 2180class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w, 2181 MSA128WOpnd>; 2182class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d, 2183 MSA128DOpnd>; 2184 2185class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w, 2186 MSA128WOpnd>; 2187class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d, 2188 MSA128DOpnd>; 2189 2190class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w, 2191 MSA128WOpnd>; 2192class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d, 2193 MSA128DOpnd>; 2194 2195class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h, 2196 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>; 2197class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w, 2198 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>; 2199 2200class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint, 2201 MSA128WOpnd>; 2202class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint, 2203 MSA128DOpnd>; 2204 2205class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint, 2206 MSA128WOpnd>; 2207class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint, 2208 MSA128DOpnd>; 2209 2210class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h, 2211 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2212class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w, 2213 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2214class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d, 2215 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2216 2217class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h, 2218 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2219class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w, 2220 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2221class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d, 2222 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2223 2224class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h, 2225 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2226class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w, 2227 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2228class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d, 2229 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2230 2231class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h, 2232 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2233class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w, 2234 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2235class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d, 2236 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2237 2238class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", MipsILVEV, MSA128BOpnd>; 2239class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", MipsILVEV, MSA128HOpnd>; 2240class ILVEV_W_DESC : MSA_3R_DESC_BASE<"ilvev.w", MipsILVEV, MSA128WOpnd>; 2241class ILVEV_D_DESC : MSA_3R_DESC_BASE<"ilvev.d", MipsILVEV, MSA128DOpnd>; 2242 2243class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>; 2244class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>; 2245class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>; 2246class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>; 2247 2248class ILVOD_B_DESC : MSA_3R_DESC_BASE<"ilvod.b", MipsILVOD, MSA128BOpnd>; 2249class ILVOD_H_DESC : MSA_3R_DESC_BASE<"ilvod.h", MipsILVOD, MSA128HOpnd>; 2250class ILVOD_W_DESC : MSA_3R_DESC_BASE<"ilvod.w", MipsILVOD, MSA128WOpnd>; 2251class ILVOD_D_DESC : MSA_3R_DESC_BASE<"ilvod.d", MipsILVOD, MSA128DOpnd>; 2252 2253class ILVR_B_DESC : MSA_3R_DESC_BASE<"ilvr.b", MipsILVR, MSA128BOpnd>; 2254class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>; 2255class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>; 2256class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>; 2257 2258class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8, uimm4, 2259 immZExt4Ptr, MSA128BOpnd, GPR32Opnd>; 2260class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16, uimm3, 2261 immZExt3Ptr, MSA128HOpnd, GPR32Opnd>; 2262class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32, uimm2, 2263 immZExt2Ptr, MSA128WOpnd, GPR32Opnd>; 2264class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64, uimm1, 2265 immZExt1Ptr, MSA128DOpnd, GPR64Opnd>; 2266 2267class INSERT_B_VIDX_PSEUDO_DESC : 2268 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR32Opnd>; 2269class INSERT_H_VIDX_PSEUDO_DESC : 2270 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR32Opnd>; 2271class INSERT_W_VIDX_PSEUDO_DESC : 2272 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR32Opnd>; 2273class INSERT_D_VIDX_PSEUDO_DESC : 2274 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR32Opnd>; 2275 2276class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32, 2277 uimm2, immZExt2Ptr, 2278 MSA128WOpnd, FGR32Opnd>; 2279class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64, 2280 uimm1, immZExt1Ptr, 2281 MSA128DOpnd, FGR64Opnd>; 2282 2283class INSERT_FW_VIDX_PSEUDO_DESC : 2284 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR32Opnd>; 2285class INSERT_FD_VIDX_PSEUDO_DESC : 2286 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR32Opnd>; 2287 2288class INSERT_B_VIDX64_PSEUDO_DESC : 2289 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR64Opnd>; 2290class INSERT_H_VIDX64_PSEUDO_DESC : 2291 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR64Opnd>; 2292class INSERT_W_VIDX64_PSEUDO_DESC : 2293 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR64Opnd>; 2294class INSERT_D_VIDX64_PSEUDO_DESC : 2295 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR64Opnd>; 2296 2297class INSERT_FW_VIDX64_PSEUDO_DESC : 2298 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR64Opnd>; 2299class INSERT_FD_VIDX64_PSEUDO_DESC : 2300 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR64Opnd>; 2301 2302class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8, uimm4, immZExt4, 2303 MSA128BOpnd>; 2304class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", insve_v8i16, uimm3, immZExt3, 2305 MSA128HOpnd>; 2306class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", insve_v4i32, uimm2, immZExt2, 2307 MSA128WOpnd>; 2308class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64, uimm1, immZExt1, 2309 MSA128DOpnd>; 2310 2311class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 2312 ValueType TyNode, RegisterOperand ROWD, 2313 Operand MemOpnd, ComplexPattern Addr = addrimm10, 2314 InstrItinClass itin = NoItinerary> { 2315 dag OutOperandList = (outs ROWD:$wd); 2316 dag InOperandList = (ins MemOpnd:$addr); 2317 string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); 2318 list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))]; 2319 InstrItinClass Itinerary = itin; 2320 string DecoderMethod = "DecodeMSA128Mem"; 2321} 2322 2323class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd, mem_simm10>; 2324class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd, 2325 mem_simm10_lsl1, addrimm10lsl1>; 2326class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd, 2327 mem_simm10_lsl2, addrimm10lsl2>; 2328class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd, 2329 mem_simm10_lsl3, addrimm10lsl3>; 2330 2331class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>; 2332class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>; 2333class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>; 2334class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>; 2335 2336class LSA_DESC_BASE<string instr_asm, RegisterOperand RORD, 2337 InstrItinClass itin = NoItinerary> { 2338 dag OutOperandList = (outs RORD:$rd); 2339 dag InOperandList = (ins RORD:$rs, RORD:$rt, uimm2_plus1:$sa); 2340 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $sa"); 2341 list<dag> Pattern = [(set RORD:$rd, (add RORD:$rt, 2342 (shl RORD:$rs, 2343 immZExt2Lsa:$sa)))]; 2344 InstrItinClass Itinerary = itin; 2345} 2346 2347class LSA_DESC : LSA_DESC_BASE<"lsa", GPR32Opnd, II_LSA>; 2348class DLSA_DESC : LSA_DESC_BASE<"dlsa", GPR64Opnd, II_DLSA>; 2349 2350class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h, 2351 MSA128HOpnd>; 2352class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w, 2353 MSA128WOpnd>; 2354 2355class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h, 2356 MSA128HOpnd>; 2357class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w, 2358 MSA128WOpnd>; 2359 2360class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", muladd, MSA128BOpnd>; 2361class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", muladd, MSA128HOpnd>; 2362class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", muladd, MSA128WOpnd>; 2363class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", muladd, MSA128DOpnd>; 2364 2365class MAX_A_B_DESC : MSA_3R_DESC_BASE<"max_a.b", int_mips_max_a_b, MSA128BOpnd>; 2366class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>; 2367class MAX_A_W_DESC : MSA_3R_DESC_BASE<"max_a.w", int_mips_max_a_w, MSA128WOpnd>; 2368class MAX_A_D_DESC : MSA_3R_DESC_BASE<"max_a.d", int_mips_max_a_d, MSA128DOpnd>; 2369 2370class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", smax, MSA128BOpnd>; 2371class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", smax, MSA128HOpnd>; 2372class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", smax, MSA128WOpnd>; 2373class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", smax, MSA128DOpnd>; 2374 2375class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", umax, MSA128BOpnd>; 2376class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", umax, MSA128HOpnd>; 2377class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", umax, MSA128WOpnd>; 2378class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", umax, MSA128DOpnd>; 2379 2380class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", smax, vsplati8_simm5, 2381 MSA128BOpnd>; 2382class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", smax, vsplati16_simm5, 2383 MSA128HOpnd>; 2384class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", smax, vsplati32_simm5, 2385 MSA128WOpnd>; 2386class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", smax, vsplati64_simm5, 2387 MSA128DOpnd>; 2388 2389class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", umax, vsplati8_uimm5, 2390 MSA128BOpnd>; 2391class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", umax, vsplati16_uimm5, 2392 MSA128HOpnd>; 2393class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", umax, vsplati32_uimm5, 2394 MSA128WOpnd>; 2395class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", umax, vsplati64_uimm5, 2396 MSA128DOpnd>; 2397 2398class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>; 2399class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>; 2400class MIN_A_W_DESC : MSA_3R_DESC_BASE<"min_a.w", int_mips_min_a_w, MSA128WOpnd>; 2401class MIN_A_D_DESC : MSA_3R_DESC_BASE<"min_a.d", int_mips_min_a_d, MSA128DOpnd>; 2402 2403class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", smin, MSA128BOpnd>; 2404class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", smin, MSA128HOpnd>; 2405class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", smin, MSA128WOpnd>; 2406class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", smin, MSA128DOpnd>; 2407 2408class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", umin, MSA128BOpnd>; 2409class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", umin, MSA128HOpnd>; 2410class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", umin, MSA128WOpnd>; 2411class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", umin, MSA128DOpnd>; 2412 2413class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", smin, vsplati8_simm5, 2414 MSA128BOpnd>; 2415class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", smin, vsplati16_simm5, 2416 MSA128HOpnd>; 2417class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", smin, vsplati32_simm5, 2418 MSA128WOpnd>; 2419class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", smin, vsplati64_simm5, 2420 MSA128DOpnd>; 2421 2422class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", umin, vsplati8_uimm5, 2423 MSA128BOpnd>; 2424class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", umin, vsplati16_uimm5, 2425 MSA128HOpnd>; 2426class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", umin, vsplati32_uimm5, 2427 MSA128WOpnd>; 2428class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", umin, vsplati64_uimm5, 2429 MSA128DOpnd>; 2430 2431class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", srem, MSA128BOpnd>; 2432class MOD_S_H_DESC : MSA_3R_DESC_BASE<"mod_s.h", srem, MSA128HOpnd>; 2433class MOD_S_W_DESC : MSA_3R_DESC_BASE<"mod_s.w", srem, MSA128WOpnd>; 2434class MOD_S_D_DESC : MSA_3R_DESC_BASE<"mod_s.d", srem, MSA128DOpnd>; 2435 2436class MOD_U_B_DESC : MSA_3R_DESC_BASE<"mod_u.b", urem, MSA128BOpnd>; 2437class MOD_U_H_DESC : MSA_3R_DESC_BASE<"mod_u.h", urem, MSA128HOpnd>; 2438class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", urem, MSA128WOpnd>; 2439class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", urem, MSA128DOpnd>; 2440 2441class MOVE_V_DESC { 2442 dag OutOperandList = (outs MSA128BOpnd:$wd); 2443 dag InOperandList = (ins MSA128BOpnd:$ws); 2444 string AsmString = "move.v\t$wd, $ws"; 2445 list<dag> Pattern = []; 2446 InstrItinClass Itinerary = NoItinerary; 2447 bit isMoveReg = 1; 2448} 2449 2450class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h, 2451 MSA128HOpnd>; 2452class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w, 2453 MSA128WOpnd>; 2454 2455class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h, 2456 MSA128HOpnd>; 2457class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w, 2458 MSA128WOpnd>; 2459 2460class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", mulsub, MSA128BOpnd>; 2461class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", mulsub, MSA128HOpnd>; 2462class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", mulsub, MSA128WOpnd>; 2463class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", mulsub, MSA128DOpnd>; 2464 2465class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h, 2466 MSA128HOpnd>; 2467class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w, 2468 MSA128WOpnd>; 2469 2470class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h, 2471 MSA128HOpnd>; 2472class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w, 2473 MSA128WOpnd>; 2474 2475class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128BOpnd>; 2476class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128HOpnd>; 2477class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", mul, MSA128WOpnd>; 2478class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", mul, MSA128DOpnd>; 2479 2480class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>; 2481class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>; 2482class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>; 2483class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>; 2484 2485class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", ctlz, MSA128BOpnd>; 2486class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128HOpnd>; 2487class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128WOpnd>; 2488class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128DOpnd>; 2489 2490class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128BOpnd>; 2491class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128HOpnd>; 2492class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128WOpnd>; 2493class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128DOpnd>; 2494 2495class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8, 2496 MSA128BOpnd>; 2497 2498class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128BOpnd>; 2499class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128HOpnd>; 2500class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128WOpnd>; 2501class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128DOpnd>; 2502 2503class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>; 2504 2505class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128BOpnd>; 2506class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128HOpnd>; 2507class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", MipsPCKEV, MSA128WOpnd>; 2508class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", MipsPCKEV, MSA128DOpnd>; 2509 2510class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", MipsPCKOD, MSA128BOpnd>; 2511class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", MipsPCKOD, MSA128HOpnd>; 2512class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>; 2513class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>; 2514 2515class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>; 2516class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>; 2517class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>; 2518class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>; 2519 2520class SAT_S_B_DESC : MSA_BIT_X_DESC_BASE<"sat_s.b", int_mips_sat_s_b, uimm3, 2521 immZExt3, MSA128BOpnd>; 2522class SAT_S_H_DESC : MSA_BIT_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h, uimm4, 2523 immZExt4, MSA128HOpnd>; 2524class SAT_S_W_DESC : MSA_BIT_X_DESC_BASE<"sat_s.w", int_mips_sat_s_w, uimm5, 2525 immZExt5, MSA128WOpnd>; 2526class SAT_S_D_DESC : MSA_BIT_X_DESC_BASE<"sat_s.d", int_mips_sat_s_d, uimm6, 2527 immZExt6, MSA128DOpnd>; 2528 2529class SAT_U_B_DESC : MSA_BIT_X_DESC_BASE<"sat_u.b", int_mips_sat_u_b, uimm3, 2530 immZExt3, MSA128BOpnd>; 2531class SAT_U_H_DESC : MSA_BIT_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h, uimm4, 2532 immZExt4, MSA128HOpnd>; 2533class SAT_U_W_DESC : MSA_BIT_X_DESC_BASE<"sat_u.w", int_mips_sat_u_w, uimm5, 2534 immZExt5, MSA128WOpnd>; 2535class SAT_U_D_DESC : MSA_BIT_X_DESC_BASE<"sat_u.d", int_mips_sat_u_d, uimm6, 2536 immZExt6, MSA128DOpnd>; 2537 2538class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>; 2539class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>; 2540class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>; 2541 2542class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>; 2543class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>; 2544class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>; 2545class SLD_D_DESC : MSA_3R_SLD_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>; 2546 2547class SLDI_B_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.b", int_mips_sldi_b, 2548 MSA128BOpnd, MSA128BOpnd, uimm4, 2549 immZExt4>; 2550class SLDI_H_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.h", int_mips_sldi_h, 2551 MSA128HOpnd, MSA128HOpnd, uimm3, 2552 immZExt3>; 2553class SLDI_W_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.w", int_mips_sldi_w, 2554 MSA128WOpnd, MSA128WOpnd, uimm2, 2555 immZExt2>; 2556class SLDI_D_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.d", int_mips_sldi_d, 2557 MSA128DOpnd, MSA128DOpnd, uimm1, 2558 immZExt1>; 2559 2560class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128BOpnd>; 2561class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128HOpnd>; 2562class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>; 2563class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>; 2564 2565class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3, 2566 MSA128BOpnd>; 2567class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4, 2568 MSA128HOpnd>; 2569class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5, 2570 MSA128WOpnd>; 2571class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6, 2572 MSA128DOpnd>; 2573 2574class SPLAT_B_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.b", vsplati8_elt, 2575 MSA128BOpnd>; 2576class SPLAT_H_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.h", vsplati16_elt, 2577 MSA128HOpnd>; 2578class SPLAT_W_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.w", vsplati32_elt, 2579 MSA128WOpnd>; 2580class SPLAT_D_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.d", vsplati64_elt, 2581 MSA128DOpnd>; 2582 2583class SPLATI_B_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.b", vsplati8_uimm4, 2584 MSA128BOpnd>; 2585class SPLATI_H_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.h", vsplati16_uimm3, 2586 MSA128HOpnd>; 2587class SPLATI_W_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.w", vsplati32_uimm2, 2588 MSA128WOpnd>; 2589class SPLATI_D_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.d", vsplati64_uimm1, 2590 MSA128DOpnd>; 2591 2592class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>; 2593class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>; 2594class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>; 2595class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>; 2596 2597class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3, 2598 MSA128BOpnd>; 2599class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4, 2600 MSA128HOpnd>; 2601class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5, 2602 MSA128WOpnd>; 2603class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6, 2604 MSA128DOpnd>; 2605 2606class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>; 2607class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>; 2608class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>; 2609class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>; 2610 2611class SRARI_B_DESC : MSA_BIT_X_DESC_BASE<"srari.b", int_mips_srari_b, uimm3, 2612 immZExt3, MSA128BOpnd>; 2613class SRARI_H_DESC : MSA_BIT_X_DESC_BASE<"srari.h", int_mips_srari_h, uimm4, 2614 immZExt4, MSA128HOpnd>; 2615class SRARI_W_DESC : MSA_BIT_X_DESC_BASE<"srari.w", int_mips_srari_w, uimm5, 2616 immZExt5, MSA128WOpnd>; 2617class SRARI_D_DESC : MSA_BIT_X_DESC_BASE<"srari.d", int_mips_srari_d, uimm6, 2618 immZExt6, MSA128DOpnd>; 2619 2620class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>; 2621class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>; 2622class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>; 2623class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>; 2624 2625class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3, 2626 MSA128BOpnd>; 2627class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4, 2628 MSA128HOpnd>; 2629class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5, 2630 MSA128WOpnd>; 2631class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6, 2632 MSA128DOpnd>; 2633 2634class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>; 2635class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>; 2636class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>; 2637class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>; 2638 2639class SRLRI_B_DESC : MSA_BIT_X_DESC_BASE<"srlri.b", int_mips_srlri_b, uimm3, 2640 immZExt3, MSA128BOpnd>; 2641class SRLRI_H_DESC : MSA_BIT_X_DESC_BASE<"srlri.h", int_mips_srlri_h, uimm4, 2642 immZExt4, MSA128HOpnd>; 2643class SRLRI_W_DESC : MSA_BIT_X_DESC_BASE<"srlri.w", int_mips_srlri_w, uimm5, 2644 immZExt5, MSA128WOpnd>; 2645class SRLRI_D_DESC : MSA_BIT_X_DESC_BASE<"srlri.d", int_mips_srlri_d, uimm6, 2646 immZExt6, MSA128DOpnd>; 2647 2648class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 2649 ValueType TyNode, RegisterOperand ROWD, 2650 Operand MemOpnd, ComplexPattern Addr = addrimm10, 2651 InstrItinClass itin = NoItinerary> { 2652 dag OutOperandList = (outs); 2653 dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr); 2654 string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); 2655 list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)]; 2656 InstrItinClass Itinerary = itin; 2657 string DecoderMethod = "DecodeMSA128Mem"; 2658} 2659 2660class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd, mem_simm10>; 2661class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd, 2662 mem_simm10_lsl1, addrimm10lsl1>; 2663class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd, 2664 mem_simm10_lsl2, addrimm10lsl2>; 2665class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd, 2666 mem_simm10_lsl3, addrimm10lsl3>; 2667 2668class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b, 2669 MSA128BOpnd>; 2670class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h, 2671 MSA128HOpnd>; 2672class SUBS_S_W_DESC : MSA_3R_DESC_BASE<"subs_s.w", int_mips_subs_s_w, 2673 MSA128WOpnd>; 2674class SUBS_S_D_DESC : MSA_3R_DESC_BASE<"subs_s.d", int_mips_subs_s_d, 2675 MSA128DOpnd>; 2676 2677class SUBS_U_B_DESC : MSA_3R_DESC_BASE<"subs_u.b", int_mips_subs_u_b, 2678 MSA128BOpnd>; 2679class SUBS_U_H_DESC : MSA_3R_DESC_BASE<"subs_u.h", int_mips_subs_u_h, 2680 MSA128HOpnd>; 2681class SUBS_U_W_DESC : MSA_3R_DESC_BASE<"subs_u.w", int_mips_subs_u_w, 2682 MSA128WOpnd>; 2683class SUBS_U_D_DESC : MSA_3R_DESC_BASE<"subs_u.d", int_mips_subs_u_d, 2684 MSA128DOpnd>; 2685 2686class SUBSUS_U_B_DESC : MSA_3R_DESC_BASE<"subsus_u.b", int_mips_subsus_u_b, 2687 MSA128BOpnd>; 2688class SUBSUS_U_H_DESC : MSA_3R_DESC_BASE<"subsus_u.h", int_mips_subsus_u_h, 2689 MSA128HOpnd>; 2690class SUBSUS_U_W_DESC : MSA_3R_DESC_BASE<"subsus_u.w", int_mips_subsus_u_w, 2691 MSA128WOpnd>; 2692class SUBSUS_U_D_DESC : MSA_3R_DESC_BASE<"subsus_u.d", int_mips_subsus_u_d, 2693 MSA128DOpnd>; 2694 2695class SUBSUU_S_B_DESC : MSA_3R_DESC_BASE<"subsuu_s.b", int_mips_subsuu_s_b, 2696 MSA128BOpnd>; 2697class SUBSUU_S_H_DESC : MSA_3R_DESC_BASE<"subsuu_s.h", int_mips_subsuu_s_h, 2698 MSA128HOpnd>; 2699class SUBSUU_S_W_DESC : MSA_3R_DESC_BASE<"subsuu_s.w", int_mips_subsuu_s_w, 2700 MSA128WOpnd>; 2701class SUBSUU_S_D_DESC : MSA_3R_DESC_BASE<"subsuu_s.d", int_mips_subsuu_s_d, 2702 MSA128DOpnd>; 2703 2704class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", sub, MSA128BOpnd>; 2705class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", sub, MSA128HOpnd>; 2706class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128WOpnd>; 2707class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128DOpnd>; 2708 2709class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5, 2710 MSA128BOpnd>; 2711class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5, 2712 MSA128HOpnd>; 2713class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5, 2714 MSA128WOpnd>; 2715class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5, 2716 MSA128DOpnd>; 2717 2718class VSHF_B_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.b", MSA128BOpnd>; 2719class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>; 2720class VSHF_W_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.w", MSA128WOpnd>; 2721class VSHF_D_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.d", MSA128DOpnd>; 2722 2723class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128BOpnd>; 2724class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128HOpnd>; 2725class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128WOpnd>; 2726class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128DOpnd>; 2727 2728class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8, 2729 MSA128BOpnd>; 2730 2731// Instruction defs. 2732def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC; 2733def ADD_A_H : ADD_A_H_ENC, ADD_A_H_DESC; 2734def ADD_A_W : ADD_A_W_ENC, ADD_A_W_DESC; 2735def ADD_A_D : ADD_A_D_ENC, ADD_A_D_DESC; 2736 2737def ADDS_A_B : ADDS_A_B_ENC, ADDS_A_B_DESC; 2738def ADDS_A_H : ADDS_A_H_ENC, ADDS_A_H_DESC; 2739def ADDS_A_W : ADDS_A_W_ENC, ADDS_A_W_DESC; 2740def ADDS_A_D : ADDS_A_D_ENC, ADDS_A_D_DESC; 2741 2742def ADDS_S_B : ADDS_S_B_ENC, ADDS_S_B_DESC; 2743def ADDS_S_H : ADDS_S_H_ENC, ADDS_S_H_DESC; 2744def ADDS_S_W : ADDS_S_W_ENC, ADDS_S_W_DESC; 2745def ADDS_S_D : ADDS_S_D_ENC, ADDS_S_D_DESC; 2746 2747def ADDS_U_B : ADDS_U_B_ENC, ADDS_U_B_DESC; 2748def ADDS_U_H : ADDS_U_H_ENC, ADDS_U_H_DESC; 2749def ADDS_U_W : ADDS_U_W_ENC, ADDS_U_W_DESC; 2750def ADDS_U_D : ADDS_U_D_ENC, ADDS_U_D_DESC; 2751 2752def ADDV_B : ADDV_B_ENC, ADDV_B_DESC; 2753def ADDV_H : ADDV_H_ENC, ADDV_H_DESC; 2754def ADDV_W : ADDV_W_ENC, ADDV_W_DESC; 2755def ADDV_D : ADDV_D_ENC, ADDV_D_DESC; 2756 2757def ADDVI_B : ADDVI_B_ENC, ADDVI_B_DESC; 2758def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC; 2759def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC; 2760def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC; 2761 2762def AND_V : AND_V_ENC, AND_V_DESC; 2763def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC, 2764 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2765 MSA128BOpnd:$ws, 2766 MSA128BOpnd:$wt)>; 2767def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC, 2768 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2769 MSA128BOpnd:$ws, 2770 MSA128BOpnd:$wt)>; 2771def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC, 2772 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2773 MSA128BOpnd:$ws, 2774 MSA128BOpnd:$wt)>; 2775 2776def ANDI_B : ANDI_B_ENC, ANDI_B_DESC; 2777 2778def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC; 2779def ASUB_S_H : ASUB_S_H_ENC, ASUB_S_H_DESC; 2780def ASUB_S_W : ASUB_S_W_ENC, ASUB_S_W_DESC; 2781def ASUB_S_D : ASUB_S_D_ENC, ASUB_S_D_DESC; 2782 2783def ASUB_U_B : ASUB_U_B_ENC, ASUB_U_B_DESC; 2784def ASUB_U_H : ASUB_U_H_ENC, ASUB_U_H_DESC; 2785def ASUB_U_W : ASUB_U_W_ENC, ASUB_U_W_DESC; 2786def ASUB_U_D : ASUB_U_D_ENC, ASUB_U_D_DESC; 2787 2788def AVE_S_B : AVE_S_B_ENC, AVE_S_B_DESC; 2789def AVE_S_H : AVE_S_H_ENC, AVE_S_H_DESC; 2790def AVE_S_W : AVE_S_W_ENC, AVE_S_W_DESC; 2791def AVE_S_D : AVE_S_D_ENC, AVE_S_D_DESC; 2792 2793def AVE_U_B : AVE_U_B_ENC, AVE_U_B_DESC; 2794def AVE_U_H : AVE_U_H_ENC, AVE_U_H_DESC; 2795def AVE_U_W : AVE_U_W_ENC, AVE_U_W_DESC; 2796def AVE_U_D : AVE_U_D_ENC, AVE_U_D_DESC; 2797 2798def AVER_S_B : AVER_S_B_ENC, AVER_S_B_DESC; 2799def AVER_S_H : AVER_S_H_ENC, AVER_S_H_DESC; 2800def AVER_S_W : AVER_S_W_ENC, AVER_S_W_DESC; 2801def AVER_S_D : AVER_S_D_ENC, AVER_S_D_DESC; 2802 2803def AVER_U_B : AVER_U_B_ENC, AVER_U_B_DESC; 2804def AVER_U_H : AVER_U_H_ENC, AVER_U_H_DESC; 2805def AVER_U_W : AVER_U_W_ENC, AVER_U_W_DESC; 2806def AVER_U_D : AVER_U_D_ENC, AVER_U_D_DESC; 2807 2808def BCLR_B : BCLR_B_ENC, BCLR_B_DESC; 2809def BCLR_H : BCLR_H_ENC, BCLR_H_DESC; 2810def BCLR_W : BCLR_W_ENC, BCLR_W_DESC; 2811def BCLR_D : BCLR_D_ENC, BCLR_D_DESC; 2812 2813def BCLRI_B : BCLRI_B_ENC, BCLRI_B_DESC; 2814def BCLRI_H : BCLRI_H_ENC, BCLRI_H_DESC; 2815def BCLRI_W : BCLRI_W_ENC, BCLRI_W_DESC; 2816def BCLRI_D : BCLRI_D_ENC, BCLRI_D_DESC; 2817 2818def BINSL_B : BINSL_B_ENC, BINSL_B_DESC; 2819def BINSL_H : BINSL_H_ENC, BINSL_H_DESC; 2820def BINSL_W : BINSL_W_ENC, BINSL_W_DESC; 2821def BINSL_D : BINSL_D_ENC, BINSL_D_DESC; 2822 2823def BINSLI_B : BINSLI_B_ENC, BINSLI_B_DESC; 2824def BINSLI_H : BINSLI_H_ENC, BINSLI_H_DESC; 2825def BINSLI_W : BINSLI_W_ENC, BINSLI_W_DESC; 2826def BINSLI_D : BINSLI_D_ENC, BINSLI_D_DESC; 2827 2828def BINSR_B : BINSR_B_ENC, BINSR_B_DESC; 2829def BINSR_H : BINSR_H_ENC, BINSR_H_DESC; 2830def BINSR_W : BINSR_W_ENC, BINSR_W_DESC; 2831def BINSR_D : BINSR_D_ENC, BINSR_D_DESC; 2832 2833def BINSRI_B : BINSRI_B_ENC, BINSRI_B_DESC; 2834def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC; 2835def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC; 2836def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC; 2837 2838def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC; 2839 2840def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC; 2841 2842def BMZ_V : BMZ_V_ENC, BMZ_V_DESC; 2843 2844def BMZI_B : BMZI_B_ENC, BMZI_B_DESC; 2845 2846def BNEG_B : BNEG_B_ENC, BNEG_B_DESC; 2847def BNEG_H : BNEG_H_ENC, BNEG_H_DESC; 2848def BNEG_W : BNEG_W_ENC, BNEG_W_DESC; 2849def BNEG_D : BNEG_D_ENC, BNEG_D_DESC; 2850 2851def BNEGI_B : BNEGI_B_ENC, BNEGI_B_DESC; 2852def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC; 2853def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC; 2854def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC; 2855 2856def BNZ_B : BNZ_B_ENC, BNZ_B_DESC; 2857def BNZ_H : BNZ_H_ENC, BNZ_H_DESC; 2858def BNZ_W : BNZ_W_ENC, BNZ_W_DESC; 2859def BNZ_D : BNZ_D_ENC, BNZ_D_DESC; 2860 2861def BNZ_V : BNZ_V_ENC, BNZ_V_DESC; 2862 2863def BSEL_V : BSEL_V_ENC, BSEL_V_DESC; 2864 2865class MSA_BSEL_PSEUDO_BASE<RegisterOperand RO, ValueType Ty> : 2866 MSAPseudo<(outs RO:$wd), (ins RO:$wd_in, RO:$ws, RO:$wt), 2867 [(set RO:$wd, (Ty (vselect RO:$wd_in, RO:$wt, RO:$ws)))]>, 2868 // Note that vselect and BSEL_V treat the condition operand the opposite way 2869 // from each other. 2870 // (vselect cond, if_set, if_clear) 2871 // (BSEL_V cond, if_clear, if_set) 2872 PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in, 2873 MSA128BOpnd:$ws, MSA128BOpnd:$wt)> { 2874 let Constraints = "$wd_in = $wd"; 2875} 2876 2877def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128HOpnd, v8i16>; 2878def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4i32>; 2879def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2i64>; 2880def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4f32>; 2881def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2f64>; 2882 2883def BSELI_B : BSELI_B_ENC, BSELI_B_DESC; 2884 2885def BSET_B : BSET_B_ENC, BSET_B_DESC; 2886def BSET_H : BSET_H_ENC, BSET_H_DESC; 2887def BSET_W : BSET_W_ENC, BSET_W_DESC; 2888def BSET_D : BSET_D_ENC, BSET_D_DESC; 2889 2890def BSETI_B : BSETI_B_ENC, BSETI_B_DESC; 2891def BSETI_H : BSETI_H_ENC, BSETI_H_DESC; 2892def BSETI_W : BSETI_W_ENC, BSETI_W_DESC; 2893def BSETI_D : BSETI_D_ENC, BSETI_D_DESC; 2894 2895def BZ_B : BZ_B_ENC, BZ_B_DESC; 2896def BZ_H : BZ_H_ENC, BZ_H_DESC; 2897def BZ_W : BZ_W_ENC, BZ_W_DESC; 2898def BZ_D : BZ_D_ENC, BZ_D_DESC; 2899 2900def BZ_V : BZ_V_ENC, BZ_V_DESC; 2901 2902def CEQ_B : CEQ_B_ENC, CEQ_B_DESC; 2903def CEQ_H : CEQ_H_ENC, CEQ_H_DESC; 2904def CEQ_W : CEQ_W_ENC, CEQ_W_DESC; 2905def CEQ_D : CEQ_D_ENC, CEQ_D_DESC; 2906 2907def CEQI_B : CEQI_B_ENC, CEQI_B_DESC; 2908def CEQI_H : CEQI_H_ENC, CEQI_H_DESC; 2909def CEQI_W : CEQI_W_ENC, CEQI_W_DESC; 2910def CEQI_D : CEQI_D_ENC, CEQI_D_DESC; 2911 2912def CFCMSA : CFCMSA_ENC, CFCMSA_DESC; 2913 2914def CLE_S_B : CLE_S_B_ENC, CLE_S_B_DESC; 2915def CLE_S_H : CLE_S_H_ENC, CLE_S_H_DESC; 2916def CLE_S_W : CLE_S_W_ENC, CLE_S_W_DESC; 2917def CLE_S_D : CLE_S_D_ENC, CLE_S_D_DESC; 2918 2919def CLE_U_B : CLE_U_B_ENC, CLE_U_B_DESC; 2920def CLE_U_H : CLE_U_H_ENC, CLE_U_H_DESC; 2921def CLE_U_W : CLE_U_W_ENC, CLE_U_W_DESC; 2922def CLE_U_D : CLE_U_D_ENC, CLE_U_D_DESC; 2923 2924def CLEI_S_B : CLEI_S_B_ENC, CLEI_S_B_DESC; 2925def CLEI_S_H : CLEI_S_H_ENC, CLEI_S_H_DESC; 2926def CLEI_S_W : CLEI_S_W_ENC, CLEI_S_W_DESC; 2927def CLEI_S_D : CLEI_S_D_ENC, CLEI_S_D_DESC; 2928 2929def CLEI_U_B : CLEI_U_B_ENC, CLEI_U_B_DESC; 2930def CLEI_U_H : CLEI_U_H_ENC, CLEI_U_H_DESC; 2931def CLEI_U_W : CLEI_U_W_ENC, CLEI_U_W_DESC; 2932def CLEI_U_D : CLEI_U_D_ENC, CLEI_U_D_DESC; 2933 2934def CLT_S_B : CLT_S_B_ENC, CLT_S_B_DESC; 2935def CLT_S_H : CLT_S_H_ENC, CLT_S_H_DESC; 2936def CLT_S_W : CLT_S_W_ENC, CLT_S_W_DESC; 2937def CLT_S_D : CLT_S_D_ENC, CLT_S_D_DESC; 2938 2939def CLT_U_B : CLT_U_B_ENC, CLT_U_B_DESC; 2940def CLT_U_H : CLT_U_H_ENC, CLT_U_H_DESC; 2941def CLT_U_W : CLT_U_W_ENC, CLT_U_W_DESC; 2942def CLT_U_D : CLT_U_D_ENC, CLT_U_D_DESC; 2943 2944def CLTI_S_B : CLTI_S_B_ENC, CLTI_S_B_DESC; 2945def CLTI_S_H : CLTI_S_H_ENC, CLTI_S_H_DESC; 2946def CLTI_S_W : CLTI_S_W_ENC, CLTI_S_W_DESC; 2947def CLTI_S_D : CLTI_S_D_ENC, CLTI_S_D_DESC; 2948 2949def CLTI_U_B : CLTI_U_B_ENC, CLTI_U_B_DESC; 2950def CLTI_U_H : CLTI_U_H_ENC, CLTI_U_H_DESC; 2951def CLTI_U_W : CLTI_U_W_ENC, CLTI_U_W_DESC; 2952def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC; 2953 2954def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC; 2955def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC; 2956def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC; 2957def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC, ASE_MSA64; 2958 2959def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC; 2960def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC; 2961def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC, ASE_MSA64; 2962 2963def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC; 2964def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC; 2965 2966def CTCMSA : CTCMSA_ENC, CTCMSA_DESC; 2967 2968def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC; 2969def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC; 2970def DIV_S_W : DIV_S_W_ENC, DIV_S_W_DESC; 2971def DIV_S_D : DIV_S_D_ENC, DIV_S_D_DESC; 2972 2973def DIV_U_B : DIV_U_B_ENC, DIV_U_B_DESC; 2974def DIV_U_H : DIV_U_H_ENC, DIV_U_H_DESC; 2975def DIV_U_W : DIV_U_W_ENC, DIV_U_W_DESC; 2976def DIV_U_D : DIV_U_D_ENC, DIV_U_D_DESC; 2977 2978def DOTP_S_H : DOTP_S_H_ENC, DOTP_S_H_DESC; 2979def DOTP_S_W : DOTP_S_W_ENC, DOTP_S_W_DESC; 2980def DOTP_S_D : DOTP_S_D_ENC, DOTP_S_D_DESC; 2981 2982def DOTP_U_H : DOTP_U_H_ENC, DOTP_U_H_DESC; 2983def DOTP_U_W : DOTP_U_W_ENC, DOTP_U_W_DESC; 2984def DOTP_U_D : DOTP_U_D_ENC, DOTP_U_D_DESC; 2985 2986def DPADD_S_H : DPADD_S_H_ENC, DPADD_S_H_DESC; 2987def DPADD_S_W : DPADD_S_W_ENC, DPADD_S_W_DESC; 2988def DPADD_S_D : DPADD_S_D_ENC, DPADD_S_D_DESC; 2989 2990def DPADD_U_H : DPADD_U_H_ENC, DPADD_U_H_DESC; 2991def DPADD_U_W : DPADD_U_W_ENC, DPADD_U_W_DESC; 2992def DPADD_U_D : DPADD_U_D_ENC, DPADD_U_D_DESC; 2993 2994def DPSUB_S_H : DPSUB_S_H_ENC, DPSUB_S_H_DESC; 2995def DPSUB_S_W : DPSUB_S_W_ENC, DPSUB_S_W_DESC; 2996def DPSUB_S_D : DPSUB_S_D_ENC, DPSUB_S_D_DESC; 2997 2998def DPSUB_U_H : DPSUB_U_H_ENC, DPSUB_U_H_DESC; 2999def DPSUB_U_W : DPSUB_U_W_ENC, DPSUB_U_W_DESC; 3000def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC; 3001 3002def FADD_W : FADD_W_ENC, FADD_W_DESC; 3003def FADD_D : FADD_D_ENC, FADD_D_DESC; 3004 3005def FCAF_W : FCAF_W_ENC, FCAF_W_DESC; 3006def FCAF_D : FCAF_D_ENC, FCAF_D_DESC; 3007 3008def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC; 3009def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC; 3010 3011def FCLE_W : FCLE_W_ENC, FCLE_W_DESC; 3012def FCLE_D : FCLE_D_ENC, FCLE_D_DESC; 3013 3014def FCLT_W : FCLT_W_ENC, FCLT_W_DESC; 3015def FCLT_D : FCLT_D_ENC, FCLT_D_DESC; 3016 3017def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC; 3018def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC; 3019 3020def FCNE_W : FCNE_W_ENC, FCNE_W_DESC; 3021def FCNE_D : FCNE_D_ENC, FCNE_D_DESC; 3022 3023def FCOR_W : FCOR_W_ENC, FCOR_W_DESC; 3024def FCOR_D : FCOR_D_ENC, FCOR_D_DESC; 3025 3026def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC; 3027def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC; 3028 3029def FCULE_W : FCULE_W_ENC, FCULE_W_DESC; 3030def FCULE_D : FCULE_D_ENC, FCULE_D_DESC; 3031 3032def FCULT_W : FCULT_W_ENC, FCULT_W_DESC; 3033def FCULT_D : FCULT_D_ENC, FCULT_D_DESC; 3034 3035def FCUN_W : FCUN_W_ENC, FCUN_W_DESC; 3036def FCUN_D : FCUN_D_ENC, FCUN_D_DESC; 3037 3038def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC; 3039def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC; 3040 3041def FDIV_W : FDIV_W_ENC, FDIV_W_DESC; 3042def FDIV_D : FDIV_D_ENC, FDIV_D_DESC; 3043 3044def FEXDO_H : FEXDO_H_ENC, FEXDO_H_DESC; 3045def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC; 3046 3047def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC; 3048def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC; 3049def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC; 3050def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC; 3051 3052def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC; 3053def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC; 3054 3055def FEXUPR_W : FEXUPR_W_ENC, FEXUPR_W_DESC; 3056def FEXUPR_D : FEXUPR_D_ENC, FEXUPR_D_DESC; 3057 3058def FFINT_S_W : FFINT_S_W_ENC, FFINT_S_W_DESC; 3059def FFINT_S_D : FFINT_S_D_ENC, FFINT_S_D_DESC; 3060 3061def FFINT_U_W : FFINT_U_W_ENC, FFINT_U_W_DESC; 3062def FFINT_U_D : FFINT_U_D_ENC, FFINT_U_D_DESC; 3063 3064def FFQL_W : FFQL_W_ENC, FFQL_W_DESC; 3065def FFQL_D : FFQL_D_ENC, FFQL_D_DESC; 3066 3067def FFQR_W : FFQR_W_ENC, FFQR_W_DESC; 3068def FFQR_D : FFQR_D_ENC, FFQR_D_DESC; 3069 3070def FILL_B : FILL_B_ENC, FILL_B_DESC; 3071def FILL_H : FILL_H_ENC, FILL_H_DESC; 3072def FILL_W : FILL_W_ENC, FILL_W_DESC; 3073def FILL_D : FILL_D_ENC, FILL_D_DESC, ASE_MSA64; 3074def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC; 3075def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC; 3076 3077def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC; 3078def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC; 3079 3080def FMADD_W : FMADD_W_ENC, FMADD_W_DESC; 3081def FMADD_D : FMADD_D_ENC, FMADD_D_DESC; 3082 3083def FMAX_W : FMAX_W_ENC, FMAX_W_DESC; 3084def FMAX_D : FMAX_D_ENC, FMAX_D_DESC; 3085 3086def FMAX_A_W : FMAX_A_W_ENC, FMAX_A_W_DESC; 3087def FMAX_A_D : FMAX_A_D_ENC, FMAX_A_D_DESC; 3088 3089def FMIN_W : FMIN_W_ENC, FMIN_W_DESC; 3090def FMIN_D : FMIN_D_ENC, FMIN_D_DESC; 3091 3092def FMIN_A_W : FMIN_A_W_ENC, FMIN_A_W_DESC; 3093def FMIN_A_D : FMIN_A_D_ENC, FMIN_A_D_DESC; 3094 3095def FMSUB_W : FMSUB_W_ENC, FMSUB_W_DESC; 3096def FMSUB_D : FMSUB_D_ENC, FMSUB_D_DESC; 3097 3098def FMUL_W : FMUL_W_ENC, FMUL_W_DESC; 3099def FMUL_D : FMUL_D_ENC, FMUL_D_DESC; 3100 3101def FRINT_W : FRINT_W_ENC, FRINT_W_DESC; 3102def FRINT_D : FRINT_D_ENC, FRINT_D_DESC; 3103 3104def FRCP_W : FRCP_W_ENC, FRCP_W_DESC; 3105def FRCP_D : FRCP_D_ENC, FRCP_D_DESC; 3106 3107def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC; 3108def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC; 3109 3110def FSAF_W : FSAF_W_ENC, FSAF_W_DESC; 3111def FSAF_D : FSAF_D_ENC, FSAF_D_DESC; 3112 3113def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC; 3114def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC; 3115 3116def FSLE_W : FSLE_W_ENC, FSLE_W_DESC; 3117def FSLE_D : FSLE_D_ENC, FSLE_D_DESC; 3118 3119def FSLT_W : FSLT_W_ENC, FSLT_W_DESC; 3120def FSLT_D : FSLT_D_ENC, FSLT_D_DESC; 3121 3122def FSNE_W : FSNE_W_ENC, FSNE_W_DESC; 3123def FSNE_D : FSNE_D_ENC, FSNE_D_DESC; 3124 3125def FSOR_W : FSOR_W_ENC, FSOR_W_DESC; 3126def FSOR_D : FSOR_D_ENC, FSOR_D_DESC; 3127 3128def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC; 3129def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC; 3130 3131def FSUB_W : FSUB_W_ENC, FSUB_W_DESC; 3132def FSUB_D : FSUB_D_ENC, FSUB_D_DESC; 3133 3134def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC; 3135def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC; 3136 3137def FSULE_W : FSULE_W_ENC, FSULE_W_DESC; 3138def FSULE_D : FSULE_D_ENC, FSULE_D_DESC; 3139 3140def FSULT_W : FSULT_W_ENC, FSULT_W_DESC; 3141def FSULT_D : FSULT_D_ENC, FSULT_D_DESC; 3142 3143def FSUN_W : FSUN_W_ENC, FSUN_W_DESC; 3144def FSUN_D : FSUN_D_ENC, FSUN_D_DESC; 3145 3146def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC; 3147def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC; 3148 3149def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC; 3150def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC; 3151 3152def FTINT_U_W : FTINT_U_W_ENC, FTINT_U_W_DESC; 3153def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC; 3154 3155def FTQ_H : FTQ_H_ENC, FTQ_H_DESC; 3156def FTQ_W : FTQ_W_ENC, FTQ_W_DESC; 3157 3158def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC; 3159def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC; 3160 3161def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC; 3162def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC; 3163 3164def : MipsPat<(fsub MSA128WOpnd:$wd, (fmul MSA128WOpnd:$ws, MSA128WOpnd:$wt)), 3165 (FMSUB_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, MSA128WOpnd:$wt)>, 3166 ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST; 3167def : MipsPat<(fsub MSA128DOpnd:$wd, (fmul MSA128DOpnd:$ws, MSA128DOpnd:$wt)), 3168 (FMSUB_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, MSA128DOpnd:$wt)>, 3169 ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST; 3170 3171def : MipsPat<(fadd MSA128WOpnd:$wd, (fmul MSA128WOpnd:$ws, MSA128WOpnd:$wt)), 3172 (FMADD_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, MSA128WOpnd:$wt)>, 3173 ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST; 3174def : MipsPat<(fadd MSA128DOpnd:$wd, (fmul MSA128DOpnd:$ws, MSA128DOpnd:$wt)), 3175 (FMADD_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, MSA128DOpnd:$wt)>, 3176 ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST; 3177 3178def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC; 3179def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC; 3180def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC; 3181 3182def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC; 3183def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC; 3184def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC; 3185 3186def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC; 3187def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC; 3188def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC; 3189 3190def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC; 3191def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC; 3192def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC; 3193 3194def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC; 3195def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC; 3196def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC; 3197def ILVEV_D : ILVEV_D_ENC, ILVEV_D_DESC; 3198 3199def ILVL_B : ILVL_B_ENC, ILVL_B_DESC; 3200def ILVL_H : ILVL_H_ENC, ILVL_H_DESC; 3201def ILVL_W : ILVL_W_ENC, ILVL_W_DESC; 3202def ILVL_D : ILVL_D_ENC, ILVL_D_DESC; 3203 3204def ILVOD_B : ILVOD_B_ENC, ILVOD_B_DESC; 3205def ILVOD_H : ILVOD_H_ENC, ILVOD_H_DESC; 3206def ILVOD_W : ILVOD_W_ENC, ILVOD_W_DESC; 3207def ILVOD_D : ILVOD_D_ENC, ILVOD_D_DESC; 3208 3209def ILVR_B : ILVR_B_ENC, ILVR_B_DESC; 3210def ILVR_H : ILVR_H_ENC, ILVR_H_DESC; 3211def ILVR_W : ILVR_W_ENC, ILVR_W_DESC; 3212def ILVR_D : ILVR_D_ENC, ILVR_D_DESC; 3213 3214def INSERT_B : INSERT_B_ENC, INSERT_B_DESC; 3215def INSERT_H : INSERT_H_ENC, INSERT_H_DESC; 3216def INSERT_W : INSERT_W_ENC, INSERT_W_DESC; 3217def INSERT_D : INSERT_D_ENC, INSERT_D_DESC, ASE_MSA64; 3218 3219// INSERT_FW_PSEUDO defined after INSVE_W 3220// INSERT_FD_PSEUDO defined after INSVE_D 3221 3222// There is a fourth operand that is not present in the encoding. Use a 3223// custom decoder to get a chance to add it. 3224let DecoderMethod = "DecodeINSVE_DF" in { 3225 def INSVE_B : INSVE_B_ENC, INSVE_B_DESC; 3226 def INSVE_H : INSVE_H_ENC, INSVE_H_DESC; 3227 def INSVE_W : INSVE_W_ENC, INSVE_W_DESC; 3228 def INSVE_D : INSVE_D_ENC, INSVE_D_DESC; 3229} 3230 3231def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC; 3232def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC; 3233 3234def INSERT_B_VIDX_PSEUDO : INSERT_B_VIDX_PSEUDO_DESC; 3235def INSERT_H_VIDX_PSEUDO : INSERT_H_VIDX_PSEUDO_DESC; 3236def INSERT_W_VIDX_PSEUDO : INSERT_W_VIDX_PSEUDO_DESC; 3237def INSERT_D_VIDX_PSEUDO : INSERT_D_VIDX_PSEUDO_DESC; 3238def INSERT_FW_VIDX_PSEUDO : INSERT_FW_VIDX_PSEUDO_DESC; 3239def INSERT_FD_VIDX_PSEUDO : INSERT_FD_VIDX_PSEUDO_DESC; 3240 3241def INSERT_B_VIDX64_PSEUDO : INSERT_B_VIDX64_PSEUDO_DESC; 3242def INSERT_H_VIDX64_PSEUDO : INSERT_H_VIDX64_PSEUDO_DESC; 3243def INSERT_W_VIDX64_PSEUDO : INSERT_W_VIDX64_PSEUDO_DESC; 3244def INSERT_D_VIDX64_PSEUDO : INSERT_D_VIDX64_PSEUDO_DESC; 3245def INSERT_FW_VIDX64_PSEUDO : INSERT_FW_VIDX64_PSEUDO_DESC; 3246def INSERT_FD_VIDX64_PSEUDO : INSERT_FD_VIDX64_PSEUDO_DESC; 3247 3248def LD_B: LD_B_ENC, LD_B_DESC; 3249def LD_H: LD_H_ENC, LD_H_DESC; 3250def LD_W: LD_W_ENC, LD_W_DESC; 3251def LD_D: LD_D_ENC, LD_D_DESC; 3252 3253def LDI_B : LDI_B_ENC, LDI_B_DESC; 3254def LDI_H : LDI_H_ENC, LDI_H_DESC; 3255def LDI_W : LDI_W_ENC, LDI_W_DESC; 3256def LDI_D : LDI_D_ENC, LDI_D_DESC; 3257 3258def LSA : LSA_ENC, LSA_DESC; 3259def DLSA : DLSA_ENC, DLSA_DESC, ASE_MSA64; 3260 3261def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC; 3262def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC; 3263 3264def MADDR_Q_H : MADDR_Q_H_ENC, MADDR_Q_H_DESC; 3265def MADDR_Q_W : MADDR_Q_W_ENC, MADDR_Q_W_DESC; 3266 3267def MADDV_B : MADDV_B_ENC, MADDV_B_DESC; 3268def MADDV_H : MADDV_H_ENC, MADDV_H_DESC; 3269def MADDV_W : MADDV_W_ENC, MADDV_W_DESC; 3270def MADDV_D : MADDV_D_ENC, MADDV_D_DESC; 3271 3272def MAX_A_B : MAX_A_B_ENC, MAX_A_B_DESC; 3273def MAX_A_H : MAX_A_H_ENC, MAX_A_H_DESC; 3274def MAX_A_W : MAX_A_W_ENC, MAX_A_W_DESC; 3275def MAX_A_D : MAX_A_D_ENC, MAX_A_D_DESC; 3276 3277def MAX_S_B : MAX_S_B_ENC, MAX_S_B_DESC; 3278def MAX_S_H : MAX_S_H_ENC, MAX_S_H_DESC; 3279def MAX_S_W : MAX_S_W_ENC, MAX_S_W_DESC; 3280def MAX_S_D : MAX_S_D_ENC, MAX_S_D_DESC; 3281 3282def MAX_U_B : MAX_U_B_ENC, MAX_U_B_DESC; 3283def MAX_U_H : MAX_U_H_ENC, MAX_U_H_DESC; 3284def MAX_U_W : MAX_U_W_ENC, MAX_U_W_DESC; 3285def MAX_U_D : MAX_U_D_ENC, MAX_U_D_DESC; 3286 3287def MAXI_S_B : MAXI_S_B_ENC, MAXI_S_B_DESC; 3288def MAXI_S_H : MAXI_S_H_ENC, MAXI_S_H_DESC; 3289def MAXI_S_W : MAXI_S_W_ENC, MAXI_S_W_DESC; 3290def MAXI_S_D : MAXI_S_D_ENC, MAXI_S_D_DESC; 3291 3292def MAXI_U_B : MAXI_U_B_ENC, MAXI_U_B_DESC; 3293def MAXI_U_H : MAXI_U_H_ENC, MAXI_U_H_DESC; 3294def MAXI_U_W : MAXI_U_W_ENC, MAXI_U_W_DESC; 3295def MAXI_U_D : MAXI_U_D_ENC, MAXI_U_D_DESC; 3296 3297def MIN_A_B : MIN_A_B_ENC, MIN_A_B_DESC; 3298def MIN_A_H : MIN_A_H_ENC, MIN_A_H_DESC; 3299def MIN_A_W : MIN_A_W_ENC, MIN_A_W_DESC; 3300def MIN_A_D : MIN_A_D_ENC, MIN_A_D_DESC; 3301 3302def MIN_S_B : MIN_S_B_ENC, MIN_S_B_DESC; 3303def MIN_S_H : MIN_S_H_ENC, MIN_S_H_DESC; 3304def MIN_S_W : MIN_S_W_ENC, MIN_S_W_DESC; 3305def MIN_S_D : MIN_S_D_ENC, MIN_S_D_DESC; 3306 3307def MIN_U_B : MIN_U_B_ENC, MIN_U_B_DESC; 3308def MIN_U_H : MIN_U_H_ENC, MIN_U_H_DESC; 3309def MIN_U_W : MIN_U_W_ENC, MIN_U_W_DESC; 3310def MIN_U_D : MIN_U_D_ENC, MIN_U_D_DESC; 3311 3312def MINI_S_B : MINI_S_B_ENC, MINI_S_B_DESC; 3313def MINI_S_H : MINI_S_H_ENC, MINI_S_H_DESC; 3314def MINI_S_W : MINI_S_W_ENC, MINI_S_W_DESC; 3315def MINI_S_D : MINI_S_D_ENC, MINI_S_D_DESC; 3316 3317def MINI_U_B : MINI_U_B_ENC, MINI_U_B_DESC; 3318def MINI_U_H : MINI_U_H_ENC, MINI_U_H_DESC; 3319def MINI_U_W : MINI_U_W_ENC, MINI_U_W_DESC; 3320def MINI_U_D : MINI_U_D_ENC, MINI_U_D_DESC; 3321 3322def MOD_S_B : MOD_S_B_ENC, MOD_S_B_DESC; 3323def MOD_S_H : MOD_S_H_ENC, MOD_S_H_DESC; 3324def MOD_S_W : MOD_S_W_ENC, MOD_S_W_DESC; 3325def MOD_S_D : MOD_S_D_ENC, MOD_S_D_DESC; 3326 3327def MOD_U_B : MOD_U_B_ENC, MOD_U_B_DESC; 3328def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC; 3329def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC; 3330def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC; 3331 3332def MOVE_V : MOVE_V_ENC, MOVE_V_DESC; 3333 3334def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC; 3335def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC; 3336 3337def MSUBR_Q_H : MSUBR_Q_H_ENC, MSUBR_Q_H_DESC; 3338def MSUBR_Q_W : MSUBR_Q_W_ENC, MSUBR_Q_W_DESC; 3339 3340def MSUBV_B : MSUBV_B_ENC, MSUBV_B_DESC; 3341def MSUBV_H : MSUBV_H_ENC, MSUBV_H_DESC; 3342def MSUBV_W : MSUBV_W_ENC, MSUBV_W_DESC; 3343def MSUBV_D : MSUBV_D_ENC, MSUBV_D_DESC; 3344 3345def MUL_Q_H : MUL_Q_H_ENC, MUL_Q_H_DESC; 3346def MUL_Q_W : MUL_Q_W_ENC, MUL_Q_W_DESC; 3347 3348def MULR_Q_H : MULR_Q_H_ENC, MULR_Q_H_DESC; 3349def MULR_Q_W : MULR_Q_W_ENC, MULR_Q_W_DESC; 3350 3351def MULV_B : MULV_B_ENC, MULV_B_DESC; 3352def MULV_H : MULV_H_ENC, MULV_H_DESC; 3353def MULV_W : MULV_W_ENC, MULV_W_DESC; 3354def MULV_D : MULV_D_ENC, MULV_D_DESC; 3355 3356def NLOC_B : NLOC_B_ENC, NLOC_B_DESC; 3357def NLOC_H : NLOC_H_ENC, NLOC_H_DESC; 3358def NLOC_W : NLOC_W_ENC, NLOC_W_DESC; 3359def NLOC_D : NLOC_D_ENC, NLOC_D_DESC; 3360 3361def NLZC_B : NLZC_B_ENC, NLZC_B_DESC; 3362def NLZC_H : NLZC_H_ENC, NLZC_H_DESC; 3363def NLZC_W : NLZC_W_ENC, NLZC_W_DESC; 3364def NLZC_D : NLZC_D_ENC, NLZC_D_DESC; 3365 3366def NOR_V : NOR_V_ENC, NOR_V_DESC; 3367def NOR_V_H_PSEUDO : NOR_V_H_PSEUDO_DESC, 3368 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3369 MSA128BOpnd:$ws, 3370 MSA128BOpnd:$wt)>; 3371def NOR_V_W_PSEUDO : NOR_V_W_PSEUDO_DESC, 3372 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3373 MSA128BOpnd:$ws, 3374 MSA128BOpnd:$wt)>; 3375def NOR_V_D_PSEUDO : NOR_V_D_PSEUDO_DESC, 3376 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3377 MSA128BOpnd:$ws, 3378 MSA128BOpnd:$wt)>; 3379 3380def NORI_B : NORI_B_ENC, NORI_B_DESC; 3381 3382def OR_V : OR_V_ENC, OR_V_DESC; 3383def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC, 3384 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3385 MSA128BOpnd:$ws, 3386 MSA128BOpnd:$wt)>; 3387def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC, 3388 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3389 MSA128BOpnd:$ws, 3390 MSA128BOpnd:$wt)>; 3391def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC, 3392 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3393 MSA128BOpnd:$ws, 3394 MSA128BOpnd:$wt)>; 3395 3396def ORI_B : ORI_B_ENC, ORI_B_DESC; 3397 3398def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC; 3399def PCKEV_H : PCKEV_H_ENC, PCKEV_H_DESC; 3400def PCKEV_W : PCKEV_W_ENC, PCKEV_W_DESC; 3401def PCKEV_D : PCKEV_D_ENC, PCKEV_D_DESC; 3402 3403def PCKOD_B : PCKOD_B_ENC, PCKOD_B_DESC; 3404def PCKOD_H : PCKOD_H_ENC, PCKOD_H_DESC; 3405def PCKOD_W : PCKOD_W_ENC, PCKOD_W_DESC; 3406def PCKOD_D : PCKOD_D_ENC, PCKOD_D_DESC; 3407 3408def PCNT_B : PCNT_B_ENC, PCNT_B_DESC; 3409def PCNT_H : PCNT_H_ENC, PCNT_H_DESC; 3410def PCNT_W : PCNT_W_ENC, PCNT_W_DESC; 3411def PCNT_D : PCNT_D_ENC, PCNT_D_DESC; 3412 3413def SAT_S_B : SAT_S_B_ENC, SAT_S_B_DESC; 3414def SAT_S_H : SAT_S_H_ENC, SAT_S_H_DESC; 3415def SAT_S_W : SAT_S_W_ENC, SAT_S_W_DESC; 3416def SAT_S_D : SAT_S_D_ENC, SAT_S_D_DESC; 3417 3418def SAT_U_B : SAT_U_B_ENC, SAT_U_B_DESC; 3419def SAT_U_H : SAT_U_H_ENC, SAT_U_H_DESC; 3420def SAT_U_W : SAT_U_W_ENC, SAT_U_W_DESC; 3421def SAT_U_D : SAT_U_D_ENC, SAT_U_D_DESC; 3422 3423def SHF_B : SHF_B_ENC, SHF_B_DESC; 3424def SHF_H : SHF_H_ENC, SHF_H_DESC; 3425def SHF_W : SHF_W_ENC, SHF_W_DESC; 3426 3427def SLD_B : SLD_B_ENC, SLD_B_DESC; 3428def SLD_H : SLD_H_ENC, SLD_H_DESC; 3429def SLD_W : SLD_W_ENC, SLD_W_DESC; 3430def SLD_D : SLD_D_ENC, SLD_D_DESC; 3431 3432def SLDI_B : SLDI_B_ENC, SLDI_B_DESC; 3433def SLDI_H : SLDI_H_ENC, SLDI_H_DESC; 3434def SLDI_W : SLDI_W_ENC, SLDI_W_DESC; 3435def SLDI_D : SLDI_D_ENC, SLDI_D_DESC; 3436 3437def SLL_B : SLL_B_ENC, SLL_B_DESC; 3438def SLL_H : SLL_H_ENC, SLL_H_DESC; 3439def SLL_W : SLL_W_ENC, SLL_W_DESC; 3440def SLL_D : SLL_D_ENC, SLL_D_DESC; 3441 3442def SLLI_B : SLLI_B_ENC, SLLI_B_DESC; 3443def SLLI_H : SLLI_H_ENC, SLLI_H_DESC; 3444def SLLI_W : SLLI_W_ENC, SLLI_W_DESC; 3445def SLLI_D : SLLI_D_ENC, SLLI_D_DESC; 3446 3447def SPLAT_B : SPLAT_B_ENC, SPLAT_B_DESC; 3448def SPLAT_H : SPLAT_H_ENC, SPLAT_H_DESC; 3449def SPLAT_W : SPLAT_W_ENC, SPLAT_W_DESC; 3450def SPLAT_D : SPLAT_D_ENC, SPLAT_D_DESC; 3451 3452def SPLATI_B : SPLATI_B_ENC, SPLATI_B_DESC; 3453def SPLATI_H : SPLATI_H_ENC, SPLATI_H_DESC; 3454def SPLATI_W : SPLATI_W_ENC, SPLATI_W_DESC; 3455def SPLATI_D : SPLATI_D_ENC, SPLATI_D_DESC; 3456 3457def SRA_B : SRA_B_ENC, SRA_B_DESC; 3458def SRA_H : SRA_H_ENC, SRA_H_DESC; 3459def SRA_W : SRA_W_ENC, SRA_W_DESC; 3460def SRA_D : SRA_D_ENC, SRA_D_DESC; 3461 3462def SRAI_B : SRAI_B_ENC, SRAI_B_DESC; 3463def SRAI_H : SRAI_H_ENC, SRAI_H_DESC; 3464def SRAI_W : SRAI_W_ENC, SRAI_W_DESC; 3465def SRAI_D : SRAI_D_ENC, SRAI_D_DESC; 3466 3467def SRAR_B : SRAR_B_ENC, SRAR_B_DESC; 3468def SRAR_H : SRAR_H_ENC, SRAR_H_DESC; 3469def SRAR_W : SRAR_W_ENC, SRAR_W_DESC; 3470def SRAR_D : SRAR_D_ENC, SRAR_D_DESC; 3471 3472def SRARI_B : SRARI_B_ENC, SRARI_B_DESC; 3473def SRARI_H : SRARI_H_ENC, SRARI_H_DESC; 3474def SRARI_W : SRARI_W_ENC, SRARI_W_DESC; 3475def SRARI_D : SRARI_D_ENC, SRARI_D_DESC; 3476 3477def SRL_B : SRL_B_ENC, SRL_B_DESC; 3478def SRL_H : SRL_H_ENC, SRL_H_DESC; 3479def SRL_W : SRL_W_ENC, SRL_W_DESC; 3480def SRL_D : SRL_D_ENC, SRL_D_DESC; 3481 3482def SRLI_B : SRLI_B_ENC, SRLI_B_DESC; 3483def SRLI_H : SRLI_H_ENC, SRLI_H_DESC; 3484def SRLI_W : SRLI_W_ENC, SRLI_W_DESC; 3485def SRLI_D : SRLI_D_ENC, SRLI_D_DESC; 3486 3487def SRLR_B : SRLR_B_ENC, SRLR_B_DESC; 3488def SRLR_H : SRLR_H_ENC, SRLR_H_DESC; 3489def SRLR_W : SRLR_W_ENC, SRLR_W_DESC; 3490def SRLR_D : SRLR_D_ENC, SRLR_D_DESC; 3491 3492def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC; 3493def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC; 3494def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC; 3495def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC; 3496 3497def ST_B: ST_B_ENC, ST_B_DESC; 3498def ST_H: ST_H_ENC, ST_H_DESC; 3499def ST_W: ST_W_ENC, ST_W_DESC; 3500def ST_D: ST_D_ENC, ST_D_DESC; 3501 3502def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC; 3503def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC; 3504def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC; 3505def SUBS_S_D : SUBS_S_D_ENC, SUBS_S_D_DESC; 3506 3507def SUBS_U_B : SUBS_U_B_ENC, SUBS_U_B_DESC; 3508def SUBS_U_H : SUBS_U_H_ENC, SUBS_U_H_DESC; 3509def SUBS_U_W : SUBS_U_W_ENC, SUBS_U_W_DESC; 3510def SUBS_U_D : SUBS_U_D_ENC, SUBS_U_D_DESC; 3511 3512def SUBSUS_U_B : SUBSUS_U_B_ENC, SUBSUS_U_B_DESC; 3513def SUBSUS_U_H : SUBSUS_U_H_ENC, SUBSUS_U_H_DESC; 3514def SUBSUS_U_W : SUBSUS_U_W_ENC, SUBSUS_U_W_DESC; 3515def SUBSUS_U_D : SUBSUS_U_D_ENC, SUBSUS_U_D_DESC; 3516 3517def SUBSUU_S_B : SUBSUU_S_B_ENC, SUBSUU_S_B_DESC; 3518def SUBSUU_S_H : SUBSUU_S_H_ENC, SUBSUU_S_H_DESC; 3519def SUBSUU_S_W : SUBSUU_S_W_ENC, SUBSUU_S_W_DESC; 3520def SUBSUU_S_D : SUBSUU_S_D_ENC, SUBSUU_S_D_DESC; 3521 3522def SUBV_B : SUBV_B_ENC, SUBV_B_DESC; 3523def SUBV_H : SUBV_H_ENC, SUBV_H_DESC; 3524def SUBV_W : SUBV_W_ENC, SUBV_W_DESC; 3525def SUBV_D : SUBV_D_ENC, SUBV_D_DESC; 3526 3527def SUBVI_B : SUBVI_B_ENC, SUBVI_B_DESC; 3528def SUBVI_H : SUBVI_H_ENC, SUBVI_H_DESC; 3529def SUBVI_W : SUBVI_W_ENC, SUBVI_W_DESC; 3530def SUBVI_D : SUBVI_D_ENC, SUBVI_D_DESC; 3531 3532def VSHF_B : VSHF_B_ENC, VSHF_B_DESC; 3533def VSHF_H : VSHF_H_ENC, VSHF_H_DESC; 3534def VSHF_W : VSHF_W_ENC, VSHF_W_DESC; 3535def VSHF_D : VSHF_D_ENC, VSHF_D_DESC; 3536 3537def XOR_V : XOR_V_ENC, XOR_V_DESC; 3538def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC, 3539 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3540 MSA128BOpnd:$ws, 3541 MSA128BOpnd:$wt)>; 3542def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC, 3543 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3544 MSA128BOpnd:$ws, 3545 MSA128BOpnd:$wt)>; 3546def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC, 3547 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3548 MSA128BOpnd:$ws, 3549 MSA128BOpnd:$wt)>; 3550 3551def XORI_B : XORI_B_ENC, XORI_B_DESC; 3552 3553// Patterns. 3554class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> : 3555 Pat<pattern, result>, Requires<pred>; 3556 3557def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx), 3558 (COPY_S_W MSA128W:$ws, immZExt4:$idx)>; 3559 3560def : MSAPat<(v8f16 (load addrimm10lsl1:$addr)), (LD_H addrimm10lsl1:$addr)>; 3561def : MSAPat<(v4f32 (load addrimm10lsl2:$addr)), (LD_W addrimm10lsl2:$addr)>; 3562def : MSAPat<(v2f64 (load addrimm10lsl3:$addr)), (LD_D addrimm10lsl3:$addr)>; 3563 3564def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10lsl1:$addr), 3565 (ST_H MSA128H:$ws, addrimm10lsl1:$addr)>; 3566def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrimm10lsl2:$addr), 3567 (ST_W MSA128W:$ws, addrimm10lsl2:$addr)>; 3568def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrimm10lsl3:$addr), 3569 (ST_D MSA128D:$ws, addrimm10lsl3:$addr)>; 3570 3571class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD, 3572 RegisterOperand ROWS = ROWD, 3573 InstrItinClass itin = NoItinerary> : 3574 MSAPseudo<(outs ROWD:$wd), 3575 (ins ROWS:$ws), 3576 [(set ROWD:$wd, (fabs ROWS:$ws))]> { 3577 InstrItinClass Itinerary = itin; 3578} 3579def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>, 3580 PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, 3581 MSA128WOpnd:$ws)>; 3582def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128DOpnd>, 3583 PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, 3584 MSA128DOpnd:$ws)>; 3585 3586class MSABitconvertPat<ValueType DstVT, ValueType SrcVT, 3587 RegisterClass DstRC, list<Predicate> preds = [HasMSA]> : 3588 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3589 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>; 3590 3591// These are endian-independent because the element size doesnt change 3592def : MSABitconvertPat<v8i16, v8f16, MSA128H>; 3593def : MSABitconvertPat<v4i32, v4f32, MSA128W>; 3594def : MSABitconvertPat<v2i64, v2f64, MSA128D>; 3595def : MSABitconvertPat<v8f16, v8i16, MSA128H>; 3596def : MSABitconvertPat<v4f32, v4i32, MSA128W>; 3597def : MSABitconvertPat<v2f64, v2i64, MSA128D>; 3598 3599// Little endian bitcasts are always no-ops 3600def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>; 3601def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>; 3602def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>; 3603def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>; 3604def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>; 3605def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>; 3606 3607def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>; 3608def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>; 3609def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>; 3610def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>; 3611def : MSABitconvertPat<v8i16, v2f64, MSA128H, [HasMSA, IsLE]>; 3612 3613def : MSABitconvertPat<v4i32, v16i8, MSA128W, [HasMSA, IsLE]>; 3614def : MSABitconvertPat<v4i32, v8i16, MSA128W, [HasMSA, IsLE]>; 3615def : MSABitconvertPat<v4i32, v2i64, MSA128W, [HasMSA, IsLE]>; 3616def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>; 3617def : MSABitconvertPat<v4i32, v2f64, MSA128W, [HasMSA, IsLE]>; 3618 3619def : MSABitconvertPat<v2i64, v16i8, MSA128D, [HasMSA, IsLE]>; 3620def : MSABitconvertPat<v2i64, v8i16, MSA128D, [HasMSA, IsLE]>; 3621def : MSABitconvertPat<v2i64, v4i32, MSA128D, [HasMSA, IsLE]>; 3622def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>; 3623def : MSABitconvertPat<v2i64, v4f32, MSA128D, [HasMSA, IsLE]>; 3624 3625def : MSABitconvertPat<v4f32, v16i8, MSA128W, [HasMSA, IsLE]>; 3626def : MSABitconvertPat<v4f32, v8i16, MSA128W, [HasMSA, IsLE]>; 3627def : MSABitconvertPat<v4f32, v2i64, MSA128W, [HasMSA, IsLE]>; 3628def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>; 3629def : MSABitconvertPat<v4f32, v2f64, MSA128W, [HasMSA, IsLE]>; 3630 3631def : MSABitconvertPat<v2f64, v16i8, MSA128D, [HasMSA, IsLE]>; 3632def : MSABitconvertPat<v2f64, v8i16, MSA128D, [HasMSA, IsLE]>; 3633def : MSABitconvertPat<v2f64, v4i32, MSA128D, [HasMSA, IsLE]>; 3634def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>; 3635def : MSABitconvertPat<v2f64, v4f32, MSA128D, [HasMSA, IsLE]>; 3636 3637// Big endian bitcasts expand to shuffle instructions. 3638// This is because bitcast is defined to be a store/load sequence and the 3639// vector store/load instructions are mixed-endian with respect to the vector 3640// as a whole (little endian with respect to element order, but big endian 3641// elements). 3642 3643class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT, 3644 RegisterClass DstRC, MSAInst Insn, 3645 RegisterClass ViaRC> : 3646 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3647 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27), 3648 DstRC), 3649 [HasMSA, IsBE]>; 3650 3651class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT, 3652 RegisterClass DstRC, MSAInst Insn, 3653 RegisterClass ViaRC> : 3654 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3655 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177), 3656 DstRC), 3657 [HasMSA, IsBE]>; 3658 3659class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT, 3660 RegisterClass DstRC> : 3661 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>; 3662 3663class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT, 3664 RegisterClass DstRC> : 3665 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>; 3666 3667class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT, 3668 RegisterClass DstRC> : 3669 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3670 (COPY_TO_REGCLASS 3671 (SHF_W 3672 (COPY_TO_REGCLASS 3673 (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27), 3674 MSA128W), 177), 3675 DstRC), 3676 [HasMSA, IsBE]>; 3677 3678class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT, 3679 RegisterClass DstRC> : 3680 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>; 3681 3682class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT, 3683 RegisterClass DstRC> : 3684 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>; 3685 3686class MSABitconvertReverseWInDPat<ValueType DstVT, ValueType SrcVT, 3687 RegisterClass DstRC> : 3688 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_W, MSA128W>; 3689 3690def : MSABitconvertReverseBInHPat<v8i16, v16i8, MSA128H>; 3691def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>; 3692def : MSABitconvertReverseBInWPat<v4i32, v16i8, MSA128W>; 3693def : MSABitconvertReverseBInWPat<v4f32, v16i8, MSA128W>; 3694def : MSABitconvertReverseBInDPat<v2i64, v16i8, MSA128D>; 3695def : MSABitconvertReverseBInDPat<v2f64, v16i8, MSA128D>; 3696 3697def : MSABitconvertReverseBInHPat<v16i8, v8i16, MSA128B>; 3698def : MSABitconvertReverseHInWPat<v4i32, v8i16, MSA128W>; 3699def : MSABitconvertReverseHInWPat<v4f32, v8i16, MSA128W>; 3700def : MSABitconvertReverseHInDPat<v2i64, v8i16, MSA128D>; 3701def : MSABitconvertReverseHInDPat<v2f64, v8i16, MSA128D>; 3702 3703def : MSABitconvertReverseBInHPat<v16i8, v8f16, MSA128B>; 3704def : MSABitconvertReverseHInWPat<v4i32, v8f16, MSA128W>; 3705def : MSABitconvertReverseHInWPat<v4f32, v8f16, MSA128W>; 3706def : MSABitconvertReverseHInDPat<v2i64, v8f16, MSA128D>; 3707def : MSABitconvertReverseHInDPat<v2f64, v8f16, MSA128D>; 3708 3709def : MSABitconvertReverseBInWPat<v16i8, v4i32, MSA128B>; 3710def : MSABitconvertReverseHInWPat<v8i16, v4i32, MSA128H>; 3711def : MSABitconvertReverseHInWPat<v8f16, v4i32, MSA128H>; 3712def : MSABitconvertReverseWInDPat<v2i64, v4i32, MSA128D>; 3713def : MSABitconvertReverseWInDPat<v2f64, v4i32, MSA128D>; 3714 3715def : MSABitconvertReverseBInWPat<v16i8, v4f32, MSA128B>; 3716def : MSABitconvertReverseHInWPat<v8i16, v4f32, MSA128H>; 3717def : MSABitconvertReverseHInWPat<v8f16, v4f32, MSA128H>; 3718def : MSABitconvertReverseWInDPat<v2i64, v4f32, MSA128D>; 3719def : MSABitconvertReverseWInDPat<v2f64, v4f32, MSA128D>; 3720 3721def : MSABitconvertReverseBInDPat<v16i8, v2i64, MSA128B>; 3722def : MSABitconvertReverseHInDPat<v8i16, v2i64, MSA128H>; 3723def : MSABitconvertReverseHInDPat<v8f16, v2i64, MSA128H>; 3724def : MSABitconvertReverseWInDPat<v4i32, v2i64, MSA128W>; 3725def : MSABitconvertReverseWInDPat<v4f32, v2i64, MSA128W>; 3726 3727def : MSABitconvertReverseBInDPat<v16i8, v2f64, MSA128B>; 3728def : MSABitconvertReverseHInDPat<v8i16, v2f64, MSA128H>; 3729def : MSABitconvertReverseHInDPat<v8f16, v2f64, MSA128H>; 3730def : MSABitconvertReverseWInDPat<v4i32, v2f64, MSA128W>; 3731def : MSABitconvertReverseWInDPat<v4f32, v2f64, MSA128W>; 3732 3733// Pseudos used to implement BNZ.df, and BZ.df 3734 3735class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode, 3736 RegisterClass RCWS, 3737 InstrItinClass itin = NoItinerary> : 3738 MipsPseudo<(outs GPR32:$dst), 3739 (ins RCWS:$ws), 3740 [(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> { 3741 bit usesCustomInserter = 1; 3742 bit hasNoSchedulingInfo = 1; 3743} 3744 3745def SNZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8, 3746 MSA128B, NoItinerary>; 3747def SNZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16, 3748 MSA128H, NoItinerary>; 3749def SNZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32, 3750 MSA128W, NoItinerary>; 3751def SNZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64, 3752 MSA128D, NoItinerary>; 3753def SNZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8, 3754 MSA128B, NoItinerary>; 3755 3756def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8, 3757 MSA128B, NoItinerary>; 3758def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16, 3759 MSA128H, NoItinerary>; 3760def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32, 3761 MSA128W, NoItinerary>; 3762def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64, 3763 MSA128D, NoItinerary>; 3764def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8, 3765 MSA128B, NoItinerary>; 3766 3767// Pseudoes used to implement transparent fp16 support. 3768 3769let ASEPredicate = [HasMSA] in { 3770 let usesCustomInserter = 1 in { 3771 def ST_F16 : 3772 MipsPseudo<(outs), (ins MSA128F16:$ws, mem_simm10:$addr), 3773 [(store (f16 MSA128F16:$ws), (addrimm10:$addr))]>; 3774 def LD_F16 : 3775 MipsPseudo<(outs MSA128F16:$ws), (ins mem_simm10:$addr), 3776 [(set MSA128F16:$ws, (f16 (load addrimm10:$addr)))]>; 3777 } 3778 3779 let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in { 3780 def MSA_FP_EXTEND_W_PSEUDO : 3781 MipsPseudo<(outs FGR32Opnd:$fd), (ins MSA128F16:$ws), 3782 [(set FGR32Opnd:$fd, (f32 (fpextend MSA128F16:$ws)))]>; 3783 def MSA_FP_ROUND_W_PSEUDO : 3784 MipsPseudo<(outs MSA128F16:$wd), (ins FGR32Opnd:$fs), 3785 [(set MSA128F16:$wd, (f16 (fpround FGR32Opnd:$fs)))]>; 3786 def MSA_FP_EXTEND_D_PSEUDO : 3787 MipsPseudo<(outs FGR64Opnd:$fd), (ins MSA128F16:$ws), 3788 [(set FGR64Opnd:$fd, (f64 (fpextend MSA128F16:$ws)))]>; 3789 def MSA_FP_ROUND_D_PSEUDO : 3790 MipsPseudo<(outs MSA128F16:$wd), (ins FGR64Opnd:$fs), 3791 [(set MSA128F16:$wd, (f16 (fpround FGR64Opnd:$fs)))]>; 3792 } 3793 3794 def : MipsPat<(MipsTruncIntFP MSA128F16:$ws), 3795 (TRUNC_W_D64 (MSA_FP_EXTEND_D_PSEUDO MSA128F16:$ws))>, 3796 ISA_MIPS1, ASE_MSA; 3797 3798 def : MipsPat<(MipsFPCmp MSA128F16:$ws, MSA128F16:$wt, imm:$cond), 3799 (FCMP_S32 (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$ws), 3800 (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$wt), imm:$cond)>, 3801 ISA_MIPS1_NOT_32R6_64R6, ASE_MSA; 3802} 3803 3804def vsplati64_imm_eq_63 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{ 3805 APInt Imm; 3806 SDNode *BV = N->getOperand(0).getNode(); 3807 EVT EltTy = N->getValueType(0).getVectorElementType(); 3808 3809 return selectVSplat(BV, Imm, EltTy.getSizeInBits()) && 3810 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 63; 3811}]>; 3812 3813def immi32Cst7 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 7;}]>; 3814def immi32Cst15 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 15;}]>; 3815def immi32Cst31 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 31;}]>; 3816 3817def vsplati8imm7 : PatFrag<(ops node:$wt), 3818 (and node:$wt, (vsplati8 immi32Cst7))>; 3819def vsplati16imm15 : PatFrag<(ops node:$wt), 3820 (and node:$wt, (vsplati16 immi32Cst15))>; 3821def vsplati32imm31 : PatFrag<(ops node:$wt), 3822 (and node:$wt, (vsplati32 immi32Cst31))>; 3823def vsplati64imm63 : PatFrag<(ops node:$wt), 3824 (and node:$wt, vsplati64_imm_eq_63)>; 3825 3826class MSAShiftPat<SDNode Node, ValueType VT, MSAInst Insn, dag Vec> : 3827 MSAPat<(VT (Node VT:$ws, (VT (and VT:$wt, Vec)))), 3828 (VT (Insn VT:$ws, VT:$wt))>; 3829 3830class MSABitPat<SDNode Node, ValueType VT, MSAInst Insn, PatFrag Frag> : 3831 MSAPat<(VT (Node VT:$ws, (shl vsplat_imm_eq_1, (Frag VT:$wt)))), 3832 (VT (Insn VT:$ws, VT:$wt))>; 3833 3834multiclass MSAShiftPats<SDNode Node, string Insn> { 3835 def : MSAShiftPat<Node, v16i8, !cast<MSAInst>(Insn#_B), 3836 (vsplati8 immi32Cst7)>; 3837 def : MSAShiftPat<Node, v8i16, !cast<MSAInst>(Insn#_H), 3838 (vsplati16 immi32Cst15)>; 3839 def : MSAShiftPat<Node, v4i32, !cast<MSAInst>(Insn#_W), 3840 (vsplati32 immi32Cst31)>; 3841 def : MSAPat<(v2i64 (Node v2i64:$ws, (v2i64 (and v2i64:$wt, 3842 vsplati64_imm_eq_63)))), 3843 (v2i64 (!cast<MSAInst>(Insn#_D) v2i64:$ws, v2i64:$wt))>; 3844} 3845 3846multiclass MSABitPats<SDNode Node, string Insn> { 3847 def : MSABitPat<Node, v16i8, !cast<MSAInst>(Insn#_B), vsplati8imm7>; 3848 def : MSABitPat<Node, v8i16, !cast<MSAInst>(Insn#_H), vsplati16imm15>; 3849 def : MSABitPat<Node, v4i32, !cast<MSAInst>(Insn#_W), vsplati32imm31>; 3850 def : MSAPat<(Node v2i64:$ws, (shl (v2i64 vsplati64_imm_eq_1), 3851 (vsplati64imm63 v2i64:$wt))), 3852 (v2i64 (!cast<MSAInst>(Insn#_D) v2i64:$ws, v2i64:$wt))>; 3853} 3854 3855defm : MSAShiftPats<shl, "SLL">; 3856defm : MSAShiftPats<srl, "SRL">; 3857defm : MSAShiftPats<sra, "SRA">; 3858defm : MSABitPats<xor, "BNEG">; 3859defm : MSABitPats<or, "BSET">; 3860 3861def : MSAPat<(and v16i8:$ws, (xor (shl vsplat_imm_eq_1, 3862 (vsplati8imm7 v16i8:$wt)), 3863 immAllOnesV)), 3864 (v16i8 (BCLR_B v16i8:$ws, v16i8:$wt))>; 3865def : MSAPat<(and v8i16:$ws, (xor (shl vsplat_imm_eq_1, 3866 (vsplati16imm15 v8i16:$wt)), 3867 immAllOnesV)), 3868 (v8i16 (BCLR_H v8i16:$ws, v8i16:$wt))>; 3869def : MSAPat<(and v4i32:$ws, (xor (shl vsplat_imm_eq_1, 3870 (vsplati32imm31 v4i32:$wt)), 3871 immAllOnesV)), 3872 (v4i32 (BCLR_W v4i32:$ws, v4i32:$wt))>; 3873def : MSAPat<(and v2i64:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1), 3874 (vsplati64imm63 v2i64:$wt)), 3875 (bitconvert (v4i32 immAllOnesV)))), 3876 (v2i64 (BCLR_D v2i64:$ws, v2i64:$wt))>; 3877 3878// Vector extraction with fixed index. 3879// 3880// Extracting 32-bit values on MSA32 should always use COPY_S_W rather than 3881// COPY_U_W, even for the zero-extended case. This is because our forward 3882// compatibility strategy is to consider registers to be infinitely 3883// sign-extended so that a MIPS64 can execute MIPS32 code without getting 3884// different register values. 3885def : MSAPat<(vextract_zext_i32 (v4i32 MSA128W:$ws), immZExt2Ptr:$idx), 3886 (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64; 3887def : MSAPat<(vextract_zext_i32 (v4f32 MSA128W:$ws), immZExt2Ptr:$idx), 3888 (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64; 3889 3890// Extracting 64-bit values on MSA64 should always use COPY_S_D rather than 3891// COPY_U_D, even for the zero-extended case. This is because our forward 3892// compatibility strategy is to consider registers to be infinitely 3893// sign-extended so that a hypothetical MIPS128 would be able to execute MIPS64 3894// code without getting different register values. 3895def : MSAPat<(vextract_zext_i64 (v2i64 MSA128D:$ws), immZExt1Ptr:$idx), 3896 (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64; 3897def : MSAPat<(vextract_zext_i64 (v2f64 MSA128D:$ws), immZExt1Ptr:$idx), 3898 (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64; 3899 3900// Vector extraction with variable index 3901def : MSAPat<(i32 (vextract_sext_i8 v16i8:$ws, i32:$idx)), 3902 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws, 3903 i32:$idx), 3904 sub_lo)), 3905 GPR32), (i32 24))>; 3906def : MSAPat<(i32 (vextract_sext_i16 v8i16:$ws, i32:$idx)), 3907 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws, 3908 i32:$idx), 3909 sub_lo)), 3910 GPR32), (i32 16))>; 3911def : MSAPat<(i32 (vextract_sext_i32 v4i32:$ws, i32:$idx)), 3912 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws, 3913 i32:$idx), 3914 sub_lo)), 3915 GPR32)>; 3916def : MSAPat<(i64 (vextract_sext_i64 v2i64:$ws, i32:$idx)), 3917 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws, 3918 i32:$idx), 3919 sub_64)), 3920 GPR64), [HasMSA, IsGP64bit]>; 3921 3922def : MSAPat<(i32 (vextract_zext_i8 v16i8:$ws, i32:$idx)), 3923 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws, 3924 i32:$idx), 3925 sub_lo)), 3926 GPR32), (i32 24))>; 3927def : MSAPat<(i32 (vextract_zext_i16 v8i16:$ws, i32:$idx)), 3928 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws, 3929 i32:$idx), 3930 sub_lo)), 3931 GPR32), (i32 16))>; 3932def : MSAPat<(i32 (vextract_zext_i32 v4i32:$ws, i32:$idx)), 3933 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws, 3934 i32:$idx), 3935 sub_lo)), 3936 GPR32)>; 3937def : MSAPat<(i64 (vextract_zext_i64 v2i64:$ws, i32:$idx)), 3938 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws, 3939 i32:$idx), 3940 sub_64)), 3941 GPR64), [HasMSA, IsGP64bit]>; 3942 3943def : MSAPat<(f32 (vector_extract v4f32:$ws, i32:$idx)), 3944 (f32 (EXTRACT_SUBREG (SPLAT_W v4f32:$ws, 3945 i32:$idx), 3946 sub_lo))>; 3947def : MSAPat<(f64 (vector_extract v2f64:$ws, i32:$idx)), 3948 (f64 (EXTRACT_SUBREG (SPLAT_D v2f64:$ws, 3949 i32:$idx), 3950 sub_64))>; 3951 3952// Vector extraction with variable index (N64 ABI) 3953def : MSAPat< 3954 (i32 (vextract_sext_i8 v16i8:$ws, i64:$idx)), 3955 (SRA (COPY_TO_REGCLASS 3956 (i32 (EXTRACT_SUBREG 3957 (SPLAT_B v16i8:$ws, 3958 (COPY_TO_REGCLASS 3959 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3960 sub_lo)), 3961 GPR32), 3962 (i32 24))>; 3963def : MSAPat< 3964 (i32 (vextract_sext_i16 v8i16:$ws, i64:$idx)), 3965 (SRA (COPY_TO_REGCLASS 3966 (i32 (EXTRACT_SUBREG 3967 (SPLAT_H v8i16:$ws, 3968 (COPY_TO_REGCLASS 3969 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3970 sub_lo)), 3971 GPR32), 3972 (i32 16))>; 3973def : MSAPat< 3974 (i32 (vextract_sext_i32 v4i32:$ws, i64:$idx)), 3975 (COPY_TO_REGCLASS 3976 (i32 (EXTRACT_SUBREG 3977 (SPLAT_W v4i32:$ws, 3978 (COPY_TO_REGCLASS 3979 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3980 sub_lo)), 3981 GPR32)>; 3982def : MSAPat< 3983 (i64 (vextract_sext_i64 v2i64:$ws, i64:$idx)), 3984 (COPY_TO_REGCLASS 3985 (i64 (EXTRACT_SUBREG 3986 (SPLAT_D v2i64:$ws, 3987 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3988 sub_64)), 3989 GPR64), [HasMSA, IsGP64bit]>; 3990 3991def : MSAPat< 3992 (i32 (vextract_zext_i8 v16i8:$ws, i64:$idx)), 3993 (SRL (COPY_TO_REGCLASS 3994 (i32 (EXTRACT_SUBREG 3995 (SPLAT_B v16i8:$ws, 3996 (COPY_TO_REGCLASS 3997 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3998 sub_lo)), 3999 GPR32), 4000 (i32 24))>; 4001def : MSAPat< 4002 (i32 (vextract_zext_i16 v8i16:$ws, i64:$idx)), 4003 (SRL (COPY_TO_REGCLASS 4004 (i32 (EXTRACT_SUBREG 4005 (SPLAT_H v8i16:$ws, 4006 (COPY_TO_REGCLASS 4007 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4008 sub_lo)), 4009 GPR32), 4010 (i32 16))>; 4011def : MSAPat< 4012 (i32 (vextract_zext_i32 v4i32:$ws, i64:$idx)), 4013 (COPY_TO_REGCLASS 4014 (i32 (EXTRACT_SUBREG 4015 (SPLAT_W v4i32:$ws, 4016 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4017 sub_lo)), 4018 GPR32)>; 4019def : MSAPat< 4020 (i64 (vextract_zext_i64 v2i64:$ws, i64:$idx)), 4021 (COPY_TO_REGCLASS 4022 (i64 (EXTRACT_SUBREG 4023 (SPLAT_D v2i64:$ws, 4024 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4025 sub_64)), 4026 GPR64), 4027 [HasMSA, IsGP64bit]>; 4028 4029def : MSAPat< 4030 (f32 (vector_extract v4f32:$ws, i64:$idx)), 4031 (f32 (EXTRACT_SUBREG 4032 (SPLAT_W v4f32:$ws, 4033 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4034 sub_lo))>; 4035def : MSAPat< 4036 (f64 (vector_extract v2f64:$ws, i64:$idx)), 4037 (f64 (EXTRACT_SUBREG 4038 (SPLAT_D v2f64:$ws, 4039 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4040 sub_64))>; 4041 4042def : MSAPat<(vfseteq_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b), 4043 (FCEQ_W MSA128WOpnd:$a, MSA128WOpnd:$b)>; 4044def : MSAPat<(vfseteq_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b), 4045 (FCEQ_D MSA128DOpnd:$a, MSA128DOpnd:$b)>; 4046def : MSAPat<(vfsetle_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b), 4047 (FCLE_W MSA128WOpnd:$a, MSA128WOpnd:$b)>; 4048def : MSAPat<(vfsetle_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b), 4049 (FCLE_D MSA128DOpnd:$a, MSA128DOpnd:$b)>; 4050def : MSAPat<(vfsetlt_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b), 4051 (FCLT_W MSA128WOpnd:$a, MSA128WOpnd:$b)>; 4052def : MSAPat<(vfsetlt_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b), 4053 (FCLT_D MSA128DOpnd:$a, MSA128DOpnd:$b)>; 4054def : MSAPat<(vfsetne_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b), 4055 (FCNE_W MSA128WOpnd:$a, MSA128WOpnd:$b)>; 4056def : MSAPat<(vfsetne_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b), 4057 (FCNE_D MSA128DOpnd:$a, MSA128DOpnd:$b)>; 4058