xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MipsMSAInstrInfo.td (revision b64c5a0ace59af62eff52bfe110a521dc73c937b) 
1//===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes Mips MSA ASE instructions.
10//
11//===----------------------------------------------------------------------===//
12
13def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>;
14def SDT_VSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
15                                      SDTCisInt<1>,
16                                      SDTCisSameAs<1, 2>,
17                                      SDTCisVT<3, OtherVT>]>;
18def SDT_VFSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
19                                       SDTCisFP<1>,
20                                       SDTCisSameAs<1, 2>,
21                                       SDTCisVT<3, OtherVT>]>;
22def SDT_VSHF : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>,
23                                    SDTCisInt<1>, SDTCisVec<1>,
24                                    SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>;
25def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
26                                   SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>;
27def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
28                                   SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
29def SDT_INSVE : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
30                                     SDTCisVT<2, i32>, SDTCisSameAs<0, 3>,
31                                     SDTCisVT<4, i32>]>;
32
33def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>;
34def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>;
35def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>;
36def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>;
37def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp,
38                      [SDNPCommutative, SDNPAssociative]>;
39def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>;
40def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>;
41def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>;
42def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>;
43def MipsILVL  : SDNode<"MipsISD::ILVL",  SDT_ILV>;
44def MipsILVR  : SDNode<"MipsISD::ILVR",  SDT_ILV>;
45def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>;
46def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>;
47def MipsINSVE : SDNode<"MipsISD::INSVE", SDT_INSVE>;
48def MipsFMS   : SDNode<"MipsISD::FMS", SDTFPTernaryOp>;
49
50def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>;
51def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>;
52
53def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT",
54    SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
55def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT",
56    SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
57
58def immZExt1Ptr : ImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>;
59def immZExt2Ptr : ImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>;
60def immZExt3Ptr : ImmLeaf<iPTR, [{return isUInt<3>(Imm);}]>;
61def immZExt4Ptr : ImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>;
62
63def timmZExt1Ptr : TImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>;
64def timmZExt2Ptr : TImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>;
65def timmZExt3Ptr : TImmLeaf<iPTR, [{return isUInt<3>(Imm);}]>;
66def timmZExt4Ptr : TImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>;
67
68// Operands
69
70def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>;
71
72// Pattern fragments
73def vextract_sext_i8  : PatFrag<(ops node:$vec, node:$idx),
74                                (MipsVExtractSExt node:$vec, node:$idx, i8)>;
75def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx),
76                                (MipsVExtractSExt node:$vec, node:$idx, i16)>;
77def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx),
78                                (MipsVExtractSExt node:$vec, node:$idx, i32)>;
79def vextract_sext_i64 : PatFrag<(ops node:$vec, node:$idx),
80                                (MipsVExtractSExt node:$vec, node:$idx, i64)>;
81
82def vextract_zext_i8  : PatFrag<(ops node:$vec, node:$idx),
83                                (MipsVExtractZExt node:$vec, node:$idx, i8)>;
84def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx),
85                                (MipsVExtractZExt node:$vec, node:$idx, i16)>;
86def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx),
87                                (MipsVExtractZExt node:$vec, node:$idx, i32)>;
88def vextract_zext_i64 : PatFrag<(ops node:$vec, node:$idx),
89                                (MipsVExtractZExt node:$vec, node:$idx, i64)>;
90
91def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx),
92    (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>;
93def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx),
94    (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>;
95def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx),
96    (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>;
97def vinsert_v2i64 : PatFrag<(ops node:$vec, node:$val, node:$idx),
98    (v2i64 (vector_insert node:$vec, node:$val, node:$idx))>;
99
100def insve_v16i8 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
101    (v16i8 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
102def insve_v8i16 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
103    (v8i16 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
104def insve_v4i32 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
105    (v4i32 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
106def insve_v2i64 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
107    (v2i64 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
108
109class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> :
110  PatFrag<(ops node:$lhs, node:$rhs),
111          (ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>;
112
113// ISD::SETFALSE cannot occur
114def vfseteq_v4f32 : vfsetcc_type<v4i32, v4f32, SETEQ>;
115def vfseteq_v2f64 : vfsetcc_type<v2i64, v2f64, SETEQ>;
116def vfsetge_v4f32 : vfsetcc_type<v4i32, v4f32, SETGE>;
117def vfsetge_v2f64 : vfsetcc_type<v2i64, v2f64, SETGE>;
118def vfsetgt_v4f32 : vfsetcc_type<v4i32, v4f32, SETGT>;
119def vfsetgt_v2f64 : vfsetcc_type<v2i64, v2f64, SETGT>;
120def vfsetle_v4f32 : vfsetcc_type<v4i32, v4f32, SETLE>;
121def vfsetle_v2f64 : vfsetcc_type<v2i64, v2f64, SETLE>;
122def vfsetlt_v4f32 : vfsetcc_type<v4i32, v4f32, SETLT>;
123def vfsetlt_v2f64 : vfsetcc_type<v2i64, v2f64, SETLT>;
124def vfsetne_v4f32 : vfsetcc_type<v4i32, v4f32, SETNE>;
125def vfsetne_v2f64 : vfsetcc_type<v2i64, v2f64, SETNE>;
126def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>;
127def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>;
128def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>;
129def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>;
130def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>;
131def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>;
132def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>;
133def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>;
134def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>;
135def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>;
136def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>;
137def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>;
138def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>;
139def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>;
140def vfsetun_v4f32  : vfsetcc_type<v4i32, v4f32, SETUO>;
141def vfsetun_v2f64  : vfsetcc_type<v2i64, v2f64, SETUO>;
142def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>;
143def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>;
144def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>;
145def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>;
146def vfsetugt_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGT>;
147def vfsetugt_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGT>;
148def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>;
149def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>;
150def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>;
151def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>;
152def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>;
153def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>;
154// ISD::SETTRUE cannot occur
155// ISD::SETFALSE2 cannot occur
156// ISD::SETTRUE2 cannot occur
157
158class vsetcc_type<ValueType ResTy, CondCode CC> :
159  PatFrag<(ops node:$lhs, node:$rhs),
160          (ResTy (vsetcc node:$lhs, node:$rhs, CC))>;
161
162def vseteq_v16i8  : vsetcc_type<v16i8, SETEQ>;
163def vseteq_v8i16  : vsetcc_type<v8i16, SETEQ>;
164def vseteq_v4i32  : vsetcc_type<v4i32, SETEQ>;
165def vseteq_v2i64  : vsetcc_type<v2i64, SETEQ>;
166def vsetle_v16i8  : vsetcc_type<v16i8, SETLE>;
167def vsetle_v8i16  : vsetcc_type<v8i16, SETLE>;
168def vsetle_v4i32  : vsetcc_type<v4i32, SETLE>;
169def vsetle_v2i64  : vsetcc_type<v2i64, SETLE>;
170def vsetlt_v16i8  : vsetcc_type<v16i8, SETLT>;
171def vsetlt_v8i16  : vsetcc_type<v8i16, SETLT>;
172def vsetlt_v4i32  : vsetcc_type<v4i32, SETLT>;
173def vsetlt_v2i64  : vsetcc_type<v2i64, SETLT>;
174def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>;
175def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>;
176def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>;
177def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>;
178def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>;
179def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>;
180def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>;
181def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>;
182
183def vsplati8  : PatFrag<(ops node:$e0),
184                        (v16i8 (build_vector node:$e0, node:$e0,
185                                             node:$e0, node:$e0,
186                                             node:$e0, node:$e0,
187                                             node:$e0, node:$e0,
188                                             node:$e0, node:$e0,
189                                             node:$e0, node:$e0,
190                                             node:$e0, node:$e0,
191                                             node:$e0, node:$e0))>;
192def vsplati16 : PatFrag<(ops node:$e0),
193                        (v8i16 (build_vector node:$e0, node:$e0,
194                                             node:$e0, node:$e0,
195                                             node:$e0, node:$e0,
196                                             node:$e0, node:$e0))>;
197def vsplati32 : PatFrag<(ops node:$e0),
198                        (v4i32 (build_vector node:$e0, node:$e0,
199                                             node:$e0, node:$e0))>;
200
201// Any build_vector that is a constant splat with a value that equals 1
202def vsplat_imm_eq_1 : ComplexPattern<vAny, 0, "selectVSplatImmEq1">;
203
204def vsplati64 : PatFrag<(ops node:$e0),
205                        (v2i64 (build_vector node:$e0, node:$e0))>;
206
207def vsplati64_splat_d : PatFrag<(ops node:$e0),
208                                (v2i64 (bitconvert
209                                         (v4i32 (and
210                                           (v4i32 (build_vector node:$e0,
211                                                                node:$e0,
212                                                                node:$e0,
213                                                                node:$e0)),
214                                           (vsplat_imm_eq_1)))))>;
215
216def vsplatf32 : PatFrag<(ops node:$e0),
217                        (v4f32 (build_vector node:$e0, node:$e0,
218                                             node:$e0, node:$e0))>;
219def vsplatf64 : PatFrag<(ops node:$e0),
220                        (v2f64 (build_vector node:$e0, node:$e0))>;
221
222def vsplati8_elt  : PatFrag<(ops node:$v, node:$i),
223                            (MipsVSHF (vsplati8 node:$i), node:$v, node:$v)>;
224def vsplati16_elt : PatFrag<(ops node:$v, node:$i),
225                            (MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>;
226def vsplati32_elt : PatFrag<(ops node:$v, node:$i),
227                            (MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>;
228def vsplati64_elt : PatFrag<(ops node:$v, node:$i),
229                            (MipsVSHF (vsplati64_splat_d node:$i),
230                                      node:$v, node:$v)>;
231
232class SplatPatLeaf<Operand opclass, dag frag, code pred = [{}],
233                   SDNodeXForm xform = NOOP_SDNodeXForm>
234  : PatLeaf<frag, pred, xform> {
235  Operand OpClass = opclass;
236}
237
238class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn,
239                          list<SDNode> roots = [],
240                          list<SDNodeProperty> props = []> :
241  ComplexPattern<ty, numops, fn, roots, props> {
242  Operand OpClass = opclass;
243}
244
245def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1,
246                                         "selectVSplatUimm3",
247                                         [build_vector, bitconvert]>;
248
249def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1,
250                                         "selectVSplatUimm4",
251                                         [build_vector, bitconvert]>;
252
253def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1,
254                                         "selectVSplatUimm5",
255                                         [build_vector, bitconvert]>;
256
257def vsplati8_uimm8 : SplatComplexPattern<vsplat_uimm8, v16i8, 1,
258                                         "selectVSplatUimm8",
259                                         [build_vector, bitconvert]>;
260
261def vsplati8_simm5 : SplatComplexPattern<vsplat_simm5, v16i8, 1,
262                                         "selectVSplatSimm5",
263                                         [build_vector, bitconvert]>;
264
265def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1,
266                                          "selectVSplatUimm3",
267                                          [build_vector, bitconvert]>;
268
269def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1,
270                                          "selectVSplatUimm4",
271                                          [build_vector, bitconvert]>;
272
273def vsplati16_uimm5 : SplatComplexPattern<vsplat_uimm5, v8i16, 1,
274                                          "selectVSplatUimm5",
275                                          [build_vector, bitconvert]>;
276
277def vsplati16_simm5 : SplatComplexPattern<vsplat_simm5, v8i16, 1,
278                                          "selectVSplatSimm5",
279                                          [build_vector, bitconvert]>;
280
281def vsplati32_uimm2 : SplatComplexPattern<vsplat_uimm2, v4i32, 1,
282                                          "selectVSplatUimm2",
283                                          [build_vector, bitconvert]>;
284
285def vsplati32_uimm5 : SplatComplexPattern<vsplat_uimm5, v4i32, 1,
286                                          "selectVSplatUimm5",
287                                          [build_vector, bitconvert]>;
288
289def vsplati32_simm5 : SplatComplexPattern<vsplat_simm5, v4i32, 1,
290                                          "selectVSplatSimm5",
291                                          [build_vector, bitconvert]>;
292
293def vsplati64_uimm1 : SplatComplexPattern<vsplat_uimm1, v2i64, 1,
294                                          "selectVSplatUimm1",
295                                          [build_vector, bitconvert]>;
296
297def vsplati64_uimm5 : SplatComplexPattern<vsplat_uimm5, v2i64, 1,
298                                          "selectVSplatUimm5",
299                                          [build_vector, bitconvert]>;
300
301def vsplati64_uimm6 : SplatComplexPattern<vsplat_uimm6, v2i64, 1,
302                                          "selectVSplatUimm6",
303                                          [build_vector, bitconvert]>;
304
305def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1,
306                                          "selectVSplatSimm5",
307                                          [build_vector, bitconvert]>;
308
309// Any build_vector that is a constant splat with a value that is an exact
310// power of 2
311def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2",
312                                      [build_vector, bitconvert]>;
313
314// Any build_vector that is a constant splat with a value that is the bitwise
315// inverse of an exact power of 2
316def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2",
317                                          [build_vector, bitconvert]>;
318
319// Any build_vector that is a constant splat with only a consecutive sequence
320// of left-most bits set.
321def vsplat_maskl_bits_uimm3
322    : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskL",
323                          [build_vector, bitconvert]>;
324def vsplat_maskl_bits_uimm4
325    : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskL",
326                          [build_vector, bitconvert]>;
327def vsplat_maskl_bits_uimm5
328    : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskL",
329                          [build_vector, bitconvert]>;
330def vsplat_maskl_bits_uimm6
331    : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskL",
332                          [build_vector, bitconvert]>;
333
334// Any build_vector that is a constant splat with only a consecutive sequence
335// of right-most bits set.
336def vsplat_maskr_bits_uimm3
337    : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskR",
338                          [build_vector, bitconvert]>;
339def vsplat_maskr_bits_uimm4
340    : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskR",
341                          [build_vector, bitconvert]>;
342def vsplat_maskr_bits_uimm5
343    : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskR",
344                          [build_vector, bitconvert]>;
345def vsplat_maskr_bits_uimm6
346    : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskR",
347                          [build_vector, bitconvert]>;
348
349
350def vbclr_b : PatFrag<(ops node:$ws, node:$wt),
351                      (and node:$ws, (vnot (shl (vsplat_imm_eq_1), node:$wt)))>;
352def vbclr_h : PatFrag<(ops node:$ws, node:$wt),
353                      (and node:$ws, (vnot (shl (vsplat_imm_eq_1), node:$wt)))>;
354def vbclr_w : PatFrag<(ops node:$ws, node:$wt),
355                      (and node:$ws, (vnot (shl (vsplat_imm_eq_1), node:$wt)))>;
356def vbclr_d : PatFrag<(ops node:$ws, node:$wt),
357                      (and node:$ws, (vnot (shl (v2i64 (vsplat_imm_eq_1)),
358                                               node:$wt)))>;
359
360def vbneg_b : PatFrag<(ops node:$ws, node:$wt),
361                      (xor node:$ws, (shl (vsplat_imm_eq_1), node:$wt))>;
362def vbneg_h : PatFrag<(ops node:$ws, node:$wt),
363                      (xor node:$ws, (shl (vsplat_imm_eq_1), node:$wt))>;
364def vbneg_w : PatFrag<(ops node:$ws, node:$wt),
365                      (xor node:$ws, (shl (vsplat_imm_eq_1), node:$wt))>;
366def vbneg_d : PatFrag<(ops node:$ws, node:$wt),
367                      (xor node:$ws, (shl (v2i64 (vsplat_imm_eq_1)),
368                                          node:$wt))>;
369
370def vbset_b : PatFrag<(ops node:$ws, node:$wt),
371                      (or node:$ws, (shl (vsplat_imm_eq_1), node:$wt))>;
372def vbset_h : PatFrag<(ops node:$ws, node:$wt),
373                      (or node:$ws, (shl (vsplat_imm_eq_1), node:$wt))>;
374def vbset_w : PatFrag<(ops node:$ws, node:$wt),
375                      (or node:$ws, (shl (vsplat_imm_eq_1), node:$wt))>;
376def vbset_d : PatFrag<(ops node:$ws, node:$wt),
377                      (or node:$ws, (shl (v2i64 (vsplat_imm_eq_1)),
378                                         node:$wt))>;
379
380def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt),
381                     (add node:$wd, (mul node:$ws, node:$wt))>;
382
383def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt),
384                     (sub node:$wd, (mul node:$ws, node:$wt))>;
385
386def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt),
387                        (fmul node:$ws, (fexp2 node:$wt))>;
388
389// Instruction encoding.
390class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>;
391class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>;
392class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>;
393class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>;
394
395class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>;
396class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>;
397class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>;
398class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>;
399
400class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>;
401class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>;
402class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>;
403class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>;
404
405class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>;
406class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>;
407class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>;
408class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>;
409
410class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>;
411class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>;
412class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>;
413class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>;
414
415class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>;
416class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>;
417class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>;
418class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>;
419
420class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>;
421
422class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>;
423
424class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>;
425class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>;
426class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>;
427class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>;
428
429class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>;
430class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>;
431class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>;
432class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>;
433
434class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>;
435class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>;
436class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>;
437class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>;
438
439class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>;
440class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>;
441class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>;
442class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>;
443
444class AVER_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010000>;
445class AVER_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010000>;
446class AVER_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010000>;
447class AVER_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010000>;
448
449class AVER_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010000>;
450class AVER_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010000>;
451class AVER_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010000>;
452class AVER_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010000>;
453
454class BCLR_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001101>;
455class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>;
456class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>;
457class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>;
458
459class BCLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001001>;
460class BCLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001001>;
461class BCLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001001>;
462class BCLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001001>;
463
464class BINSL_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001101>;
465class BINSL_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001101>;
466class BINSL_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001101>;
467class BINSL_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001101>;
468
469class BINSLI_B_ENC : MSA_BIT_B_FMT<0b110, 0b001001>;
470class BINSLI_H_ENC : MSA_BIT_H_FMT<0b110, 0b001001>;
471class BINSLI_W_ENC : MSA_BIT_W_FMT<0b110, 0b001001>;
472class BINSLI_D_ENC : MSA_BIT_D_FMT<0b110, 0b001001>;
473
474class BINSR_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001101>;
475class BINSR_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001101>;
476class BINSR_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001101>;
477class BINSR_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001101>;
478
479class BINSRI_B_ENC : MSA_BIT_B_FMT<0b111, 0b001001>;
480class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>;
481class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>;
482class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>;
483
484class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>;
485
486class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>;
487
488class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>;
489
490class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>;
491
492class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>;
493class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>;
494class BNEG_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001101>;
495class BNEG_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001101>;
496
497class BNEGI_B_ENC : MSA_BIT_B_FMT<0b101, 0b001001>;
498class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>;
499class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>;
500class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>;
501
502class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>;
503class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>;
504class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>;
505class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>;
506
507class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01111>;
508
509class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>;
510
511class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>;
512
513class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>;
514class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>;
515class BSET_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001101>;
516class BSET_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001101>;
517
518class BSETI_B_ENC : MSA_BIT_B_FMT<0b100, 0b001001>;
519class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>;
520class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>;
521class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>;
522
523class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>;
524class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>;
525class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>;
526class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>;
527
528class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>;
529
530class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>;
531class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>;
532class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>;
533class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>;
534
535class CEQI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000111>;
536class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>;
537class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>;
538class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>;
539
540class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>;
541
542class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>;
543class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>;
544class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>;
545class CLE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001111>;
546
547class CLE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001111>;
548class CLE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001111>;
549class CLE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001111>;
550class CLE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001111>;
551
552class CLEI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000111>;
553class CLEI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000111>;
554class CLEI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000111>;
555class CLEI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000111>;
556
557class CLEI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000111>;
558class CLEI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000111>;
559class CLEI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000111>;
560class CLEI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000111>;
561
562class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>;
563class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>;
564class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>;
565class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>;
566
567class CLT_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001111>;
568class CLT_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001111>;
569class CLT_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001111>;
570class CLT_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001111>;
571
572class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>;
573class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>;
574class CLTI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000111>;
575class CLTI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000111>;
576
577class CLTI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000111>;
578class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>;
579class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>;
580class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>;
581
582class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>;
583class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>;
584class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>;
585class COPY_S_D_ENC : MSA_ELM_COPY_D_FMT<0b0010, 0b011001>;
586
587class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>;
588class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>;
589class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>;
590
591class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>;
592
593class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>;
594class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>;
595class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>;
596class DIV_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010010>;
597
598class DIV_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010010>;
599class DIV_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010010>;
600class DIV_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010010>;
601class DIV_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010010>;
602
603class DOTP_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010011>;
604class DOTP_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010011>;
605class DOTP_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010011>;
606
607class DOTP_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010011>;
608class DOTP_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010011>;
609class DOTP_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010011>;
610
611class DPADD_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010011>;
612class DPADD_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010011>;
613class DPADD_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010011>;
614
615class DPADD_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010011>;
616class DPADD_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010011>;
617class DPADD_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010011>;
618
619class DPSUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010011>;
620class DPSUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010011>;
621class DPSUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010011>;
622
623class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>;
624class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>;
625class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>;
626
627class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>;
628class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>;
629
630class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>;
631class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>;
632
633class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>;
634class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>;
635
636class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>;
637class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>;
638
639class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>;
640class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>;
641
642class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>;
643class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>;
644
645class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>;
646class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>;
647
648class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>;
649class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>;
650
651class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>;
652class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>;
653
654class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>;
655class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>;
656
657class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>;
658class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>;
659
660class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>;
661class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>;
662
663class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>;
664class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>;
665
666class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>;
667class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>;
668
669class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>;
670class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>;
671
672class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>;
673class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>;
674
675class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>;
676class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>;
677
678class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>;
679class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>;
680
681class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>;
682class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>;
683
684class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>;
685class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>;
686
687class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>;
688class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>;
689
690class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>;
691class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>;
692
693class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>;
694class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>;
695class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>;
696class FILL_D_ENC : MSA_2R_FILL_D_FMT<0b11000000, 0b11, 0b011110>;
697
698class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>;
699class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>;
700
701class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>;
702class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>;
703
704class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>;
705class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>;
706
707class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>;
708class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>;
709
710class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>;
711class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>;
712
713class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>;
714class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>;
715
716class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>;
717class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>;
718
719class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>;
720class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>;
721
722class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>;
723class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>;
724
725class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>;
726class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>;
727
728class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>;
729class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>;
730
731class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>;
732class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>;
733
734class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>;
735class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>;
736
737class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>;
738class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>;
739
740class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>;
741class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>;
742
743class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>;
744class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>;
745
746class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>;
747class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>;
748
749class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>;
750class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>;
751
752class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>;
753class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>;
754
755class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>;
756class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>;
757
758class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>;
759class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>;
760
761class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>;
762class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>;
763
764class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>;
765class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>;
766
767class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>;
768class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>;
769
770class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>;
771class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>;
772
773class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>;
774class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>;
775
776class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>;
777class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>;
778
779class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>;
780class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>;
781
782class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>;
783class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>;
784
785class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>;
786class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>;
787class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>;
788
789class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>;
790class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>;
791class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>;
792
793class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>;
794class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>;
795class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>;
796
797class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>;
798class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>;
799class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>;
800
801class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>;
802class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>;
803class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>;
804class ILVEV_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010100>;
805
806class ILVL_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010100>;
807class ILVL_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010100>;
808class ILVL_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010100>;
809class ILVL_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010100>;
810
811class ILVOD_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010100>;
812class ILVOD_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010100>;
813class ILVOD_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010100>;
814class ILVOD_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010100>;
815
816class ILVR_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010100>;
817class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>;
818class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>;
819class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>;
820
821class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>;
822class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>;
823class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>;
824class INSERT_D_ENC : MSA_ELM_INSERT_D_FMT<0b0100, 0b011001>;
825
826class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>;
827class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>;
828class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>;
829class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>;
830
831class LD_B_ENC   : MSA_MI10_FMT<0b00, 0b1000>;
832class LD_H_ENC   : MSA_MI10_FMT<0b01, 0b1000>;
833class LD_W_ENC   : MSA_MI10_FMT<0b10, 0b1000>;
834class LD_D_ENC   : MSA_MI10_FMT<0b11, 0b1000>;
835
836class LDI_B_ENC  : MSA_I10_FMT<0b110, 0b00, 0b000111>;
837class LDI_H_ENC  : MSA_I10_FMT<0b110, 0b01, 0b000111>;
838class LDI_W_ENC  : MSA_I10_FMT<0b110, 0b10, 0b000111>;
839class LDI_D_ENC  : MSA_I10_FMT<0b110, 0b11, 0b000111>;
840
841class LSA_ENC : SPECIAL_LSA_FMT<0b000101>;
842class DLSA_ENC : SPECIAL_DLSA_FMT<0b010101>;
843
844class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>;
845class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>;
846
847class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>;
848class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>;
849
850class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>;
851class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>;
852class MADDV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010010>;
853class MADDV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010010>;
854
855class MAX_A_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001110>;
856class MAX_A_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001110>;
857class MAX_A_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001110>;
858class MAX_A_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001110>;
859
860class MAX_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001110>;
861class MAX_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001110>;
862class MAX_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001110>;
863class MAX_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001110>;
864
865class MAX_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001110>;
866class MAX_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001110>;
867class MAX_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001110>;
868class MAX_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001110>;
869
870class MAXI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000110>;
871class MAXI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000110>;
872class MAXI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000110>;
873class MAXI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000110>;
874
875class MAXI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000110>;
876class MAXI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000110>;
877class MAXI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000110>;
878class MAXI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000110>;
879
880class MIN_A_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001110>;
881class MIN_A_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001110>;
882class MIN_A_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001110>;
883class MIN_A_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001110>;
884
885class MIN_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001110>;
886class MIN_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001110>;
887class MIN_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001110>;
888class MIN_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001110>;
889
890class MIN_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001110>;
891class MIN_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001110>;
892class MIN_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001110>;
893class MIN_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001110>;
894
895class MINI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000110>;
896class MINI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000110>;
897class MINI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000110>;
898class MINI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000110>;
899
900class MINI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000110>;
901class MINI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000110>;
902class MINI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000110>;
903class MINI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000110>;
904
905class MOD_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010010>;
906class MOD_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010010>;
907class MOD_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010010>;
908class MOD_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010010>;
909
910class MOD_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010010>;
911class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>;
912class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>;
913class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>;
914
915class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>;
916
917class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>;
918class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>;
919
920class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>;
921class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>;
922
923class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>;
924class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>;
925class MSUBV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010010>;
926class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>;
927
928class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>;
929class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>;
930
931class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>;
932class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>;
933
934class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>;
935class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>;
936class MULV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010010>;
937class MULV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010010>;
938
939class NLOC_B_ENC : MSA_2R_FMT<0b11000010, 0b00, 0b011110>;
940class NLOC_H_ENC : MSA_2R_FMT<0b11000010, 0b01, 0b011110>;
941class NLOC_W_ENC : MSA_2R_FMT<0b11000010, 0b10, 0b011110>;
942class NLOC_D_ENC : MSA_2R_FMT<0b11000010, 0b11, 0b011110>;
943
944class NLZC_B_ENC : MSA_2R_FMT<0b11000011, 0b00, 0b011110>;
945class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>;
946class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>;
947class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>;
948
949class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>;
950
951class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>;
952
953class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>;
954
955class ORI_B_ENC  : MSA_I8_FMT<0b01, 0b000000>;
956
957class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>;
958class PCKEV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010100>;
959class PCKEV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010100>;
960class PCKEV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010100>;
961
962class PCKOD_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010100>;
963class PCKOD_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010100>;
964class PCKOD_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010100>;
965class PCKOD_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010100>;
966
967class PCNT_B_ENC : MSA_2R_FMT<0b11000001, 0b00, 0b011110>;
968class PCNT_H_ENC : MSA_2R_FMT<0b11000001, 0b01, 0b011110>;
969class PCNT_W_ENC : MSA_2R_FMT<0b11000001, 0b10, 0b011110>;
970class PCNT_D_ENC : MSA_2R_FMT<0b11000001, 0b11, 0b011110>;
971
972class SAT_S_B_ENC : MSA_BIT_B_FMT<0b000, 0b001010>;
973class SAT_S_H_ENC : MSA_BIT_H_FMT<0b000, 0b001010>;
974class SAT_S_W_ENC : MSA_BIT_W_FMT<0b000, 0b001010>;
975class SAT_S_D_ENC : MSA_BIT_D_FMT<0b000, 0b001010>;
976
977class SAT_U_B_ENC : MSA_BIT_B_FMT<0b001, 0b001010>;
978class SAT_U_H_ENC : MSA_BIT_H_FMT<0b001, 0b001010>;
979class SAT_U_W_ENC : MSA_BIT_W_FMT<0b001, 0b001010>;
980class SAT_U_D_ENC : MSA_BIT_D_FMT<0b001, 0b001010>;
981
982class SHF_B_ENC  : MSA_I8_FMT<0b00, 0b000010>;
983class SHF_H_ENC  : MSA_I8_FMT<0b01, 0b000010>;
984class SHF_W_ENC  : MSA_I8_FMT<0b10, 0b000010>;
985
986class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>;
987class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>;
988class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>;
989class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>;
990
991class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>;
992class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>;
993class SLDI_W_ENC : MSA_ELM_W_FMT<0b0000, 0b011001>;
994class SLDI_D_ENC : MSA_ELM_D_FMT<0b0000, 0b011001>;
995
996class SLL_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001101>;
997class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>;
998class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>;
999class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>;
1000
1001class SLLI_B_ENC : MSA_BIT_B_FMT<0b000, 0b001001>;
1002class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>;
1003class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>;
1004class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>;
1005
1006class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>;
1007class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>;
1008class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>;
1009class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>;
1010
1011class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>;
1012class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>;
1013class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>;
1014class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>;
1015
1016class SRA_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001101>;
1017class SRA_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001101>;
1018class SRA_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001101>;
1019class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>;
1020
1021class SRAI_B_ENC : MSA_BIT_B_FMT<0b001, 0b001001>;
1022class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>;
1023class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>;
1024class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>;
1025
1026class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>;
1027class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>;
1028class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>;
1029class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>;
1030
1031class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>;
1032class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>;
1033class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>;
1034class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>;
1035
1036class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>;
1037class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>;
1038class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>;
1039class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>;
1040
1041class SRLI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001001>;
1042class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>;
1043class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>;
1044class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>;
1045
1046class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>;
1047class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>;
1048class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>;
1049class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>;
1050
1051class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>;
1052class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>;
1053class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>;
1054class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>;
1055
1056class ST_B_ENC   : MSA_MI10_FMT<0b00, 0b1001>;
1057class ST_H_ENC   : MSA_MI10_FMT<0b01, 0b1001>;
1058class ST_W_ENC   : MSA_MI10_FMT<0b10, 0b1001>;
1059class ST_D_ENC   : MSA_MI10_FMT<0b11, 0b1001>;
1060
1061class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>;
1062class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>;
1063class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>;
1064class SUBS_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010001>;
1065
1066class SUBS_U_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010001>;
1067class SUBS_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010001>;
1068class SUBS_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010001>;
1069class SUBS_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010001>;
1070
1071class SUBSUS_U_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010001>;
1072class SUBSUS_U_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010001>;
1073class SUBSUS_U_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010001>;
1074class SUBSUS_U_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010001>;
1075
1076class SUBSUU_S_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010001>;
1077class SUBSUU_S_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010001>;
1078class SUBSUU_S_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010001>;
1079class SUBSUU_S_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010001>;
1080
1081class SUBV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001110>;
1082class SUBV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001110>;
1083class SUBV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001110>;
1084class SUBV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001110>;
1085
1086class SUBVI_B_ENC : MSA_I5_FMT<0b001, 0b00, 0b000110>;
1087class SUBVI_H_ENC : MSA_I5_FMT<0b001, 0b01, 0b000110>;
1088class SUBVI_W_ENC : MSA_I5_FMT<0b001, 0b10, 0b000110>;
1089class SUBVI_D_ENC : MSA_I5_FMT<0b001, 0b11, 0b000110>;
1090
1091class VSHF_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010101>;
1092class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>;
1093class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>;
1094class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>;
1095
1096class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>;
1097
1098class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>;
1099
1100// Instruction desc.
1101class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1102                          ComplexPattern Imm, RegisterOperand ROWD,
1103                          RegisterOperand ROWS = ROWD,
1104                          InstrItinClass itin = NoItinerary> {
1105  dag OutOperandList = (outs ROWD:$wd);
1106  dag InOperandList = (ins ROWS:$ws, vsplat_uimm3:$m);
1107  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1108  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1109  InstrItinClass Itinerary = itin;
1110}
1111
1112class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1113                          ComplexPattern Imm, RegisterOperand ROWD,
1114                          RegisterOperand ROWS = ROWD,
1115                          InstrItinClass itin = NoItinerary> {
1116  dag OutOperandList = (outs ROWD:$wd);
1117  dag InOperandList = (ins ROWS:$ws, vsplat_uimm4:$m);
1118  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1119  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1120  InstrItinClass Itinerary = itin;
1121}
1122
1123class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1124                          ComplexPattern Imm, RegisterOperand ROWD,
1125                          RegisterOperand ROWS = ROWD,
1126                          InstrItinClass itin = NoItinerary> {
1127  dag OutOperandList = (outs ROWD:$wd);
1128  dag InOperandList = (ins ROWS:$ws, vsplat_uimm5:$m);
1129  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1130  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1131  InstrItinClass Itinerary = itin;
1132}
1133
1134class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1135                          ComplexPattern Imm, RegisterOperand ROWD,
1136                          RegisterOperand ROWS = ROWD,
1137                          InstrItinClass itin = NoItinerary> {
1138  dag OutOperandList = (outs ROWD:$wd);
1139  dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m);
1140  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1141  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1142  InstrItinClass Itinerary = itin;
1143}
1144
1145class MSA_BIT_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1146                          Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
1147                          RegisterOperand ROWS = ROWD,
1148                          InstrItinClass itin = NoItinerary> {
1149  dag OutOperandList = (outs ROWD:$wd);
1150  dag InOperandList = (ins ROWS:$ws, ImmOp:$m);
1151  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1152  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1153  InstrItinClass Itinerary = itin;
1154}
1155
1156class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty,
1157                               SplatComplexPattern Mask, RegisterOperand ROWD,
1158                               RegisterOperand ROWS = ROWD,
1159                               InstrItinClass itin = NoItinerary> {
1160  dag OutOperandList = (outs ROWD:$wd);
1161  dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, Mask.OpClass:$m);
1162  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1163  // Note that binsxi and vselect treat the condition operand the opposite
1164  // way to each other.
1165  //   (vselect cond, if_set, if_clear)
1166  //   (BSEL_V cond, if_clear, if_set)
1167  list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$ws),
1168                                               ROWS:$wd_in))];
1169  InstrItinClass Itinerary = itin;
1170  string Constraints = "$wd = $wd_in";
1171}
1172
1173class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty,
1174                               SplatComplexPattern ImmOp, RegisterOperand ROWD,
1175                               RegisterOperand ROWS = ROWD,
1176                               InstrItinClass itin = NoItinerary> :
1177  MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>;
1178
1179class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty,
1180                               SplatComplexPattern ImmOp, RegisterOperand ROWD,
1181                               RegisterOperand ROWS = ROWD,
1182                               InstrItinClass itin = NoItinerary> :
1183  MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>;
1184
1185class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1186                              SplatComplexPattern SplatImm,
1187                              RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1188                              InstrItinClass itin = NoItinerary> {
1189  dag OutOperandList = (outs ROWD:$wd);
1190  dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m);
1191  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1192  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))];
1193  InstrItinClass Itinerary = itin;
1194}
1195
1196class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1197                         ValueType VecTy, Operand ImmOp, ImmLeaf Imm,
1198                         RegisterOperand ROD, RegisterOperand ROWS,
1199                         InstrItinClass itin = NoItinerary> {
1200  dag OutOperandList = (outs ROD:$rd);
1201  dag InOperandList = (ins ROWS:$ws, ImmOp:$n);
1202  string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]");
1203  list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), Imm:$n))];
1204  InstrItinClass Itinerary = itin;
1205}
1206
1207class MSA_ELM_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1208                            RegisterOperand ROWD, RegisterOperand ROWS,
1209                            Operand ImmOp, ImmLeaf Imm,
1210                            InstrItinClass itin = NoItinerary> {
1211  dag OutOperandList = (outs ROWD:$wd);
1212  dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ImmOp:$n);
1213  string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1214  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1215                                              Imm:$n))];
1216  string Constraints = "$wd = $wd_in";
1217  InstrItinClass Itinerary = itin;
1218}
1219
1220class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy,
1221                           Operand ImmOp, ImmLeaf Imm, RegisterClass RCD,
1222                           RegisterClass RCWS> :
1223      MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, ImmOp:$n),
1224                [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), Imm:$n))]> {
1225  bit usesCustomInserter = 1;
1226  bit hasNoSchedulingInfo = 1;
1227}
1228
1229class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1230                       SplatComplexPattern SplatImm, RegisterOperand ROWD,
1231                       RegisterOperand ROWS = ROWD,
1232                       InstrItinClass itin = NoItinerary> {
1233  dag OutOperandList = (outs ROWD:$wd);
1234  dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm);
1235  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm");
1236  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))];
1237  InstrItinClass Itinerary = itin;
1238}
1239
1240class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1241                       SplatComplexPattern SplatImm, RegisterOperand ROWD,
1242                       RegisterOperand ROWS = ROWD,
1243                       InstrItinClass itin = NoItinerary> {
1244  dag OutOperandList = (outs ROWD:$wd);
1245  dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8);
1246  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1247  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))];
1248  InstrItinClass Itinerary = itin;
1249}
1250
1251class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1252                           RegisterOperand ROWS = ROWD,
1253                           InstrItinClass itin = NoItinerary> {
1254  dag OutOperandList = (outs ROWD:$wd);
1255  dag InOperandList = (ins ROWS:$ws, uimm8:$u8);
1256  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1257  list<dag> Pattern = [(set ROWD:$wd, (MipsSHF timmZExt8:$u8, ROWS:$ws))];
1258  InstrItinClass Itinerary = itin;
1259}
1260
1261class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1262                            InstrItinClass itin = NoItinerary> {
1263  dag OutOperandList = (outs ROWD:$wd);
1264  dag InOperandList = (ins vsplat_simm10:$s10);
1265  string AsmString = !strconcat(instr_asm, "\t$wd, $s10");
1266  // LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp
1267  list<dag> Pattern = [];
1268  bit hasSideEffects = 0;
1269  bit isReMaterializable = 1;
1270  InstrItinClass Itinerary = itin;
1271}
1272
1273class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1274                       RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1275                       InstrItinClass itin = NoItinerary> {
1276  dag OutOperandList = (outs ROWD:$wd);
1277  dag InOperandList = (ins ROWS:$ws);
1278  string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1279  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1280  InstrItinClass Itinerary = itin;
1281}
1282
1283class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT,
1284                            SDPatternOperator OpNode, RegisterOperand ROWD,
1285                            RegisterOperand ROS = ROWD,
1286                            InstrItinClass itin = NoItinerary> {
1287  dag OutOperandList = (outs ROWD:$wd);
1288  dag InOperandList = (ins ROS:$rs);
1289  string AsmString = !strconcat(instr_asm, "\t$wd, $rs");
1290  list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))];
1291  InstrItinClass Itinerary = itin;
1292}
1293
1294class MSA_2R_FILL_PSEUDO_BASE<SDPatternOperator OpNode,
1295                              RegisterClass RCWD, RegisterClass RCWS> :
1296      MSAPseudo<(outs RCWD:$wd), (ins RCWS:$fs),
1297                [(set RCWD:$wd, (OpNode RCWS:$fs))]> {
1298  let usesCustomInserter = 1;
1299}
1300
1301class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1302                        RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1303                        InstrItinClass itin = NoItinerary> {
1304  dag OutOperandList = (outs ROWD:$wd);
1305  dag InOperandList = (ins ROWS:$ws);
1306  string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1307  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1308  InstrItinClass Itinerary = itin;
1309}
1310
1311class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1312                       RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1313                       RegisterOperand ROWT = ROWD,
1314                       InstrItinClass itin = NoItinerary> {
1315  dag OutOperandList = (outs ROWD:$wd);
1316  dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1317  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1318  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1319  InstrItinClass Itinerary = itin;
1320}
1321
1322class MSA_3R_BINSX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1323                             RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1324                             RegisterOperand ROWT = ROWD,
1325                             InstrItinClass itin = NoItinerary> {
1326  dag OutOperandList = (outs ROWD:$wd);
1327  dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1328  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1329  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1330                                              ROWT:$wt))];
1331  string Constraints = "$wd = $wd_in";
1332  InstrItinClass Itinerary = itin;
1333}
1334
1335class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1336                             RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1337                             InstrItinClass itin = NoItinerary> {
1338  dag OutOperandList = (outs ROWD:$wd);
1339  dag InOperandList = (ins ROWS:$ws, GPR32Opnd:$rt);
1340  string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1341  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32Opnd:$rt))];
1342  InstrItinClass Itinerary = itin;
1343}
1344
1345class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1346                            RegisterOperand ROWS = ROWD,
1347                            RegisterOperand ROWT = ROWD,
1348                            InstrItinClass itin = NoItinerary> {
1349  dag OutOperandList = (outs ROWD:$wd);
1350  dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1351  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1352  list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws,
1353                                                ROWT:$wt))];
1354  string Constraints = "$wd = $wd_in";
1355  InstrItinClass Itinerary = itin;
1356}
1357
1358class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1359                           RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1360                           InstrItinClass itin = NoItinerary> {
1361  dag OutOperandList = (outs ROWD:$wd);
1362  dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, GPR32Opnd:$rt);
1363  string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1364  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1365                                              GPR32Opnd:$rt))];
1366  InstrItinClass Itinerary = itin;
1367  string Constraints = "$wd = $wd_in";
1368}
1369
1370class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1371                          RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1372                          RegisterOperand ROWT = ROWD,
1373                          InstrItinClass itin = NoItinerary> {
1374  dag OutOperandList = (outs ROWD:$wd);
1375  dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1376  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1377  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1378                                              ROWT:$wt))];
1379  InstrItinClass Itinerary = itin;
1380  string Constraints = "$wd = $wd_in";
1381}
1382
1383class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1384                        RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1385                        RegisterOperand ROWT = ROWD,
1386                        InstrItinClass itin = NoItinerary> :
1387  MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1388
1389class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1390                            RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1391                            RegisterOperand ROWT = ROWD,
1392                            InstrItinClass itin = NoItinerary> :
1393  MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1394
1395class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> {
1396  dag OutOperandList = (outs);
1397  dag InOperandList = (ins ROWD:$wt, brtarget:$offset);
1398  string AsmString = !strconcat(instr_asm, "\t$wt, $offset");
1399  list<dag> Pattern = [];
1400  InstrItinClass Itinerary = NoItinerary;
1401  bit isBranch = 1;
1402  bit isTerminator = 1;
1403  bit hasDelaySlot = 1;
1404  list<Register> Defs = [AT];
1405}
1406
1407class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1408                           Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
1409                           RegisterOperand ROS,
1410                           InstrItinClass itin = NoItinerary> {
1411  dag OutOperandList = (outs ROWD:$wd);
1412  dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, ImmOp:$n);
1413  string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs");
1414  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROS:$rs, Imm:$n))];
1415  InstrItinClass Itinerary = itin;
1416  string Constraints = "$wd = $wd_in";
1417}
1418
1419class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
1420                             Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
1421                             RegisterOperand ROFS> :
1422      MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ImmOp:$n, ROFS:$fs),
1423                [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, Imm:$n))]> {
1424  bit usesCustomInserter = 1;
1425  string Constraints = "$wd = $wd_in";
1426}
1427
1428class MSA_INSERT_VIDX_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
1429                                  RegisterOperand ROWD, RegisterOperand ROFS,
1430                                  RegisterOperand ROIdx> :
1431      MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ROIdx:$n, ROFS:$fs),
1432                [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs,
1433                                        ROIdx:$n))]> {
1434  bit usesCustomInserter = 1;
1435  bit hasNoSchedulingInfo = 1;
1436  string Constraints = "$wd = $wd_in";
1437}
1438
1439class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1440                          Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
1441                          RegisterOperand ROWS = ROWD,
1442                          InstrItinClass itin = NoItinerary> {
1443  dag OutOperandList = (outs ROWD:$wd);
1444  dag InOperandList = (ins ROWD:$wd_in, ImmOp:$n, ROWS:$ws, uimmz:$n2);
1445  string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[$n2]");
1446  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
1447                                              Imm:$n,
1448                                              ROWS:$ws,
1449                                              immz:$n2))];
1450  InstrItinClass Itinerary = itin;
1451  string Constraints = "$wd = $wd_in";
1452}
1453
1454class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1455                        RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1456                        RegisterOperand ROWT = ROWD,
1457                        InstrItinClass itin = NoItinerary> {
1458  dag OutOperandList = (outs ROWD:$wd);
1459  dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1460  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1461  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1462  InstrItinClass Itinerary = itin;
1463}
1464
1465class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm,
1466                              RegisterOperand ROWD,
1467                              RegisterOperand ROWS = ROWD,
1468                              InstrItinClass itin = NoItinerary> {
1469  dag OutOperandList = (outs ROWD:$wd);
1470  dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n);
1471  string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1472  list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws,
1473                                                ROWS:$ws))];
1474  InstrItinClass Itinerary = itin;
1475}
1476
1477class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD,
1478                          RegisterOperand ROWS = ROWD,
1479                          RegisterOperand ROWT = ROWD> :
1480      MSAPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt),
1481                [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>;
1482
1483class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>,
1484                     IsCommutable;
1485class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>,
1486                     IsCommutable;
1487class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>,
1488                     IsCommutable;
1489class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>,
1490                     IsCommutable;
1491
1492class ADDS_A_B_DESC : MSA_3R_DESC_BASE<"adds_a.b", int_mips_adds_a_b,
1493                                       MSA128BOpnd>, IsCommutable;
1494class ADDS_A_H_DESC : MSA_3R_DESC_BASE<"adds_a.h", int_mips_adds_a_h,
1495                                       MSA128HOpnd>, IsCommutable;
1496class ADDS_A_W_DESC : MSA_3R_DESC_BASE<"adds_a.w", int_mips_adds_a_w,
1497                                       MSA128WOpnd>, IsCommutable;
1498class ADDS_A_D_DESC : MSA_3R_DESC_BASE<"adds_a.d", int_mips_adds_a_d,
1499                                       MSA128DOpnd>, IsCommutable;
1500
1501class ADDS_S_B_DESC : MSA_3R_DESC_BASE<"adds_s.b", int_mips_adds_s_b,
1502                                       MSA128BOpnd>, IsCommutable;
1503class ADDS_S_H_DESC : MSA_3R_DESC_BASE<"adds_s.h", int_mips_adds_s_h,
1504                                       MSA128HOpnd>, IsCommutable;
1505class ADDS_S_W_DESC : MSA_3R_DESC_BASE<"adds_s.w", int_mips_adds_s_w,
1506                                       MSA128WOpnd>, IsCommutable;
1507class ADDS_S_D_DESC : MSA_3R_DESC_BASE<"adds_s.d", int_mips_adds_s_d,
1508                                       MSA128DOpnd>, IsCommutable;
1509
1510class ADDS_U_B_DESC : MSA_3R_DESC_BASE<"adds_u.b", int_mips_adds_u_b,
1511                                       MSA128BOpnd>, IsCommutable;
1512class ADDS_U_H_DESC : MSA_3R_DESC_BASE<"adds_u.h", int_mips_adds_u_h,
1513                                       MSA128HOpnd>, IsCommutable;
1514class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w,
1515                                       MSA128WOpnd>, IsCommutable;
1516class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d,
1517                                       MSA128DOpnd>, IsCommutable;
1518
1519class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable;
1520class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable;
1521class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable;
1522class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable;
1523
1524class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5,
1525                                      MSA128BOpnd>;
1526class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5,
1527                                      MSA128HOpnd>;
1528class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5,
1529                                      MSA128WOpnd>;
1530class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5,
1531                                      MSA128DOpnd>;
1532
1533class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>;
1534class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128HOpnd>;
1535class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128WOpnd>;
1536class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128DOpnd>;
1537
1538class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8,
1539                                     MSA128BOpnd>;
1540
1541class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b,
1542                                       MSA128BOpnd>;
1543class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h,
1544                                       MSA128HOpnd>;
1545class ASUB_S_W_DESC : MSA_3R_DESC_BASE<"asub_s.w", int_mips_asub_s_w,
1546                                       MSA128WOpnd>;
1547class ASUB_S_D_DESC : MSA_3R_DESC_BASE<"asub_s.d", int_mips_asub_s_d,
1548                                       MSA128DOpnd>;
1549
1550class ASUB_U_B_DESC : MSA_3R_DESC_BASE<"asub_u.b", int_mips_asub_u_b,
1551                                       MSA128BOpnd>;
1552class ASUB_U_H_DESC : MSA_3R_DESC_BASE<"asub_u.h", int_mips_asub_u_h,
1553                                       MSA128HOpnd>;
1554class ASUB_U_W_DESC : MSA_3R_DESC_BASE<"asub_u.w", int_mips_asub_u_w,
1555                                       MSA128WOpnd>;
1556class ASUB_U_D_DESC : MSA_3R_DESC_BASE<"asub_u.d", int_mips_asub_u_d,
1557                                       MSA128DOpnd>;
1558
1559class AVE_S_B_DESC : MSA_3R_DESC_BASE<"ave_s.b", int_mips_ave_s_b, MSA128BOpnd>,
1560                     IsCommutable;
1561class AVE_S_H_DESC : MSA_3R_DESC_BASE<"ave_s.h", int_mips_ave_s_h, MSA128HOpnd>,
1562                     IsCommutable;
1563class AVE_S_W_DESC : MSA_3R_DESC_BASE<"ave_s.w", int_mips_ave_s_w, MSA128WOpnd>,
1564                     IsCommutable;
1565class AVE_S_D_DESC : MSA_3R_DESC_BASE<"ave_s.d", int_mips_ave_s_d, MSA128DOpnd>,
1566                     IsCommutable;
1567
1568class AVE_U_B_DESC : MSA_3R_DESC_BASE<"ave_u.b", int_mips_ave_u_b, MSA128BOpnd>,
1569                     IsCommutable;
1570class AVE_U_H_DESC : MSA_3R_DESC_BASE<"ave_u.h", int_mips_ave_u_h, MSA128HOpnd>,
1571                     IsCommutable;
1572class AVE_U_W_DESC : MSA_3R_DESC_BASE<"ave_u.w", int_mips_ave_u_w, MSA128WOpnd>,
1573                     IsCommutable;
1574class AVE_U_D_DESC : MSA_3R_DESC_BASE<"ave_u.d", int_mips_ave_u_d, MSA128DOpnd>,
1575                     IsCommutable;
1576
1577class AVER_S_B_DESC : MSA_3R_DESC_BASE<"aver_s.b", int_mips_aver_s_b,
1578                                       MSA128BOpnd>, IsCommutable;
1579class AVER_S_H_DESC : MSA_3R_DESC_BASE<"aver_s.h", int_mips_aver_s_h,
1580                                       MSA128HOpnd>, IsCommutable;
1581class AVER_S_W_DESC : MSA_3R_DESC_BASE<"aver_s.w", int_mips_aver_s_w,
1582                                       MSA128WOpnd>, IsCommutable;
1583class AVER_S_D_DESC : MSA_3R_DESC_BASE<"aver_s.d", int_mips_aver_s_d,
1584                                       MSA128DOpnd>, IsCommutable;
1585
1586class AVER_U_B_DESC : MSA_3R_DESC_BASE<"aver_u.b", int_mips_aver_u_b,
1587                                       MSA128BOpnd>, IsCommutable;
1588class AVER_U_H_DESC : MSA_3R_DESC_BASE<"aver_u.h", int_mips_aver_u_h,
1589                                       MSA128HOpnd>, IsCommutable;
1590class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w,
1591                                       MSA128WOpnd>, IsCommutable;
1592class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d,
1593                                       MSA128DOpnd>, IsCommutable;
1594
1595class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", vbclr_b, MSA128BOpnd>;
1596class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", vbclr_h, MSA128HOpnd>;
1597class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", vbclr_w, MSA128WOpnd>;
1598class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", vbclr_d, MSA128DOpnd>;
1599
1600class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", and, vsplat_uimm_inv_pow2,
1601                                         MSA128BOpnd>;
1602class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", and, vsplat_uimm_inv_pow2,
1603                                         MSA128HOpnd>;
1604class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", and, vsplat_uimm_inv_pow2,
1605                                         MSA128WOpnd>;
1606class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", and, vsplat_uimm_inv_pow2,
1607                                         MSA128DOpnd>;
1608
1609class BINSL_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.b", int_mips_binsl_b,
1610                                            MSA128BOpnd>;
1611class BINSL_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.h", int_mips_binsl_h,
1612                                            MSA128HOpnd>;
1613class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w,
1614                                            MSA128WOpnd>;
1615class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d,
1616                                            MSA128DOpnd>;
1617
1618class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, vsplat_maskl_bits_uimm3, MSA128BOpnd>;
1619class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, vsplat_maskl_bits_uimm4, MSA128HOpnd>;
1620class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, vsplat_maskl_bits_uimm5, MSA128WOpnd>;
1621class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, vsplat_maskl_bits_uimm6, MSA128DOpnd>;
1622
1623class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b,
1624                                            MSA128BOpnd>;
1625class BINSR_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.h", int_mips_binsr_h,
1626                                            MSA128HOpnd>;
1627class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w,
1628                                            MSA128WOpnd>;
1629class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d,
1630                                            MSA128DOpnd>;
1631
1632class BINSRI_B_DESC
1633    : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, vsplat_maskr_bits_uimm3,
1634                               MSA128BOpnd>;
1635class BINSRI_H_DESC
1636    : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, vsplat_maskr_bits_uimm4,
1637                               MSA128HOpnd>;
1638class BINSRI_W_DESC
1639    : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, vsplat_maskr_bits_uimm5,
1640                               MSA128WOpnd>;
1641class BINSRI_D_DESC
1642    : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, vsplat_maskr_bits_uimm6,
1643                               MSA128DOpnd>;
1644
1645class BMNZ_V_DESC {
1646  dag OutOperandList = (outs MSA128BOpnd:$wd);
1647  dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1648                       MSA128BOpnd:$wt);
1649  string AsmString = "bmnz.v\t$wd, $ws, $wt";
1650  list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
1651                                                      MSA128BOpnd:$ws,
1652                                                      MSA128BOpnd:$wd_in))];
1653  InstrItinClass Itinerary = NoItinerary;
1654  string Constraints = "$wd = $wd_in";
1655}
1656
1657class BMNZI_B_DESC {
1658  dag OutOperandList = (outs MSA128BOpnd:$wd);
1659  dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1660                           vsplat_uimm8:$u8);
1661  string AsmString = "bmnzi.b\t$wd, $ws, $u8";
1662  list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
1663                                                      MSA128BOpnd:$ws,
1664                                                      MSA128BOpnd:$wd_in))];
1665  InstrItinClass Itinerary = NoItinerary;
1666  string Constraints = "$wd = $wd_in";
1667}
1668
1669class BMZ_V_DESC {
1670  dag OutOperandList = (outs MSA128BOpnd:$wd);
1671  dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1672                       MSA128BOpnd:$wt);
1673  string AsmString = "bmz.v\t$wd, $ws, $wt";
1674  list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
1675                                                      MSA128BOpnd:$wd_in,
1676                                                      MSA128BOpnd:$ws))];
1677  InstrItinClass Itinerary = NoItinerary;
1678  string Constraints = "$wd = $wd_in";
1679}
1680
1681class BMZI_B_DESC {
1682  dag OutOperandList = (outs MSA128BOpnd:$wd);
1683  dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1684                           vsplat_uimm8:$u8);
1685  string AsmString = "bmzi.b\t$wd, $ws, $u8";
1686  list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
1687                                                      MSA128BOpnd:$wd_in,
1688                                                      MSA128BOpnd:$ws))];
1689  InstrItinClass Itinerary = NoItinerary;
1690  string Constraints = "$wd = $wd_in";
1691}
1692
1693class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg_b, MSA128BOpnd>;
1694class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg_h, MSA128HOpnd>;
1695class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg_w, MSA128WOpnd>;
1696class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg_d, MSA128DOpnd>;
1697
1698class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", xor, vsplat_uimm_pow2,
1699                                         MSA128BOpnd>;
1700class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", xor, vsplat_uimm_pow2,
1701                                         MSA128HOpnd>;
1702class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", xor, vsplat_uimm_pow2,
1703                                         MSA128WOpnd>;
1704class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", xor, vsplat_uimm_pow2,
1705                                         MSA128DOpnd>;
1706
1707class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>;
1708class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>;
1709class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>;
1710class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>;
1711
1712class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>;
1713
1714class BSEL_V_DESC {
1715  dag OutOperandList = (outs MSA128BOpnd:$wd);
1716  dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1717                       MSA128BOpnd:$wt);
1718  string AsmString = "bsel.v\t$wd, $ws, $wt";
1719  // Note that vselect and BSEL_V treat the condition operand the opposite way
1720  // from each other.
1721  //   (vselect cond, if_set, if_clear)
1722  //   (BSEL_V cond, if_clear, if_set)
1723  list<dag> Pattern = [(set MSA128BOpnd:$wd,
1724                        (vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$wt,
1725                                                     MSA128BOpnd:$ws))];
1726  InstrItinClass Itinerary = NoItinerary;
1727  string Constraints = "$wd = $wd_in";
1728}
1729
1730class BSELI_B_DESC {
1731  dag OutOperandList = (outs MSA128BOpnd:$wd);
1732  dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1733                           vsplat_uimm8:$u8);
1734  string AsmString = "bseli.b\t$wd, $ws, $u8";
1735  // Note that vselect and BSEL_V treat the condition operand the opposite way
1736  // from each other.
1737  //   (vselect cond, if_set, if_clear)
1738  //   (BSEL_V cond, if_clear, if_set)
1739  list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in,
1740                                                      vsplati8_uimm8:$u8,
1741                                                      MSA128BOpnd:$ws))];
1742  InstrItinClass Itinerary = NoItinerary;
1743  string Constraints = "$wd = $wd_in";
1744}
1745
1746class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", vbset_b, MSA128BOpnd>;
1747class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", vbset_h, MSA128HOpnd>;
1748class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", vbset_w, MSA128WOpnd>;
1749class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", vbset_d, MSA128DOpnd>;
1750
1751class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", or, vsplat_uimm_pow2,
1752                                         MSA128BOpnd>;
1753class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", or, vsplat_uimm_pow2,
1754                                         MSA128HOpnd>;
1755class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", or, vsplat_uimm_pow2,
1756                                         MSA128WOpnd>;
1757class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", or, vsplat_uimm_pow2,
1758                                         MSA128DOpnd>;
1759
1760class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>;
1761class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>;
1762class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>;
1763class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>;
1764
1765class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>;
1766
1767class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>,
1768                   IsCommutable;
1769class CEQ_H_DESC : MSA_3R_DESC_BASE<"ceq.h", vseteq_v8i16, MSA128HOpnd>,
1770                   IsCommutable;
1771class CEQ_W_DESC : MSA_3R_DESC_BASE<"ceq.w", vseteq_v4i32, MSA128WOpnd>,
1772                   IsCommutable;
1773class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq.d", vseteq_v2i64, MSA128DOpnd>,
1774                   IsCommutable;
1775
1776class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5,
1777                                     MSA128BOpnd>;
1778class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5,
1779                                     MSA128HOpnd>;
1780class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5,
1781                                     MSA128WOpnd>;
1782class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5,
1783                                     MSA128DOpnd>;
1784
1785class CFCMSA_DESC {
1786  dag OutOperandList = (outs GPR32Opnd:$rd);
1787  dag InOperandList = (ins MSA128CROpnd:$cs);
1788  string AsmString = "cfcmsa\t$rd, $cs";
1789  InstrItinClass Itinerary = NoItinerary;
1790  bit hasSideEffects = 1;
1791  bit isMoveReg = 1;
1792}
1793
1794class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>;
1795class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", vsetle_v8i16, MSA128HOpnd>;
1796class CLE_S_W_DESC : MSA_3R_DESC_BASE<"cle_s.w", vsetle_v4i32, MSA128WOpnd>;
1797class CLE_S_D_DESC : MSA_3R_DESC_BASE<"cle_s.d", vsetle_v2i64, MSA128DOpnd>;
1798
1799class CLE_U_B_DESC : MSA_3R_DESC_BASE<"cle_u.b", vsetule_v16i8, MSA128BOpnd>;
1800class CLE_U_H_DESC : MSA_3R_DESC_BASE<"cle_u.h", vsetule_v8i16, MSA128HOpnd>;
1801class CLE_U_W_DESC : MSA_3R_DESC_BASE<"cle_u.w", vsetule_v4i32, MSA128WOpnd>;
1802class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>;
1803
1804class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8,
1805                                       vsplati8_simm5,  MSA128BOpnd>;
1806class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16,
1807                                       vsplati16_simm5, MSA128HOpnd>;
1808class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32,
1809                                       vsplati32_simm5, MSA128WOpnd>;
1810class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64,
1811                                       vsplati64_simm5, MSA128DOpnd>;
1812
1813class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8,
1814                                       vsplati8_uimm5,  MSA128BOpnd>;
1815class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16,
1816                                       vsplati16_uimm5, MSA128HOpnd>;
1817class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32,
1818                                       vsplati32_uimm5, MSA128WOpnd>;
1819class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64,
1820                                       vsplati64_uimm5, MSA128DOpnd>;
1821
1822class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>;
1823class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>;
1824class CLT_S_W_DESC : MSA_3R_DESC_BASE<"clt_s.w", vsetlt_v4i32, MSA128WOpnd>;
1825class CLT_S_D_DESC : MSA_3R_DESC_BASE<"clt_s.d", vsetlt_v2i64, MSA128DOpnd>;
1826
1827class CLT_U_B_DESC : MSA_3R_DESC_BASE<"clt_u.b", vsetult_v16i8, MSA128BOpnd>;
1828class CLT_U_H_DESC : MSA_3R_DESC_BASE<"clt_u.h", vsetult_v8i16, MSA128HOpnd>;
1829class CLT_U_W_DESC : MSA_3R_DESC_BASE<"clt_u.w", vsetult_v4i32, MSA128WOpnd>;
1830class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>;
1831
1832class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8,
1833                                       vsplati8_simm5, MSA128BOpnd>;
1834class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16,
1835                                       vsplati16_simm5, MSA128HOpnd>;
1836class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32,
1837                                       vsplati32_simm5, MSA128WOpnd>;
1838class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64,
1839                                       vsplati64_simm5, MSA128DOpnd>;
1840
1841class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8,
1842                                       vsplati8_uimm5, MSA128BOpnd>;
1843class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16,
1844                                       vsplati16_uimm5, MSA128HOpnd>;
1845class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32,
1846                                       vsplati32_uimm5, MSA128WOpnd>;
1847class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64,
1848                                       vsplati64_uimm5, MSA128DOpnd>;
1849
1850class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8,  v16i8,
1851                                         uimm4_ptr, immZExt4Ptr, GPR32Opnd,
1852                                         MSA128BOpnd>;
1853class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16,
1854                                         uimm3_ptr, immZExt3Ptr, GPR32Opnd,
1855                                         MSA128HOpnd>;
1856class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32,
1857                                         uimm2_ptr, immZExt2Ptr, GPR32Opnd,
1858                                         MSA128WOpnd>;
1859class COPY_S_D_DESC : MSA_COPY_DESC_BASE<"copy_s.d", vextract_sext_i64, v2i64,
1860                                         uimm1_ptr, immZExt1Ptr, GPR64Opnd,
1861                                         MSA128DOpnd>;
1862
1863class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8,  v16i8,
1864                                         uimm4_ptr, immZExt4Ptr, GPR32Opnd,
1865                                         MSA128BOpnd>;
1866class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16,
1867                                         uimm3_ptr, immZExt3Ptr, GPR32Opnd,
1868                                         MSA128HOpnd>;
1869class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32,
1870                                         uimm2_ptr, immZExt2Ptr, GPR32Opnd,
1871                                         MSA128WOpnd>;
1872
1873class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32,
1874                                                 uimm2_ptr, immZExt2Ptr, FGR32,
1875                                                 MSA128W>;
1876class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64,
1877                                                 uimm1_ptr, immZExt1Ptr, FGR64,
1878                                                 MSA128D>;
1879
1880class CTCMSA_DESC {
1881  dag OutOperandList = (outs);
1882  dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs);
1883  string AsmString = "ctcmsa\t$cd, $rs";
1884  InstrItinClass Itinerary = NoItinerary;
1885  bit hasSideEffects = 1;
1886  bit isMoveReg = 1;
1887}
1888
1889class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>;
1890class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128HOpnd>;
1891class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128WOpnd>;
1892class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128DOpnd>;
1893
1894class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128BOpnd>;
1895class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128HOpnd>;
1896class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128WOpnd>;
1897class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128DOpnd>;
1898
1899class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h,
1900                                       MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1901                      IsCommutable;
1902class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w,
1903                                       MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1904                      IsCommutable;
1905class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d,
1906                                       MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1907                      IsCommutable;
1908
1909class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h,
1910                                       MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1911                      IsCommutable;
1912class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w,
1913                                       MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1914                      IsCommutable;
1915class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d,
1916                                       MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1917                      IsCommutable;
1918
1919class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h,
1920                                           MSA128HOpnd, MSA128BOpnd,
1921                                           MSA128BOpnd>, IsCommutable;
1922class DPADD_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.w", int_mips_dpadd_s_w,
1923                                           MSA128WOpnd, MSA128HOpnd,
1924                                           MSA128HOpnd>, IsCommutable;
1925class DPADD_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.d", int_mips_dpadd_s_d,
1926                                           MSA128DOpnd, MSA128WOpnd,
1927                                           MSA128WOpnd>, IsCommutable;
1928
1929class DPADD_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.h", int_mips_dpadd_u_h,
1930                                           MSA128HOpnd, MSA128BOpnd,
1931                                           MSA128BOpnd>, IsCommutable;
1932class DPADD_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.w", int_mips_dpadd_u_w,
1933                                           MSA128WOpnd, MSA128HOpnd,
1934                                           MSA128HOpnd>, IsCommutable;
1935class DPADD_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.d", int_mips_dpadd_u_d,
1936                                           MSA128DOpnd, MSA128WOpnd,
1937                                           MSA128WOpnd>, IsCommutable;
1938
1939class DPSUB_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.h", int_mips_dpsub_s_h,
1940                                           MSA128HOpnd, MSA128BOpnd,
1941                                           MSA128BOpnd>;
1942class DPSUB_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.w", int_mips_dpsub_s_w,
1943                                           MSA128WOpnd, MSA128HOpnd,
1944                                           MSA128HOpnd>;
1945class DPSUB_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.d", int_mips_dpsub_s_d,
1946                                           MSA128DOpnd, MSA128WOpnd,
1947                                           MSA128WOpnd>;
1948
1949class DPSUB_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.h", int_mips_dpsub_u_h,
1950                                           MSA128HOpnd, MSA128BOpnd,
1951                                           MSA128BOpnd>;
1952class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w,
1953                                           MSA128WOpnd, MSA128HOpnd,
1954                                           MSA128HOpnd>;
1955class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d,
1956                                           MSA128DOpnd, MSA128WOpnd,
1957                                           MSA128WOpnd>;
1958
1959class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>,
1960                    IsCommutable;
1961class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>,
1962                    IsCommutable;
1963
1964class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>,
1965                    IsCommutable;
1966class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>,
1967                    IsCommutable;
1968
1969class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>,
1970                    IsCommutable;
1971class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>,
1972                    IsCommutable;
1973
1974class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w,
1975                                        MSA128WOpnd>;
1976class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d,
1977                                        MSA128DOpnd>;
1978
1979class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>;
1980class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>;
1981
1982class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>;
1983class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>;
1984
1985class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>,
1986                    IsCommutable;
1987class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>,
1988                    IsCommutable;
1989
1990class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>,
1991                    IsCommutable;
1992class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>,
1993                    IsCommutable;
1994
1995class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>,
1996                     IsCommutable;
1997class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>,
1998                     IsCommutable;
1999
2000class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>,
2001                     IsCommutable;
2002class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>,
2003                     IsCommutable;
2004
2005class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>,
2006                     IsCommutable;
2007class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>,
2008                     IsCommutable;
2009
2010class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>,
2011                    IsCommutable;
2012class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>,
2013                    IsCommutable;
2014
2015class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>,
2016                     IsCommutable;
2017class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>,
2018                     IsCommutable;
2019
2020class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>;
2021class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>;
2022
2023class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h,
2024                                       MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
2025class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w,
2026                                       MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
2027
2028// The fexp2.df instruction multiplies the first operand by 2 to the power of
2029// the second operand. We therefore need a pseudo-insn in order to invent the
2030// 1.0 when we only need to match ISD::FEXP2.
2031class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>;
2032class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>;
2033let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
2034  class FEXP2_W_1_PSEUDO_DESC :
2035      MSAPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws),
2036                [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>;
2037  class FEXP2_D_1_PSEUDO_DESC :
2038      MSAPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws),
2039                [(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>;
2040}
2041
2042class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w,
2043                                        MSA128WOpnd, MSA128HOpnd>;
2044class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d,
2045                                        MSA128DOpnd, MSA128WOpnd>;
2046
2047class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w,
2048                                        MSA128WOpnd, MSA128HOpnd>;
2049class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d,
2050                                        MSA128DOpnd, MSA128WOpnd>;
2051
2052class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>;
2053class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>;
2054
2055class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>;
2056class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>;
2057
2058class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w,
2059                                      MSA128WOpnd, MSA128HOpnd>;
2060class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d,
2061                                      MSA128DOpnd, MSA128WOpnd>;
2062
2063class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w,
2064                                      MSA128WOpnd, MSA128HOpnd>;
2065class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d,
2066                                      MSA128DOpnd, MSA128WOpnd>;
2067
2068class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8,
2069                                          MSA128BOpnd, GPR32Opnd>;
2070class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16,
2071                                          MSA128HOpnd, GPR32Opnd>;
2072class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32,
2073                                          MSA128WOpnd, GPR32Opnd>;
2074class FILL_D_DESC : MSA_2R_FILL_DESC_BASE<"fill.d", v2i64, vsplati64,
2075                                          MSA128DOpnd, GPR64Opnd>;
2076
2077class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<vsplatf32, MSA128W, FGR32>;
2078class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<vsplatf64, MSA128D, FGR64>;
2079
2080class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>;
2081class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>;
2082
2083class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>;
2084class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>;
2085
2086class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>;
2087class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>;
2088
2089class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w,
2090                                        MSA128WOpnd>;
2091class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d,
2092                                        MSA128DOpnd>;
2093
2094class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>;
2095class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>;
2096
2097class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w,
2098                                        MSA128WOpnd>;
2099class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d,
2100                                        MSA128DOpnd>;
2101
2102class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", MipsFMS, MSA128WOpnd>;
2103class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", MipsFMS, MSA128DOpnd>;
2104
2105class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>;
2106class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>;
2107
2108class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>;
2109class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>;
2110
2111class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>;
2112class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>;
2113
2114class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w,
2115                                        MSA128WOpnd>;
2116class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d,
2117                                        MSA128DOpnd>;
2118
2119class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>;
2120class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>;
2121
2122class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>;
2123class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>;
2124
2125class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>;
2126class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>;
2127
2128class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>;
2129class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>;
2130
2131class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>;
2132class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>;
2133
2134class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>;
2135class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>;
2136
2137class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>;
2138class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>;
2139
2140class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>;
2141class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>;
2142
2143class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w,
2144                                       MSA128WOpnd>;
2145class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d,
2146                                       MSA128DOpnd>;
2147
2148class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w,
2149                                       MSA128WOpnd>;
2150class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d,
2151                                       MSA128DOpnd>;
2152
2153class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w,
2154                                       MSA128WOpnd>;
2155class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d,
2156                                       MSA128DOpnd>;
2157
2158class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w,
2159                                      MSA128WOpnd>;
2160class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d,
2161                                      MSA128DOpnd>;
2162
2163class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w,
2164                                       MSA128WOpnd>;
2165class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d,
2166                                       MSA128DOpnd>;
2167
2168class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w,
2169                                         MSA128WOpnd>;
2170class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d,
2171                                         MSA128DOpnd>;
2172
2173class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w,
2174                                         MSA128WOpnd>;
2175class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d,
2176                                         MSA128DOpnd>;
2177
2178class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h,
2179                                     MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
2180class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w,
2181                                     MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
2182
2183class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint,
2184                                          MSA128WOpnd>;
2185class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint,
2186                                          MSA128DOpnd>;
2187
2188class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint,
2189                                          MSA128WOpnd>;
2190class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint,
2191                                          MSA128DOpnd>;
2192
2193class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h,
2194                                       MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2195class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w,
2196                                       MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2197class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d,
2198                                       MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2199
2200class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h,
2201                                       MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2202class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w,
2203                                       MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2204class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d,
2205                                       MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2206
2207class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h,
2208                                       MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2209class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w,
2210                                       MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2211class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d,
2212                                       MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2213
2214class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h,
2215                                       MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2216class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w,
2217                                       MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2218class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d,
2219                                       MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2220
2221class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", MipsILVEV, MSA128BOpnd>;
2222class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", MipsILVEV, MSA128HOpnd>;
2223class ILVEV_W_DESC : MSA_3R_DESC_BASE<"ilvev.w", MipsILVEV, MSA128WOpnd>;
2224class ILVEV_D_DESC : MSA_3R_DESC_BASE<"ilvev.d", MipsILVEV, MSA128DOpnd>;
2225
2226class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>;
2227class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>;
2228class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>;
2229class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>;
2230
2231class ILVOD_B_DESC : MSA_3R_DESC_BASE<"ilvod.b", MipsILVOD, MSA128BOpnd>;
2232class ILVOD_H_DESC : MSA_3R_DESC_BASE<"ilvod.h", MipsILVOD, MSA128HOpnd>;
2233class ILVOD_W_DESC : MSA_3R_DESC_BASE<"ilvod.w", MipsILVOD, MSA128WOpnd>;
2234class ILVOD_D_DESC : MSA_3R_DESC_BASE<"ilvod.d", MipsILVOD, MSA128DOpnd>;
2235
2236class ILVR_B_DESC : MSA_3R_DESC_BASE<"ilvr.b", MipsILVR, MSA128BOpnd>;
2237class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>;
2238class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>;
2239class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>;
2240
2241class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8, uimm4,
2242                                           immZExt4Ptr, MSA128BOpnd, GPR32Opnd>;
2243class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16, uimm3,
2244                                           immZExt3Ptr, MSA128HOpnd, GPR32Opnd>;
2245class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32, uimm2,
2246                                           immZExt2Ptr, MSA128WOpnd, GPR32Opnd>;
2247class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64, uimm1,
2248                                           immZExt1Ptr, MSA128DOpnd, GPR64Opnd>;
2249
2250class INSERT_B_VIDX_PSEUDO_DESC :
2251    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR32Opnd>;
2252class INSERT_H_VIDX_PSEUDO_DESC :
2253    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR32Opnd>;
2254class INSERT_W_VIDX_PSEUDO_DESC :
2255    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR32Opnd>;
2256class INSERT_D_VIDX_PSEUDO_DESC :
2257    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR32Opnd>;
2258
2259class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32,
2260                                                     uimm2, immZExt2Ptr,
2261                                                     MSA128WOpnd, FGR32Opnd>;
2262class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64,
2263                                                     uimm1, immZExt1Ptr,
2264                                                     MSA128DOpnd, FGR64Opnd>;
2265
2266class INSERT_FW_VIDX_PSEUDO_DESC :
2267    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR32Opnd>;
2268class INSERT_FD_VIDX_PSEUDO_DESC :
2269    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR32Opnd>;
2270
2271class INSERT_B_VIDX64_PSEUDO_DESC :
2272    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR64Opnd>;
2273class INSERT_H_VIDX64_PSEUDO_DESC :
2274    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR64Opnd>;
2275class INSERT_W_VIDX64_PSEUDO_DESC :
2276    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR64Opnd>;
2277class INSERT_D_VIDX64_PSEUDO_DESC :
2278    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR64Opnd>;
2279
2280class INSERT_FW_VIDX64_PSEUDO_DESC :
2281    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR64Opnd>;
2282class INSERT_FD_VIDX64_PSEUDO_DESC :
2283    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR64Opnd>;
2284
2285class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8, uimm4, timmZExt4,
2286                                         MSA128BOpnd>;
2287class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", insve_v8i16, uimm3, timmZExt3,
2288                                         MSA128HOpnd>;
2289class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", insve_v4i32, uimm2, timmZExt2,
2290                                         MSA128WOpnd>;
2291class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64, uimm1, timmZExt1,
2292                                         MSA128DOpnd>;
2293
2294class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2295                   ValueType TyNode, RegisterOperand ROWD,
2296                   Operand MemOpnd, ComplexPattern Addr = addrimm10,
2297                   InstrItinClass itin = NoItinerary> {
2298  dag OutOperandList = (outs ROWD:$wd);
2299  dag InOperandList = (ins MemOpnd:$addr);
2300  string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2301  list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))];
2302  InstrItinClass Itinerary = itin;
2303  string DecoderMethod = "DecodeMSA128Mem";
2304}
2305
2306class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd, mem_simm10>;
2307class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd,
2308                               mem_simm10_lsl1, addrimm10lsl1>;
2309class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd,
2310                               mem_simm10_lsl2, addrimm10lsl2>;
2311class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd,
2312                               mem_simm10_lsl3, addrimm10lsl3>;
2313
2314class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>;
2315class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>;
2316class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>;
2317class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>;
2318
2319class MSA_LOAD_PSEUDO_BASE<SDPatternOperator intrinsic, RegisterOperand RO> :
2320  PseudoSE<(outs RO:$dst), (ins PtrRC:$ptr, GPR32:$imm),
2321           [(set RO:$dst, (intrinsic iPTR:$ptr, GPR32:$imm))]> {
2322  let hasNoSchedulingInfo = 1;
2323  let usesCustomInserter = 1;
2324}
2325
2326def LDR_D : MSA_LOAD_PSEUDO_BASE<int_mips_ldr_d, MSA128DOpnd>;
2327def LDR_W : MSA_LOAD_PSEUDO_BASE<int_mips_ldr_w, MSA128WOpnd>;
2328
2329class LSA_DESC_BASE<string instr_asm, RegisterOperand RORD,
2330                    InstrItinClass itin = NoItinerary> {
2331  dag OutOperandList = (outs RORD:$rd);
2332  dag InOperandList = (ins RORD:$rs, RORD:$rt, uimm2_plus1:$sa);
2333  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $sa");
2334  list<dag> Pattern = [(set RORD:$rd, (add RORD:$rt,
2335                                                (shl RORD:$rs,
2336                                                     immZExt2Lsa:$sa)))];
2337  InstrItinClass Itinerary = itin;
2338}
2339
2340class LSA_DESC : LSA_DESC_BASE<"lsa", GPR32Opnd, II_LSA>;
2341class DLSA_DESC : LSA_DESC_BASE<"dlsa", GPR64Opnd, II_DLSA>;
2342
2343class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h,
2344                                            MSA128HOpnd>;
2345class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w,
2346                                            MSA128WOpnd>;
2347
2348class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h,
2349                                             MSA128HOpnd>;
2350class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w,
2351                                             MSA128WOpnd>;
2352
2353class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", muladd, MSA128BOpnd>;
2354class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", muladd, MSA128HOpnd>;
2355class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", muladd, MSA128WOpnd>;
2356class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", muladd, MSA128DOpnd>;
2357
2358class MAX_A_B_DESC : MSA_3R_DESC_BASE<"max_a.b", int_mips_max_a_b, MSA128BOpnd>;
2359class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>;
2360class MAX_A_W_DESC : MSA_3R_DESC_BASE<"max_a.w", int_mips_max_a_w, MSA128WOpnd>;
2361class MAX_A_D_DESC : MSA_3R_DESC_BASE<"max_a.d", int_mips_max_a_d, MSA128DOpnd>;
2362
2363class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", smax, MSA128BOpnd>;
2364class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", smax, MSA128HOpnd>;
2365class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", smax, MSA128WOpnd>;
2366class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", smax, MSA128DOpnd>;
2367
2368class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", umax, MSA128BOpnd>;
2369class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", umax, MSA128HOpnd>;
2370class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", umax, MSA128WOpnd>;
2371class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", umax, MSA128DOpnd>;
2372
2373class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", smax, vsplati8_simm5,
2374                                       MSA128BOpnd>;
2375class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", smax, vsplati16_simm5,
2376                                       MSA128HOpnd>;
2377class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", smax, vsplati32_simm5,
2378                                       MSA128WOpnd>;
2379class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", smax, vsplati64_simm5,
2380                                       MSA128DOpnd>;
2381
2382class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", umax, vsplati8_uimm5,
2383                                       MSA128BOpnd>;
2384class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", umax, vsplati16_uimm5,
2385                                       MSA128HOpnd>;
2386class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", umax, vsplati32_uimm5,
2387                                       MSA128WOpnd>;
2388class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", umax, vsplati64_uimm5,
2389                                       MSA128DOpnd>;
2390
2391class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>;
2392class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>;
2393class MIN_A_W_DESC : MSA_3R_DESC_BASE<"min_a.w", int_mips_min_a_w, MSA128WOpnd>;
2394class MIN_A_D_DESC : MSA_3R_DESC_BASE<"min_a.d", int_mips_min_a_d, MSA128DOpnd>;
2395
2396class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", smin, MSA128BOpnd>;
2397class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", smin, MSA128HOpnd>;
2398class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", smin, MSA128WOpnd>;
2399class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", smin, MSA128DOpnd>;
2400
2401class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", umin, MSA128BOpnd>;
2402class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", umin, MSA128HOpnd>;
2403class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", umin, MSA128WOpnd>;
2404class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", umin, MSA128DOpnd>;
2405
2406class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", smin, vsplati8_simm5,
2407                                       MSA128BOpnd>;
2408class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", smin, vsplati16_simm5,
2409                                       MSA128HOpnd>;
2410class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", smin, vsplati32_simm5,
2411                                       MSA128WOpnd>;
2412class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", smin, vsplati64_simm5,
2413                                       MSA128DOpnd>;
2414
2415class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", umin, vsplati8_uimm5,
2416                                       MSA128BOpnd>;
2417class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", umin, vsplati16_uimm5,
2418                                       MSA128HOpnd>;
2419class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", umin, vsplati32_uimm5,
2420                                       MSA128WOpnd>;
2421class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", umin, vsplati64_uimm5,
2422                                       MSA128DOpnd>;
2423
2424class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", srem, MSA128BOpnd>;
2425class MOD_S_H_DESC : MSA_3R_DESC_BASE<"mod_s.h", srem, MSA128HOpnd>;
2426class MOD_S_W_DESC : MSA_3R_DESC_BASE<"mod_s.w", srem, MSA128WOpnd>;
2427class MOD_S_D_DESC : MSA_3R_DESC_BASE<"mod_s.d", srem, MSA128DOpnd>;
2428
2429class MOD_U_B_DESC : MSA_3R_DESC_BASE<"mod_u.b", urem, MSA128BOpnd>;
2430class MOD_U_H_DESC : MSA_3R_DESC_BASE<"mod_u.h", urem, MSA128HOpnd>;
2431class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", urem, MSA128WOpnd>;
2432class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", urem, MSA128DOpnd>;
2433
2434class MOVE_V_DESC {
2435  dag OutOperandList = (outs MSA128BOpnd:$wd);
2436  dag InOperandList = (ins MSA128BOpnd:$ws);
2437  string AsmString = "move.v\t$wd, $ws";
2438  list<dag> Pattern = [];
2439  InstrItinClass Itinerary = NoItinerary;
2440  bit isMoveReg = 1;
2441}
2442
2443class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h,
2444                                            MSA128HOpnd>;
2445class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w,
2446                                            MSA128WOpnd>;
2447
2448class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h,
2449                                             MSA128HOpnd>;
2450class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w,
2451                                             MSA128WOpnd>;
2452
2453class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", mulsub, MSA128BOpnd>;
2454class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", mulsub, MSA128HOpnd>;
2455class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", mulsub, MSA128WOpnd>;
2456class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", mulsub, MSA128DOpnd>;
2457
2458class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h,
2459                                       MSA128HOpnd>;
2460class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w,
2461                                       MSA128WOpnd>;
2462
2463class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h,
2464                                        MSA128HOpnd>;
2465class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w,
2466                                        MSA128WOpnd>;
2467
2468class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128BOpnd>;
2469class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128HOpnd>;
2470class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", mul, MSA128WOpnd>;
2471class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", mul, MSA128DOpnd>;
2472
2473class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>;
2474class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>;
2475class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>;
2476class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>;
2477
2478class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", ctlz, MSA128BOpnd>;
2479class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128HOpnd>;
2480class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128WOpnd>;
2481class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128DOpnd>;
2482
2483class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128BOpnd>;
2484class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128HOpnd>;
2485class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128WOpnd>;
2486class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128DOpnd>;
2487
2488class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8,
2489                                     MSA128BOpnd>;
2490
2491class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128BOpnd>;
2492class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128HOpnd>;
2493class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128WOpnd>;
2494class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128DOpnd>;
2495
2496class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>;
2497
2498class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128BOpnd>;
2499class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128HOpnd>;
2500class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", MipsPCKEV, MSA128WOpnd>;
2501class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", MipsPCKEV, MSA128DOpnd>;
2502
2503class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", MipsPCKOD, MSA128BOpnd>;
2504class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", MipsPCKOD, MSA128HOpnd>;
2505class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>;
2506class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>;
2507
2508class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>;
2509class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>;
2510class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>;
2511class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>;
2512
2513class SAT_S_B_DESC : MSA_BIT_X_DESC_BASE<"sat_s.b", int_mips_sat_s_b, uimm3,
2514                                         timmZExt3, MSA128BOpnd>;
2515class SAT_S_H_DESC : MSA_BIT_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h, uimm4,
2516                                         timmZExt4, MSA128HOpnd>;
2517class SAT_S_W_DESC : MSA_BIT_X_DESC_BASE<"sat_s.w", int_mips_sat_s_w, uimm5,
2518                                         timmZExt5, MSA128WOpnd>;
2519class SAT_S_D_DESC : MSA_BIT_X_DESC_BASE<"sat_s.d", int_mips_sat_s_d, uimm6,
2520                                         timmZExt6, MSA128DOpnd>;
2521
2522class SAT_U_B_DESC : MSA_BIT_X_DESC_BASE<"sat_u.b", int_mips_sat_u_b, uimm3,
2523                                         timmZExt3, MSA128BOpnd>;
2524class SAT_U_H_DESC : MSA_BIT_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h, uimm4,
2525                                         timmZExt4, MSA128HOpnd>;
2526class SAT_U_W_DESC : MSA_BIT_X_DESC_BASE<"sat_u.w", int_mips_sat_u_w, uimm5,
2527                                         timmZExt5, MSA128WOpnd>;
2528class SAT_U_D_DESC : MSA_BIT_X_DESC_BASE<"sat_u.d", int_mips_sat_u_d, uimm6,
2529                                         timmZExt6, MSA128DOpnd>;
2530
2531class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>;
2532class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>;
2533class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>;
2534
2535class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>;
2536class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>;
2537class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>;
2538class SLD_D_DESC : MSA_3R_SLD_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>;
2539
2540class SLDI_B_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.b", int_mips_sldi_b,
2541                                          MSA128BOpnd, MSA128BOpnd, uimm4,
2542                                          timmZExt4>;
2543class SLDI_H_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.h", int_mips_sldi_h,
2544                                          MSA128HOpnd, MSA128HOpnd, uimm3,
2545                                          timmZExt3>;
2546class SLDI_W_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.w", int_mips_sldi_w,
2547                                          MSA128WOpnd, MSA128WOpnd, uimm2,
2548                                          timmZExt2>;
2549class SLDI_D_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.d", int_mips_sldi_d,
2550                                          MSA128DOpnd, MSA128DOpnd, uimm1,
2551                                          timmZExt1>;
2552
2553class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128BOpnd>;
2554class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128HOpnd>;
2555class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>;
2556class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>;
2557
2558class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3,
2559                                            MSA128BOpnd>;
2560class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4,
2561                                            MSA128HOpnd>;
2562class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5,
2563                                            MSA128WOpnd>;
2564class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6,
2565                                            MSA128DOpnd>;
2566
2567class SPLAT_B_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.b", vsplati8_elt,
2568                                            MSA128BOpnd>;
2569class SPLAT_H_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.h", vsplati16_elt,
2570                                            MSA128HOpnd>;
2571class SPLAT_W_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.w", vsplati32_elt,
2572                                            MSA128WOpnd>;
2573class SPLAT_D_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.d", vsplati64_elt,
2574                                            MSA128DOpnd>;
2575
2576class SPLATI_B_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.b", vsplati8_uimm4,
2577                                              MSA128BOpnd>;
2578class SPLATI_H_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.h", vsplati16_uimm3,
2579                                              MSA128HOpnd>;
2580class SPLATI_W_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.w", vsplati32_uimm2,
2581                                              MSA128WOpnd>;
2582class SPLATI_D_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.d", vsplati64_uimm1,
2583                                              MSA128DOpnd>;
2584
2585class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>;
2586class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>;
2587class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>;
2588class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>;
2589
2590class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3,
2591                                            MSA128BOpnd>;
2592class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4,
2593                                            MSA128HOpnd>;
2594class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5,
2595                                            MSA128WOpnd>;
2596class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6,
2597                                            MSA128DOpnd>;
2598
2599class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>;
2600class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>;
2601class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>;
2602class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>;
2603
2604class SRARI_B_DESC : MSA_BIT_X_DESC_BASE<"srari.b", int_mips_srari_b, uimm3,
2605                                         timmZExt3, MSA128BOpnd>;
2606class SRARI_H_DESC : MSA_BIT_X_DESC_BASE<"srari.h", int_mips_srari_h, uimm4,
2607                                         timmZExt4, MSA128HOpnd>;
2608class SRARI_W_DESC : MSA_BIT_X_DESC_BASE<"srari.w", int_mips_srari_w, uimm5,
2609                                         timmZExt5, MSA128WOpnd>;
2610class SRARI_D_DESC : MSA_BIT_X_DESC_BASE<"srari.d", int_mips_srari_d, uimm6,
2611                                         timmZExt6, MSA128DOpnd>;
2612
2613class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>;
2614class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>;
2615class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>;
2616class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>;
2617
2618class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3,
2619                                            MSA128BOpnd>;
2620class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4,
2621                                            MSA128HOpnd>;
2622class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5,
2623                                            MSA128WOpnd>;
2624class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6,
2625                                            MSA128DOpnd>;
2626
2627class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>;
2628class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>;
2629class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>;
2630class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>;
2631
2632class SRLRI_B_DESC : MSA_BIT_X_DESC_BASE<"srlri.b", int_mips_srlri_b, uimm3,
2633                                         timmZExt3, MSA128BOpnd>;
2634class SRLRI_H_DESC : MSA_BIT_X_DESC_BASE<"srlri.h", int_mips_srlri_h, uimm4,
2635                                         timmZExt4, MSA128HOpnd>;
2636class SRLRI_W_DESC : MSA_BIT_X_DESC_BASE<"srlri.w", int_mips_srlri_w, uimm5,
2637                                         timmZExt5, MSA128WOpnd>;
2638class SRLRI_D_DESC : MSA_BIT_X_DESC_BASE<"srlri.d", int_mips_srlri_d, uimm6,
2639                                         timmZExt6, MSA128DOpnd>;
2640
2641class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2642                   ValueType TyNode, RegisterOperand ROWD,
2643                   Operand MemOpnd, ComplexPattern Addr = addrimm10,
2644                   InstrItinClass itin = NoItinerary> {
2645  dag OutOperandList = (outs);
2646  dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr);
2647  string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2648  list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)];
2649  InstrItinClass Itinerary = itin;
2650  string DecoderMethod = "DecodeMSA128Mem";
2651}
2652
2653class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd, mem_simm10>;
2654class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd,
2655                               mem_simm10_lsl1, addrimm10lsl1>;
2656class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd,
2657                               mem_simm10_lsl2, addrimm10lsl2>;
2658class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd,
2659                               mem_simm10_lsl3, addrimm10lsl3>;
2660
2661class MSA_STORE_PSEUDO_BASE<SDPatternOperator intrinsic, RegisterOperand RO> :
2662  PseudoSE<(outs), (ins RO:$dst, PtrRC:$ptr, GPR32:$imm),
2663           [(intrinsic RO:$dst, iPTR:$ptr, GPR32:$imm)]> {
2664  let hasNoSchedulingInfo = 1;
2665  let usesCustomInserter = 1;
2666}
2667
2668def STR_D : MSA_STORE_PSEUDO_BASE<int_mips_str_d, MSA128DOpnd>;
2669def STR_W : MSA_STORE_PSEUDO_BASE<int_mips_str_w, MSA128WOpnd>;
2670
2671class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b,
2672                                       MSA128BOpnd>;
2673class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h,
2674                                       MSA128HOpnd>;
2675class SUBS_S_W_DESC : MSA_3R_DESC_BASE<"subs_s.w", int_mips_subs_s_w,
2676                                       MSA128WOpnd>;
2677class SUBS_S_D_DESC : MSA_3R_DESC_BASE<"subs_s.d", int_mips_subs_s_d,
2678                                       MSA128DOpnd>;
2679
2680class SUBS_U_B_DESC : MSA_3R_DESC_BASE<"subs_u.b", int_mips_subs_u_b,
2681                                       MSA128BOpnd>;
2682class SUBS_U_H_DESC : MSA_3R_DESC_BASE<"subs_u.h", int_mips_subs_u_h,
2683                                       MSA128HOpnd>;
2684class SUBS_U_W_DESC : MSA_3R_DESC_BASE<"subs_u.w", int_mips_subs_u_w,
2685                                       MSA128WOpnd>;
2686class SUBS_U_D_DESC : MSA_3R_DESC_BASE<"subs_u.d", int_mips_subs_u_d,
2687                                       MSA128DOpnd>;
2688
2689class SUBSUS_U_B_DESC : MSA_3R_DESC_BASE<"subsus_u.b", int_mips_subsus_u_b,
2690                                         MSA128BOpnd>;
2691class SUBSUS_U_H_DESC : MSA_3R_DESC_BASE<"subsus_u.h", int_mips_subsus_u_h,
2692                                         MSA128HOpnd>;
2693class SUBSUS_U_W_DESC : MSA_3R_DESC_BASE<"subsus_u.w", int_mips_subsus_u_w,
2694                                         MSA128WOpnd>;
2695class SUBSUS_U_D_DESC : MSA_3R_DESC_BASE<"subsus_u.d", int_mips_subsus_u_d,
2696                                         MSA128DOpnd>;
2697
2698class SUBSUU_S_B_DESC : MSA_3R_DESC_BASE<"subsuu_s.b", int_mips_subsuu_s_b,
2699                                         MSA128BOpnd>;
2700class SUBSUU_S_H_DESC : MSA_3R_DESC_BASE<"subsuu_s.h", int_mips_subsuu_s_h,
2701                                         MSA128HOpnd>;
2702class SUBSUU_S_W_DESC : MSA_3R_DESC_BASE<"subsuu_s.w", int_mips_subsuu_s_w,
2703                                         MSA128WOpnd>;
2704class SUBSUU_S_D_DESC : MSA_3R_DESC_BASE<"subsuu_s.d", int_mips_subsuu_s_d,
2705                                         MSA128DOpnd>;
2706
2707class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", sub, MSA128BOpnd>;
2708class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", sub, MSA128HOpnd>;
2709class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128WOpnd>;
2710class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128DOpnd>;
2711
2712class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5,
2713                                      MSA128BOpnd>;
2714class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5,
2715                                      MSA128HOpnd>;
2716class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5,
2717                                      MSA128WOpnd>;
2718class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5,
2719                                      MSA128DOpnd>;
2720
2721class VSHF_B_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.b", MSA128BOpnd>;
2722class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>;
2723class VSHF_W_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.w", MSA128WOpnd>;
2724class VSHF_D_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.d", MSA128DOpnd>;
2725
2726class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128BOpnd>;
2727class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128HOpnd>;
2728class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128WOpnd>;
2729class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128DOpnd>;
2730
2731class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8,
2732                                     MSA128BOpnd>;
2733
2734// Instruction defs.
2735def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC;
2736def ADD_A_H : ADD_A_H_ENC, ADD_A_H_DESC;
2737def ADD_A_W : ADD_A_W_ENC, ADD_A_W_DESC;
2738def ADD_A_D : ADD_A_D_ENC, ADD_A_D_DESC;
2739
2740def ADDS_A_B : ADDS_A_B_ENC, ADDS_A_B_DESC;
2741def ADDS_A_H : ADDS_A_H_ENC, ADDS_A_H_DESC;
2742def ADDS_A_W : ADDS_A_W_ENC, ADDS_A_W_DESC;
2743def ADDS_A_D : ADDS_A_D_ENC, ADDS_A_D_DESC;
2744
2745def ADDS_S_B : ADDS_S_B_ENC, ADDS_S_B_DESC;
2746def ADDS_S_H : ADDS_S_H_ENC, ADDS_S_H_DESC;
2747def ADDS_S_W : ADDS_S_W_ENC, ADDS_S_W_DESC;
2748def ADDS_S_D : ADDS_S_D_ENC, ADDS_S_D_DESC;
2749
2750def ADDS_U_B : ADDS_U_B_ENC, ADDS_U_B_DESC;
2751def ADDS_U_H : ADDS_U_H_ENC, ADDS_U_H_DESC;
2752def ADDS_U_W : ADDS_U_W_ENC, ADDS_U_W_DESC;
2753def ADDS_U_D : ADDS_U_D_ENC, ADDS_U_D_DESC;
2754
2755def ADDV_B : ADDV_B_ENC, ADDV_B_DESC;
2756def ADDV_H : ADDV_H_ENC, ADDV_H_DESC;
2757def ADDV_W : ADDV_W_ENC, ADDV_W_DESC;
2758def ADDV_D : ADDV_D_ENC, ADDV_D_DESC;
2759
2760def ADDVI_B : ADDVI_B_ENC, ADDVI_B_DESC;
2761def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC;
2762def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC;
2763def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC;
2764
2765def AND_V : AND_V_ENC, AND_V_DESC;
2766def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC,
2767                     PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2768                                                MSA128BOpnd:$ws,
2769                                                MSA128BOpnd:$wt)>;
2770def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC,
2771                     PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2772                                                MSA128BOpnd:$ws,
2773                                                MSA128BOpnd:$wt)>;
2774def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC,
2775                     PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2776                                                MSA128BOpnd:$ws,
2777                                                MSA128BOpnd:$wt)>;
2778
2779def ANDI_B : ANDI_B_ENC, ANDI_B_DESC;
2780
2781def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC;
2782def ASUB_S_H : ASUB_S_H_ENC, ASUB_S_H_DESC;
2783def ASUB_S_W : ASUB_S_W_ENC, ASUB_S_W_DESC;
2784def ASUB_S_D : ASUB_S_D_ENC, ASUB_S_D_DESC;
2785
2786def ASUB_U_B : ASUB_U_B_ENC, ASUB_U_B_DESC;
2787def ASUB_U_H : ASUB_U_H_ENC, ASUB_U_H_DESC;
2788def ASUB_U_W : ASUB_U_W_ENC, ASUB_U_W_DESC;
2789def ASUB_U_D : ASUB_U_D_ENC, ASUB_U_D_DESC;
2790
2791def AVE_S_B : AVE_S_B_ENC, AVE_S_B_DESC;
2792def AVE_S_H : AVE_S_H_ENC, AVE_S_H_DESC;
2793def AVE_S_W : AVE_S_W_ENC, AVE_S_W_DESC;
2794def AVE_S_D : AVE_S_D_ENC, AVE_S_D_DESC;
2795
2796def AVE_U_B : AVE_U_B_ENC, AVE_U_B_DESC;
2797def AVE_U_H : AVE_U_H_ENC, AVE_U_H_DESC;
2798def AVE_U_W : AVE_U_W_ENC, AVE_U_W_DESC;
2799def AVE_U_D : AVE_U_D_ENC, AVE_U_D_DESC;
2800
2801def AVER_S_B : AVER_S_B_ENC, AVER_S_B_DESC;
2802def AVER_S_H : AVER_S_H_ENC, AVER_S_H_DESC;
2803def AVER_S_W : AVER_S_W_ENC, AVER_S_W_DESC;
2804def AVER_S_D : AVER_S_D_ENC, AVER_S_D_DESC;
2805
2806def AVER_U_B : AVER_U_B_ENC, AVER_U_B_DESC;
2807def AVER_U_H : AVER_U_H_ENC, AVER_U_H_DESC;
2808def AVER_U_W : AVER_U_W_ENC, AVER_U_W_DESC;
2809def AVER_U_D : AVER_U_D_ENC, AVER_U_D_DESC;
2810
2811def BCLR_B : BCLR_B_ENC, BCLR_B_DESC;
2812def BCLR_H : BCLR_H_ENC, BCLR_H_DESC;
2813def BCLR_W : BCLR_W_ENC, BCLR_W_DESC;
2814def BCLR_D : BCLR_D_ENC, BCLR_D_DESC;
2815
2816def BCLRI_B : BCLRI_B_ENC, BCLRI_B_DESC;
2817def BCLRI_H : BCLRI_H_ENC, BCLRI_H_DESC;
2818def BCLRI_W : BCLRI_W_ENC, BCLRI_W_DESC;
2819def BCLRI_D : BCLRI_D_ENC, BCLRI_D_DESC;
2820
2821def BINSL_B : BINSL_B_ENC, BINSL_B_DESC;
2822def BINSL_H : BINSL_H_ENC, BINSL_H_DESC;
2823def BINSL_W : BINSL_W_ENC, BINSL_W_DESC;
2824def BINSL_D : BINSL_D_ENC, BINSL_D_DESC;
2825
2826def BINSLI_B : BINSLI_B_ENC, BINSLI_B_DESC;
2827def BINSLI_H : BINSLI_H_ENC, BINSLI_H_DESC;
2828def BINSLI_W : BINSLI_W_ENC, BINSLI_W_DESC;
2829def BINSLI_D : BINSLI_D_ENC, BINSLI_D_DESC;
2830
2831def BINSR_B : BINSR_B_ENC, BINSR_B_DESC;
2832def BINSR_H : BINSR_H_ENC, BINSR_H_DESC;
2833def BINSR_W : BINSR_W_ENC, BINSR_W_DESC;
2834def BINSR_D : BINSR_D_ENC, BINSR_D_DESC;
2835
2836def BINSRI_B : BINSRI_B_ENC, BINSRI_B_DESC;
2837def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC;
2838def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC;
2839def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC;
2840
2841def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC;
2842
2843def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC;
2844
2845def BMZ_V : BMZ_V_ENC, BMZ_V_DESC;
2846
2847def BMZI_B : BMZI_B_ENC, BMZI_B_DESC;
2848
2849def BNEG_B : BNEG_B_ENC, BNEG_B_DESC;
2850def BNEG_H : BNEG_H_ENC, BNEG_H_DESC;
2851def BNEG_W : BNEG_W_ENC, BNEG_W_DESC;
2852def BNEG_D : BNEG_D_ENC, BNEG_D_DESC;
2853
2854def BNEGI_B : BNEGI_B_ENC, BNEGI_B_DESC;
2855def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC;
2856def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC;
2857def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC;
2858
2859def BNZ_B : BNZ_B_ENC, BNZ_B_DESC;
2860def BNZ_H : BNZ_H_ENC, BNZ_H_DESC;
2861def BNZ_W : BNZ_W_ENC, BNZ_W_DESC;
2862def BNZ_D : BNZ_D_ENC, BNZ_D_DESC;
2863
2864def BNZ_V : BNZ_V_ENC, BNZ_V_DESC;
2865
2866def BSEL_V : BSEL_V_ENC, BSEL_V_DESC;
2867
2868class MSA_BSEL_PSEUDO_BASE<RegisterOperand RO, ValueType Ty> :
2869  MSAPseudo<(outs RO:$wd), (ins RO:$wd_in, RO:$ws, RO:$wt),
2870            [(set RO:$wd, (Ty (vselect RO:$wd_in, RO:$wt, RO:$ws)))]>,
2871  // Note that vselect and BSEL_V treat the condition operand the opposite way
2872  // from each other.
2873  //   (vselect cond, if_set, if_clear)
2874  //   (BSEL_V cond, if_clear, if_set)
2875  PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in,
2876                              MSA128BOpnd:$ws, MSA128BOpnd:$wt)> {
2877  let Constraints = "$wd_in = $wd";
2878}
2879
2880def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128HOpnd, v8i16>;
2881def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4i32>;
2882def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2i64>;
2883def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4f32>;
2884def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2f64>;
2885
2886def BSELI_B : BSELI_B_ENC, BSELI_B_DESC;
2887
2888def BSET_B : BSET_B_ENC, BSET_B_DESC;
2889def BSET_H : BSET_H_ENC, BSET_H_DESC;
2890def BSET_W : BSET_W_ENC, BSET_W_DESC;
2891def BSET_D : BSET_D_ENC, BSET_D_DESC;
2892
2893def BSETI_B : BSETI_B_ENC, BSETI_B_DESC;
2894def BSETI_H : BSETI_H_ENC, BSETI_H_DESC;
2895def BSETI_W : BSETI_W_ENC, BSETI_W_DESC;
2896def BSETI_D : BSETI_D_ENC, BSETI_D_DESC;
2897
2898def BZ_B : BZ_B_ENC, BZ_B_DESC;
2899def BZ_H : BZ_H_ENC, BZ_H_DESC;
2900def BZ_W : BZ_W_ENC, BZ_W_DESC;
2901def BZ_D : BZ_D_ENC, BZ_D_DESC;
2902
2903def BZ_V : BZ_V_ENC, BZ_V_DESC;
2904
2905def CEQ_B : CEQ_B_ENC, CEQ_B_DESC;
2906def CEQ_H : CEQ_H_ENC, CEQ_H_DESC;
2907def CEQ_W : CEQ_W_ENC, CEQ_W_DESC;
2908def CEQ_D : CEQ_D_ENC, CEQ_D_DESC;
2909
2910def CEQI_B : CEQI_B_ENC, CEQI_B_DESC;
2911def CEQI_H : CEQI_H_ENC, CEQI_H_DESC;
2912def CEQI_W : CEQI_W_ENC, CEQI_W_DESC;
2913def CEQI_D : CEQI_D_ENC, CEQI_D_DESC;
2914
2915def CFCMSA : CFCMSA_ENC, CFCMSA_DESC;
2916
2917def CLE_S_B : CLE_S_B_ENC, CLE_S_B_DESC;
2918def CLE_S_H : CLE_S_H_ENC, CLE_S_H_DESC;
2919def CLE_S_W : CLE_S_W_ENC, CLE_S_W_DESC;
2920def CLE_S_D : CLE_S_D_ENC, CLE_S_D_DESC;
2921
2922def CLE_U_B : CLE_U_B_ENC, CLE_U_B_DESC;
2923def CLE_U_H : CLE_U_H_ENC, CLE_U_H_DESC;
2924def CLE_U_W : CLE_U_W_ENC, CLE_U_W_DESC;
2925def CLE_U_D : CLE_U_D_ENC, CLE_U_D_DESC;
2926
2927def CLEI_S_B : CLEI_S_B_ENC, CLEI_S_B_DESC;
2928def CLEI_S_H : CLEI_S_H_ENC, CLEI_S_H_DESC;
2929def CLEI_S_W : CLEI_S_W_ENC, CLEI_S_W_DESC;
2930def CLEI_S_D : CLEI_S_D_ENC, CLEI_S_D_DESC;
2931
2932def CLEI_U_B : CLEI_U_B_ENC, CLEI_U_B_DESC;
2933def CLEI_U_H : CLEI_U_H_ENC, CLEI_U_H_DESC;
2934def CLEI_U_W : CLEI_U_W_ENC, CLEI_U_W_DESC;
2935def CLEI_U_D : CLEI_U_D_ENC, CLEI_U_D_DESC;
2936
2937def CLT_S_B : CLT_S_B_ENC, CLT_S_B_DESC;
2938def CLT_S_H : CLT_S_H_ENC, CLT_S_H_DESC;
2939def CLT_S_W : CLT_S_W_ENC, CLT_S_W_DESC;
2940def CLT_S_D : CLT_S_D_ENC, CLT_S_D_DESC;
2941
2942def CLT_U_B : CLT_U_B_ENC, CLT_U_B_DESC;
2943def CLT_U_H : CLT_U_H_ENC, CLT_U_H_DESC;
2944def CLT_U_W : CLT_U_W_ENC, CLT_U_W_DESC;
2945def CLT_U_D : CLT_U_D_ENC, CLT_U_D_DESC;
2946
2947def CLTI_S_B : CLTI_S_B_ENC, CLTI_S_B_DESC;
2948def CLTI_S_H : CLTI_S_H_ENC, CLTI_S_H_DESC;
2949def CLTI_S_W : CLTI_S_W_ENC, CLTI_S_W_DESC;
2950def CLTI_S_D : CLTI_S_D_ENC, CLTI_S_D_DESC;
2951
2952def CLTI_U_B : CLTI_U_B_ENC, CLTI_U_B_DESC;
2953def CLTI_U_H : CLTI_U_H_ENC, CLTI_U_H_DESC;
2954def CLTI_U_W : CLTI_U_W_ENC, CLTI_U_W_DESC;
2955def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC;
2956
2957def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC;
2958def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC;
2959def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC;
2960def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC, ASE_MSA64;
2961
2962def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC;
2963def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC;
2964def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC, ASE_MSA64;
2965
2966def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC;
2967def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC;
2968
2969def CTCMSA : CTCMSA_ENC, CTCMSA_DESC;
2970
2971def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC;
2972def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC;
2973def DIV_S_W : DIV_S_W_ENC, DIV_S_W_DESC;
2974def DIV_S_D : DIV_S_D_ENC, DIV_S_D_DESC;
2975
2976def DIV_U_B : DIV_U_B_ENC, DIV_U_B_DESC;
2977def DIV_U_H : DIV_U_H_ENC, DIV_U_H_DESC;
2978def DIV_U_W : DIV_U_W_ENC, DIV_U_W_DESC;
2979def DIV_U_D : DIV_U_D_ENC, DIV_U_D_DESC;
2980
2981def DOTP_S_H : DOTP_S_H_ENC, DOTP_S_H_DESC;
2982def DOTP_S_W : DOTP_S_W_ENC, DOTP_S_W_DESC;
2983def DOTP_S_D : DOTP_S_D_ENC, DOTP_S_D_DESC;
2984
2985def DOTP_U_H : DOTP_U_H_ENC, DOTP_U_H_DESC;
2986def DOTP_U_W : DOTP_U_W_ENC, DOTP_U_W_DESC;
2987def DOTP_U_D : DOTP_U_D_ENC, DOTP_U_D_DESC;
2988
2989def DPADD_S_H : DPADD_S_H_ENC, DPADD_S_H_DESC;
2990def DPADD_S_W : DPADD_S_W_ENC, DPADD_S_W_DESC;
2991def DPADD_S_D : DPADD_S_D_ENC, DPADD_S_D_DESC;
2992
2993def DPADD_U_H : DPADD_U_H_ENC, DPADD_U_H_DESC;
2994def DPADD_U_W : DPADD_U_W_ENC, DPADD_U_W_DESC;
2995def DPADD_U_D : DPADD_U_D_ENC, DPADD_U_D_DESC;
2996
2997def DPSUB_S_H : DPSUB_S_H_ENC, DPSUB_S_H_DESC;
2998def DPSUB_S_W : DPSUB_S_W_ENC, DPSUB_S_W_DESC;
2999def DPSUB_S_D : DPSUB_S_D_ENC, DPSUB_S_D_DESC;
3000
3001def DPSUB_U_H : DPSUB_U_H_ENC, DPSUB_U_H_DESC;
3002def DPSUB_U_W : DPSUB_U_W_ENC, DPSUB_U_W_DESC;
3003def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC;
3004
3005def FADD_W : FADD_W_ENC, FADD_W_DESC;
3006def FADD_D : FADD_D_ENC, FADD_D_DESC;
3007
3008def FCAF_W : FCAF_W_ENC, FCAF_W_DESC;
3009def FCAF_D : FCAF_D_ENC, FCAF_D_DESC;
3010
3011def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC;
3012def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC;
3013
3014def FCLE_W : FCLE_W_ENC, FCLE_W_DESC;
3015def FCLE_D : FCLE_D_ENC, FCLE_D_DESC;
3016
3017def FCLT_W : FCLT_W_ENC, FCLT_W_DESC;
3018def FCLT_D : FCLT_D_ENC, FCLT_D_DESC;
3019
3020def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC;
3021def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC;
3022
3023def FCNE_W : FCNE_W_ENC, FCNE_W_DESC;
3024def FCNE_D : FCNE_D_ENC, FCNE_D_DESC;
3025
3026def FCOR_W : FCOR_W_ENC, FCOR_W_DESC;
3027def FCOR_D : FCOR_D_ENC, FCOR_D_DESC;
3028
3029def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC;
3030def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC;
3031
3032def FCULE_W : FCULE_W_ENC, FCULE_W_DESC;
3033def FCULE_D : FCULE_D_ENC, FCULE_D_DESC;
3034
3035def FCULT_W : FCULT_W_ENC, FCULT_W_DESC;
3036def FCULT_D : FCULT_D_ENC, FCULT_D_DESC;
3037
3038def FCUN_W : FCUN_W_ENC, FCUN_W_DESC;
3039def FCUN_D : FCUN_D_ENC, FCUN_D_DESC;
3040
3041def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC;
3042def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC;
3043
3044def FDIV_W : FDIV_W_ENC, FDIV_W_DESC;
3045def FDIV_D : FDIV_D_ENC, FDIV_D_DESC;
3046
3047def FEXDO_H : FEXDO_H_ENC, FEXDO_H_DESC;
3048def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC;
3049
3050def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC;
3051def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC;
3052def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC;
3053def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC;
3054
3055def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC;
3056def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC;
3057
3058def FEXUPR_W : FEXUPR_W_ENC, FEXUPR_W_DESC;
3059def FEXUPR_D : FEXUPR_D_ENC, FEXUPR_D_DESC;
3060
3061def FFINT_S_W : FFINT_S_W_ENC, FFINT_S_W_DESC;
3062def FFINT_S_D : FFINT_S_D_ENC, FFINT_S_D_DESC;
3063
3064def FFINT_U_W : FFINT_U_W_ENC, FFINT_U_W_DESC;
3065def FFINT_U_D : FFINT_U_D_ENC, FFINT_U_D_DESC;
3066
3067def FFQL_W : FFQL_W_ENC, FFQL_W_DESC;
3068def FFQL_D : FFQL_D_ENC, FFQL_D_DESC;
3069
3070def FFQR_W : FFQR_W_ENC, FFQR_W_DESC;
3071def FFQR_D : FFQR_D_ENC, FFQR_D_DESC;
3072
3073def FILL_B : FILL_B_ENC, FILL_B_DESC;
3074def FILL_H : FILL_H_ENC, FILL_H_DESC;
3075def FILL_W : FILL_W_ENC, FILL_W_DESC;
3076def FILL_D : FILL_D_ENC, FILL_D_DESC, ASE_MSA64;
3077def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC;
3078def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC;
3079
3080def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC;
3081def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC;
3082
3083def FMADD_W : FMADD_W_ENC, FMADD_W_DESC;
3084def FMADD_D : FMADD_D_ENC, FMADD_D_DESC;
3085
3086def FMAX_W : FMAX_W_ENC, FMAX_W_DESC;
3087def FMAX_D : FMAX_D_ENC, FMAX_D_DESC;
3088
3089def FMAX_A_W : FMAX_A_W_ENC, FMAX_A_W_DESC;
3090def FMAX_A_D : FMAX_A_D_ENC, FMAX_A_D_DESC;
3091
3092def FMIN_W : FMIN_W_ENC, FMIN_W_DESC;
3093def FMIN_D : FMIN_D_ENC, FMIN_D_DESC;
3094
3095def FMIN_A_W : FMIN_A_W_ENC, FMIN_A_W_DESC;
3096def FMIN_A_D : FMIN_A_D_ENC, FMIN_A_D_DESC;
3097
3098def FMSUB_W : FMSUB_W_ENC, FMSUB_W_DESC;
3099def FMSUB_D : FMSUB_D_ENC, FMSUB_D_DESC;
3100
3101def FMUL_W : FMUL_W_ENC, FMUL_W_DESC;
3102def FMUL_D : FMUL_D_ENC, FMUL_D_DESC;
3103
3104def FRINT_W : FRINT_W_ENC, FRINT_W_DESC;
3105def FRINT_D : FRINT_D_ENC, FRINT_D_DESC;
3106
3107def FRCP_W : FRCP_W_ENC, FRCP_W_DESC;
3108def FRCP_D : FRCP_D_ENC, FRCP_D_DESC;
3109
3110def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC;
3111def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC;
3112
3113def FSAF_W : FSAF_W_ENC, FSAF_W_DESC;
3114def FSAF_D : FSAF_D_ENC, FSAF_D_DESC;
3115
3116def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC;
3117def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC;
3118
3119def FSLE_W : FSLE_W_ENC, FSLE_W_DESC;
3120def FSLE_D : FSLE_D_ENC, FSLE_D_DESC;
3121
3122def FSLT_W : FSLT_W_ENC, FSLT_W_DESC;
3123def FSLT_D : FSLT_D_ENC, FSLT_D_DESC;
3124
3125def FSNE_W : FSNE_W_ENC, FSNE_W_DESC;
3126def FSNE_D : FSNE_D_ENC, FSNE_D_DESC;
3127
3128def FSOR_W : FSOR_W_ENC, FSOR_W_DESC;
3129def FSOR_D : FSOR_D_ENC, FSOR_D_DESC;
3130
3131def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC;
3132def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC;
3133
3134def FSUB_W : FSUB_W_ENC, FSUB_W_DESC;
3135def FSUB_D : FSUB_D_ENC, FSUB_D_DESC;
3136
3137def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC;
3138def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC;
3139
3140def FSULE_W : FSULE_W_ENC, FSULE_W_DESC;
3141def FSULE_D : FSULE_D_ENC, FSULE_D_DESC;
3142
3143def FSULT_W : FSULT_W_ENC, FSULT_W_DESC;
3144def FSULT_D : FSULT_D_ENC, FSULT_D_DESC;
3145
3146def FSUN_W : FSUN_W_ENC, FSUN_W_DESC;
3147def FSUN_D : FSUN_D_ENC, FSUN_D_DESC;
3148
3149def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC;
3150def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC;
3151
3152def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC;
3153def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC;
3154
3155def FTINT_U_W : FTINT_U_W_ENC, FTINT_U_W_DESC;
3156def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC;
3157
3158def FTQ_H : FTQ_H_ENC, FTQ_H_DESC;
3159def FTQ_W : FTQ_W_ENC, FTQ_W_DESC;
3160
3161def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC;
3162def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC;
3163
3164def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC;
3165def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC;
3166
3167def : MipsPat<(fsub MSA128WOpnd:$wd, (fmul MSA128WOpnd:$ws, MSA128WOpnd:$wt)),
3168              (FMSUB_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, MSA128WOpnd:$wt)>,
3169              ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST;
3170def : MipsPat<(fsub MSA128DOpnd:$wd, (fmul MSA128DOpnd:$ws, MSA128DOpnd:$wt)),
3171              (FMSUB_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, MSA128DOpnd:$wt)>,
3172              ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST;
3173
3174def : MipsPat<(fadd MSA128WOpnd:$wd, (fmul MSA128WOpnd:$ws, MSA128WOpnd:$wt)),
3175              (FMADD_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, MSA128WOpnd:$wt)>,
3176              ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST;
3177def : MipsPat<(fadd MSA128DOpnd:$wd, (fmul MSA128DOpnd:$ws, MSA128DOpnd:$wt)),
3178              (FMADD_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, MSA128DOpnd:$wt)>,
3179              ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST;
3180
3181def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC;
3182def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC;
3183def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC;
3184
3185def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC;
3186def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC;
3187def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC;
3188
3189def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC;
3190def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC;
3191def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC;
3192
3193def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC;
3194def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC;
3195def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC;
3196
3197def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC;
3198def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC;
3199def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC;
3200def ILVEV_D : ILVEV_D_ENC, ILVEV_D_DESC;
3201
3202def ILVL_B : ILVL_B_ENC, ILVL_B_DESC;
3203def ILVL_H : ILVL_H_ENC, ILVL_H_DESC;
3204def ILVL_W : ILVL_W_ENC, ILVL_W_DESC;
3205def ILVL_D : ILVL_D_ENC, ILVL_D_DESC;
3206
3207def ILVOD_B : ILVOD_B_ENC, ILVOD_B_DESC;
3208def ILVOD_H : ILVOD_H_ENC, ILVOD_H_DESC;
3209def ILVOD_W : ILVOD_W_ENC, ILVOD_W_DESC;
3210def ILVOD_D : ILVOD_D_ENC, ILVOD_D_DESC;
3211
3212def ILVR_B : ILVR_B_ENC, ILVR_B_DESC;
3213def ILVR_H : ILVR_H_ENC, ILVR_H_DESC;
3214def ILVR_W : ILVR_W_ENC, ILVR_W_DESC;
3215def ILVR_D : ILVR_D_ENC, ILVR_D_DESC;
3216
3217def INSERT_B : INSERT_B_ENC, INSERT_B_DESC;
3218def INSERT_H : INSERT_H_ENC, INSERT_H_DESC;
3219def INSERT_W : INSERT_W_ENC, INSERT_W_DESC;
3220def INSERT_D : INSERT_D_ENC, INSERT_D_DESC, ASE_MSA64;
3221
3222// INSERT_FW_PSEUDO defined after INSVE_W
3223// INSERT_FD_PSEUDO defined after INSVE_D
3224
3225// There is a fourth operand that is not present in the encoding. Use a
3226// custom decoder to get a chance to add it.
3227let DecoderMethod = "DecodeINSVE_DF" in {
3228  def INSVE_B : INSVE_B_ENC, INSVE_B_DESC;
3229  def INSVE_H : INSVE_H_ENC, INSVE_H_DESC;
3230  def INSVE_W : INSVE_W_ENC, INSVE_W_DESC;
3231  def INSVE_D : INSVE_D_ENC, INSVE_D_DESC;
3232}
3233
3234def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC;
3235def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC;
3236
3237def INSERT_B_VIDX_PSEUDO : INSERT_B_VIDX_PSEUDO_DESC;
3238def INSERT_H_VIDX_PSEUDO : INSERT_H_VIDX_PSEUDO_DESC;
3239def INSERT_W_VIDX_PSEUDO : INSERT_W_VIDX_PSEUDO_DESC;
3240def INSERT_D_VIDX_PSEUDO : INSERT_D_VIDX_PSEUDO_DESC;
3241def INSERT_FW_VIDX_PSEUDO : INSERT_FW_VIDX_PSEUDO_DESC;
3242def INSERT_FD_VIDX_PSEUDO : INSERT_FD_VIDX_PSEUDO_DESC;
3243
3244def INSERT_B_VIDX64_PSEUDO : INSERT_B_VIDX64_PSEUDO_DESC;
3245def INSERT_H_VIDX64_PSEUDO : INSERT_H_VIDX64_PSEUDO_DESC;
3246def INSERT_W_VIDX64_PSEUDO : INSERT_W_VIDX64_PSEUDO_DESC;
3247def INSERT_D_VIDX64_PSEUDO : INSERT_D_VIDX64_PSEUDO_DESC;
3248def INSERT_FW_VIDX64_PSEUDO : INSERT_FW_VIDX64_PSEUDO_DESC;
3249def INSERT_FD_VIDX64_PSEUDO : INSERT_FD_VIDX64_PSEUDO_DESC;
3250
3251def LD_B: LD_B_ENC, LD_B_DESC;
3252def LD_H: LD_H_ENC, LD_H_DESC;
3253def LD_W: LD_W_ENC, LD_W_DESC;
3254def LD_D: LD_D_ENC, LD_D_DESC;
3255
3256def LDI_B : LDI_B_ENC, LDI_B_DESC;
3257def LDI_H : LDI_H_ENC, LDI_H_DESC;
3258def LDI_W : LDI_W_ENC, LDI_W_DESC;
3259def LDI_D : LDI_D_ENC, LDI_D_DESC;
3260
3261def LSA : LSA_ENC, LSA_DESC;
3262def DLSA : DLSA_ENC, DLSA_DESC, ASE_MSA64;
3263
3264def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC;
3265def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC;
3266
3267def MADDR_Q_H : MADDR_Q_H_ENC, MADDR_Q_H_DESC;
3268def MADDR_Q_W : MADDR_Q_W_ENC, MADDR_Q_W_DESC;
3269
3270def MADDV_B : MADDV_B_ENC, MADDV_B_DESC;
3271def MADDV_H : MADDV_H_ENC, MADDV_H_DESC;
3272def MADDV_W : MADDV_W_ENC, MADDV_W_DESC;
3273def MADDV_D : MADDV_D_ENC, MADDV_D_DESC;
3274
3275def MAX_A_B : MAX_A_B_ENC, MAX_A_B_DESC;
3276def MAX_A_H : MAX_A_H_ENC, MAX_A_H_DESC;
3277def MAX_A_W : MAX_A_W_ENC, MAX_A_W_DESC;
3278def MAX_A_D : MAX_A_D_ENC, MAX_A_D_DESC;
3279
3280def MAX_S_B : MAX_S_B_ENC, MAX_S_B_DESC;
3281def MAX_S_H : MAX_S_H_ENC, MAX_S_H_DESC;
3282def MAX_S_W : MAX_S_W_ENC, MAX_S_W_DESC;
3283def MAX_S_D : MAX_S_D_ENC, MAX_S_D_DESC;
3284
3285def MAX_U_B : MAX_U_B_ENC, MAX_U_B_DESC;
3286def MAX_U_H : MAX_U_H_ENC, MAX_U_H_DESC;
3287def MAX_U_W : MAX_U_W_ENC, MAX_U_W_DESC;
3288def MAX_U_D : MAX_U_D_ENC, MAX_U_D_DESC;
3289
3290def MAXI_S_B : MAXI_S_B_ENC, MAXI_S_B_DESC;
3291def MAXI_S_H : MAXI_S_H_ENC, MAXI_S_H_DESC;
3292def MAXI_S_W : MAXI_S_W_ENC, MAXI_S_W_DESC;
3293def MAXI_S_D : MAXI_S_D_ENC, MAXI_S_D_DESC;
3294
3295def MAXI_U_B : MAXI_U_B_ENC, MAXI_U_B_DESC;
3296def MAXI_U_H : MAXI_U_H_ENC, MAXI_U_H_DESC;
3297def MAXI_U_W : MAXI_U_W_ENC, MAXI_U_W_DESC;
3298def MAXI_U_D : MAXI_U_D_ENC, MAXI_U_D_DESC;
3299
3300def MIN_A_B : MIN_A_B_ENC, MIN_A_B_DESC;
3301def MIN_A_H : MIN_A_H_ENC, MIN_A_H_DESC;
3302def MIN_A_W : MIN_A_W_ENC, MIN_A_W_DESC;
3303def MIN_A_D : MIN_A_D_ENC, MIN_A_D_DESC;
3304
3305def MIN_S_B : MIN_S_B_ENC, MIN_S_B_DESC;
3306def MIN_S_H : MIN_S_H_ENC, MIN_S_H_DESC;
3307def MIN_S_W : MIN_S_W_ENC, MIN_S_W_DESC;
3308def MIN_S_D : MIN_S_D_ENC, MIN_S_D_DESC;
3309
3310def MIN_U_B : MIN_U_B_ENC, MIN_U_B_DESC;
3311def MIN_U_H : MIN_U_H_ENC, MIN_U_H_DESC;
3312def MIN_U_W : MIN_U_W_ENC, MIN_U_W_DESC;
3313def MIN_U_D : MIN_U_D_ENC, MIN_U_D_DESC;
3314
3315def MINI_S_B : MINI_S_B_ENC, MINI_S_B_DESC;
3316def MINI_S_H : MINI_S_H_ENC, MINI_S_H_DESC;
3317def MINI_S_W : MINI_S_W_ENC, MINI_S_W_DESC;
3318def MINI_S_D : MINI_S_D_ENC, MINI_S_D_DESC;
3319
3320def MINI_U_B : MINI_U_B_ENC, MINI_U_B_DESC;
3321def MINI_U_H : MINI_U_H_ENC, MINI_U_H_DESC;
3322def MINI_U_W : MINI_U_W_ENC, MINI_U_W_DESC;
3323def MINI_U_D : MINI_U_D_ENC, MINI_U_D_DESC;
3324
3325def MOD_S_B : MOD_S_B_ENC, MOD_S_B_DESC;
3326def MOD_S_H : MOD_S_H_ENC, MOD_S_H_DESC;
3327def MOD_S_W : MOD_S_W_ENC, MOD_S_W_DESC;
3328def MOD_S_D : MOD_S_D_ENC, MOD_S_D_DESC;
3329
3330def MOD_U_B : MOD_U_B_ENC, MOD_U_B_DESC;
3331def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC;
3332def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC;
3333def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC;
3334
3335def MOVE_V : MOVE_V_ENC, MOVE_V_DESC;
3336
3337def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC;
3338def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC;
3339
3340def MSUBR_Q_H : MSUBR_Q_H_ENC, MSUBR_Q_H_DESC;
3341def MSUBR_Q_W : MSUBR_Q_W_ENC, MSUBR_Q_W_DESC;
3342
3343def MSUBV_B : MSUBV_B_ENC, MSUBV_B_DESC;
3344def MSUBV_H : MSUBV_H_ENC, MSUBV_H_DESC;
3345def MSUBV_W : MSUBV_W_ENC, MSUBV_W_DESC;
3346def MSUBV_D : MSUBV_D_ENC, MSUBV_D_DESC;
3347
3348def MUL_Q_H : MUL_Q_H_ENC, MUL_Q_H_DESC;
3349def MUL_Q_W : MUL_Q_W_ENC, MUL_Q_W_DESC;
3350
3351def MULR_Q_H : MULR_Q_H_ENC, MULR_Q_H_DESC;
3352def MULR_Q_W : MULR_Q_W_ENC, MULR_Q_W_DESC;
3353
3354def MULV_B : MULV_B_ENC, MULV_B_DESC;
3355def MULV_H : MULV_H_ENC, MULV_H_DESC;
3356def MULV_W : MULV_W_ENC, MULV_W_DESC;
3357def MULV_D : MULV_D_ENC, MULV_D_DESC;
3358
3359def NLOC_B : NLOC_B_ENC, NLOC_B_DESC;
3360def NLOC_H : NLOC_H_ENC, NLOC_H_DESC;
3361def NLOC_W : NLOC_W_ENC, NLOC_W_DESC;
3362def NLOC_D : NLOC_D_ENC, NLOC_D_DESC;
3363
3364def NLZC_B : NLZC_B_ENC, NLZC_B_DESC;
3365def NLZC_H : NLZC_H_ENC, NLZC_H_DESC;
3366def NLZC_W : NLZC_W_ENC, NLZC_W_DESC;
3367def NLZC_D : NLZC_D_ENC, NLZC_D_DESC;
3368
3369def NOR_V : NOR_V_ENC, NOR_V_DESC;
3370def NOR_V_H_PSEUDO : NOR_V_H_PSEUDO_DESC,
3371                     PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3372                                                MSA128BOpnd:$ws,
3373                                                MSA128BOpnd:$wt)>;
3374def NOR_V_W_PSEUDO : NOR_V_W_PSEUDO_DESC,
3375                     PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3376                                                MSA128BOpnd:$ws,
3377                                                MSA128BOpnd:$wt)>;
3378def NOR_V_D_PSEUDO : NOR_V_D_PSEUDO_DESC,
3379                     PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3380                                                MSA128BOpnd:$ws,
3381                                                MSA128BOpnd:$wt)>;
3382
3383def NORI_B : NORI_B_ENC, NORI_B_DESC;
3384
3385def OR_V : OR_V_ENC, OR_V_DESC;
3386def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC,
3387                    PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3388                                              MSA128BOpnd:$ws,
3389                                              MSA128BOpnd:$wt)>;
3390def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC,
3391                    PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3392                                              MSA128BOpnd:$ws,
3393                                              MSA128BOpnd:$wt)>;
3394def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC,
3395                    PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3396                                              MSA128BOpnd:$ws,
3397                                              MSA128BOpnd:$wt)>;
3398
3399def ORI_B : ORI_B_ENC, ORI_B_DESC;
3400
3401def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC;
3402def PCKEV_H : PCKEV_H_ENC, PCKEV_H_DESC;
3403def PCKEV_W : PCKEV_W_ENC, PCKEV_W_DESC;
3404def PCKEV_D : PCKEV_D_ENC, PCKEV_D_DESC;
3405
3406def PCKOD_B : PCKOD_B_ENC, PCKOD_B_DESC;
3407def PCKOD_H : PCKOD_H_ENC, PCKOD_H_DESC;
3408def PCKOD_W : PCKOD_W_ENC, PCKOD_W_DESC;
3409def PCKOD_D : PCKOD_D_ENC, PCKOD_D_DESC;
3410
3411def PCNT_B : PCNT_B_ENC, PCNT_B_DESC;
3412def PCNT_H : PCNT_H_ENC, PCNT_H_DESC;
3413def PCNT_W : PCNT_W_ENC, PCNT_W_DESC;
3414def PCNT_D : PCNT_D_ENC, PCNT_D_DESC;
3415
3416def SAT_S_B : SAT_S_B_ENC, SAT_S_B_DESC;
3417def SAT_S_H : SAT_S_H_ENC, SAT_S_H_DESC;
3418def SAT_S_W : SAT_S_W_ENC, SAT_S_W_DESC;
3419def SAT_S_D : SAT_S_D_ENC, SAT_S_D_DESC;
3420
3421def SAT_U_B : SAT_U_B_ENC, SAT_U_B_DESC;
3422def SAT_U_H : SAT_U_H_ENC, SAT_U_H_DESC;
3423def SAT_U_W : SAT_U_W_ENC, SAT_U_W_DESC;
3424def SAT_U_D : SAT_U_D_ENC, SAT_U_D_DESC;
3425
3426def SHF_B : SHF_B_ENC, SHF_B_DESC;
3427def SHF_H : SHF_H_ENC, SHF_H_DESC;
3428def SHF_W : SHF_W_ENC, SHF_W_DESC;
3429
3430def SLD_B : SLD_B_ENC, SLD_B_DESC;
3431def SLD_H : SLD_H_ENC, SLD_H_DESC;
3432def SLD_W : SLD_W_ENC, SLD_W_DESC;
3433def SLD_D : SLD_D_ENC, SLD_D_DESC;
3434
3435def SLDI_B : SLDI_B_ENC, SLDI_B_DESC;
3436def SLDI_H : SLDI_H_ENC, SLDI_H_DESC;
3437def SLDI_W : SLDI_W_ENC, SLDI_W_DESC;
3438def SLDI_D : SLDI_D_ENC, SLDI_D_DESC;
3439
3440def SLL_B : SLL_B_ENC, SLL_B_DESC;
3441def SLL_H : SLL_H_ENC, SLL_H_DESC;
3442def SLL_W : SLL_W_ENC, SLL_W_DESC;
3443def SLL_D : SLL_D_ENC, SLL_D_DESC;
3444
3445def SLLI_B : SLLI_B_ENC, SLLI_B_DESC;
3446def SLLI_H : SLLI_H_ENC, SLLI_H_DESC;
3447def SLLI_W : SLLI_W_ENC, SLLI_W_DESC;
3448def SLLI_D : SLLI_D_ENC, SLLI_D_DESC;
3449
3450def SPLAT_B : SPLAT_B_ENC, SPLAT_B_DESC;
3451def SPLAT_H : SPLAT_H_ENC, SPLAT_H_DESC;
3452def SPLAT_W : SPLAT_W_ENC, SPLAT_W_DESC;
3453def SPLAT_D : SPLAT_D_ENC, SPLAT_D_DESC;
3454
3455def SPLATI_B : SPLATI_B_ENC, SPLATI_B_DESC;
3456def SPLATI_H : SPLATI_H_ENC, SPLATI_H_DESC;
3457def SPLATI_W : SPLATI_W_ENC, SPLATI_W_DESC;
3458def SPLATI_D : SPLATI_D_ENC, SPLATI_D_DESC;
3459
3460def SRA_B : SRA_B_ENC, SRA_B_DESC;
3461def SRA_H : SRA_H_ENC, SRA_H_DESC;
3462def SRA_W : SRA_W_ENC, SRA_W_DESC;
3463def SRA_D : SRA_D_ENC, SRA_D_DESC;
3464
3465def SRAI_B : SRAI_B_ENC, SRAI_B_DESC;
3466def SRAI_H : SRAI_H_ENC, SRAI_H_DESC;
3467def SRAI_W : SRAI_W_ENC, SRAI_W_DESC;
3468def SRAI_D : SRAI_D_ENC, SRAI_D_DESC;
3469
3470def SRAR_B : SRAR_B_ENC, SRAR_B_DESC;
3471def SRAR_H : SRAR_H_ENC, SRAR_H_DESC;
3472def SRAR_W : SRAR_W_ENC, SRAR_W_DESC;
3473def SRAR_D : SRAR_D_ENC, SRAR_D_DESC;
3474
3475def SRARI_B : SRARI_B_ENC, SRARI_B_DESC;
3476def SRARI_H : SRARI_H_ENC, SRARI_H_DESC;
3477def SRARI_W : SRARI_W_ENC, SRARI_W_DESC;
3478def SRARI_D : SRARI_D_ENC, SRARI_D_DESC;
3479
3480def SRL_B : SRL_B_ENC, SRL_B_DESC;
3481def SRL_H : SRL_H_ENC, SRL_H_DESC;
3482def SRL_W : SRL_W_ENC, SRL_W_DESC;
3483def SRL_D : SRL_D_ENC, SRL_D_DESC;
3484
3485def SRLI_B : SRLI_B_ENC, SRLI_B_DESC;
3486def SRLI_H : SRLI_H_ENC, SRLI_H_DESC;
3487def SRLI_W : SRLI_W_ENC, SRLI_W_DESC;
3488def SRLI_D : SRLI_D_ENC, SRLI_D_DESC;
3489
3490def SRLR_B : SRLR_B_ENC, SRLR_B_DESC;
3491def SRLR_H : SRLR_H_ENC, SRLR_H_DESC;
3492def SRLR_W : SRLR_W_ENC, SRLR_W_DESC;
3493def SRLR_D : SRLR_D_ENC, SRLR_D_DESC;
3494
3495def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC;
3496def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC;
3497def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC;
3498def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC;
3499
3500def ST_B: ST_B_ENC, ST_B_DESC;
3501def ST_H: ST_H_ENC, ST_H_DESC;
3502def ST_W: ST_W_ENC, ST_W_DESC;
3503def ST_D: ST_D_ENC, ST_D_DESC;
3504
3505def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC;
3506def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC;
3507def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC;
3508def SUBS_S_D : SUBS_S_D_ENC, SUBS_S_D_DESC;
3509
3510def SUBS_U_B : SUBS_U_B_ENC, SUBS_U_B_DESC;
3511def SUBS_U_H : SUBS_U_H_ENC, SUBS_U_H_DESC;
3512def SUBS_U_W : SUBS_U_W_ENC, SUBS_U_W_DESC;
3513def SUBS_U_D : SUBS_U_D_ENC, SUBS_U_D_DESC;
3514
3515def SUBSUS_U_B : SUBSUS_U_B_ENC, SUBSUS_U_B_DESC;
3516def SUBSUS_U_H : SUBSUS_U_H_ENC, SUBSUS_U_H_DESC;
3517def SUBSUS_U_W : SUBSUS_U_W_ENC, SUBSUS_U_W_DESC;
3518def SUBSUS_U_D : SUBSUS_U_D_ENC, SUBSUS_U_D_DESC;
3519
3520def SUBSUU_S_B : SUBSUU_S_B_ENC, SUBSUU_S_B_DESC;
3521def SUBSUU_S_H : SUBSUU_S_H_ENC, SUBSUU_S_H_DESC;
3522def SUBSUU_S_W : SUBSUU_S_W_ENC, SUBSUU_S_W_DESC;
3523def SUBSUU_S_D : SUBSUU_S_D_ENC, SUBSUU_S_D_DESC;
3524
3525def SUBV_B : SUBV_B_ENC, SUBV_B_DESC;
3526def SUBV_H : SUBV_H_ENC, SUBV_H_DESC;
3527def SUBV_W : SUBV_W_ENC, SUBV_W_DESC;
3528def SUBV_D : SUBV_D_ENC, SUBV_D_DESC;
3529
3530def SUBVI_B : SUBVI_B_ENC, SUBVI_B_DESC;
3531def SUBVI_H : SUBVI_H_ENC, SUBVI_H_DESC;
3532def SUBVI_W : SUBVI_W_ENC, SUBVI_W_DESC;
3533def SUBVI_D : SUBVI_D_ENC, SUBVI_D_DESC;
3534
3535def VSHF_B : VSHF_B_ENC, VSHF_B_DESC;
3536def VSHF_H : VSHF_H_ENC, VSHF_H_DESC;
3537def VSHF_W : VSHF_W_ENC, VSHF_W_DESC;
3538def VSHF_D : VSHF_D_ENC, VSHF_D_DESC;
3539
3540def XOR_V : XOR_V_ENC, XOR_V_DESC;
3541def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC,
3542                     PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3543                                                MSA128BOpnd:$ws,
3544                                                MSA128BOpnd:$wt)>;
3545def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC,
3546                     PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3547                                                MSA128BOpnd:$ws,
3548                                                MSA128BOpnd:$wt)>;
3549def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC,
3550                     PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3551                                                MSA128BOpnd:$ws,
3552                                                MSA128BOpnd:$wt)>;
3553
3554def XORI_B : XORI_B_ENC, XORI_B_DESC;
3555
3556// Patterns.
3557class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> :
3558  Pat<pattern, result>, Requires<pred>;
3559
3560def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx),
3561             (COPY_S_W MSA128W:$ws, immZExt4:$idx)>;
3562
3563def : MSAPat<(v8f16 (load addrimm10lsl1:$addr)), (LD_H addrimm10lsl1:$addr)>;
3564def : MSAPat<(v4f32 (load addrimm10lsl2:$addr)), (LD_W addrimm10lsl2:$addr)>;
3565def : MSAPat<(v2f64 (load addrimm10lsl3:$addr)), (LD_D addrimm10lsl3:$addr)>;
3566
3567def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10lsl1:$addr),
3568                   (ST_H MSA128H:$ws, addrimm10lsl1:$addr)>;
3569def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrimm10lsl2:$addr),
3570                   (ST_W MSA128W:$ws, addrimm10lsl2:$addr)>;
3571def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrimm10lsl3:$addr),
3572                   (ST_D MSA128D:$ws, addrimm10lsl3:$addr)>;
3573
3574class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD,
3575                                RegisterOperand ROWS = ROWD,
3576                                InstrItinClass itin = NoItinerary> :
3577  MSAPseudo<(outs ROWD:$wd),
3578            (ins ROWS:$ws),
3579            [(set ROWD:$wd, (fabs ROWS:$ws))]> {
3580  InstrItinClass Itinerary = itin;
3581}
3582def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>,
3583             PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws,
3584                                           MSA128WOpnd:$ws)>;
3585def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128DOpnd>,
3586             PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws,
3587                                           MSA128DOpnd:$ws)>;
3588
3589class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3590                       RegisterClass DstRC, list<Predicate> preds = [HasMSA]> :
3591   MSAPat<(DstVT (bitconvert SrcVT:$src)),
3592          (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3593
3594// These are endian-independent because the element size doesnt change
3595def : MSABitconvertPat<v8i16, v8f16, MSA128H>;
3596def : MSABitconvertPat<v4i32, v4f32, MSA128W>;
3597def : MSABitconvertPat<v2i64, v2f64, MSA128D>;
3598def : MSABitconvertPat<v8f16, v8i16, MSA128H>;
3599def : MSABitconvertPat<v4f32, v4i32, MSA128W>;
3600def : MSABitconvertPat<v2f64, v2i64, MSA128D>;
3601
3602// Little endian bitcasts are always no-ops
3603def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>;
3604def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>;
3605def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>;
3606def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>;
3607def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>;
3608def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>;
3609
3610def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>;
3611def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>;
3612def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>;
3613def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>;
3614def : MSABitconvertPat<v8i16, v2f64, MSA128H, [HasMSA, IsLE]>;
3615
3616def : MSABitconvertPat<v4i32, v16i8, MSA128W, [HasMSA, IsLE]>;
3617def : MSABitconvertPat<v4i32, v8i16, MSA128W, [HasMSA, IsLE]>;
3618def : MSABitconvertPat<v4i32, v2i64, MSA128W, [HasMSA, IsLE]>;
3619def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>;
3620def : MSABitconvertPat<v4i32, v2f64, MSA128W, [HasMSA, IsLE]>;
3621
3622def : MSABitconvertPat<v2i64, v16i8, MSA128D, [HasMSA, IsLE]>;
3623def : MSABitconvertPat<v2i64, v8i16, MSA128D, [HasMSA, IsLE]>;
3624def : MSABitconvertPat<v2i64, v4i32, MSA128D, [HasMSA, IsLE]>;
3625def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>;
3626def : MSABitconvertPat<v2i64, v4f32, MSA128D, [HasMSA, IsLE]>;
3627
3628def : MSABitconvertPat<v4f32, v16i8, MSA128W, [HasMSA, IsLE]>;
3629def : MSABitconvertPat<v4f32, v8i16, MSA128W, [HasMSA, IsLE]>;
3630def : MSABitconvertPat<v4f32, v2i64, MSA128W, [HasMSA, IsLE]>;
3631def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>;
3632def : MSABitconvertPat<v4f32, v2f64, MSA128W, [HasMSA, IsLE]>;
3633
3634def : MSABitconvertPat<v2f64, v16i8, MSA128D, [HasMSA, IsLE]>;
3635def : MSABitconvertPat<v2f64, v8i16, MSA128D, [HasMSA, IsLE]>;
3636def : MSABitconvertPat<v2f64, v4i32, MSA128D, [HasMSA, IsLE]>;
3637def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>;
3638def : MSABitconvertPat<v2f64, v4f32, MSA128D, [HasMSA, IsLE]>;
3639
3640// Big endian bitcasts expand to shuffle instructions.
3641// This is because bitcast is defined to be a store/load sequence and the
3642// vector store/load instructions are mixed-endian with respect to the vector
3643// as a whole (little endian with respect to element order, but big endian
3644// elements).
3645
3646class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3647                                      RegisterClass DstRC, MSAInst Insn,
3648                                      RegisterClass ViaRC> :
3649  MSAPat<(DstVT (bitconvert SrcVT:$src)),
3650         (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27),
3651                           DstRC),
3652         [HasMSA, IsBE]>;
3653
3654class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3655                                    RegisterClass DstRC, MSAInst Insn,
3656                                    RegisterClass ViaRC> :
3657  MSAPat<(DstVT (bitconvert SrcVT:$src)),
3658         (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177),
3659                           DstRC),
3660         [HasMSA, IsBE]>;
3661
3662class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
3663                                  RegisterClass DstRC> :
3664  MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3665
3666class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
3667                                  RegisterClass DstRC> :
3668  MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3669
3670class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT,
3671                                  RegisterClass DstRC> :
3672  MSAPat<(DstVT (bitconvert SrcVT:$src)),
3673         (COPY_TO_REGCLASS
3674           (SHF_W
3675             (COPY_TO_REGCLASS
3676               (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27),
3677               MSA128W), 177),
3678           DstRC),
3679         [HasMSA, IsBE]>;
3680
3681class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT,
3682                                  RegisterClass DstRC> :
3683  MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3684
3685class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT,
3686                                  RegisterClass DstRC> :
3687  MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3688
3689class MSABitconvertReverseWInDPat<ValueType DstVT, ValueType SrcVT,
3690                                  RegisterClass DstRC> :
3691  MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_W, MSA128W>;
3692
3693def : MSABitconvertReverseBInHPat<v8i16, v16i8, MSA128H>;
3694def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>;
3695def : MSABitconvertReverseBInWPat<v4i32, v16i8, MSA128W>;
3696def : MSABitconvertReverseBInWPat<v4f32, v16i8, MSA128W>;
3697def : MSABitconvertReverseBInDPat<v2i64, v16i8, MSA128D>;
3698def : MSABitconvertReverseBInDPat<v2f64, v16i8, MSA128D>;
3699
3700def : MSABitconvertReverseBInHPat<v16i8, v8i16, MSA128B>;
3701def : MSABitconvertReverseHInWPat<v4i32, v8i16, MSA128W>;
3702def : MSABitconvertReverseHInWPat<v4f32, v8i16, MSA128W>;
3703def : MSABitconvertReverseHInDPat<v2i64, v8i16, MSA128D>;
3704def : MSABitconvertReverseHInDPat<v2f64, v8i16, MSA128D>;
3705
3706def : MSABitconvertReverseBInHPat<v16i8, v8f16, MSA128B>;
3707def : MSABitconvertReverseHInWPat<v4i32, v8f16, MSA128W>;
3708def : MSABitconvertReverseHInWPat<v4f32, v8f16, MSA128W>;
3709def : MSABitconvertReverseHInDPat<v2i64, v8f16, MSA128D>;
3710def : MSABitconvertReverseHInDPat<v2f64, v8f16, MSA128D>;
3711
3712def : MSABitconvertReverseBInWPat<v16i8, v4i32, MSA128B>;
3713def : MSABitconvertReverseHInWPat<v8i16, v4i32, MSA128H>;
3714def : MSABitconvertReverseHInWPat<v8f16, v4i32, MSA128H>;
3715def : MSABitconvertReverseWInDPat<v2i64, v4i32, MSA128D>;
3716def : MSABitconvertReverseWInDPat<v2f64, v4i32, MSA128D>;
3717
3718def : MSABitconvertReverseBInWPat<v16i8, v4f32, MSA128B>;
3719def : MSABitconvertReverseHInWPat<v8i16, v4f32, MSA128H>;
3720def : MSABitconvertReverseHInWPat<v8f16, v4f32, MSA128H>;
3721def : MSABitconvertReverseWInDPat<v2i64, v4f32, MSA128D>;
3722def : MSABitconvertReverseWInDPat<v2f64, v4f32, MSA128D>;
3723
3724def : MSABitconvertReverseBInDPat<v16i8, v2i64, MSA128B>;
3725def : MSABitconvertReverseHInDPat<v8i16, v2i64, MSA128H>;
3726def : MSABitconvertReverseHInDPat<v8f16, v2i64, MSA128H>;
3727def : MSABitconvertReverseWInDPat<v4i32, v2i64, MSA128W>;
3728def : MSABitconvertReverseWInDPat<v4f32, v2i64, MSA128W>;
3729
3730def : MSABitconvertReverseBInDPat<v16i8, v2f64, MSA128B>;
3731def : MSABitconvertReverseHInDPat<v8i16, v2f64, MSA128H>;
3732def : MSABitconvertReverseHInDPat<v8f16, v2f64, MSA128H>;
3733def : MSABitconvertReverseWInDPat<v4i32, v2f64, MSA128W>;
3734def : MSABitconvertReverseWInDPat<v4f32, v2f64, MSA128W>;
3735
3736// Pseudos used to implement BNZ.df, and BZ.df
3737
3738class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode,
3739                                   RegisterClass RCWS> :
3740  MipsPseudo<(outs GPR32:$dst),
3741             (ins RCWS:$ws),
3742             [(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> {
3743  bit usesCustomInserter = 1;
3744  bit hasNoSchedulingInfo = 1;
3745}
3746
3747def SNZ_B_PSEUDO
3748    : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8, MSA128B>;
3749def SNZ_H_PSEUDO
3750    : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16, MSA128H>;
3751def SNZ_W_PSEUDO
3752    : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32, MSA128W>;
3753def SNZ_D_PSEUDO
3754    : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64, MSA128D>;
3755def SNZ_V_PSEUDO
3756    : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8, MSA128B>;
3757
3758def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8, MSA128B>;
3759def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16, MSA128H>;
3760def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32, MSA128W>;
3761def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64, MSA128D>;
3762def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8, MSA128B>;
3763
3764// Pseudoes used to implement transparent fp16 support.
3765
3766let ASEPredicate = [HasMSA] in {
3767  let usesCustomInserter = 1 in {
3768    def ST_F16 :
3769        MipsPseudo<(outs), (ins MSA128F16:$ws, mem_simm10:$addr),
3770                   [(store (f16 MSA128F16:$ws), (addrimm10:$addr))]>;
3771    def LD_F16 :
3772        MipsPseudo<(outs MSA128F16:$ws), (ins mem_simm10:$addr),
3773                   [(set MSA128F16:$ws, (f16 (load addrimm10:$addr)))]>;
3774  }
3775
3776  let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
3777    def MSA_FP_EXTEND_W_PSEUDO :
3778        MipsPseudo<(outs FGR32Opnd:$fd), (ins MSA128F16:$ws),
3779                   [(set FGR32Opnd:$fd, (f32 (fpextend MSA128F16:$ws)))]>;
3780    def MSA_FP_ROUND_W_PSEUDO :
3781        MipsPseudo<(outs MSA128F16:$wd), (ins FGR32Opnd:$fs),
3782                   [(set MSA128F16:$wd, (f16 (fpround FGR32Opnd:$fs)))]>;
3783    def MSA_FP_EXTEND_D_PSEUDO :
3784        MipsPseudo<(outs FGR64Opnd:$fd), (ins MSA128F16:$ws),
3785                   [(set FGR64Opnd:$fd, (f64 (fpextend MSA128F16:$ws)))]>;
3786    def MSA_FP_ROUND_D_PSEUDO :
3787        MipsPseudo<(outs MSA128F16:$wd), (ins FGR64Opnd:$fs),
3788                   [(set MSA128F16:$wd, (f16 (fpround FGR64Opnd:$fs)))]>;
3789  }
3790
3791  def : MipsPat<(MipsTruncIntFP MSA128F16:$ws),
3792                (TRUNC_W_D64 (MSA_FP_EXTEND_D_PSEUDO MSA128F16:$ws))>,
3793        ISA_MIPS1, ASE_MSA;
3794
3795  def : MipsPat<(MipsFPCmp MSA128F16:$ws, MSA128F16:$wt, imm:$cond),
3796                (FCMP_S32 (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$ws),
3797                          (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$wt), imm:$cond)>,
3798        ISA_MIPS1_NOT_32R6_64R6, ASE_MSA;
3799}
3800
3801def vsplati64_imm_eq_63 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{
3802  APInt Imm;
3803  SDNode *BV = N->getOperand(0).getNode();
3804  EVT EltTy = N->getValueType(0).getVectorElementType();
3805
3806  return selectVSplat(BV, Imm, EltTy.getSizeInBits()) &&
3807         Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 63;
3808}]>;
3809
3810def immi32Cst7  : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 7;}]>;
3811def immi32Cst15 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 15;}]>;
3812def immi32Cst31 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 31;}]>;
3813
3814def vsplati8imm7 :   PatFrag<(ops node:$wt),
3815                             (and node:$wt, (vsplati8 immi32Cst7))>;
3816def vsplati16imm15 : PatFrag<(ops node:$wt),
3817                             (and node:$wt, (vsplati16 immi32Cst15))>;
3818def vsplati32imm31 : PatFrag<(ops node:$wt),
3819                             (and node:$wt, (vsplati32 immi32Cst31))>;
3820def vsplati64imm63 : PatFrag<(ops node:$wt),
3821                             (and node:$wt, vsplati64_imm_eq_63)>;
3822
3823class MSAShiftPat<SDNode Node, ValueType VT, MSAInst Insn, dag Vec> :
3824  MSAPat<(VT (Node VT:$ws, (VT (and VT:$wt, Vec)))),
3825         (VT (Insn VT:$ws, VT:$wt))>;
3826
3827class MSABitPat<SDNode Node, ValueType VT, MSAInst Insn, PatFrag Frag> :
3828  MSAPat<(VT (Node VT:$ws, (shl (vsplat_imm_eq_1), (Frag VT:$wt)))),
3829         (VT (Insn VT:$ws, VT:$wt))>;
3830
3831multiclass MSAShiftPats<SDNode Node, string Insn> {
3832  def : MSAShiftPat<Node, v16i8, !cast<MSAInst>(Insn#_B),
3833                    (vsplati8 immi32Cst7)>;
3834  def : MSAShiftPat<Node, v8i16, !cast<MSAInst>(Insn#_H),
3835                    (vsplati16 immi32Cst15)>;
3836  def : MSAShiftPat<Node, v4i32, !cast<MSAInst>(Insn#_W),
3837                    (vsplati32 immi32Cst31)>;
3838  def : MSAPat<(v2i64 (Node v2i64:$ws, (v2i64 (and v2i64:$wt,
3839                                                   vsplati64_imm_eq_63)))),
3840               (v2i64 (!cast<MSAInst>(Insn#_D) v2i64:$ws, v2i64:$wt))>;
3841}
3842
3843multiclass MSABitPats<SDNode Node, string Insn> {
3844  def : MSABitPat<Node, v16i8, !cast<MSAInst>(Insn#_B), vsplati8imm7>;
3845  def : MSABitPat<Node, v8i16, !cast<MSAInst>(Insn#_H), vsplati16imm15>;
3846  def : MSABitPat<Node, v4i32, !cast<MSAInst>(Insn#_W), vsplati32imm31>;
3847  def : MSAPat<(Node v2i64:$ws, (shl (v2i64 (vsplat_imm_eq_1)),
3848                                     (vsplati64imm63 v2i64:$wt))),
3849               (v2i64 (!cast<MSAInst>(Insn#_D) v2i64:$ws, v2i64:$wt))>;
3850}
3851
3852defm : MSAShiftPats<shl, "SLL">;
3853defm : MSAShiftPats<srl, "SRL">;
3854defm : MSAShiftPats<sra, "SRA">;
3855defm : MSABitPats<xor, "BNEG">;
3856defm : MSABitPats<or, "BSET">;
3857
3858def : MSAPat<(and v16i8:$ws, (vnot (shl (vsplat_imm_eq_1),
3859                                        (vsplati8imm7 v16i8:$wt)))),
3860             (v16i8 (BCLR_B v16i8:$ws, v16i8:$wt))>;
3861def : MSAPat<(and v8i16:$ws, (vnot (shl (vsplat_imm_eq_1),
3862                                        (vsplati16imm15 v8i16:$wt)))),
3863             (v8i16 (BCLR_H v8i16:$ws, v8i16:$wt))>;
3864def : MSAPat<(and v4i32:$ws, (vnot (shl (vsplat_imm_eq_1),
3865                                        (vsplati32imm31 v4i32:$wt)))),
3866             (v4i32 (BCLR_W v4i32:$ws, v4i32:$wt))>;
3867def : MSAPat<(and v2i64:$ws, (vnot (shl (v2i64 (vsplat_imm_eq_1)),
3868                                        (vsplati64imm63 v2i64:$wt)))),
3869             (v2i64 (BCLR_D v2i64:$ws, v2i64:$wt))>;
3870
3871// Vector extraction with fixed index.
3872//
3873// Extracting 32-bit values on MSA32 should always use COPY_S_W rather than
3874// COPY_U_W, even for the zero-extended case. This is because our forward
3875// compatibility strategy is to consider registers to be infinitely
3876// sign-extended so that a MIPS64 can execute MIPS32 code without getting
3877// different register values.
3878def : MSAPat<(vextract_zext_i32 (v4i32 MSA128W:$ws), immZExt2Ptr:$idx),
3879             (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64;
3880def : MSAPat<(vextract_zext_i32 (v4f32 MSA128W:$ws), immZExt2Ptr:$idx),
3881             (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64;
3882
3883// Extracting 64-bit values on MSA64 should always use COPY_S_D rather than
3884// COPY_U_D, even for the zero-extended case. This is because our forward
3885// compatibility strategy is to consider registers to be infinitely
3886// sign-extended so that a hypothetical MIPS128 would be able to execute MIPS64
3887// code without getting different register values.
3888def : MSAPat<(vextract_zext_i64 (v2i64 MSA128D:$ws), immZExt1Ptr:$idx),
3889             (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64;
3890def : MSAPat<(vextract_zext_i64 (v2f64 MSA128D:$ws), immZExt1Ptr:$idx),
3891             (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64;
3892
3893// Vector extraction with variable index
3894def : MSAPat<(i32 (vextract_sext_i8 v16i8:$ws, i32:$idx)),
3895             (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
3896                                                                  i32:$idx),
3897                                                         sub_lo)),
3898                                    GPR32), (i32 24))>;
3899def : MSAPat<(i32 (vextract_sext_i16 v8i16:$ws, i32:$idx)),
3900             (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
3901                                                                  i32:$idx),
3902                                                         sub_lo)),
3903                                    GPR32), (i32 16))>;
3904def : MSAPat<(i32 (vextract_sext_i32 v4i32:$ws, i32:$idx)),
3905             (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
3906                                                             i32:$idx),
3907                                                    sub_lo)),
3908                               GPR32)>;
3909def : MSAPat<(i64 (vextract_sext_i64 v2i64:$ws, i32:$idx)),
3910             (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
3911                                                             i32:$idx),
3912                                                    sub_64)),
3913                               GPR64), [HasMSA, IsGP64bit]>;
3914
3915def : MSAPat<(i32 (vextract_zext_i8 v16i8:$ws, i32:$idx)),
3916             (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
3917                                                                  i32:$idx),
3918                                                         sub_lo)),
3919                                    GPR32), (i32 24))>;
3920def : MSAPat<(i32 (vextract_zext_i16 v8i16:$ws, i32:$idx)),
3921             (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
3922                                                                  i32:$idx),
3923                                                         sub_lo)),
3924                                    GPR32), (i32 16))>;
3925def : MSAPat<(i32 (vextract_zext_i32 v4i32:$ws, i32:$idx)),
3926             (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
3927                                                             i32:$idx),
3928                                                    sub_lo)),
3929                               GPR32)>;
3930def : MSAPat<(i64 (vextract_zext_i64 v2i64:$ws, i32:$idx)),
3931             (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
3932                                                             i32:$idx),
3933                                                    sub_64)),
3934                               GPR64), [HasMSA, IsGP64bit]>;
3935
3936def : MSAPat<(f32 (vector_extract v4f32:$ws, i32:$idx)),
3937             (f32 (EXTRACT_SUBREG (SPLAT_W v4f32:$ws,
3938                                           i32:$idx),
3939                                  sub_lo))>;
3940def : MSAPat<(f64 (vector_extract v2f64:$ws, i32:$idx)),
3941             (f64 (EXTRACT_SUBREG (SPLAT_D v2f64:$ws,
3942                                           i32:$idx),
3943                                  sub_64))>;
3944
3945// Vector extraction with variable index (N64 ABI)
3946def : MSAPat<
3947  (i32 (vextract_sext_i8 v16i8:$ws, i64:$idx)),
3948  (SRA (COPY_TO_REGCLASS
3949         (i32 (EXTRACT_SUBREG
3950                (SPLAT_B v16i8:$ws,
3951                  (COPY_TO_REGCLASS
3952                    (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3953                sub_lo)),
3954         GPR32),
3955       (i32 24))>;
3956def : MSAPat<
3957  (i32 (vextract_sext_i16 v8i16:$ws, i64:$idx)),
3958  (SRA (COPY_TO_REGCLASS
3959         (i32 (EXTRACT_SUBREG
3960                (SPLAT_H v8i16:$ws,
3961                  (COPY_TO_REGCLASS
3962                    (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3963                sub_lo)),
3964         GPR32),
3965       (i32 16))>;
3966def : MSAPat<
3967  (i32 (vextract_sext_i32 v4i32:$ws, i64:$idx)),
3968  (COPY_TO_REGCLASS
3969    (i32 (EXTRACT_SUBREG
3970           (SPLAT_W v4i32:$ws,
3971             (COPY_TO_REGCLASS
3972               (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3973           sub_lo)),
3974    GPR32)>;
3975def : MSAPat<
3976  (i64 (vextract_sext_i64 v2i64:$ws, i64:$idx)),
3977  (COPY_TO_REGCLASS
3978    (i64 (EXTRACT_SUBREG
3979           (SPLAT_D v2i64:$ws,
3980             (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3981           sub_64)),
3982    GPR64), [HasMSA, IsGP64bit]>;
3983
3984def : MSAPat<
3985  (i32 (vextract_zext_i8 v16i8:$ws, i64:$idx)),
3986  (SRL (COPY_TO_REGCLASS
3987         (i32 (EXTRACT_SUBREG
3988                 (SPLAT_B v16i8:$ws,
3989                   (COPY_TO_REGCLASS
3990                     (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3991                 sub_lo)),
3992         GPR32),
3993       (i32 24))>;
3994def : MSAPat<
3995  (i32 (vextract_zext_i16 v8i16:$ws, i64:$idx)),
3996  (SRL (COPY_TO_REGCLASS
3997         (i32 (EXTRACT_SUBREG
3998                (SPLAT_H v8i16:$ws,
3999                  (COPY_TO_REGCLASS
4000                    (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
4001                sub_lo)),
4002         GPR32),
4003       (i32 16))>;
4004def : MSAPat<
4005  (i32 (vextract_zext_i32 v4i32:$ws, i64:$idx)),
4006  (COPY_TO_REGCLASS
4007    (i32 (EXTRACT_SUBREG
4008           (SPLAT_W v4i32:$ws,
4009             (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
4010           sub_lo)),
4011    GPR32)>;
4012def : MSAPat<
4013  (i64 (vextract_zext_i64 v2i64:$ws, i64:$idx)),
4014  (COPY_TO_REGCLASS
4015    (i64 (EXTRACT_SUBREG
4016           (SPLAT_D v2i64:$ws,
4017             (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
4018           sub_64)),
4019    GPR64),
4020  [HasMSA, IsGP64bit]>;
4021
4022def : MSAPat<
4023  (f32 (vector_extract v4f32:$ws, i64:$idx)),
4024  (f32 (EXTRACT_SUBREG
4025         (SPLAT_W v4f32:$ws,
4026           (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
4027         sub_lo))>;
4028def : MSAPat<
4029  (f64 (vector_extract v2f64:$ws, i64:$idx)),
4030  (f64 (EXTRACT_SUBREG
4031         (SPLAT_D v2f64:$ws,
4032           (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
4033         sub_64))>;
4034
4035def : MSAPat<(vfseteq_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
4036             (FCEQ_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
4037def : MSAPat<(vfseteq_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
4038             (FCEQ_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;
4039def : MSAPat<(vfsetle_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
4040             (FCLE_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
4041def : MSAPat<(vfsetle_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
4042             (FCLE_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;
4043def : MSAPat<(vfsetlt_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
4044             (FCLT_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
4045def : MSAPat<(vfsetlt_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
4046             (FCLT_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;
4047def : MSAPat<(vfsetne_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
4048             (FCNE_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
4049def : MSAPat<(vfsetne_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
4050             (FCNE_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;
4051