1//===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes Mips MSA ASE instructions. 10// 11//===----------------------------------------------------------------------===// 12 13def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>; 14def SDT_VSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>, 15 SDTCisInt<1>, 16 SDTCisSameAs<1, 2>, 17 SDTCisVT<3, OtherVT>]>; 18def SDT_VFSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>, 19 SDTCisFP<1>, 20 SDTCisSameAs<1, 2>, 21 SDTCisVT<3, OtherVT>]>; 22def SDT_VSHF : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>, 23 SDTCisInt<1>, SDTCisVec<1>, 24 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>; 25def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>, 26 SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>; 27def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>, 28 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>; 29def SDT_INSVE : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0, 1>, 30 SDTCisVT<2, i32>, SDTCisSameAs<0, 3>, 31 SDTCisVT<4, i32>]>; 32 33def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>; 34def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>; 35def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>; 36def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>; 37def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp, 38 [SDNPCommutative, SDNPAssociative]>; 39def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>; 40def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>; 41def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>; 42def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>; 43def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>; 44def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>; 45def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>; 46def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>; 47def MipsINSVE : SDNode<"MipsISD::INSVE", SDT_INSVE>; 48def MipsFMS : SDNode<"MipsISD::FMS", SDTFPTernaryOp>; 49 50def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>; 51def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>; 52 53def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT", 54 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>; 55def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT", 56 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>; 57 58def immZExt1Ptr : ImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>; 59def immZExt2Ptr : ImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>; 60def immZExt3Ptr : ImmLeaf<iPTR, [{return isUInt<3>(Imm);}]>; 61def immZExt4Ptr : ImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>; 62 63def timmZExt1Ptr : TImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>; 64def timmZExt2Ptr : TImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>; 65def timmZExt3Ptr : TImmLeaf<iPTR, [{return isUInt<3>(Imm);}]>; 66def timmZExt4Ptr : TImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>; 67 68// Operands 69 70def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>; 71 72// Pattern fragments 73def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx), 74 (MipsVExtractSExt node:$vec, node:$idx, i8)>; 75def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx), 76 (MipsVExtractSExt node:$vec, node:$idx, i16)>; 77def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx), 78 (MipsVExtractSExt node:$vec, node:$idx, i32)>; 79def vextract_sext_i64 : PatFrag<(ops node:$vec, node:$idx), 80 (MipsVExtractSExt node:$vec, node:$idx, i64)>; 81 82def vextract_zext_i8 : PatFrag<(ops node:$vec, node:$idx), 83 (MipsVExtractZExt node:$vec, node:$idx, i8)>; 84def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx), 85 (MipsVExtractZExt node:$vec, node:$idx, i16)>; 86def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx), 87 (MipsVExtractZExt node:$vec, node:$idx, i32)>; 88def vextract_zext_i64 : PatFrag<(ops node:$vec, node:$idx), 89 (MipsVExtractZExt node:$vec, node:$idx, i64)>; 90 91def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx), 92 (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>; 93def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx), 94 (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>; 95def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx), 96 (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>; 97def vinsert_v2i64 : PatFrag<(ops node:$vec, node:$val, node:$idx), 98 (v2i64 (vector_insert node:$vec, node:$val, node:$idx))>; 99 100def insve_v16i8 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 101 (v16i8 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 102def insve_v8i16 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 103 (v8i16 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 104def insve_v4i32 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 105 (v4i32 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 106def insve_v2i64 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 107 (v2i64 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 108 109class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> : 110 PatFrag<(ops node:$lhs, node:$rhs), 111 (ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>; 112 113// ISD::SETFALSE cannot occur 114def vfseteq_v4f32 : vfsetcc_type<v4i32, v4f32, SETEQ>; 115def vfseteq_v2f64 : vfsetcc_type<v2i64, v2f64, SETEQ>; 116def vfsetge_v4f32 : vfsetcc_type<v4i32, v4f32, SETGE>; 117def vfsetge_v2f64 : vfsetcc_type<v2i64, v2f64, SETGE>; 118def vfsetgt_v4f32 : vfsetcc_type<v4i32, v4f32, SETGT>; 119def vfsetgt_v2f64 : vfsetcc_type<v2i64, v2f64, SETGT>; 120def vfsetle_v4f32 : vfsetcc_type<v4i32, v4f32, SETLE>; 121def vfsetle_v2f64 : vfsetcc_type<v2i64, v2f64, SETLE>; 122def vfsetlt_v4f32 : vfsetcc_type<v4i32, v4f32, SETLT>; 123def vfsetlt_v2f64 : vfsetcc_type<v2i64, v2f64, SETLT>; 124def vfsetne_v4f32 : vfsetcc_type<v4i32, v4f32, SETNE>; 125def vfsetne_v2f64 : vfsetcc_type<v2i64, v2f64, SETNE>; 126def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>; 127def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>; 128def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>; 129def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>; 130def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>; 131def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>; 132def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>; 133def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>; 134def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>; 135def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>; 136def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>; 137def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>; 138def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>; 139def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>; 140def vfsetun_v4f32 : vfsetcc_type<v4i32, v4f32, SETUO>; 141def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>; 142def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>; 143def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>; 144def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>; 145def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>; 146def vfsetugt_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGT>; 147def vfsetugt_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGT>; 148def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>; 149def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>; 150def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>; 151def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>; 152def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>; 153def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>; 154// ISD::SETTRUE cannot occur 155// ISD::SETFALSE2 cannot occur 156// ISD::SETTRUE2 cannot occur 157 158class vsetcc_type<ValueType ResTy, CondCode CC> : 159 PatFrag<(ops node:$lhs, node:$rhs), 160 (ResTy (vsetcc node:$lhs, node:$rhs, CC))>; 161 162def vseteq_v16i8 : vsetcc_type<v16i8, SETEQ>; 163def vseteq_v8i16 : vsetcc_type<v8i16, SETEQ>; 164def vseteq_v4i32 : vsetcc_type<v4i32, SETEQ>; 165def vseteq_v2i64 : vsetcc_type<v2i64, SETEQ>; 166def vsetle_v16i8 : vsetcc_type<v16i8, SETLE>; 167def vsetle_v8i16 : vsetcc_type<v8i16, SETLE>; 168def vsetle_v4i32 : vsetcc_type<v4i32, SETLE>; 169def vsetle_v2i64 : vsetcc_type<v2i64, SETLE>; 170def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>; 171def vsetlt_v8i16 : vsetcc_type<v8i16, SETLT>; 172def vsetlt_v4i32 : vsetcc_type<v4i32, SETLT>; 173def vsetlt_v2i64 : vsetcc_type<v2i64, SETLT>; 174def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>; 175def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>; 176def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>; 177def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>; 178def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>; 179def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>; 180def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>; 181def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>; 182 183def vsplati8 : PatFrag<(ops node:$e0), 184 (v16i8 (build_vector node:$e0, node:$e0, 185 node:$e0, node:$e0, 186 node:$e0, node:$e0, 187 node:$e0, node:$e0, 188 node:$e0, node:$e0, 189 node:$e0, node:$e0, 190 node:$e0, node:$e0, 191 node:$e0, node:$e0))>; 192def vsplati16 : PatFrag<(ops node:$e0), 193 (v8i16 (build_vector node:$e0, node:$e0, 194 node:$e0, node:$e0, 195 node:$e0, node:$e0, 196 node:$e0, node:$e0))>; 197def vsplati32 : PatFrag<(ops node:$e0), 198 (v4i32 (build_vector node:$e0, node:$e0, 199 node:$e0, node:$e0))>; 200 201def vsplati64_imm_eq_1 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{ 202 APInt Imm; 203 SDNode *BV = N->getOperand(0).getNode(); 204 EVT EltTy = N->getValueType(0).getVectorElementType(); 205 206 return selectVSplat(BV, Imm, EltTy.getSizeInBits()) && 207 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; 208}]>; 209 210def vsplati64 : PatFrag<(ops node:$e0), 211 (v2i64 (build_vector node:$e0, node:$e0))>; 212 213def vsplati64_splat_d : PatFrag<(ops node:$e0), 214 (v2i64 (bitconvert 215 (v4i32 (and 216 (v4i32 (build_vector node:$e0, 217 node:$e0, 218 node:$e0, 219 node:$e0)), 220 vsplati64_imm_eq_1))))>; 221 222def vsplatf32 : PatFrag<(ops node:$e0), 223 (v4f32 (build_vector node:$e0, node:$e0, 224 node:$e0, node:$e0))>; 225def vsplatf64 : PatFrag<(ops node:$e0), 226 (v2f64 (build_vector node:$e0, node:$e0))>; 227 228def vsplati8_elt : PatFrag<(ops node:$v, node:$i), 229 (MipsVSHF (vsplati8 node:$i), node:$v, node:$v)>; 230def vsplati16_elt : PatFrag<(ops node:$v, node:$i), 231 (MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>; 232def vsplati32_elt : PatFrag<(ops node:$v, node:$i), 233 (MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>; 234def vsplati64_elt : PatFrag<(ops node:$v, node:$i), 235 (MipsVSHF (vsplati64_splat_d node:$i), 236 node:$v, node:$v)>; 237 238class SplatPatLeaf<Operand opclass, dag frag, code pred = [{}], 239 SDNodeXForm xform = NOOP_SDNodeXForm> 240 : PatLeaf<frag, pred, xform> { 241 Operand OpClass = opclass; 242} 243 244class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn, 245 list<SDNode> roots = [], 246 list<SDNodeProperty> props = []> : 247 ComplexPattern<ty, numops, fn, roots, props> { 248 Operand OpClass = opclass; 249} 250 251def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1, 252 "selectVSplatUimm3", 253 [build_vector, bitconvert]>; 254 255def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1, 256 "selectVSplatUimm4", 257 [build_vector, bitconvert]>; 258 259def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1, 260 "selectVSplatUimm5", 261 [build_vector, bitconvert]>; 262 263def vsplati8_uimm8 : SplatComplexPattern<vsplat_uimm8, v16i8, 1, 264 "selectVSplatUimm8", 265 [build_vector, bitconvert]>; 266 267def vsplati8_simm5 : SplatComplexPattern<vsplat_simm5, v16i8, 1, 268 "selectVSplatSimm5", 269 [build_vector, bitconvert]>; 270 271def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1, 272 "selectVSplatUimm3", 273 [build_vector, bitconvert]>; 274 275def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1, 276 "selectVSplatUimm4", 277 [build_vector, bitconvert]>; 278 279def vsplati16_uimm5 : SplatComplexPattern<vsplat_uimm5, v8i16, 1, 280 "selectVSplatUimm5", 281 [build_vector, bitconvert]>; 282 283def vsplati16_simm5 : SplatComplexPattern<vsplat_simm5, v8i16, 1, 284 "selectVSplatSimm5", 285 [build_vector, bitconvert]>; 286 287def vsplati32_uimm2 : SplatComplexPattern<vsplat_uimm2, v4i32, 1, 288 "selectVSplatUimm2", 289 [build_vector, bitconvert]>; 290 291def vsplati32_uimm5 : SplatComplexPattern<vsplat_uimm5, v4i32, 1, 292 "selectVSplatUimm5", 293 [build_vector, bitconvert]>; 294 295def vsplati32_simm5 : SplatComplexPattern<vsplat_simm5, v4i32, 1, 296 "selectVSplatSimm5", 297 [build_vector, bitconvert]>; 298 299def vsplati64_uimm1 : SplatComplexPattern<vsplat_uimm1, v2i64, 1, 300 "selectVSplatUimm1", 301 [build_vector, bitconvert]>; 302 303def vsplati64_uimm5 : SplatComplexPattern<vsplat_uimm5, v2i64, 1, 304 "selectVSplatUimm5", 305 [build_vector, bitconvert]>; 306 307def vsplati64_uimm6 : SplatComplexPattern<vsplat_uimm6, v2i64, 1, 308 "selectVSplatUimm6", 309 [build_vector, bitconvert]>; 310 311def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1, 312 "selectVSplatSimm5", 313 [build_vector, bitconvert]>; 314 315// Any build_vector that is a constant splat with a value that is an exact 316// power of 2 317def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2", 318 [build_vector, bitconvert]>; 319 320// Any build_vector that is a constant splat with a value that is the bitwise 321// inverse of an exact power of 2 322def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2", 323 [build_vector, bitconvert]>; 324 325// Any build_vector that is a constant splat with only a consecutive sequence 326// of left-most bits set. 327def vsplat_maskl_bits_uimm3 328 : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskL", 329 [build_vector, bitconvert]>; 330def vsplat_maskl_bits_uimm4 331 : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskL", 332 [build_vector, bitconvert]>; 333def vsplat_maskl_bits_uimm5 334 : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskL", 335 [build_vector, bitconvert]>; 336def vsplat_maskl_bits_uimm6 337 : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskL", 338 [build_vector, bitconvert]>; 339 340// Any build_vector that is a constant splat with only a consecutive sequence 341// of right-most bits set. 342def vsplat_maskr_bits_uimm3 343 : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskR", 344 [build_vector, bitconvert]>; 345def vsplat_maskr_bits_uimm4 346 : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskR", 347 [build_vector, bitconvert]>; 348def vsplat_maskr_bits_uimm5 349 : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskR", 350 [build_vector, bitconvert]>; 351def vsplat_maskr_bits_uimm6 352 : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskR", 353 [build_vector, bitconvert]>; 354 355// Any build_vector that is a constant splat with a value that equals 1 356// FIXME: These should be a ComplexPattern but we can't use them because the 357// ISel generator requires the uses to have a name, but providing a name 358// causes other errors ("used in pattern but not operand list") 359def vsplat_imm_eq_1 : PatLeaf<(build_vector), [{ 360 APInt Imm; 361 EVT EltTy = N->getValueType(0).getVectorElementType(); 362 363 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 364 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; 365}]>; 366 367def vbclr_b : PatFrag<(ops node:$ws, node:$wt), 368 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 369 immAllOnesV))>; 370def vbclr_h : PatFrag<(ops node:$ws, node:$wt), 371 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 372 immAllOnesV))>; 373def vbclr_w : PatFrag<(ops node:$ws, node:$wt), 374 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 375 immAllOnesV))>; 376def vbclr_d : PatFrag<(ops node:$ws, node:$wt), 377 (and node:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1), 378 node:$wt), 379 (bitconvert (v4i32 immAllOnesV))))>; 380 381def vbneg_b : PatFrag<(ops node:$ws, node:$wt), 382 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 383def vbneg_h : PatFrag<(ops node:$ws, node:$wt), 384 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 385def vbneg_w : PatFrag<(ops node:$ws, node:$wt), 386 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 387def vbneg_d : PatFrag<(ops node:$ws, node:$wt), 388 (xor node:$ws, (shl (v2i64 vsplati64_imm_eq_1), 389 node:$wt))>; 390 391def vbset_b : PatFrag<(ops node:$ws, node:$wt), 392 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 393def vbset_h : PatFrag<(ops node:$ws, node:$wt), 394 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 395def vbset_w : PatFrag<(ops node:$ws, node:$wt), 396 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 397def vbset_d : PatFrag<(ops node:$ws, node:$wt), 398 (or node:$ws, (shl (v2i64 vsplati64_imm_eq_1), 399 node:$wt))>; 400 401def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt), 402 (add node:$wd, (mul node:$ws, node:$wt))>; 403 404def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt), 405 (sub node:$wd, (mul node:$ws, node:$wt))>; 406 407def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt), 408 (fmul node:$ws, (fexp2 node:$wt))>; 409 410// Instruction encoding. 411class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>; 412class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>; 413class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>; 414class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>; 415 416class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>; 417class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>; 418class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>; 419class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>; 420 421class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>; 422class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>; 423class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>; 424class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>; 425 426class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>; 427class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>; 428class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>; 429class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>; 430 431class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>; 432class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>; 433class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>; 434class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>; 435 436class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>; 437class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>; 438class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>; 439class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>; 440 441class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>; 442 443class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>; 444 445class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>; 446class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>; 447class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>; 448class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>; 449 450class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>; 451class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>; 452class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>; 453class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>; 454 455class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>; 456class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>; 457class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>; 458class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>; 459 460class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>; 461class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>; 462class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>; 463class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>; 464 465class AVER_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010000>; 466class AVER_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010000>; 467class AVER_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010000>; 468class AVER_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010000>; 469 470class AVER_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010000>; 471class AVER_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010000>; 472class AVER_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010000>; 473class AVER_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010000>; 474 475class BCLR_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001101>; 476class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>; 477class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>; 478class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>; 479 480class BCLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001001>; 481class BCLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001001>; 482class BCLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001001>; 483class BCLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001001>; 484 485class BINSL_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001101>; 486class BINSL_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001101>; 487class BINSL_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001101>; 488class BINSL_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001101>; 489 490class BINSLI_B_ENC : MSA_BIT_B_FMT<0b110, 0b001001>; 491class BINSLI_H_ENC : MSA_BIT_H_FMT<0b110, 0b001001>; 492class BINSLI_W_ENC : MSA_BIT_W_FMT<0b110, 0b001001>; 493class BINSLI_D_ENC : MSA_BIT_D_FMT<0b110, 0b001001>; 494 495class BINSR_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001101>; 496class BINSR_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001101>; 497class BINSR_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001101>; 498class BINSR_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001101>; 499 500class BINSRI_B_ENC : MSA_BIT_B_FMT<0b111, 0b001001>; 501class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>; 502class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>; 503class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>; 504 505class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>; 506 507class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>; 508 509class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>; 510 511class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>; 512 513class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>; 514class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>; 515class BNEG_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001101>; 516class BNEG_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001101>; 517 518class BNEGI_B_ENC : MSA_BIT_B_FMT<0b101, 0b001001>; 519class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>; 520class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>; 521class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>; 522 523class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>; 524class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>; 525class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>; 526class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>; 527 528class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01111>; 529 530class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>; 531 532class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>; 533 534class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>; 535class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>; 536class BSET_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001101>; 537class BSET_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001101>; 538 539class BSETI_B_ENC : MSA_BIT_B_FMT<0b100, 0b001001>; 540class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>; 541class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>; 542class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>; 543 544class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>; 545class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>; 546class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>; 547class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>; 548 549class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>; 550 551class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>; 552class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>; 553class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>; 554class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>; 555 556class CEQI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000111>; 557class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>; 558class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>; 559class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>; 560 561class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>; 562 563class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>; 564class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>; 565class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>; 566class CLE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001111>; 567 568class CLE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001111>; 569class CLE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001111>; 570class CLE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001111>; 571class CLE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001111>; 572 573class CLEI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000111>; 574class CLEI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000111>; 575class CLEI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000111>; 576class CLEI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000111>; 577 578class CLEI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000111>; 579class CLEI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000111>; 580class CLEI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000111>; 581class CLEI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000111>; 582 583class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>; 584class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>; 585class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>; 586class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>; 587 588class CLT_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001111>; 589class CLT_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001111>; 590class CLT_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001111>; 591class CLT_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001111>; 592 593class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>; 594class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>; 595class CLTI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000111>; 596class CLTI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000111>; 597 598class CLTI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000111>; 599class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>; 600class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>; 601class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>; 602 603class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>; 604class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>; 605class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>; 606class COPY_S_D_ENC : MSA_ELM_COPY_D_FMT<0b0010, 0b011001>; 607 608class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>; 609class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>; 610class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>; 611 612class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>; 613 614class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>; 615class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>; 616class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>; 617class DIV_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010010>; 618 619class DIV_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010010>; 620class DIV_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010010>; 621class DIV_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010010>; 622class DIV_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010010>; 623 624class DOTP_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010011>; 625class DOTP_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010011>; 626class DOTP_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010011>; 627 628class DOTP_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010011>; 629class DOTP_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010011>; 630class DOTP_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010011>; 631 632class DPADD_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010011>; 633class DPADD_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010011>; 634class DPADD_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010011>; 635 636class DPADD_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010011>; 637class DPADD_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010011>; 638class DPADD_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010011>; 639 640class DPSUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010011>; 641class DPSUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010011>; 642class DPSUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010011>; 643 644class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>; 645class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>; 646class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>; 647 648class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>; 649class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>; 650 651class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>; 652class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>; 653 654class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>; 655class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>; 656 657class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>; 658class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>; 659 660class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>; 661class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>; 662 663class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>; 664class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>; 665 666class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>; 667class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>; 668 669class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>; 670class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>; 671 672class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>; 673class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>; 674 675class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>; 676class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>; 677 678class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>; 679class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>; 680 681class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>; 682class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>; 683 684class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>; 685class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>; 686 687class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>; 688class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>; 689 690class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>; 691class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>; 692 693class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>; 694class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>; 695 696class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>; 697class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>; 698 699class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>; 700class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>; 701 702class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>; 703class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>; 704 705class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>; 706class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>; 707 708class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>; 709class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>; 710 711class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>; 712class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>; 713 714class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>; 715class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>; 716class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>; 717class FILL_D_ENC : MSA_2R_FILL_D_FMT<0b11000000, 0b11, 0b011110>; 718 719class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>; 720class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>; 721 722class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>; 723class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>; 724 725class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>; 726class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>; 727 728class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>; 729class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>; 730 731class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>; 732class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>; 733 734class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>; 735class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>; 736 737class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>; 738class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>; 739 740class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>; 741class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>; 742 743class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>; 744class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>; 745 746class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>; 747class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>; 748 749class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>; 750class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>; 751 752class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>; 753class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>; 754 755class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>; 756class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>; 757 758class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>; 759class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>; 760 761class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>; 762class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>; 763 764class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>; 765class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>; 766 767class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>; 768class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>; 769 770class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>; 771class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>; 772 773class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>; 774class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>; 775 776class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>; 777class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>; 778 779class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>; 780class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>; 781 782class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>; 783class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>; 784 785class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>; 786class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>; 787 788class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>; 789class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>; 790 791class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>; 792class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>; 793 794class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>; 795class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>; 796 797class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>; 798class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>; 799 800class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>; 801class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>; 802 803class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>; 804class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>; 805 806class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>; 807class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>; 808class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>; 809 810class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>; 811class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>; 812class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>; 813 814class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>; 815class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>; 816class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>; 817 818class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>; 819class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>; 820class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>; 821 822class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>; 823class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>; 824class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>; 825class ILVEV_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010100>; 826 827class ILVL_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010100>; 828class ILVL_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010100>; 829class ILVL_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010100>; 830class ILVL_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010100>; 831 832class ILVOD_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010100>; 833class ILVOD_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010100>; 834class ILVOD_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010100>; 835class ILVOD_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010100>; 836 837class ILVR_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010100>; 838class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>; 839class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>; 840class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>; 841 842class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>; 843class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>; 844class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>; 845class INSERT_D_ENC : MSA_ELM_INSERT_D_FMT<0b0100, 0b011001>; 846 847class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>; 848class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>; 849class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>; 850class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>; 851 852class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>; 853class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>; 854class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>; 855class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>; 856 857class LDI_B_ENC : MSA_I10_FMT<0b110, 0b00, 0b000111>; 858class LDI_H_ENC : MSA_I10_FMT<0b110, 0b01, 0b000111>; 859class LDI_W_ENC : MSA_I10_FMT<0b110, 0b10, 0b000111>; 860class LDI_D_ENC : MSA_I10_FMT<0b110, 0b11, 0b000111>; 861 862class LSA_ENC : SPECIAL_LSA_FMT<0b000101>; 863class DLSA_ENC : SPECIAL_DLSA_FMT<0b010101>; 864 865class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>; 866class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>; 867 868class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>; 869class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>; 870 871class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>; 872class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>; 873class MADDV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010010>; 874class MADDV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010010>; 875 876class MAX_A_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001110>; 877class MAX_A_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001110>; 878class MAX_A_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001110>; 879class MAX_A_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001110>; 880 881class MAX_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001110>; 882class MAX_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001110>; 883class MAX_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001110>; 884class MAX_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001110>; 885 886class MAX_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001110>; 887class MAX_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001110>; 888class MAX_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001110>; 889class MAX_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001110>; 890 891class MAXI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000110>; 892class MAXI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000110>; 893class MAXI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000110>; 894class MAXI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000110>; 895 896class MAXI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000110>; 897class MAXI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000110>; 898class MAXI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000110>; 899class MAXI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000110>; 900 901class MIN_A_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001110>; 902class MIN_A_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001110>; 903class MIN_A_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001110>; 904class MIN_A_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001110>; 905 906class MIN_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001110>; 907class MIN_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001110>; 908class MIN_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001110>; 909class MIN_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001110>; 910 911class MIN_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001110>; 912class MIN_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001110>; 913class MIN_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001110>; 914class MIN_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001110>; 915 916class MINI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000110>; 917class MINI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000110>; 918class MINI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000110>; 919class MINI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000110>; 920 921class MINI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000110>; 922class MINI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000110>; 923class MINI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000110>; 924class MINI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000110>; 925 926class MOD_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010010>; 927class MOD_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010010>; 928class MOD_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010010>; 929class MOD_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010010>; 930 931class MOD_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010010>; 932class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>; 933class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>; 934class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>; 935 936class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>; 937 938class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>; 939class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>; 940 941class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>; 942class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>; 943 944class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>; 945class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>; 946class MSUBV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010010>; 947class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>; 948 949class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>; 950class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>; 951 952class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>; 953class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>; 954 955class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>; 956class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>; 957class MULV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010010>; 958class MULV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010010>; 959 960class NLOC_B_ENC : MSA_2R_FMT<0b11000010, 0b00, 0b011110>; 961class NLOC_H_ENC : MSA_2R_FMT<0b11000010, 0b01, 0b011110>; 962class NLOC_W_ENC : MSA_2R_FMT<0b11000010, 0b10, 0b011110>; 963class NLOC_D_ENC : MSA_2R_FMT<0b11000010, 0b11, 0b011110>; 964 965class NLZC_B_ENC : MSA_2R_FMT<0b11000011, 0b00, 0b011110>; 966class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>; 967class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>; 968class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>; 969 970class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>; 971 972class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>; 973 974class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>; 975 976class ORI_B_ENC : MSA_I8_FMT<0b01, 0b000000>; 977 978class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>; 979class PCKEV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010100>; 980class PCKEV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010100>; 981class PCKEV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010100>; 982 983class PCKOD_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010100>; 984class PCKOD_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010100>; 985class PCKOD_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010100>; 986class PCKOD_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010100>; 987 988class PCNT_B_ENC : MSA_2R_FMT<0b11000001, 0b00, 0b011110>; 989class PCNT_H_ENC : MSA_2R_FMT<0b11000001, 0b01, 0b011110>; 990class PCNT_W_ENC : MSA_2R_FMT<0b11000001, 0b10, 0b011110>; 991class PCNT_D_ENC : MSA_2R_FMT<0b11000001, 0b11, 0b011110>; 992 993class SAT_S_B_ENC : MSA_BIT_B_FMT<0b000, 0b001010>; 994class SAT_S_H_ENC : MSA_BIT_H_FMT<0b000, 0b001010>; 995class SAT_S_W_ENC : MSA_BIT_W_FMT<0b000, 0b001010>; 996class SAT_S_D_ENC : MSA_BIT_D_FMT<0b000, 0b001010>; 997 998class SAT_U_B_ENC : MSA_BIT_B_FMT<0b001, 0b001010>; 999class SAT_U_H_ENC : MSA_BIT_H_FMT<0b001, 0b001010>; 1000class SAT_U_W_ENC : MSA_BIT_W_FMT<0b001, 0b001010>; 1001class SAT_U_D_ENC : MSA_BIT_D_FMT<0b001, 0b001010>; 1002 1003class SHF_B_ENC : MSA_I8_FMT<0b00, 0b000010>; 1004class SHF_H_ENC : MSA_I8_FMT<0b01, 0b000010>; 1005class SHF_W_ENC : MSA_I8_FMT<0b10, 0b000010>; 1006 1007class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>; 1008class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>; 1009class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>; 1010class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>; 1011 1012class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>; 1013class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>; 1014class SLDI_W_ENC : MSA_ELM_W_FMT<0b0000, 0b011001>; 1015class SLDI_D_ENC : MSA_ELM_D_FMT<0b0000, 0b011001>; 1016 1017class SLL_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001101>; 1018class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>; 1019class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>; 1020class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>; 1021 1022class SLLI_B_ENC : MSA_BIT_B_FMT<0b000, 0b001001>; 1023class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>; 1024class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>; 1025class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>; 1026 1027class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>; 1028class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>; 1029class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>; 1030class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>; 1031 1032class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>; 1033class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>; 1034class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>; 1035class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>; 1036 1037class SRA_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001101>; 1038class SRA_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001101>; 1039class SRA_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001101>; 1040class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>; 1041 1042class SRAI_B_ENC : MSA_BIT_B_FMT<0b001, 0b001001>; 1043class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>; 1044class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>; 1045class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>; 1046 1047class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>; 1048class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>; 1049class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>; 1050class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>; 1051 1052class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>; 1053class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>; 1054class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>; 1055class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>; 1056 1057class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>; 1058class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>; 1059class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>; 1060class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>; 1061 1062class SRLI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001001>; 1063class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>; 1064class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>; 1065class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>; 1066 1067class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>; 1068class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>; 1069class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>; 1070class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>; 1071 1072class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>; 1073class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>; 1074class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>; 1075class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>; 1076 1077class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>; 1078class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>; 1079class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>; 1080class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>; 1081 1082class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>; 1083class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>; 1084class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>; 1085class SUBS_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010001>; 1086 1087class SUBS_U_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010001>; 1088class SUBS_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010001>; 1089class SUBS_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010001>; 1090class SUBS_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010001>; 1091 1092class SUBSUS_U_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010001>; 1093class SUBSUS_U_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010001>; 1094class SUBSUS_U_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010001>; 1095class SUBSUS_U_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010001>; 1096 1097class SUBSUU_S_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010001>; 1098class SUBSUU_S_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010001>; 1099class SUBSUU_S_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010001>; 1100class SUBSUU_S_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010001>; 1101 1102class SUBV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001110>; 1103class SUBV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001110>; 1104class SUBV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001110>; 1105class SUBV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001110>; 1106 1107class SUBVI_B_ENC : MSA_I5_FMT<0b001, 0b00, 0b000110>; 1108class SUBVI_H_ENC : MSA_I5_FMT<0b001, 0b01, 0b000110>; 1109class SUBVI_W_ENC : MSA_I5_FMT<0b001, 0b10, 0b000110>; 1110class SUBVI_D_ENC : MSA_I5_FMT<0b001, 0b11, 0b000110>; 1111 1112class VSHF_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010101>; 1113class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>; 1114class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>; 1115class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>; 1116 1117class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>; 1118 1119class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>; 1120 1121// Instruction desc. 1122class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1123 ComplexPattern Imm, RegisterOperand ROWD, 1124 RegisterOperand ROWS = ROWD, 1125 InstrItinClass itin = NoItinerary> { 1126 dag OutOperandList = (outs ROWD:$wd); 1127 dag InOperandList = (ins ROWS:$ws, vsplat_uimm3:$m); 1128 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1129 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1130 InstrItinClass Itinerary = itin; 1131} 1132 1133class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1134 ComplexPattern Imm, RegisterOperand ROWD, 1135 RegisterOperand ROWS = ROWD, 1136 InstrItinClass itin = NoItinerary> { 1137 dag OutOperandList = (outs ROWD:$wd); 1138 dag InOperandList = (ins ROWS:$ws, vsplat_uimm4:$m); 1139 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1140 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1141 InstrItinClass Itinerary = itin; 1142} 1143 1144class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1145 ComplexPattern Imm, RegisterOperand ROWD, 1146 RegisterOperand ROWS = ROWD, 1147 InstrItinClass itin = NoItinerary> { 1148 dag OutOperandList = (outs ROWD:$wd); 1149 dag InOperandList = (ins ROWS:$ws, vsplat_uimm5:$m); 1150 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1151 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1152 InstrItinClass Itinerary = itin; 1153} 1154 1155class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1156 ComplexPattern Imm, RegisterOperand ROWD, 1157 RegisterOperand ROWS = ROWD, 1158 InstrItinClass itin = NoItinerary> { 1159 dag OutOperandList = (outs ROWD:$wd); 1160 dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m); 1161 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1162 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1163 InstrItinClass Itinerary = itin; 1164} 1165 1166class MSA_BIT_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1167 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1168 RegisterOperand ROWS = ROWD, 1169 InstrItinClass itin = NoItinerary> { 1170 dag OutOperandList = (outs ROWD:$wd); 1171 dag InOperandList = (ins ROWS:$ws, ImmOp:$m); 1172 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1173 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1174 InstrItinClass Itinerary = itin; 1175} 1176 1177class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty, 1178 SplatComplexPattern Mask, RegisterOperand ROWD, 1179 RegisterOperand ROWS = ROWD, 1180 InstrItinClass itin = NoItinerary> { 1181 dag OutOperandList = (outs ROWD:$wd); 1182 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, Mask.OpClass:$m); 1183 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1184 // Note that binsxi and vselect treat the condition operand the opposite 1185 // way to each other. 1186 // (vselect cond, if_set, if_clear) 1187 // (BSEL_V cond, if_clear, if_set) 1188 list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$ws), 1189 ROWS:$wd_in))]; 1190 InstrItinClass Itinerary = itin; 1191 string Constraints = "$wd = $wd_in"; 1192} 1193 1194class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty, 1195 SplatComplexPattern ImmOp, RegisterOperand ROWD, 1196 RegisterOperand ROWS = ROWD, 1197 InstrItinClass itin = NoItinerary> : 1198 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>; 1199 1200class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty, 1201 SplatComplexPattern ImmOp, RegisterOperand ROWD, 1202 RegisterOperand ROWS = ROWD, 1203 InstrItinClass itin = NoItinerary> : 1204 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>; 1205 1206class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1207 SplatComplexPattern SplatImm, 1208 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1209 InstrItinClass itin = NoItinerary> { 1210 dag OutOperandList = (outs ROWD:$wd); 1211 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m); 1212 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1213 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))]; 1214 InstrItinClass Itinerary = itin; 1215} 1216 1217class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1218 ValueType VecTy, Operand ImmOp, ImmLeaf Imm, 1219 RegisterOperand ROD, RegisterOperand ROWS, 1220 InstrItinClass itin = NoItinerary> { 1221 dag OutOperandList = (outs ROD:$rd); 1222 dag InOperandList = (ins ROWS:$ws, ImmOp:$n); 1223 string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]"); 1224 list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), Imm:$n))]; 1225 InstrItinClass Itinerary = itin; 1226} 1227 1228class MSA_ELM_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1229 RegisterOperand ROWD, RegisterOperand ROWS, 1230 Operand ImmOp, ImmLeaf Imm, 1231 InstrItinClass itin = NoItinerary> { 1232 dag OutOperandList = (outs ROWD:$wd); 1233 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ImmOp:$n); 1234 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]"); 1235 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1236 Imm:$n))]; 1237 string Constraints = "$wd = $wd_in"; 1238 InstrItinClass Itinerary = itin; 1239} 1240 1241class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy, 1242 Operand ImmOp, ImmLeaf Imm, RegisterClass RCD, 1243 RegisterClass RCWS> : 1244 MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, ImmOp:$n), 1245 [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), Imm:$n))]> { 1246 bit usesCustomInserter = 1; 1247 bit hasNoSchedulingInfo = 1; 1248} 1249 1250class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1251 SplatComplexPattern SplatImm, RegisterOperand ROWD, 1252 RegisterOperand ROWS = ROWD, 1253 InstrItinClass itin = NoItinerary> { 1254 dag OutOperandList = (outs ROWD:$wd); 1255 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm); 1256 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm"); 1257 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))]; 1258 InstrItinClass Itinerary = itin; 1259} 1260 1261class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1262 SplatComplexPattern SplatImm, RegisterOperand ROWD, 1263 RegisterOperand ROWS = ROWD, 1264 InstrItinClass itin = NoItinerary> { 1265 dag OutOperandList = (outs ROWD:$wd); 1266 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8); 1267 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8"); 1268 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))]; 1269 InstrItinClass Itinerary = itin; 1270} 1271 1272class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1273 RegisterOperand ROWS = ROWD, 1274 InstrItinClass itin = NoItinerary> { 1275 dag OutOperandList = (outs ROWD:$wd); 1276 dag InOperandList = (ins ROWS:$ws, uimm8:$u8); 1277 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8"); 1278 list<dag> Pattern = [(set ROWD:$wd, (MipsSHF timmZExt8:$u8, ROWS:$ws))]; 1279 InstrItinClass Itinerary = itin; 1280} 1281 1282class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1283 InstrItinClass itin = NoItinerary> { 1284 dag OutOperandList = (outs ROWD:$wd); 1285 dag InOperandList = (ins vsplat_simm10:$s10); 1286 string AsmString = !strconcat(instr_asm, "\t$wd, $s10"); 1287 // LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp 1288 list<dag> Pattern = []; 1289 bit hasSideEffects = 0; 1290 InstrItinClass Itinerary = itin; 1291} 1292 1293class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1294 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1295 InstrItinClass itin = NoItinerary> { 1296 dag OutOperandList = (outs ROWD:$wd); 1297 dag InOperandList = (ins ROWS:$ws); 1298 string AsmString = !strconcat(instr_asm, "\t$wd, $ws"); 1299 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))]; 1300 InstrItinClass Itinerary = itin; 1301} 1302 1303class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT, 1304 SDPatternOperator OpNode, RegisterOperand ROWD, 1305 RegisterOperand ROS = ROWD, 1306 InstrItinClass itin = NoItinerary> { 1307 dag OutOperandList = (outs ROWD:$wd); 1308 dag InOperandList = (ins ROS:$rs); 1309 string AsmString = !strconcat(instr_asm, "\t$wd, $rs"); 1310 list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))]; 1311 InstrItinClass Itinerary = itin; 1312} 1313 1314class MSA_2R_FILL_PSEUDO_BASE<ValueType VT, SDPatternOperator OpNode, 1315 RegisterClass RCWD, RegisterClass RCWS = RCWD> : 1316 MSAPseudo<(outs RCWD:$wd), (ins RCWS:$fs), 1317 [(set RCWD:$wd, (OpNode RCWS:$fs))]> { 1318 let usesCustomInserter = 1; 1319} 1320 1321class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1322 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1323 InstrItinClass itin = NoItinerary> { 1324 dag OutOperandList = (outs ROWD:$wd); 1325 dag InOperandList = (ins ROWS:$ws); 1326 string AsmString = !strconcat(instr_asm, "\t$wd, $ws"); 1327 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))]; 1328 InstrItinClass Itinerary = itin; 1329} 1330 1331class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1332 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1333 RegisterOperand ROWT = ROWD, 1334 InstrItinClass itin = NoItinerary> { 1335 dag OutOperandList = (outs ROWD:$wd); 1336 dag InOperandList = (ins ROWS:$ws, ROWT:$wt); 1337 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1338 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]; 1339 InstrItinClass Itinerary = itin; 1340} 1341 1342class MSA_3R_BINSX_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1343 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1344 RegisterOperand ROWT = ROWD, 1345 InstrItinClass itin = NoItinerary> { 1346 dag OutOperandList = (outs ROWD:$wd); 1347 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1348 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1349 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1350 ROWT:$wt))]; 1351 string Constraints = "$wd = $wd_in"; 1352 InstrItinClass Itinerary = itin; 1353} 1354 1355class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1356 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1357 InstrItinClass itin = NoItinerary> { 1358 dag OutOperandList = (outs ROWD:$wd); 1359 dag InOperandList = (ins ROWS:$ws, GPR32Opnd:$rt); 1360 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]"); 1361 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32Opnd:$rt))]; 1362 InstrItinClass Itinerary = itin; 1363} 1364 1365class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1366 RegisterOperand ROWS = ROWD, 1367 RegisterOperand ROWT = ROWD, 1368 InstrItinClass itin = NoItinerary> { 1369 dag OutOperandList = (outs ROWD:$wd); 1370 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1371 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1372 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws, 1373 ROWT:$wt))]; 1374 string Constraints = "$wd = $wd_in"; 1375 InstrItinClass Itinerary = itin; 1376} 1377 1378class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1379 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1380 InstrItinClass itin = NoItinerary> { 1381 dag OutOperandList = (outs ROWD:$wd); 1382 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, GPR32Opnd:$rt); 1383 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]"); 1384 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1385 GPR32Opnd:$rt))]; 1386 InstrItinClass Itinerary = itin; 1387 string Constraints = "$wd = $wd_in"; 1388} 1389 1390class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1391 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1392 RegisterOperand ROWT = ROWD, 1393 InstrItinClass itin = NoItinerary> { 1394 dag OutOperandList = (outs ROWD:$wd); 1395 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1396 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1397 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1398 ROWT:$wt))]; 1399 InstrItinClass Itinerary = itin; 1400 string Constraints = "$wd = $wd_in"; 1401} 1402 1403class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1404 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1405 RegisterOperand ROWT = ROWD, 1406 InstrItinClass itin = NoItinerary> : 1407 MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>; 1408 1409class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1410 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1411 RegisterOperand ROWT = ROWD, 1412 InstrItinClass itin = NoItinerary> : 1413 MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>; 1414 1415class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> { 1416 dag OutOperandList = (outs); 1417 dag InOperandList = (ins ROWD:$wt, brtarget:$offset); 1418 string AsmString = !strconcat(instr_asm, "\t$wt, $offset"); 1419 list<dag> Pattern = []; 1420 InstrItinClass Itinerary = NoItinerary; 1421 bit isBranch = 1; 1422 bit isTerminator = 1; 1423 bit hasDelaySlot = 1; 1424 list<Register> Defs = [AT]; 1425} 1426 1427class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1428 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1429 RegisterOperand ROS, 1430 InstrItinClass itin = NoItinerary> { 1431 dag OutOperandList = (outs ROWD:$wd); 1432 dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, ImmOp:$n); 1433 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs"); 1434 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROS:$rs, Imm:$n))]; 1435 InstrItinClass Itinerary = itin; 1436 string Constraints = "$wd = $wd_in"; 1437} 1438 1439class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty, 1440 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1441 RegisterOperand ROFS> : 1442 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ImmOp:$n, ROFS:$fs), 1443 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, Imm:$n))]> { 1444 bit usesCustomInserter = 1; 1445 string Constraints = "$wd = $wd_in"; 1446} 1447 1448class MSA_INSERT_VIDX_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty, 1449 RegisterOperand ROWD, RegisterOperand ROFS, 1450 RegisterOperand ROIdx> : 1451 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ROIdx:$n, ROFS:$fs), 1452 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, 1453 ROIdx:$n))]> { 1454 bit usesCustomInserter = 1; 1455 bit hasNoSchedulingInfo = 1; 1456 string Constraints = "$wd = $wd_in"; 1457} 1458 1459class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1460 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1461 RegisterOperand ROWS = ROWD, 1462 InstrItinClass itin = NoItinerary> { 1463 dag OutOperandList = (outs ROWD:$wd); 1464 dag InOperandList = (ins ROWD:$wd_in, ImmOp:$n, ROWS:$ws, uimmz:$n2); 1465 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[$n2]"); 1466 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, 1467 Imm:$n, 1468 ROWS:$ws, 1469 immz:$n2))]; 1470 InstrItinClass Itinerary = itin; 1471 string Constraints = "$wd = $wd_in"; 1472} 1473 1474class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1475 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1476 RegisterOperand ROWT = ROWD, 1477 InstrItinClass itin = NoItinerary> { 1478 dag OutOperandList = (outs ROWD:$wd); 1479 dag InOperandList = (ins ROWS:$ws, ROWT:$wt); 1480 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1481 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]; 1482 InstrItinClass Itinerary = itin; 1483} 1484 1485class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm, 1486 RegisterOperand ROWD, 1487 RegisterOperand ROWS = ROWD, 1488 InstrItinClass itin = NoItinerary> { 1489 dag OutOperandList = (outs ROWD:$wd); 1490 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n); 1491 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]"); 1492 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws, 1493 ROWS:$ws))]; 1494 InstrItinClass Itinerary = itin; 1495} 1496 1497class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD, 1498 RegisterOperand ROWS = ROWD, 1499 RegisterOperand ROWT = ROWD> : 1500 MSAPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt), 1501 [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>; 1502 1503class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>, 1504 IsCommutable; 1505class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>, 1506 IsCommutable; 1507class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>, 1508 IsCommutable; 1509class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>, 1510 IsCommutable; 1511 1512class ADDS_A_B_DESC : MSA_3R_DESC_BASE<"adds_a.b", int_mips_adds_a_b, 1513 MSA128BOpnd>, IsCommutable; 1514class ADDS_A_H_DESC : MSA_3R_DESC_BASE<"adds_a.h", int_mips_adds_a_h, 1515 MSA128HOpnd>, IsCommutable; 1516class ADDS_A_W_DESC : MSA_3R_DESC_BASE<"adds_a.w", int_mips_adds_a_w, 1517 MSA128WOpnd>, IsCommutable; 1518class ADDS_A_D_DESC : MSA_3R_DESC_BASE<"adds_a.d", int_mips_adds_a_d, 1519 MSA128DOpnd>, IsCommutable; 1520 1521class ADDS_S_B_DESC : MSA_3R_DESC_BASE<"adds_s.b", int_mips_adds_s_b, 1522 MSA128BOpnd>, IsCommutable; 1523class ADDS_S_H_DESC : MSA_3R_DESC_BASE<"adds_s.h", int_mips_adds_s_h, 1524 MSA128HOpnd>, IsCommutable; 1525class ADDS_S_W_DESC : MSA_3R_DESC_BASE<"adds_s.w", int_mips_adds_s_w, 1526 MSA128WOpnd>, IsCommutable; 1527class ADDS_S_D_DESC : MSA_3R_DESC_BASE<"adds_s.d", int_mips_adds_s_d, 1528 MSA128DOpnd>, IsCommutable; 1529 1530class ADDS_U_B_DESC : MSA_3R_DESC_BASE<"adds_u.b", int_mips_adds_u_b, 1531 MSA128BOpnd>, IsCommutable; 1532class ADDS_U_H_DESC : MSA_3R_DESC_BASE<"adds_u.h", int_mips_adds_u_h, 1533 MSA128HOpnd>, IsCommutable; 1534class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w, 1535 MSA128WOpnd>, IsCommutable; 1536class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d, 1537 MSA128DOpnd>, IsCommutable; 1538 1539class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable; 1540class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable; 1541class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable; 1542class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable; 1543 1544class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5, 1545 MSA128BOpnd>; 1546class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5, 1547 MSA128HOpnd>; 1548class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5, 1549 MSA128WOpnd>; 1550class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5, 1551 MSA128DOpnd>; 1552 1553class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>; 1554class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128HOpnd>; 1555class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128WOpnd>; 1556class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128DOpnd>; 1557 1558class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8, 1559 MSA128BOpnd>; 1560 1561class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b, 1562 MSA128BOpnd>; 1563class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h, 1564 MSA128HOpnd>; 1565class ASUB_S_W_DESC : MSA_3R_DESC_BASE<"asub_s.w", int_mips_asub_s_w, 1566 MSA128WOpnd>; 1567class ASUB_S_D_DESC : MSA_3R_DESC_BASE<"asub_s.d", int_mips_asub_s_d, 1568 MSA128DOpnd>; 1569 1570class ASUB_U_B_DESC : MSA_3R_DESC_BASE<"asub_u.b", int_mips_asub_u_b, 1571 MSA128BOpnd>; 1572class ASUB_U_H_DESC : MSA_3R_DESC_BASE<"asub_u.h", int_mips_asub_u_h, 1573 MSA128HOpnd>; 1574class ASUB_U_W_DESC : MSA_3R_DESC_BASE<"asub_u.w", int_mips_asub_u_w, 1575 MSA128WOpnd>; 1576class ASUB_U_D_DESC : MSA_3R_DESC_BASE<"asub_u.d", int_mips_asub_u_d, 1577 MSA128DOpnd>; 1578 1579class AVE_S_B_DESC : MSA_3R_DESC_BASE<"ave_s.b", int_mips_ave_s_b, MSA128BOpnd>, 1580 IsCommutable; 1581class AVE_S_H_DESC : MSA_3R_DESC_BASE<"ave_s.h", int_mips_ave_s_h, MSA128HOpnd>, 1582 IsCommutable; 1583class AVE_S_W_DESC : MSA_3R_DESC_BASE<"ave_s.w", int_mips_ave_s_w, MSA128WOpnd>, 1584 IsCommutable; 1585class AVE_S_D_DESC : MSA_3R_DESC_BASE<"ave_s.d", int_mips_ave_s_d, MSA128DOpnd>, 1586 IsCommutable; 1587 1588class AVE_U_B_DESC : MSA_3R_DESC_BASE<"ave_u.b", int_mips_ave_u_b, MSA128BOpnd>, 1589 IsCommutable; 1590class AVE_U_H_DESC : MSA_3R_DESC_BASE<"ave_u.h", int_mips_ave_u_h, MSA128HOpnd>, 1591 IsCommutable; 1592class AVE_U_W_DESC : MSA_3R_DESC_BASE<"ave_u.w", int_mips_ave_u_w, MSA128WOpnd>, 1593 IsCommutable; 1594class AVE_U_D_DESC : MSA_3R_DESC_BASE<"ave_u.d", int_mips_ave_u_d, MSA128DOpnd>, 1595 IsCommutable; 1596 1597class AVER_S_B_DESC : MSA_3R_DESC_BASE<"aver_s.b", int_mips_aver_s_b, 1598 MSA128BOpnd>, IsCommutable; 1599class AVER_S_H_DESC : MSA_3R_DESC_BASE<"aver_s.h", int_mips_aver_s_h, 1600 MSA128HOpnd>, IsCommutable; 1601class AVER_S_W_DESC : MSA_3R_DESC_BASE<"aver_s.w", int_mips_aver_s_w, 1602 MSA128WOpnd>, IsCommutable; 1603class AVER_S_D_DESC : MSA_3R_DESC_BASE<"aver_s.d", int_mips_aver_s_d, 1604 MSA128DOpnd>, IsCommutable; 1605 1606class AVER_U_B_DESC : MSA_3R_DESC_BASE<"aver_u.b", int_mips_aver_u_b, 1607 MSA128BOpnd>, IsCommutable; 1608class AVER_U_H_DESC : MSA_3R_DESC_BASE<"aver_u.h", int_mips_aver_u_h, 1609 MSA128HOpnd>, IsCommutable; 1610class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w, 1611 MSA128WOpnd>, IsCommutable; 1612class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d, 1613 MSA128DOpnd>, IsCommutable; 1614 1615class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", vbclr_b, MSA128BOpnd>; 1616class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", vbclr_h, MSA128HOpnd>; 1617class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", vbclr_w, MSA128WOpnd>; 1618class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", vbclr_d, MSA128DOpnd>; 1619 1620class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", and, vsplat_uimm_inv_pow2, 1621 MSA128BOpnd>; 1622class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", and, vsplat_uimm_inv_pow2, 1623 MSA128HOpnd>; 1624class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", and, vsplat_uimm_inv_pow2, 1625 MSA128WOpnd>; 1626class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", and, vsplat_uimm_inv_pow2, 1627 MSA128DOpnd>; 1628 1629class BINSL_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.b", int_mips_binsl_b, 1630 MSA128BOpnd>; 1631class BINSL_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.h", int_mips_binsl_h, 1632 MSA128HOpnd>; 1633class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w, 1634 MSA128WOpnd>; 1635class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d, 1636 MSA128DOpnd>; 1637 1638class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, vsplat_maskl_bits_uimm3, MSA128BOpnd>; 1639class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, vsplat_maskl_bits_uimm4, MSA128HOpnd>; 1640class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, vsplat_maskl_bits_uimm5, MSA128WOpnd>; 1641class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, vsplat_maskl_bits_uimm6, MSA128DOpnd>; 1642 1643class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b, 1644 MSA128BOpnd>; 1645class BINSR_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.h", int_mips_binsr_h, 1646 MSA128HOpnd>; 1647class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w, 1648 MSA128WOpnd>; 1649class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d, 1650 MSA128DOpnd>; 1651 1652class BINSRI_B_DESC 1653 : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, vsplat_maskr_bits_uimm3, 1654 MSA128BOpnd>; 1655class BINSRI_H_DESC 1656 : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, vsplat_maskr_bits_uimm4, 1657 MSA128HOpnd>; 1658class BINSRI_W_DESC 1659 : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, vsplat_maskr_bits_uimm5, 1660 MSA128WOpnd>; 1661class BINSRI_D_DESC 1662 : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, vsplat_maskr_bits_uimm6, 1663 MSA128DOpnd>; 1664 1665class BMNZ_V_DESC { 1666 dag OutOperandList = (outs MSA128BOpnd:$wd); 1667 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1668 MSA128BOpnd:$wt); 1669 string AsmString = "bmnz.v\t$wd, $ws, $wt"; 1670 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt, 1671 MSA128BOpnd:$ws, 1672 MSA128BOpnd:$wd_in))]; 1673 InstrItinClass Itinerary = NoItinerary; 1674 string Constraints = "$wd = $wd_in"; 1675} 1676 1677class BMNZI_B_DESC { 1678 dag OutOperandList = (outs MSA128BOpnd:$wd); 1679 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1680 vsplat_uimm8:$u8); 1681 string AsmString = "bmnzi.b\t$wd, $ws, $u8"; 1682 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8, 1683 MSA128BOpnd:$ws, 1684 MSA128BOpnd:$wd_in))]; 1685 InstrItinClass Itinerary = NoItinerary; 1686 string Constraints = "$wd = $wd_in"; 1687} 1688 1689class BMZ_V_DESC { 1690 dag OutOperandList = (outs MSA128BOpnd:$wd); 1691 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1692 MSA128BOpnd:$wt); 1693 string AsmString = "bmz.v\t$wd, $ws, $wt"; 1694 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt, 1695 MSA128BOpnd:$wd_in, 1696 MSA128BOpnd:$ws))]; 1697 InstrItinClass Itinerary = NoItinerary; 1698 string Constraints = "$wd = $wd_in"; 1699} 1700 1701class BMZI_B_DESC { 1702 dag OutOperandList = (outs MSA128BOpnd:$wd); 1703 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1704 vsplat_uimm8:$u8); 1705 string AsmString = "bmzi.b\t$wd, $ws, $u8"; 1706 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8, 1707 MSA128BOpnd:$wd_in, 1708 MSA128BOpnd:$ws))]; 1709 InstrItinClass Itinerary = NoItinerary; 1710 string Constraints = "$wd = $wd_in"; 1711} 1712 1713class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg_b, MSA128BOpnd>; 1714class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg_h, MSA128HOpnd>; 1715class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg_w, MSA128WOpnd>; 1716class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg_d, MSA128DOpnd>; 1717 1718class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", xor, vsplat_uimm_pow2, 1719 MSA128BOpnd>; 1720class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", xor, vsplat_uimm_pow2, 1721 MSA128HOpnd>; 1722class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", xor, vsplat_uimm_pow2, 1723 MSA128WOpnd>; 1724class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", xor, vsplat_uimm_pow2, 1725 MSA128DOpnd>; 1726 1727class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>; 1728class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>; 1729class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>; 1730class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>; 1731 1732class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>; 1733 1734class BSEL_V_DESC { 1735 dag OutOperandList = (outs MSA128BOpnd:$wd); 1736 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1737 MSA128BOpnd:$wt); 1738 string AsmString = "bsel.v\t$wd, $ws, $wt"; 1739 // Note that vselect and BSEL_V treat the condition operand the opposite way 1740 // from each other. 1741 // (vselect cond, if_set, if_clear) 1742 // (BSEL_V cond, if_clear, if_set) 1743 list<dag> Pattern = [(set MSA128BOpnd:$wd, 1744 (vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$wt, 1745 MSA128BOpnd:$ws))]; 1746 InstrItinClass Itinerary = NoItinerary; 1747 string Constraints = "$wd = $wd_in"; 1748} 1749 1750class BSELI_B_DESC { 1751 dag OutOperandList = (outs MSA128BOpnd:$wd); 1752 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1753 vsplat_uimm8:$u8); 1754 string AsmString = "bseli.b\t$wd, $ws, $u8"; 1755 // Note that vselect and BSEL_V treat the condition operand the opposite way 1756 // from each other. 1757 // (vselect cond, if_set, if_clear) 1758 // (BSEL_V cond, if_clear, if_set) 1759 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in, 1760 vsplati8_uimm8:$u8, 1761 MSA128BOpnd:$ws))]; 1762 InstrItinClass Itinerary = NoItinerary; 1763 string Constraints = "$wd = $wd_in"; 1764} 1765 1766class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", vbset_b, MSA128BOpnd>; 1767class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", vbset_h, MSA128HOpnd>; 1768class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", vbset_w, MSA128WOpnd>; 1769class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", vbset_d, MSA128DOpnd>; 1770 1771class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", or, vsplat_uimm_pow2, 1772 MSA128BOpnd>; 1773class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", or, vsplat_uimm_pow2, 1774 MSA128HOpnd>; 1775class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", or, vsplat_uimm_pow2, 1776 MSA128WOpnd>; 1777class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", or, vsplat_uimm_pow2, 1778 MSA128DOpnd>; 1779 1780class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>; 1781class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>; 1782class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>; 1783class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>; 1784 1785class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>; 1786 1787class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>, 1788 IsCommutable; 1789class CEQ_H_DESC : MSA_3R_DESC_BASE<"ceq.h", vseteq_v8i16, MSA128HOpnd>, 1790 IsCommutable; 1791class CEQ_W_DESC : MSA_3R_DESC_BASE<"ceq.w", vseteq_v4i32, MSA128WOpnd>, 1792 IsCommutable; 1793class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq.d", vseteq_v2i64, MSA128DOpnd>, 1794 IsCommutable; 1795 1796class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5, 1797 MSA128BOpnd>; 1798class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5, 1799 MSA128HOpnd>; 1800class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5, 1801 MSA128WOpnd>; 1802class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5, 1803 MSA128DOpnd>; 1804 1805class CFCMSA_DESC { 1806 dag OutOperandList = (outs GPR32Opnd:$rd); 1807 dag InOperandList = (ins MSA128CROpnd:$cs); 1808 string AsmString = "cfcmsa\t$rd, $cs"; 1809 InstrItinClass Itinerary = NoItinerary; 1810 bit hasSideEffects = 1; 1811 bit isMoveReg = 1; 1812} 1813 1814class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>; 1815class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", vsetle_v8i16, MSA128HOpnd>; 1816class CLE_S_W_DESC : MSA_3R_DESC_BASE<"cle_s.w", vsetle_v4i32, MSA128WOpnd>; 1817class CLE_S_D_DESC : MSA_3R_DESC_BASE<"cle_s.d", vsetle_v2i64, MSA128DOpnd>; 1818 1819class CLE_U_B_DESC : MSA_3R_DESC_BASE<"cle_u.b", vsetule_v16i8, MSA128BOpnd>; 1820class CLE_U_H_DESC : MSA_3R_DESC_BASE<"cle_u.h", vsetule_v8i16, MSA128HOpnd>; 1821class CLE_U_W_DESC : MSA_3R_DESC_BASE<"cle_u.w", vsetule_v4i32, MSA128WOpnd>; 1822class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>; 1823 1824class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8, 1825 vsplati8_simm5, MSA128BOpnd>; 1826class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16, 1827 vsplati16_simm5, MSA128HOpnd>; 1828class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32, 1829 vsplati32_simm5, MSA128WOpnd>; 1830class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64, 1831 vsplati64_simm5, MSA128DOpnd>; 1832 1833class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8, 1834 vsplati8_uimm5, MSA128BOpnd>; 1835class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16, 1836 vsplati16_uimm5, MSA128HOpnd>; 1837class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32, 1838 vsplati32_uimm5, MSA128WOpnd>; 1839class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64, 1840 vsplati64_uimm5, MSA128DOpnd>; 1841 1842class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>; 1843class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>; 1844class CLT_S_W_DESC : MSA_3R_DESC_BASE<"clt_s.w", vsetlt_v4i32, MSA128WOpnd>; 1845class CLT_S_D_DESC : MSA_3R_DESC_BASE<"clt_s.d", vsetlt_v2i64, MSA128DOpnd>; 1846 1847class CLT_U_B_DESC : MSA_3R_DESC_BASE<"clt_u.b", vsetult_v16i8, MSA128BOpnd>; 1848class CLT_U_H_DESC : MSA_3R_DESC_BASE<"clt_u.h", vsetult_v8i16, MSA128HOpnd>; 1849class CLT_U_W_DESC : MSA_3R_DESC_BASE<"clt_u.w", vsetult_v4i32, MSA128WOpnd>; 1850class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>; 1851 1852class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8, 1853 vsplati8_simm5, MSA128BOpnd>; 1854class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16, 1855 vsplati16_simm5, MSA128HOpnd>; 1856class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32, 1857 vsplati32_simm5, MSA128WOpnd>; 1858class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64, 1859 vsplati64_simm5, MSA128DOpnd>; 1860 1861class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8, 1862 vsplati8_uimm5, MSA128BOpnd>; 1863class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16, 1864 vsplati16_uimm5, MSA128HOpnd>; 1865class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32, 1866 vsplati32_uimm5, MSA128WOpnd>; 1867class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64, 1868 vsplati64_uimm5, MSA128DOpnd>; 1869 1870class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8, 1871 uimm4_ptr, immZExt4Ptr, GPR32Opnd, 1872 MSA128BOpnd>; 1873class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16, 1874 uimm3_ptr, immZExt3Ptr, GPR32Opnd, 1875 MSA128HOpnd>; 1876class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32, 1877 uimm2_ptr, immZExt2Ptr, GPR32Opnd, 1878 MSA128WOpnd>; 1879class COPY_S_D_DESC : MSA_COPY_DESC_BASE<"copy_s.d", vextract_sext_i64, v2i64, 1880 uimm1_ptr, immZExt1Ptr, GPR64Opnd, 1881 MSA128DOpnd>; 1882 1883class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8, 1884 uimm4_ptr, immZExt4Ptr, GPR32Opnd, 1885 MSA128BOpnd>; 1886class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16, 1887 uimm3_ptr, immZExt3Ptr, GPR32Opnd, 1888 MSA128HOpnd>; 1889class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32, 1890 uimm2_ptr, immZExt2Ptr, GPR32Opnd, 1891 MSA128WOpnd>; 1892 1893class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, 1894 uimm2_ptr, immZExt2Ptr, FGR32, 1895 MSA128W>; 1896class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64, 1897 uimm1_ptr, immZExt1Ptr, FGR64, 1898 MSA128D>; 1899 1900class CTCMSA_DESC { 1901 dag OutOperandList = (outs); 1902 dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs); 1903 string AsmString = "ctcmsa\t$cd, $rs"; 1904 InstrItinClass Itinerary = NoItinerary; 1905 bit hasSideEffects = 1; 1906 bit isMoveReg = 1; 1907} 1908 1909class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>; 1910class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128HOpnd>; 1911class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128WOpnd>; 1912class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128DOpnd>; 1913 1914class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128BOpnd>; 1915class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128HOpnd>; 1916class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128WOpnd>; 1917class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128DOpnd>; 1918 1919class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h, 1920 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>, 1921 IsCommutable; 1922class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w, 1923 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>, 1924 IsCommutable; 1925class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d, 1926 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>, 1927 IsCommutable; 1928 1929class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h, 1930 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>, 1931 IsCommutable; 1932class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w, 1933 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>, 1934 IsCommutable; 1935class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d, 1936 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>, 1937 IsCommutable; 1938 1939class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h, 1940 MSA128HOpnd, MSA128BOpnd, 1941 MSA128BOpnd>, IsCommutable; 1942class DPADD_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.w", int_mips_dpadd_s_w, 1943 MSA128WOpnd, MSA128HOpnd, 1944 MSA128HOpnd>, IsCommutable; 1945class DPADD_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.d", int_mips_dpadd_s_d, 1946 MSA128DOpnd, MSA128WOpnd, 1947 MSA128WOpnd>, IsCommutable; 1948 1949class DPADD_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.h", int_mips_dpadd_u_h, 1950 MSA128HOpnd, MSA128BOpnd, 1951 MSA128BOpnd>, IsCommutable; 1952class DPADD_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.w", int_mips_dpadd_u_w, 1953 MSA128WOpnd, MSA128HOpnd, 1954 MSA128HOpnd>, IsCommutable; 1955class DPADD_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.d", int_mips_dpadd_u_d, 1956 MSA128DOpnd, MSA128WOpnd, 1957 MSA128WOpnd>, IsCommutable; 1958 1959class DPSUB_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.h", int_mips_dpsub_s_h, 1960 MSA128HOpnd, MSA128BOpnd, 1961 MSA128BOpnd>; 1962class DPSUB_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.w", int_mips_dpsub_s_w, 1963 MSA128WOpnd, MSA128HOpnd, 1964 MSA128HOpnd>; 1965class DPSUB_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.d", int_mips_dpsub_s_d, 1966 MSA128DOpnd, MSA128WOpnd, 1967 MSA128WOpnd>; 1968 1969class DPSUB_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.h", int_mips_dpsub_u_h, 1970 MSA128HOpnd, MSA128BOpnd, 1971 MSA128BOpnd>; 1972class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w, 1973 MSA128WOpnd, MSA128HOpnd, 1974 MSA128HOpnd>; 1975class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d, 1976 MSA128DOpnd, MSA128WOpnd, 1977 MSA128WOpnd>; 1978 1979class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>, 1980 IsCommutable; 1981class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>, 1982 IsCommutable; 1983 1984class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>, 1985 IsCommutable; 1986class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>, 1987 IsCommutable; 1988 1989class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>, 1990 IsCommutable; 1991class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>, 1992 IsCommutable; 1993 1994class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w, 1995 MSA128WOpnd>; 1996class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d, 1997 MSA128DOpnd>; 1998 1999class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>; 2000class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>; 2001 2002class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>; 2003class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>; 2004 2005class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>, 2006 IsCommutable; 2007class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>, 2008 IsCommutable; 2009 2010class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>, 2011 IsCommutable; 2012class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>, 2013 IsCommutable; 2014 2015class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>, 2016 IsCommutable; 2017class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>, 2018 IsCommutable; 2019 2020class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>, 2021 IsCommutable; 2022class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>, 2023 IsCommutable; 2024 2025class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>, 2026 IsCommutable; 2027class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>, 2028 IsCommutable; 2029 2030class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>, 2031 IsCommutable; 2032class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>, 2033 IsCommutable; 2034 2035class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>, 2036 IsCommutable; 2037class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>, 2038 IsCommutable; 2039 2040class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>; 2041class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>; 2042 2043class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h, 2044 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>; 2045class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w, 2046 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>; 2047 2048// The fexp2.df instruction multiplies the first operand by 2 to the power of 2049// the second operand. We therefore need a pseudo-insn in order to invent the 2050// 1.0 when we only need to match ISD::FEXP2. 2051class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>; 2052class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>; 2053let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in { 2054 class FEXP2_W_1_PSEUDO_DESC : 2055 MSAPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws), 2056 [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>; 2057 class FEXP2_D_1_PSEUDO_DESC : 2058 MSAPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws), 2059 [(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>; 2060} 2061 2062class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w, 2063 MSA128WOpnd, MSA128HOpnd>; 2064class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d, 2065 MSA128DOpnd, MSA128WOpnd>; 2066 2067class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w, 2068 MSA128WOpnd, MSA128HOpnd>; 2069class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d, 2070 MSA128DOpnd, MSA128WOpnd>; 2071 2072class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>; 2073class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>; 2074 2075class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>; 2076class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>; 2077 2078class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w, 2079 MSA128WOpnd, MSA128HOpnd>; 2080class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d, 2081 MSA128DOpnd, MSA128WOpnd>; 2082 2083class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w, 2084 MSA128WOpnd, MSA128HOpnd>; 2085class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d, 2086 MSA128DOpnd, MSA128WOpnd>; 2087 2088class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8, 2089 MSA128BOpnd, GPR32Opnd>; 2090class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16, 2091 MSA128HOpnd, GPR32Opnd>; 2092class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32, 2093 MSA128WOpnd, GPR32Opnd>; 2094class FILL_D_DESC : MSA_2R_FILL_DESC_BASE<"fill.d", v2i64, vsplati64, 2095 MSA128DOpnd, GPR64Opnd>; 2096 2097class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v4f32, vsplatf32, MSA128W, 2098 FGR32>; 2099class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v2f64, vsplatf64, MSA128D, 2100 FGR64>; 2101 2102class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>; 2103class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>; 2104 2105class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>; 2106class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>; 2107 2108class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>; 2109class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>; 2110 2111class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w, 2112 MSA128WOpnd>; 2113class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d, 2114 MSA128DOpnd>; 2115 2116class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>; 2117class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>; 2118 2119class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w, 2120 MSA128WOpnd>; 2121class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d, 2122 MSA128DOpnd>; 2123 2124class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", MipsFMS, MSA128WOpnd>; 2125class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", MipsFMS, MSA128DOpnd>; 2126 2127class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>; 2128class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>; 2129 2130class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>; 2131class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>; 2132 2133class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>; 2134class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>; 2135 2136class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w, 2137 MSA128WOpnd>; 2138class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d, 2139 MSA128DOpnd>; 2140 2141class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>; 2142class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>; 2143 2144class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>; 2145class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>; 2146 2147class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>; 2148class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>; 2149 2150class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>; 2151class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>; 2152 2153class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>; 2154class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>; 2155 2156class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>; 2157class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>; 2158 2159class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>; 2160class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>; 2161 2162class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>; 2163class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>; 2164 2165class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w, 2166 MSA128WOpnd>; 2167class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d, 2168 MSA128DOpnd>; 2169 2170class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w, 2171 MSA128WOpnd>; 2172class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d, 2173 MSA128DOpnd>; 2174 2175class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w, 2176 MSA128WOpnd>; 2177class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d, 2178 MSA128DOpnd>; 2179 2180class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w, 2181 MSA128WOpnd>; 2182class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d, 2183 MSA128DOpnd>; 2184 2185class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w, 2186 MSA128WOpnd>; 2187class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d, 2188 MSA128DOpnd>; 2189 2190class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w, 2191 MSA128WOpnd>; 2192class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d, 2193 MSA128DOpnd>; 2194 2195class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w, 2196 MSA128WOpnd>; 2197class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d, 2198 MSA128DOpnd>; 2199 2200class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h, 2201 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>; 2202class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w, 2203 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>; 2204 2205class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint, 2206 MSA128WOpnd>; 2207class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint, 2208 MSA128DOpnd>; 2209 2210class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint, 2211 MSA128WOpnd>; 2212class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint, 2213 MSA128DOpnd>; 2214 2215class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h, 2216 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2217class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w, 2218 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2219class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d, 2220 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2221 2222class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h, 2223 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2224class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w, 2225 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2226class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d, 2227 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2228 2229class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h, 2230 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2231class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w, 2232 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2233class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d, 2234 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2235 2236class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h, 2237 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2238class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w, 2239 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2240class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d, 2241 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2242 2243class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", MipsILVEV, MSA128BOpnd>; 2244class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", MipsILVEV, MSA128HOpnd>; 2245class ILVEV_W_DESC : MSA_3R_DESC_BASE<"ilvev.w", MipsILVEV, MSA128WOpnd>; 2246class ILVEV_D_DESC : MSA_3R_DESC_BASE<"ilvev.d", MipsILVEV, MSA128DOpnd>; 2247 2248class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>; 2249class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>; 2250class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>; 2251class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>; 2252 2253class ILVOD_B_DESC : MSA_3R_DESC_BASE<"ilvod.b", MipsILVOD, MSA128BOpnd>; 2254class ILVOD_H_DESC : MSA_3R_DESC_BASE<"ilvod.h", MipsILVOD, MSA128HOpnd>; 2255class ILVOD_W_DESC : MSA_3R_DESC_BASE<"ilvod.w", MipsILVOD, MSA128WOpnd>; 2256class ILVOD_D_DESC : MSA_3R_DESC_BASE<"ilvod.d", MipsILVOD, MSA128DOpnd>; 2257 2258class ILVR_B_DESC : MSA_3R_DESC_BASE<"ilvr.b", MipsILVR, MSA128BOpnd>; 2259class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>; 2260class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>; 2261class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>; 2262 2263class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8, uimm4, 2264 immZExt4Ptr, MSA128BOpnd, GPR32Opnd>; 2265class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16, uimm3, 2266 immZExt3Ptr, MSA128HOpnd, GPR32Opnd>; 2267class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32, uimm2, 2268 immZExt2Ptr, MSA128WOpnd, GPR32Opnd>; 2269class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64, uimm1, 2270 immZExt1Ptr, MSA128DOpnd, GPR64Opnd>; 2271 2272class INSERT_B_VIDX_PSEUDO_DESC : 2273 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR32Opnd>; 2274class INSERT_H_VIDX_PSEUDO_DESC : 2275 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR32Opnd>; 2276class INSERT_W_VIDX_PSEUDO_DESC : 2277 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR32Opnd>; 2278class INSERT_D_VIDX_PSEUDO_DESC : 2279 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR32Opnd>; 2280 2281class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32, 2282 uimm2, immZExt2Ptr, 2283 MSA128WOpnd, FGR32Opnd>; 2284class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64, 2285 uimm1, immZExt1Ptr, 2286 MSA128DOpnd, FGR64Opnd>; 2287 2288class INSERT_FW_VIDX_PSEUDO_DESC : 2289 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR32Opnd>; 2290class INSERT_FD_VIDX_PSEUDO_DESC : 2291 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR32Opnd>; 2292 2293class INSERT_B_VIDX64_PSEUDO_DESC : 2294 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR64Opnd>; 2295class INSERT_H_VIDX64_PSEUDO_DESC : 2296 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR64Opnd>; 2297class INSERT_W_VIDX64_PSEUDO_DESC : 2298 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR64Opnd>; 2299class INSERT_D_VIDX64_PSEUDO_DESC : 2300 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR64Opnd>; 2301 2302class INSERT_FW_VIDX64_PSEUDO_DESC : 2303 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR64Opnd>; 2304class INSERT_FD_VIDX64_PSEUDO_DESC : 2305 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR64Opnd>; 2306 2307class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8, uimm4, timmZExt4, 2308 MSA128BOpnd>; 2309class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", insve_v8i16, uimm3, timmZExt3, 2310 MSA128HOpnd>; 2311class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", insve_v4i32, uimm2, timmZExt2, 2312 MSA128WOpnd>; 2313class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64, uimm1, timmZExt1, 2314 MSA128DOpnd>; 2315 2316class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 2317 ValueType TyNode, RegisterOperand ROWD, 2318 Operand MemOpnd, ComplexPattern Addr = addrimm10, 2319 InstrItinClass itin = NoItinerary> { 2320 dag OutOperandList = (outs ROWD:$wd); 2321 dag InOperandList = (ins MemOpnd:$addr); 2322 string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); 2323 list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))]; 2324 InstrItinClass Itinerary = itin; 2325 string DecoderMethod = "DecodeMSA128Mem"; 2326} 2327 2328class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd, mem_simm10>; 2329class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd, 2330 mem_simm10_lsl1, addrimm10lsl1>; 2331class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd, 2332 mem_simm10_lsl2, addrimm10lsl2>; 2333class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd, 2334 mem_simm10_lsl3, addrimm10lsl3>; 2335 2336class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>; 2337class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>; 2338class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>; 2339class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>; 2340 2341class LSA_DESC_BASE<string instr_asm, RegisterOperand RORD, 2342 InstrItinClass itin = NoItinerary> { 2343 dag OutOperandList = (outs RORD:$rd); 2344 dag InOperandList = (ins RORD:$rs, RORD:$rt, uimm2_plus1:$sa); 2345 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $sa"); 2346 list<dag> Pattern = [(set RORD:$rd, (add RORD:$rt, 2347 (shl RORD:$rs, 2348 immZExt2Lsa:$sa)))]; 2349 InstrItinClass Itinerary = itin; 2350} 2351 2352class LSA_DESC : LSA_DESC_BASE<"lsa", GPR32Opnd, II_LSA>; 2353class DLSA_DESC : LSA_DESC_BASE<"dlsa", GPR64Opnd, II_DLSA>; 2354 2355class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h, 2356 MSA128HOpnd>; 2357class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w, 2358 MSA128WOpnd>; 2359 2360class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h, 2361 MSA128HOpnd>; 2362class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w, 2363 MSA128WOpnd>; 2364 2365class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", muladd, MSA128BOpnd>; 2366class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", muladd, MSA128HOpnd>; 2367class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", muladd, MSA128WOpnd>; 2368class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", muladd, MSA128DOpnd>; 2369 2370class MAX_A_B_DESC : MSA_3R_DESC_BASE<"max_a.b", int_mips_max_a_b, MSA128BOpnd>; 2371class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>; 2372class MAX_A_W_DESC : MSA_3R_DESC_BASE<"max_a.w", int_mips_max_a_w, MSA128WOpnd>; 2373class MAX_A_D_DESC : MSA_3R_DESC_BASE<"max_a.d", int_mips_max_a_d, MSA128DOpnd>; 2374 2375class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", smax, MSA128BOpnd>; 2376class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", smax, MSA128HOpnd>; 2377class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", smax, MSA128WOpnd>; 2378class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", smax, MSA128DOpnd>; 2379 2380class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", umax, MSA128BOpnd>; 2381class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", umax, MSA128HOpnd>; 2382class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", umax, MSA128WOpnd>; 2383class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", umax, MSA128DOpnd>; 2384 2385class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", smax, vsplati8_simm5, 2386 MSA128BOpnd>; 2387class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", smax, vsplati16_simm5, 2388 MSA128HOpnd>; 2389class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", smax, vsplati32_simm5, 2390 MSA128WOpnd>; 2391class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", smax, vsplati64_simm5, 2392 MSA128DOpnd>; 2393 2394class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", umax, vsplati8_uimm5, 2395 MSA128BOpnd>; 2396class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", umax, vsplati16_uimm5, 2397 MSA128HOpnd>; 2398class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", umax, vsplati32_uimm5, 2399 MSA128WOpnd>; 2400class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", umax, vsplati64_uimm5, 2401 MSA128DOpnd>; 2402 2403class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>; 2404class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>; 2405class MIN_A_W_DESC : MSA_3R_DESC_BASE<"min_a.w", int_mips_min_a_w, MSA128WOpnd>; 2406class MIN_A_D_DESC : MSA_3R_DESC_BASE<"min_a.d", int_mips_min_a_d, MSA128DOpnd>; 2407 2408class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", smin, MSA128BOpnd>; 2409class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", smin, MSA128HOpnd>; 2410class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", smin, MSA128WOpnd>; 2411class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", smin, MSA128DOpnd>; 2412 2413class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", umin, MSA128BOpnd>; 2414class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", umin, MSA128HOpnd>; 2415class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", umin, MSA128WOpnd>; 2416class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", umin, MSA128DOpnd>; 2417 2418class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", smin, vsplati8_simm5, 2419 MSA128BOpnd>; 2420class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", smin, vsplati16_simm5, 2421 MSA128HOpnd>; 2422class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", smin, vsplati32_simm5, 2423 MSA128WOpnd>; 2424class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", smin, vsplati64_simm5, 2425 MSA128DOpnd>; 2426 2427class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", umin, vsplati8_uimm5, 2428 MSA128BOpnd>; 2429class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", umin, vsplati16_uimm5, 2430 MSA128HOpnd>; 2431class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", umin, vsplati32_uimm5, 2432 MSA128WOpnd>; 2433class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", umin, vsplati64_uimm5, 2434 MSA128DOpnd>; 2435 2436class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", srem, MSA128BOpnd>; 2437class MOD_S_H_DESC : MSA_3R_DESC_BASE<"mod_s.h", srem, MSA128HOpnd>; 2438class MOD_S_W_DESC : MSA_3R_DESC_BASE<"mod_s.w", srem, MSA128WOpnd>; 2439class MOD_S_D_DESC : MSA_3R_DESC_BASE<"mod_s.d", srem, MSA128DOpnd>; 2440 2441class MOD_U_B_DESC : MSA_3R_DESC_BASE<"mod_u.b", urem, MSA128BOpnd>; 2442class MOD_U_H_DESC : MSA_3R_DESC_BASE<"mod_u.h", urem, MSA128HOpnd>; 2443class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", urem, MSA128WOpnd>; 2444class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", urem, MSA128DOpnd>; 2445 2446class MOVE_V_DESC { 2447 dag OutOperandList = (outs MSA128BOpnd:$wd); 2448 dag InOperandList = (ins MSA128BOpnd:$ws); 2449 string AsmString = "move.v\t$wd, $ws"; 2450 list<dag> Pattern = []; 2451 InstrItinClass Itinerary = NoItinerary; 2452 bit isMoveReg = 1; 2453} 2454 2455class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h, 2456 MSA128HOpnd>; 2457class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w, 2458 MSA128WOpnd>; 2459 2460class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h, 2461 MSA128HOpnd>; 2462class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w, 2463 MSA128WOpnd>; 2464 2465class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", mulsub, MSA128BOpnd>; 2466class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", mulsub, MSA128HOpnd>; 2467class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", mulsub, MSA128WOpnd>; 2468class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", mulsub, MSA128DOpnd>; 2469 2470class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h, 2471 MSA128HOpnd>; 2472class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w, 2473 MSA128WOpnd>; 2474 2475class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h, 2476 MSA128HOpnd>; 2477class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w, 2478 MSA128WOpnd>; 2479 2480class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128BOpnd>; 2481class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128HOpnd>; 2482class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", mul, MSA128WOpnd>; 2483class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", mul, MSA128DOpnd>; 2484 2485class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>; 2486class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>; 2487class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>; 2488class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>; 2489 2490class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", ctlz, MSA128BOpnd>; 2491class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128HOpnd>; 2492class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128WOpnd>; 2493class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128DOpnd>; 2494 2495class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128BOpnd>; 2496class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128HOpnd>; 2497class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128WOpnd>; 2498class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128DOpnd>; 2499 2500class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8, 2501 MSA128BOpnd>; 2502 2503class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128BOpnd>; 2504class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128HOpnd>; 2505class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128WOpnd>; 2506class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128DOpnd>; 2507 2508class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>; 2509 2510class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128BOpnd>; 2511class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128HOpnd>; 2512class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", MipsPCKEV, MSA128WOpnd>; 2513class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", MipsPCKEV, MSA128DOpnd>; 2514 2515class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", MipsPCKOD, MSA128BOpnd>; 2516class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", MipsPCKOD, MSA128HOpnd>; 2517class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>; 2518class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>; 2519 2520class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>; 2521class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>; 2522class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>; 2523class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>; 2524 2525class SAT_S_B_DESC : MSA_BIT_X_DESC_BASE<"sat_s.b", int_mips_sat_s_b, uimm3, 2526 timmZExt3, MSA128BOpnd>; 2527class SAT_S_H_DESC : MSA_BIT_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h, uimm4, 2528 timmZExt4, MSA128HOpnd>; 2529class SAT_S_W_DESC : MSA_BIT_X_DESC_BASE<"sat_s.w", int_mips_sat_s_w, uimm5, 2530 timmZExt5, MSA128WOpnd>; 2531class SAT_S_D_DESC : MSA_BIT_X_DESC_BASE<"sat_s.d", int_mips_sat_s_d, uimm6, 2532 timmZExt6, MSA128DOpnd>; 2533 2534class SAT_U_B_DESC : MSA_BIT_X_DESC_BASE<"sat_u.b", int_mips_sat_u_b, uimm3, 2535 timmZExt3, MSA128BOpnd>; 2536class SAT_U_H_DESC : MSA_BIT_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h, uimm4, 2537 timmZExt4, MSA128HOpnd>; 2538class SAT_U_W_DESC : MSA_BIT_X_DESC_BASE<"sat_u.w", int_mips_sat_u_w, uimm5, 2539 timmZExt5, MSA128WOpnd>; 2540class SAT_U_D_DESC : MSA_BIT_X_DESC_BASE<"sat_u.d", int_mips_sat_u_d, uimm6, 2541 timmZExt6, MSA128DOpnd>; 2542 2543class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>; 2544class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>; 2545class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>; 2546 2547class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>; 2548class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>; 2549class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>; 2550class SLD_D_DESC : MSA_3R_SLD_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>; 2551 2552class SLDI_B_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.b", int_mips_sldi_b, 2553 MSA128BOpnd, MSA128BOpnd, uimm4, 2554 timmZExt4>; 2555class SLDI_H_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.h", int_mips_sldi_h, 2556 MSA128HOpnd, MSA128HOpnd, uimm3, 2557 timmZExt3>; 2558class SLDI_W_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.w", int_mips_sldi_w, 2559 MSA128WOpnd, MSA128WOpnd, uimm2, 2560 timmZExt2>; 2561class SLDI_D_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.d", int_mips_sldi_d, 2562 MSA128DOpnd, MSA128DOpnd, uimm1, 2563 timmZExt1>; 2564 2565class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128BOpnd>; 2566class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128HOpnd>; 2567class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>; 2568class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>; 2569 2570class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3, 2571 MSA128BOpnd>; 2572class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4, 2573 MSA128HOpnd>; 2574class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5, 2575 MSA128WOpnd>; 2576class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6, 2577 MSA128DOpnd>; 2578 2579class SPLAT_B_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.b", vsplati8_elt, 2580 MSA128BOpnd>; 2581class SPLAT_H_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.h", vsplati16_elt, 2582 MSA128HOpnd>; 2583class SPLAT_W_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.w", vsplati32_elt, 2584 MSA128WOpnd>; 2585class SPLAT_D_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.d", vsplati64_elt, 2586 MSA128DOpnd>; 2587 2588class SPLATI_B_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.b", vsplati8_uimm4, 2589 MSA128BOpnd>; 2590class SPLATI_H_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.h", vsplati16_uimm3, 2591 MSA128HOpnd>; 2592class SPLATI_W_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.w", vsplati32_uimm2, 2593 MSA128WOpnd>; 2594class SPLATI_D_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.d", vsplati64_uimm1, 2595 MSA128DOpnd>; 2596 2597class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>; 2598class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>; 2599class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>; 2600class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>; 2601 2602class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3, 2603 MSA128BOpnd>; 2604class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4, 2605 MSA128HOpnd>; 2606class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5, 2607 MSA128WOpnd>; 2608class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6, 2609 MSA128DOpnd>; 2610 2611class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>; 2612class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>; 2613class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>; 2614class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>; 2615 2616class SRARI_B_DESC : MSA_BIT_X_DESC_BASE<"srari.b", int_mips_srari_b, uimm3, 2617 timmZExt3, MSA128BOpnd>; 2618class SRARI_H_DESC : MSA_BIT_X_DESC_BASE<"srari.h", int_mips_srari_h, uimm4, 2619 timmZExt4, MSA128HOpnd>; 2620class SRARI_W_DESC : MSA_BIT_X_DESC_BASE<"srari.w", int_mips_srari_w, uimm5, 2621 timmZExt5, MSA128WOpnd>; 2622class SRARI_D_DESC : MSA_BIT_X_DESC_BASE<"srari.d", int_mips_srari_d, uimm6, 2623 timmZExt6, MSA128DOpnd>; 2624 2625class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>; 2626class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>; 2627class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>; 2628class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>; 2629 2630class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3, 2631 MSA128BOpnd>; 2632class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4, 2633 MSA128HOpnd>; 2634class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5, 2635 MSA128WOpnd>; 2636class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6, 2637 MSA128DOpnd>; 2638 2639class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>; 2640class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>; 2641class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>; 2642class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>; 2643 2644class SRLRI_B_DESC : MSA_BIT_X_DESC_BASE<"srlri.b", int_mips_srlri_b, uimm3, 2645 timmZExt3, MSA128BOpnd>; 2646class SRLRI_H_DESC : MSA_BIT_X_DESC_BASE<"srlri.h", int_mips_srlri_h, uimm4, 2647 timmZExt4, MSA128HOpnd>; 2648class SRLRI_W_DESC : MSA_BIT_X_DESC_BASE<"srlri.w", int_mips_srlri_w, uimm5, 2649 timmZExt5, MSA128WOpnd>; 2650class SRLRI_D_DESC : MSA_BIT_X_DESC_BASE<"srlri.d", int_mips_srlri_d, uimm6, 2651 timmZExt6, MSA128DOpnd>; 2652 2653class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 2654 ValueType TyNode, RegisterOperand ROWD, 2655 Operand MemOpnd, ComplexPattern Addr = addrimm10, 2656 InstrItinClass itin = NoItinerary> { 2657 dag OutOperandList = (outs); 2658 dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr); 2659 string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); 2660 list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)]; 2661 InstrItinClass Itinerary = itin; 2662 string DecoderMethod = "DecodeMSA128Mem"; 2663} 2664 2665class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd, mem_simm10>; 2666class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd, 2667 mem_simm10_lsl1, addrimm10lsl1>; 2668class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd, 2669 mem_simm10_lsl2, addrimm10lsl2>; 2670class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd, 2671 mem_simm10_lsl3, addrimm10lsl3>; 2672 2673class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b, 2674 MSA128BOpnd>; 2675class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h, 2676 MSA128HOpnd>; 2677class SUBS_S_W_DESC : MSA_3R_DESC_BASE<"subs_s.w", int_mips_subs_s_w, 2678 MSA128WOpnd>; 2679class SUBS_S_D_DESC : MSA_3R_DESC_BASE<"subs_s.d", int_mips_subs_s_d, 2680 MSA128DOpnd>; 2681 2682class SUBS_U_B_DESC : MSA_3R_DESC_BASE<"subs_u.b", int_mips_subs_u_b, 2683 MSA128BOpnd>; 2684class SUBS_U_H_DESC : MSA_3R_DESC_BASE<"subs_u.h", int_mips_subs_u_h, 2685 MSA128HOpnd>; 2686class SUBS_U_W_DESC : MSA_3R_DESC_BASE<"subs_u.w", int_mips_subs_u_w, 2687 MSA128WOpnd>; 2688class SUBS_U_D_DESC : MSA_3R_DESC_BASE<"subs_u.d", int_mips_subs_u_d, 2689 MSA128DOpnd>; 2690 2691class SUBSUS_U_B_DESC : MSA_3R_DESC_BASE<"subsus_u.b", int_mips_subsus_u_b, 2692 MSA128BOpnd>; 2693class SUBSUS_U_H_DESC : MSA_3R_DESC_BASE<"subsus_u.h", int_mips_subsus_u_h, 2694 MSA128HOpnd>; 2695class SUBSUS_U_W_DESC : MSA_3R_DESC_BASE<"subsus_u.w", int_mips_subsus_u_w, 2696 MSA128WOpnd>; 2697class SUBSUS_U_D_DESC : MSA_3R_DESC_BASE<"subsus_u.d", int_mips_subsus_u_d, 2698 MSA128DOpnd>; 2699 2700class SUBSUU_S_B_DESC : MSA_3R_DESC_BASE<"subsuu_s.b", int_mips_subsuu_s_b, 2701 MSA128BOpnd>; 2702class SUBSUU_S_H_DESC : MSA_3R_DESC_BASE<"subsuu_s.h", int_mips_subsuu_s_h, 2703 MSA128HOpnd>; 2704class SUBSUU_S_W_DESC : MSA_3R_DESC_BASE<"subsuu_s.w", int_mips_subsuu_s_w, 2705 MSA128WOpnd>; 2706class SUBSUU_S_D_DESC : MSA_3R_DESC_BASE<"subsuu_s.d", int_mips_subsuu_s_d, 2707 MSA128DOpnd>; 2708 2709class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", sub, MSA128BOpnd>; 2710class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", sub, MSA128HOpnd>; 2711class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128WOpnd>; 2712class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128DOpnd>; 2713 2714class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5, 2715 MSA128BOpnd>; 2716class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5, 2717 MSA128HOpnd>; 2718class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5, 2719 MSA128WOpnd>; 2720class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5, 2721 MSA128DOpnd>; 2722 2723class VSHF_B_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.b", MSA128BOpnd>; 2724class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>; 2725class VSHF_W_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.w", MSA128WOpnd>; 2726class VSHF_D_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.d", MSA128DOpnd>; 2727 2728class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128BOpnd>; 2729class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128HOpnd>; 2730class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128WOpnd>; 2731class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128DOpnd>; 2732 2733class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8, 2734 MSA128BOpnd>; 2735 2736// Instruction defs. 2737def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC; 2738def ADD_A_H : ADD_A_H_ENC, ADD_A_H_DESC; 2739def ADD_A_W : ADD_A_W_ENC, ADD_A_W_DESC; 2740def ADD_A_D : ADD_A_D_ENC, ADD_A_D_DESC; 2741 2742def ADDS_A_B : ADDS_A_B_ENC, ADDS_A_B_DESC; 2743def ADDS_A_H : ADDS_A_H_ENC, ADDS_A_H_DESC; 2744def ADDS_A_W : ADDS_A_W_ENC, ADDS_A_W_DESC; 2745def ADDS_A_D : ADDS_A_D_ENC, ADDS_A_D_DESC; 2746 2747def ADDS_S_B : ADDS_S_B_ENC, ADDS_S_B_DESC; 2748def ADDS_S_H : ADDS_S_H_ENC, ADDS_S_H_DESC; 2749def ADDS_S_W : ADDS_S_W_ENC, ADDS_S_W_DESC; 2750def ADDS_S_D : ADDS_S_D_ENC, ADDS_S_D_DESC; 2751 2752def ADDS_U_B : ADDS_U_B_ENC, ADDS_U_B_DESC; 2753def ADDS_U_H : ADDS_U_H_ENC, ADDS_U_H_DESC; 2754def ADDS_U_W : ADDS_U_W_ENC, ADDS_U_W_DESC; 2755def ADDS_U_D : ADDS_U_D_ENC, ADDS_U_D_DESC; 2756 2757def ADDV_B : ADDV_B_ENC, ADDV_B_DESC; 2758def ADDV_H : ADDV_H_ENC, ADDV_H_DESC; 2759def ADDV_W : ADDV_W_ENC, ADDV_W_DESC; 2760def ADDV_D : ADDV_D_ENC, ADDV_D_DESC; 2761 2762def ADDVI_B : ADDVI_B_ENC, ADDVI_B_DESC; 2763def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC; 2764def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC; 2765def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC; 2766 2767def AND_V : AND_V_ENC, AND_V_DESC; 2768def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC, 2769 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2770 MSA128BOpnd:$ws, 2771 MSA128BOpnd:$wt)>; 2772def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC, 2773 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2774 MSA128BOpnd:$ws, 2775 MSA128BOpnd:$wt)>; 2776def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC, 2777 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2778 MSA128BOpnd:$ws, 2779 MSA128BOpnd:$wt)>; 2780 2781def ANDI_B : ANDI_B_ENC, ANDI_B_DESC; 2782 2783def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC; 2784def ASUB_S_H : ASUB_S_H_ENC, ASUB_S_H_DESC; 2785def ASUB_S_W : ASUB_S_W_ENC, ASUB_S_W_DESC; 2786def ASUB_S_D : ASUB_S_D_ENC, ASUB_S_D_DESC; 2787 2788def ASUB_U_B : ASUB_U_B_ENC, ASUB_U_B_DESC; 2789def ASUB_U_H : ASUB_U_H_ENC, ASUB_U_H_DESC; 2790def ASUB_U_W : ASUB_U_W_ENC, ASUB_U_W_DESC; 2791def ASUB_U_D : ASUB_U_D_ENC, ASUB_U_D_DESC; 2792 2793def AVE_S_B : AVE_S_B_ENC, AVE_S_B_DESC; 2794def AVE_S_H : AVE_S_H_ENC, AVE_S_H_DESC; 2795def AVE_S_W : AVE_S_W_ENC, AVE_S_W_DESC; 2796def AVE_S_D : AVE_S_D_ENC, AVE_S_D_DESC; 2797 2798def AVE_U_B : AVE_U_B_ENC, AVE_U_B_DESC; 2799def AVE_U_H : AVE_U_H_ENC, AVE_U_H_DESC; 2800def AVE_U_W : AVE_U_W_ENC, AVE_U_W_DESC; 2801def AVE_U_D : AVE_U_D_ENC, AVE_U_D_DESC; 2802 2803def AVER_S_B : AVER_S_B_ENC, AVER_S_B_DESC; 2804def AVER_S_H : AVER_S_H_ENC, AVER_S_H_DESC; 2805def AVER_S_W : AVER_S_W_ENC, AVER_S_W_DESC; 2806def AVER_S_D : AVER_S_D_ENC, AVER_S_D_DESC; 2807 2808def AVER_U_B : AVER_U_B_ENC, AVER_U_B_DESC; 2809def AVER_U_H : AVER_U_H_ENC, AVER_U_H_DESC; 2810def AVER_U_W : AVER_U_W_ENC, AVER_U_W_DESC; 2811def AVER_U_D : AVER_U_D_ENC, AVER_U_D_DESC; 2812 2813def BCLR_B : BCLR_B_ENC, BCLR_B_DESC; 2814def BCLR_H : BCLR_H_ENC, BCLR_H_DESC; 2815def BCLR_W : BCLR_W_ENC, BCLR_W_DESC; 2816def BCLR_D : BCLR_D_ENC, BCLR_D_DESC; 2817 2818def BCLRI_B : BCLRI_B_ENC, BCLRI_B_DESC; 2819def BCLRI_H : BCLRI_H_ENC, BCLRI_H_DESC; 2820def BCLRI_W : BCLRI_W_ENC, BCLRI_W_DESC; 2821def BCLRI_D : BCLRI_D_ENC, BCLRI_D_DESC; 2822 2823def BINSL_B : BINSL_B_ENC, BINSL_B_DESC; 2824def BINSL_H : BINSL_H_ENC, BINSL_H_DESC; 2825def BINSL_W : BINSL_W_ENC, BINSL_W_DESC; 2826def BINSL_D : BINSL_D_ENC, BINSL_D_DESC; 2827 2828def BINSLI_B : BINSLI_B_ENC, BINSLI_B_DESC; 2829def BINSLI_H : BINSLI_H_ENC, BINSLI_H_DESC; 2830def BINSLI_W : BINSLI_W_ENC, BINSLI_W_DESC; 2831def BINSLI_D : BINSLI_D_ENC, BINSLI_D_DESC; 2832 2833def BINSR_B : BINSR_B_ENC, BINSR_B_DESC; 2834def BINSR_H : BINSR_H_ENC, BINSR_H_DESC; 2835def BINSR_W : BINSR_W_ENC, BINSR_W_DESC; 2836def BINSR_D : BINSR_D_ENC, BINSR_D_DESC; 2837 2838def BINSRI_B : BINSRI_B_ENC, BINSRI_B_DESC; 2839def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC; 2840def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC; 2841def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC; 2842 2843def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC; 2844 2845def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC; 2846 2847def BMZ_V : BMZ_V_ENC, BMZ_V_DESC; 2848 2849def BMZI_B : BMZI_B_ENC, BMZI_B_DESC; 2850 2851def BNEG_B : BNEG_B_ENC, BNEG_B_DESC; 2852def BNEG_H : BNEG_H_ENC, BNEG_H_DESC; 2853def BNEG_W : BNEG_W_ENC, BNEG_W_DESC; 2854def BNEG_D : BNEG_D_ENC, BNEG_D_DESC; 2855 2856def BNEGI_B : BNEGI_B_ENC, BNEGI_B_DESC; 2857def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC; 2858def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC; 2859def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC; 2860 2861def BNZ_B : BNZ_B_ENC, BNZ_B_DESC; 2862def BNZ_H : BNZ_H_ENC, BNZ_H_DESC; 2863def BNZ_W : BNZ_W_ENC, BNZ_W_DESC; 2864def BNZ_D : BNZ_D_ENC, BNZ_D_DESC; 2865 2866def BNZ_V : BNZ_V_ENC, BNZ_V_DESC; 2867 2868def BSEL_V : BSEL_V_ENC, BSEL_V_DESC; 2869 2870class MSA_BSEL_PSEUDO_BASE<RegisterOperand RO, ValueType Ty> : 2871 MSAPseudo<(outs RO:$wd), (ins RO:$wd_in, RO:$ws, RO:$wt), 2872 [(set RO:$wd, (Ty (vselect RO:$wd_in, RO:$wt, RO:$ws)))]>, 2873 // Note that vselect and BSEL_V treat the condition operand the opposite way 2874 // from each other. 2875 // (vselect cond, if_set, if_clear) 2876 // (BSEL_V cond, if_clear, if_set) 2877 PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in, 2878 MSA128BOpnd:$ws, MSA128BOpnd:$wt)> { 2879 let Constraints = "$wd_in = $wd"; 2880} 2881 2882def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128HOpnd, v8i16>; 2883def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4i32>; 2884def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2i64>; 2885def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4f32>; 2886def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2f64>; 2887 2888def BSELI_B : BSELI_B_ENC, BSELI_B_DESC; 2889 2890def BSET_B : BSET_B_ENC, BSET_B_DESC; 2891def BSET_H : BSET_H_ENC, BSET_H_DESC; 2892def BSET_W : BSET_W_ENC, BSET_W_DESC; 2893def BSET_D : BSET_D_ENC, BSET_D_DESC; 2894 2895def BSETI_B : BSETI_B_ENC, BSETI_B_DESC; 2896def BSETI_H : BSETI_H_ENC, BSETI_H_DESC; 2897def BSETI_W : BSETI_W_ENC, BSETI_W_DESC; 2898def BSETI_D : BSETI_D_ENC, BSETI_D_DESC; 2899 2900def BZ_B : BZ_B_ENC, BZ_B_DESC; 2901def BZ_H : BZ_H_ENC, BZ_H_DESC; 2902def BZ_W : BZ_W_ENC, BZ_W_DESC; 2903def BZ_D : BZ_D_ENC, BZ_D_DESC; 2904 2905def BZ_V : BZ_V_ENC, BZ_V_DESC; 2906 2907def CEQ_B : CEQ_B_ENC, CEQ_B_DESC; 2908def CEQ_H : CEQ_H_ENC, CEQ_H_DESC; 2909def CEQ_W : CEQ_W_ENC, CEQ_W_DESC; 2910def CEQ_D : CEQ_D_ENC, CEQ_D_DESC; 2911 2912def CEQI_B : CEQI_B_ENC, CEQI_B_DESC; 2913def CEQI_H : CEQI_H_ENC, CEQI_H_DESC; 2914def CEQI_W : CEQI_W_ENC, CEQI_W_DESC; 2915def CEQI_D : CEQI_D_ENC, CEQI_D_DESC; 2916 2917def CFCMSA : CFCMSA_ENC, CFCMSA_DESC; 2918 2919def CLE_S_B : CLE_S_B_ENC, CLE_S_B_DESC; 2920def CLE_S_H : CLE_S_H_ENC, CLE_S_H_DESC; 2921def CLE_S_W : CLE_S_W_ENC, CLE_S_W_DESC; 2922def CLE_S_D : CLE_S_D_ENC, CLE_S_D_DESC; 2923 2924def CLE_U_B : CLE_U_B_ENC, CLE_U_B_DESC; 2925def CLE_U_H : CLE_U_H_ENC, CLE_U_H_DESC; 2926def CLE_U_W : CLE_U_W_ENC, CLE_U_W_DESC; 2927def CLE_U_D : CLE_U_D_ENC, CLE_U_D_DESC; 2928 2929def CLEI_S_B : CLEI_S_B_ENC, CLEI_S_B_DESC; 2930def CLEI_S_H : CLEI_S_H_ENC, CLEI_S_H_DESC; 2931def CLEI_S_W : CLEI_S_W_ENC, CLEI_S_W_DESC; 2932def CLEI_S_D : CLEI_S_D_ENC, CLEI_S_D_DESC; 2933 2934def CLEI_U_B : CLEI_U_B_ENC, CLEI_U_B_DESC; 2935def CLEI_U_H : CLEI_U_H_ENC, CLEI_U_H_DESC; 2936def CLEI_U_W : CLEI_U_W_ENC, CLEI_U_W_DESC; 2937def CLEI_U_D : CLEI_U_D_ENC, CLEI_U_D_DESC; 2938 2939def CLT_S_B : CLT_S_B_ENC, CLT_S_B_DESC; 2940def CLT_S_H : CLT_S_H_ENC, CLT_S_H_DESC; 2941def CLT_S_W : CLT_S_W_ENC, CLT_S_W_DESC; 2942def CLT_S_D : CLT_S_D_ENC, CLT_S_D_DESC; 2943 2944def CLT_U_B : CLT_U_B_ENC, CLT_U_B_DESC; 2945def CLT_U_H : CLT_U_H_ENC, CLT_U_H_DESC; 2946def CLT_U_W : CLT_U_W_ENC, CLT_U_W_DESC; 2947def CLT_U_D : CLT_U_D_ENC, CLT_U_D_DESC; 2948 2949def CLTI_S_B : CLTI_S_B_ENC, CLTI_S_B_DESC; 2950def CLTI_S_H : CLTI_S_H_ENC, CLTI_S_H_DESC; 2951def CLTI_S_W : CLTI_S_W_ENC, CLTI_S_W_DESC; 2952def CLTI_S_D : CLTI_S_D_ENC, CLTI_S_D_DESC; 2953 2954def CLTI_U_B : CLTI_U_B_ENC, CLTI_U_B_DESC; 2955def CLTI_U_H : CLTI_U_H_ENC, CLTI_U_H_DESC; 2956def CLTI_U_W : CLTI_U_W_ENC, CLTI_U_W_DESC; 2957def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC; 2958 2959def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC; 2960def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC; 2961def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC; 2962def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC, ASE_MSA64; 2963 2964def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC; 2965def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC; 2966def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC, ASE_MSA64; 2967 2968def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC; 2969def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC; 2970 2971def CTCMSA : CTCMSA_ENC, CTCMSA_DESC; 2972 2973def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC; 2974def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC; 2975def DIV_S_W : DIV_S_W_ENC, DIV_S_W_DESC; 2976def DIV_S_D : DIV_S_D_ENC, DIV_S_D_DESC; 2977 2978def DIV_U_B : DIV_U_B_ENC, DIV_U_B_DESC; 2979def DIV_U_H : DIV_U_H_ENC, DIV_U_H_DESC; 2980def DIV_U_W : DIV_U_W_ENC, DIV_U_W_DESC; 2981def DIV_U_D : DIV_U_D_ENC, DIV_U_D_DESC; 2982 2983def DOTP_S_H : DOTP_S_H_ENC, DOTP_S_H_DESC; 2984def DOTP_S_W : DOTP_S_W_ENC, DOTP_S_W_DESC; 2985def DOTP_S_D : DOTP_S_D_ENC, DOTP_S_D_DESC; 2986 2987def DOTP_U_H : DOTP_U_H_ENC, DOTP_U_H_DESC; 2988def DOTP_U_W : DOTP_U_W_ENC, DOTP_U_W_DESC; 2989def DOTP_U_D : DOTP_U_D_ENC, DOTP_U_D_DESC; 2990 2991def DPADD_S_H : DPADD_S_H_ENC, DPADD_S_H_DESC; 2992def DPADD_S_W : DPADD_S_W_ENC, DPADD_S_W_DESC; 2993def DPADD_S_D : DPADD_S_D_ENC, DPADD_S_D_DESC; 2994 2995def DPADD_U_H : DPADD_U_H_ENC, DPADD_U_H_DESC; 2996def DPADD_U_W : DPADD_U_W_ENC, DPADD_U_W_DESC; 2997def DPADD_U_D : DPADD_U_D_ENC, DPADD_U_D_DESC; 2998 2999def DPSUB_S_H : DPSUB_S_H_ENC, DPSUB_S_H_DESC; 3000def DPSUB_S_W : DPSUB_S_W_ENC, DPSUB_S_W_DESC; 3001def DPSUB_S_D : DPSUB_S_D_ENC, DPSUB_S_D_DESC; 3002 3003def DPSUB_U_H : DPSUB_U_H_ENC, DPSUB_U_H_DESC; 3004def DPSUB_U_W : DPSUB_U_W_ENC, DPSUB_U_W_DESC; 3005def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC; 3006 3007def FADD_W : FADD_W_ENC, FADD_W_DESC; 3008def FADD_D : FADD_D_ENC, FADD_D_DESC; 3009 3010def FCAF_W : FCAF_W_ENC, FCAF_W_DESC; 3011def FCAF_D : FCAF_D_ENC, FCAF_D_DESC; 3012 3013def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC; 3014def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC; 3015 3016def FCLE_W : FCLE_W_ENC, FCLE_W_DESC; 3017def FCLE_D : FCLE_D_ENC, FCLE_D_DESC; 3018 3019def FCLT_W : FCLT_W_ENC, FCLT_W_DESC; 3020def FCLT_D : FCLT_D_ENC, FCLT_D_DESC; 3021 3022def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC; 3023def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC; 3024 3025def FCNE_W : FCNE_W_ENC, FCNE_W_DESC; 3026def FCNE_D : FCNE_D_ENC, FCNE_D_DESC; 3027 3028def FCOR_W : FCOR_W_ENC, FCOR_W_DESC; 3029def FCOR_D : FCOR_D_ENC, FCOR_D_DESC; 3030 3031def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC; 3032def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC; 3033 3034def FCULE_W : FCULE_W_ENC, FCULE_W_DESC; 3035def FCULE_D : FCULE_D_ENC, FCULE_D_DESC; 3036 3037def FCULT_W : FCULT_W_ENC, FCULT_W_DESC; 3038def FCULT_D : FCULT_D_ENC, FCULT_D_DESC; 3039 3040def FCUN_W : FCUN_W_ENC, FCUN_W_DESC; 3041def FCUN_D : FCUN_D_ENC, FCUN_D_DESC; 3042 3043def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC; 3044def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC; 3045 3046def FDIV_W : FDIV_W_ENC, FDIV_W_DESC; 3047def FDIV_D : FDIV_D_ENC, FDIV_D_DESC; 3048 3049def FEXDO_H : FEXDO_H_ENC, FEXDO_H_DESC; 3050def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC; 3051 3052def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC; 3053def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC; 3054def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC; 3055def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC; 3056 3057def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC; 3058def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC; 3059 3060def FEXUPR_W : FEXUPR_W_ENC, FEXUPR_W_DESC; 3061def FEXUPR_D : FEXUPR_D_ENC, FEXUPR_D_DESC; 3062 3063def FFINT_S_W : FFINT_S_W_ENC, FFINT_S_W_DESC; 3064def FFINT_S_D : FFINT_S_D_ENC, FFINT_S_D_DESC; 3065 3066def FFINT_U_W : FFINT_U_W_ENC, FFINT_U_W_DESC; 3067def FFINT_U_D : FFINT_U_D_ENC, FFINT_U_D_DESC; 3068 3069def FFQL_W : FFQL_W_ENC, FFQL_W_DESC; 3070def FFQL_D : FFQL_D_ENC, FFQL_D_DESC; 3071 3072def FFQR_W : FFQR_W_ENC, FFQR_W_DESC; 3073def FFQR_D : FFQR_D_ENC, FFQR_D_DESC; 3074 3075def FILL_B : FILL_B_ENC, FILL_B_DESC; 3076def FILL_H : FILL_H_ENC, FILL_H_DESC; 3077def FILL_W : FILL_W_ENC, FILL_W_DESC; 3078def FILL_D : FILL_D_ENC, FILL_D_DESC, ASE_MSA64; 3079def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC; 3080def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC; 3081 3082def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC; 3083def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC; 3084 3085def FMADD_W : FMADD_W_ENC, FMADD_W_DESC; 3086def FMADD_D : FMADD_D_ENC, FMADD_D_DESC; 3087 3088def FMAX_W : FMAX_W_ENC, FMAX_W_DESC; 3089def FMAX_D : FMAX_D_ENC, FMAX_D_DESC; 3090 3091def FMAX_A_W : FMAX_A_W_ENC, FMAX_A_W_DESC; 3092def FMAX_A_D : FMAX_A_D_ENC, FMAX_A_D_DESC; 3093 3094def FMIN_W : FMIN_W_ENC, FMIN_W_DESC; 3095def FMIN_D : FMIN_D_ENC, FMIN_D_DESC; 3096 3097def FMIN_A_W : FMIN_A_W_ENC, FMIN_A_W_DESC; 3098def FMIN_A_D : FMIN_A_D_ENC, FMIN_A_D_DESC; 3099 3100def FMSUB_W : FMSUB_W_ENC, FMSUB_W_DESC; 3101def FMSUB_D : FMSUB_D_ENC, FMSUB_D_DESC; 3102 3103def FMUL_W : FMUL_W_ENC, FMUL_W_DESC; 3104def FMUL_D : FMUL_D_ENC, FMUL_D_DESC; 3105 3106def FRINT_W : FRINT_W_ENC, FRINT_W_DESC; 3107def FRINT_D : FRINT_D_ENC, FRINT_D_DESC; 3108 3109def FRCP_W : FRCP_W_ENC, FRCP_W_DESC; 3110def FRCP_D : FRCP_D_ENC, FRCP_D_DESC; 3111 3112def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC; 3113def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC; 3114 3115def FSAF_W : FSAF_W_ENC, FSAF_W_DESC; 3116def FSAF_D : FSAF_D_ENC, FSAF_D_DESC; 3117 3118def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC; 3119def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC; 3120 3121def FSLE_W : FSLE_W_ENC, FSLE_W_DESC; 3122def FSLE_D : FSLE_D_ENC, FSLE_D_DESC; 3123 3124def FSLT_W : FSLT_W_ENC, FSLT_W_DESC; 3125def FSLT_D : FSLT_D_ENC, FSLT_D_DESC; 3126 3127def FSNE_W : FSNE_W_ENC, FSNE_W_DESC; 3128def FSNE_D : FSNE_D_ENC, FSNE_D_DESC; 3129 3130def FSOR_W : FSOR_W_ENC, FSOR_W_DESC; 3131def FSOR_D : FSOR_D_ENC, FSOR_D_DESC; 3132 3133def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC; 3134def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC; 3135 3136def FSUB_W : FSUB_W_ENC, FSUB_W_DESC; 3137def FSUB_D : FSUB_D_ENC, FSUB_D_DESC; 3138 3139def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC; 3140def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC; 3141 3142def FSULE_W : FSULE_W_ENC, FSULE_W_DESC; 3143def FSULE_D : FSULE_D_ENC, FSULE_D_DESC; 3144 3145def FSULT_W : FSULT_W_ENC, FSULT_W_DESC; 3146def FSULT_D : FSULT_D_ENC, FSULT_D_DESC; 3147 3148def FSUN_W : FSUN_W_ENC, FSUN_W_DESC; 3149def FSUN_D : FSUN_D_ENC, FSUN_D_DESC; 3150 3151def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC; 3152def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC; 3153 3154def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC; 3155def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC; 3156 3157def FTINT_U_W : FTINT_U_W_ENC, FTINT_U_W_DESC; 3158def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC; 3159 3160def FTQ_H : FTQ_H_ENC, FTQ_H_DESC; 3161def FTQ_W : FTQ_W_ENC, FTQ_W_DESC; 3162 3163def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC; 3164def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC; 3165 3166def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC; 3167def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC; 3168 3169def : MipsPat<(fsub MSA128WOpnd:$wd, (fmul MSA128WOpnd:$ws, MSA128WOpnd:$wt)), 3170 (FMSUB_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, MSA128WOpnd:$wt)>, 3171 ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST; 3172def : MipsPat<(fsub MSA128DOpnd:$wd, (fmul MSA128DOpnd:$ws, MSA128DOpnd:$wt)), 3173 (FMSUB_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, MSA128DOpnd:$wt)>, 3174 ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST; 3175 3176def : MipsPat<(fadd MSA128WOpnd:$wd, (fmul MSA128WOpnd:$ws, MSA128WOpnd:$wt)), 3177 (FMADD_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, MSA128WOpnd:$wt)>, 3178 ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST; 3179def : MipsPat<(fadd MSA128DOpnd:$wd, (fmul MSA128DOpnd:$ws, MSA128DOpnd:$wt)), 3180 (FMADD_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, MSA128DOpnd:$wt)>, 3181 ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST; 3182 3183def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC; 3184def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC; 3185def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC; 3186 3187def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC; 3188def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC; 3189def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC; 3190 3191def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC; 3192def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC; 3193def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC; 3194 3195def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC; 3196def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC; 3197def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC; 3198 3199def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC; 3200def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC; 3201def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC; 3202def ILVEV_D : ILVEV_D_ENC, ILVEV_D_DESC; 3203 3204def ILVL_B : ILVL_B_ENC, ILVL_B_DESC; 3205def ILVL_H : ILVL_H_ENC, ILVL_H_DESC; 3206def ILVL_W : ILVL_W_ENC, ILVL_W_DESC; 3207def ILVL_D : ILVL_D_ENC, ILVL_D_DESC; 3208 3209def ILVOD_B : ILVOD_B_ENC, ILVOD_B_DESC; 3210def ILVOD_H : ILVOD_H_ENC, ILVOD_H_DESC; 3211def ILVOD_W : ILVOD_W_ENC, ILVOD_W_DESC; 3212def ILVOD_D : ILVOD_D_ENC, ILVOD_D_DESC; 3213 3214def ILVR_B : ILVR_B_ENC, ILVR_B_DESC; 3215def ILVR_H : ILVR_H_ENC, ILVR_H_DESC; 3216def ILVR_W : ILVR_W_ENC, ILVR_W_DESC; 3217def ILVR_D : ILVR_D_ENC, ILVR_D_DESC; 3218 3219def INSERT_B : INSERT_B_ENC, INSERT_B_DESC; 3220def INSERT_H : INSERT_H_ENC, INSERT_H_DESC; 3221def INSERT_W : INSERT_W_ENC, INSERT_W_DESC; 3222def INSERT_D : INSERT_D_ENC, INSERT_D_DESC, ASE_MSA64; 3223 3224// INSERT_FW_PSEUDO defined after INSVE_W 3225// INSERT_FD_PSEUDO defined after INSVE_D 3226 3227// There is a fourth operand that is not present in the encoding. Use a 3228// custom decoder to get a chance to add it. 3229let DecoderMethod = "DecodeINSVE_DF" in { 3230 def INSVE_B : INSVE_B_ENC, INSVE_B_DESC; 3231 def INSVE_H : INSVE_H_ENC, INSVE_H_DESC; 3232 def INSVE_W : INSVE_W_ENC, INSVE_W_DESC; 3233 def INSVE_D : INSVE_D_ENC, INSVE_D_DESC; 3234} 3235 3236def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC; 3237def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC; 3238 3239def INSERT_B_VIDX_PSEUDO : INSERT_B_VIDX_PSEUDO_DESC; 3240def INSERT_H_VIDX_PSEUDO : INSERT_H_VIDX_PSEUDO_DESC; 3241def INSERT_W_VIDX_PSEUDO : INSERT_W_VIDX_PSEUDO_DESC; 3242def INSERT_D_VIDX_PSEUDO : INSERT_D_VIDX_PSEUDO_DESC; 3243def INSERT_FW_VIDX_PSEUDO : INSERT_FW_VIDX_PSEUDO_DESC; 3244def INSERT_FD_VIDX_PSEUDO : INSERT_FD_VIDX_PSEUDO_DESC; 3245 3246def INSERT_B_VIDX64_PSEUDO : INSERT_B_VIDX64_PSEUDO_DESC; 3247def INSERT_H_VIDX64_PSEUDO : INSERT_H_VIDX64_PSEUDO_DESC; 3248def INSERT_W_VIDX64_PSEUDO : INSERT_W_VIDX64_PSEUDO_DESC; 3249def INSERT_D_VIDX64_PSEUDO : INSERT_D_VIDX64_PSEUDO_DESC; 3250def INSERT_FW_VIDX64_PSEUDO : INSERT_FW_VIDX64_PSEUDO_DESC; 3251def INSERT_FD_VIDX64_PSEUDO : INSERT_FD_VIDX64_PSEUDO_DESC; 3252 3253def LD_B: LD_B_ENC, LD_B_DESC; 3254def LD_H: LD_H_ENC, LD_H_DESC; 3255def LD_W: LD_W_ENC, LD_W_DESC; 3256def LD_D: LD_D_ENC, LD_D_DESC; 3257 3258def LDI_B : LDI_B_ENC, LDI_B_DESC; 3259def LDI_H : LDI_H_ENC, LDI_H_DESC; 3260def LDI_W : LDI_W_ENC, LDI_W_DESC; 3261def LDI_D : LDI_D_ENC, LDI_D_DESC; 3262 3263def LSA : LSA_ENC, LSA_DESC; 3264def DLSA : DLSA_ENC, DLSA_DESC, ASE_MSA64; 3265 3266def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC; 3267def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC; 3268 3269def MADDR_Q_H : MADDR_Q_H_ENC, MADDR_Q_H_DESC; 3270def MADDR_Q_W : MADDR_Q_W_ENC, MADDR_Q_W_DESC; 3271 3272def MADDV_B : MADDV_B_ENC, MADDV_B_DESC; 3273def MADDV_H : MADDV_H_ENC, MADDV_H_DESC; 3274def MADDV_W : MADDV_W_ENC, MADDV_W_DESC; 3275def MADDV_D : MADDV_D_ENC, MADDV_D_DESC; 3276 3277def MAX_A_B : MAX_A_B_ENC, MAX_A_B_DESC; 3278def MAX_A_H : MAX_A_H_ENC, MAX_A_H_DESC; 3279def MAX_A_W : MAX_A_W_ENC, MAX_A_W_DESC; 3280def MAX_A_D : MAX_A_D_ENC, MAX_A_D_DESC; 3281 3282def MAX_S_B : MAX_S_B_ENC, MAX_S_B_DESC; 3283def MAX_S_H : MAX_S_H_ENC, MAX_S_H_DESC; 3284def MAX_S_W : MAX_S_W_ENC, MAX_S_W_DESC; 3285def MAX_S_D : MAX_S_D_ENC, MAX_S_D_DESC; 3286 3287def MAX_U_B : MAX_U_B_ENC, MAX_U_B_DESC; 3288def MAX_U_H : MAX_U_H_ENC, MAX_U_H_DESC; 3289def MAX_U_W : MAX_U_W_ENC, MAX_U_W_DESC; 3290def MAX_U_D : MAX_U_D_ENC, MAX_U_D_DESC; 3291 3292def MAXI_S_B : MAXI_S_B_ENC, MAXI_S_B_DESC; 3293def MAXI_S_H : MAXI_S_H_ENC, MAXI_S_H_DESC; 3294def MAXI_S_W : MAXI_S_W_ENC, MAXI_S_W_DESC; 3295def MAXI_S_D : MAXI_S_D_ENC, MAXI_S_D_DESC; 3296 3297def MAXI_U_B : MAXI_U_B_ENC, MAXI_U_B_DESC; 3298def MAXI_U_H : MAXI_U_H_ENC, MAXI_U_H_DESC; 3299def MAXI_U_W : MAXI_U_W_ENC, MAXI_U_W_DESC; 3300def MAXI_U_D : MAXI_U_D_ENC, MAXI_U_D_DESC; 3301 3302def MIN_A_B : MIN_A_B_ENC, MIN_A_B_DESC; 3303def MIN_A_H : MIN_A_H_ENC, MIN_A_H_DESC; 3304def MIN_A_W : MIN_A_W_ENC, MIN_A_W_DESC; 3305def MIN_A_D : MIN_A_D_ENC, MIN_A_D_DESC; 3306 3307def MIN_S_B : MIN_S_B_ENC, MIN_S_B_DESC; 3308def MIN_S_H : MIN_S_H_ENC, MIN_S_H_DESC; 3309def MIN_S_W : MIN_S_W_ENC, MIN_S_W_DESC; 3310def MIN_S_D : MIN_S_D_ENC, MIN_S_D_DESC; 3311 3312def MIN_U_B : MIN_U_B_ENC, MIN_U_B_DESC; 3313def MIN_U_H : MIN_U_H_ENC, MIN_U_H_DESC; 3314def MIN_U_W : MIN_U_W_ENC, MIN_U_W_DESC; 3315def MIN_U_D : MIN_U_D_ENC, MIN_U_D_DESC; 3316 3317def MINI_S_B : MINI_S_B_ENC, MINI_S_B_DESC; 3318def MINI_S_H : MINI_S_H_ENC, MINI_S_H_DESC; 3319def MINI_S_W : MINI_S_W_ENC, MINI_S_W_DESC; 3320def MINI_S_D : MINI_S_D_ENC, MINI_S_D_DESC; 3321 3322def MINI_U_B : MINI_U_B_ENC, MINI_U_B_DESC; 3323def MINI_U_H : MINI_U_H_ENC, MINI_U_H_DESC; 3324def MINI_U_W : MINI_U_W_ENC, MINI_U_W_DESC; 3325def MINI_U_D : MINI_U_D_ENC, MINI_U_D_DESC; 3326 3327def MOD_S_B : MOD_S_B_ENC, MOD_S_B_DESC; 3328def MOD_S_H : MOD_S_H_ENC, MOD_S_H_DESC; 3329def MOD_S_W : MOD_S_W_ENC, MOD_S_W_DESC; 3330def MOD_S_D : MOD_S_D_ENC, MOD_S_D_DESC; 3331 3332def MOD_U_B : MOD_U_B_ENC, MOD_U_B_DESC; 3333def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC; 3334def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC; 3335def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC; 3336 3337def MOVE_V : MOVE_V_ENC, MOVE_V_DESC; 3338 3339def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC; 3340def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC; 3341 3342def MSUBR_Q_H : MSUBR_Q_H_ENC, MSUBR_Q_H_DESC; 3343def MSUBR_Q_W : MSUBR_Q_W_ENC, MSUBR_Q_W_DESC; 3344 3345def MSUBV_B : MSUBV_B_ENC, MSUBV_B_DESC; 3346def MSUBV_H : MSUBV_H_ENC, MSUBV_H_DESC; 3347def MSUBV_W : MSUBV_W_ENC, MSUBV_W_DESC; 3348def MSUBV_D : MSUBV_D_ENC, MSUBV_D_DESC; 3349 3350def MUL_Q_H : MUL_Q_H_ENC, MUL_Q_H_DESC; 3351def MUL_Q_W : MUL_Q_W_ENC, MUL_Q_W_DESC; 3352 3353def MULR_Q_H : MULR_Q_H_ENC, MULR_Q_H_DESC; 3354def MULR_Q_W : MULR_Q_W_ENC, MULR_Q_W_DESC; 3355 3356def MULV_B : MULV_B_ENC, MULV_B_DESC; 3357def MULV_H : MULV_H_ENC, MULV_H_DESC; 3358def MULV_W : MULV_W_ENC, MULV_W_DESC; 3359def MULV_D : MULV_D_ENC, MULV_D_DESC; 3360 3361def NLOC_B : NLOC_B_ENC, NLOC_B_DESC; 3362def NLOC_H : NLOC_H_ENC, NLOC_H_DESC; 3363def NLOC_W : NLOC_W_ENC, NLOC_W_DESC; 3364def NLOC_D : NLOC_D_ENC, NLOC_D_DESC; 3365 3366def NLZC_B : NLZC_B_ENC, NLZC_B_DESC; 3367def NLZC_H : NLZC_H_ENC, NLZC_H_DESC; 3368def NLZC_W : NLZC_W_ENC, NLZC_W_DESC; 3369def NLZC_D : NLZC_D_ENC, NLZC_D_DESC; 3370 3371def NOR_V : NOR_V_ENC, NOR_V_DESC; 3372def NOR_V_H_PSEUDO : NOR_V_H_PSEUDO_DESC, 3373 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3374 MSA128BOpnd:$ws, 3375 MSA128BOpnd:$wt)>; 3376def NOR_V_W_PSEUDO : NOR_V_W_PSEUDO_DESC, 3377 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3378 MSA128BOpnd:$ws, 3379 MSA128BOpnd:$wt)>; 3380def NOR_V_D_PSEUDO : NOR_V_D_PSEUDO_DESC, 3381 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3382 MSA128BOpnd:$ws, 3383 MSA128BOpnd:$wt)>; 3384 3385def NORI_B : NORI_B_ENC, NORI_B_DESC; 3386 3387def OR_V : OR_V_ENC, OR_V_DESC; 3388def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC, 3389 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3390 MSA128BOpnd:$ws, 3391 MSA128BOpnd:$wt)>; 3392def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC, 3393 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3394 MSA128BOpnd:$ws, 3395 MSA128BOpnd:$wt)>; 3396def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC, 3397 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3398 MSA128BOpnd:$ws, 3399 MSA128BOpnd:$wt)>; 3400 3401def ORI_B : ORI_B_ENC, ORI_B_DESC; 3402 3403def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC; 3404def PCKEV_H : PCKEV_H_ENC, PCKEV_H_DESC; 3405def PCKEV_W : PCKEV_W_ENC, PCKEV_W_DESC; 3406def PCKEV_D : PCKEV_D_ENC, PCKEV_D_DESC; 3407 3408def PCKOD_B : PCKOD_B_ENC, PCKOD_B_DESC; 3409def PCKOD_H : PCKOD_H_ENC, PCKOD_H_DESC; 3410def PCKOD_W : PCKOD_W_ENC, PCKOD_W_DESC; 3411def PCKOD_D : PCKOD_D_ENC, PCKOD_D_DESC; 3412 3413def PCNT_B : PCNT_B_ENC, PCNT_B_DESC; 3414def PCNT_H : PCNT_H_ENC, PCNT_H_DESC; 3415def PCNT_W : PCNT_W_ENC, PCNT_W_DESC; 3416def PCNT_D : PCNT_D_ENC, PCNT_D_DESC; 3417 3418def SAT_S_B : SAT_S_B_ENC, SAT_S_B_DESC; 3419def SAT_S_H : SAT_S_H_ENC, SAT_S_H_DESC; 3420def SAT_S_W : SAT_S_W_ENC, SAT_S_W_DESC; 3421def SAT_S_D : SAT_S_D_ENC, SAT_S_D_DESC; 3422 3423def SAT_U_B : SAT_U_B_ENC, SAT_U_B_DESC; 3424def SAT_U_H : SAT_U_H_ENC, SAT_U_H_DESC; 3425def SAT_U_W : SAT_U_W_ENC, SAT_U_W_DESC; 3426def SAT_U_D : SAT_U_D_ENC, SAT_U_D_DESC; 3427 3428def SHF_B : SHF_B_ENC, SHF_B_DESC; 3429def SHF_H : SHF_H_ENC, SHF_H_DESC; 3430def SHF_W : SHF_W_ENC, SHF_W_DESC; 3431 3432def SLD_B : SLD_B_ENC, SLD_B_DESC; 3433def SLD_H : SLD_H_ENC, SLD_H_DESC; 3434def SLD_W : SLD_W_ENC, SLD_W_DESC; 3435def SLD_D : SLD_D_ENC, SLD_D_DESC; 3436 3437def SLDI_B : SLDI_B_ENC, SLDI_B_DESC; 3438def SLDI_H : SLDI_H_ENC, SLDI_H_DESC; 3439def SLDI_W : SLDI_W_ENC, SLDI_W_DESC; 3440def SLDI_D : SLDI_D_ENC, SLDI_D_DESC; 3441 3442def SLL_B : SLL_B_ENC, SLL_B_DESC; 3443def SLL_H : SLL_H_ENC, SLL_H_DESC; 3444def SLL_W : SLL_W_ENC, SLL_W_DESC; 3445def SLL_D : SLL_D_ENC, SLL_D_DESC; 3446 3447def SLLI_B : SLLI_B_ENC, SLLI_B_DESC; 3448def SLLI_H : SLLI_H_ENC, SLLI_H_DESC; 3449def SLLI_W : SLLI_W_ENC, SLLI_W_DESC; 3450def SLLI_D : SLLI_D_ENC, SLLI_D_DESC; 3451 3452def SPLAT_B : SPLAT_B_ENC, SPLAT_B_DESC; 3453def SPLAT_H : SPLAT_H_ENC, SPLAT_H_DESC; 3454def SPLAT_W : SPLAT_W_ENC, SPLAT_W_DESC; 3455def SPLAT_D : SPLAT_D_ENC, SPLAT_D_DESC; 3456 3457def SPLATI_B : SPLATI_B_ENC, SPLATI_B_DESC; 3458def SPLATI_H : SPLATI_H_ENC, SPLATI_H_DESC; 3459def SPLATI_W : SPLATI_W_ENC, SPLATI_W_DESC; 3460def SPLATI_D : SPLATI_D_ENC, SPLATI_D_DESC; 3461 3462def SRA_B : SRA_B_ENC, SRA_B_DESC; 3463def SRA_H : SRA_H_ENC, SRA_H_DESC; 3464def SRA_W : SRA_W_ENC, SRA_W_DESC; 3465def SRA_D : SRA_D_ENC, SRA_D_DESC; 3466 3467def SRAI_B : SRAI_B_ENC, SRAI_B_DESC; 3468def SRAI_H : SRAI_H_ENC, SRAI_H_DESC; 3469def SRAI_W : SRAI_W_ENC, SRAI_W_DESC; 3470def SRAI_D : SRAI_D_ENC, SRAI_D_DESC; 3471 3472def SRAR_B : SRAR_B_ENC, SRAR_B_DESC; 3473def SRAR_H : SRAR_H_ENC, SRAR_H_DESC; 3474def SRAR_W : SRAR_W_ENC, SRAR_W_DESC; 3475def SRAR_D : SRAR_D_ENC, SRAR_D_DESC; 3476 3477def SRARI_B : SRARI_B_ENC, SRARI_B_DESC; 3478def SRARI_H : SRARI_H_ENC, SRARI_H_DESC; 3479def SRARI_W : SRARI_W_ENC, SRARI_W_DESC; 3480def SRARI_D : SRARI_D_ENC, SRARI_D_DESC; 3481 3482def SRL_B : SRL_B_ENC, SRL_B_DESC; 3483def SRL_H : SRL_H_ENC, SRL_H_DESC; 3484def SRL_W : SRL_W_ENC, SRL_W_DESC; 3485def SRL_D : SRL_D_ENC, SRL_D_DESC; 3486 3487def SRLI_B : SRLI_B_ENC, SRLI_B_DESC; 3488def SRLI_H : SRLI_H_ENC, SRLI_H_DESC; 3489def SRLI_W : SRLI_W_ENC, SRLI_W_DESC; 3490def SRLI_D : SRLI_D_ENC, SRLI_D_DESC; 3491 3492def SRLR_B : SRLR_B_ENC, SRLR_B_DESC; 3493def SRLR_H : SRLR_H_ENC, SRLR_H_DESC; 3494def SRLR_W : SRLR_W_ENC, SRLR_W_DESC; 3495def SRLR_D : SRLR_D_ENC, SRLR_D_DESC; 3496 3497def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC; 3498def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC; 3499def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC; 3500def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC; 3501 3502def ST_B: ST_B_ENC, ST_B_DESC; 3503def ST_H: ST_H_ENC, ST_H_DESC; 3504def ST_W: ST_W_ENC, ST_W_DESC; 3505def ST_D: ST_D_ENC, ST_D_DESC; 3506 3507def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC; 3508def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC; 3509def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC; 3510def SUBS_S_D : SUBS_S_D_ENC, SUBS_S_D_DESC; 3511 3512def SUBS_U_B : SUBS_U_B_ENC, SUBS_U_B_DESC; 3513def SUBS_U_H : SUBS_U_H_ENC, SUBS_U_H_DESC; 3514def SUBS_U_W : SUBS_U_W_ENC, SUBS_U_W_DESC; 3515def SUBS_U_D : SUBS_U_D_ENC, SUBS_U_D_DESC; 3516 3517def SUBSUS_U_B : SUBSUS_U_B_ENC, SUBSUS_U_B_DESC; 3518def SUBSUS_U_H : SUBSUS_U_H_ENC, SUBSUS_U_H_DESC; 3519def SUBSUS_U_W : SUBSUS_U_W_ENC, SUBSUS_U_W_DESC; 3520def SUBSUS_U_D : SUBSUS_U_D_ENC, SUBSUS_U_D_DESC; 3521 3522def SUBSUU_S_B : SUBSUU_S_B_ENC, SUBSUU_S_B_DESC; 3523def SUBSUU_S_H : SUBSUU_S_H_ENC, SUBSUU_S_H_DESC; 3524def SUBSUU_S_W : SUBSUU_S_W_ENC, SUBSUU_S_W_DESC; 3525def SUBSUU_S_D : SUBSUU_S_D_ENC, SUBSUU_S_D_DESC; 3526 3527def SUBV_B : SUBV_B_ENC, SUBV_B_DESC; 3528def SUBV_H : SUBV_H_ENC, SUBV_H_DESC; 3529def SUBV_W : SUBV_W_ENC, SUBV_W_DESC; 3530def SUBV_D : SUBV_D_ENC, SUBV_D_DESC; 3531 3532def SUBVI_B : SUBVI_B_ENC, SUBVI_B_DESC; 3533def SUBVI_H : SUBVI_H_ENC, SUBVI_H_DESC; 3534def SUBVI_W : SUBVI_W_ENC, SUBVI_W_DESC; 3535def SUBVI_D : SUBVI_D_ENC, SUBVI_D_DESC; 3536 3537def VSHF_B : VSHF_B_ENC, VSHF_B_DESC; 3538def VSHF_H : VSHF_H_ENC, VSHF_H_DESC; 3539def VSHF_W : VSHF_W_ENC, VSHF_W_DESC; 3540def VSHF_D : VSHF_D_ENC, VSHF_D_DESC; 3541 3542def XOR_V : XOR_V_ENC, XOR_V_DESC; 3543def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC, 3544 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3545 MSA128BOpnd:$ws, 3546 MSA128BOpnd:$wt)>; 3547def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC, 3548 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3549 MSA128BOpnd:$ws, 3550 MSA128BOpnd:$wt)>; 3551def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC, 3552 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3553 MSA128BOpnd:$ws, 3554 MSA128BOpnd:$wt)>; 3555 3556def XORI_B : XORI_B_ENC, XORI_B_DESC; 3557 3558// Patterns. 3559class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> : 3560 Pat<pattern, result>, Requires<pred>; 3561 3562def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx), 3563 (COPY_S_W MSA128W:$ws, immZExt4:$idx)>; 3564 3565def : MSAPat<(v8f16 (load addrimm10lsl1:$addr)), (LD_H addrimm10lsl1:$addr)>; 3566def : MSAPat<(v4f32 (load addrimm10lsl2:$addr)), (LD_W addrimm10lsl2:$addr)>; 3567def : MSAPat<(v2f64 (load addrimm10lsl3:$addr)), (LD_D addrimm10lsl3:$addr)>; 3568 3569def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10lsl1:$addr), 3570 (ST_H MSA128H:$ws, addrimm10lsl1:$addr)>; 3571def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrimm10lsl2:$addr), 3572 (ST_W MSA128W:$ws, addrimm10lsl2:$addr)>; 3573def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrimm10lsl3:$addr), 3574 (ST_D MSA128D:$ws, addrimm10lsl3:$addr)>; 3575 3576class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD, 3577 RegisterOperand ROWS = ROWD, 3578 InstrItinClass itin = NoItinerary> : 3579 MSAPseudo<(outs ROWD:$wd), 3580 (ins ROWS:$ws), 3581 [(set ROWD:$wd, (fabs ROWS:$ws))]> { 3582 InstrItinClass Itinerary = itin; 3583} 3584def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>, 3585 PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, 3586 MSA128WOpnd:$ws)>; 3587def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128DOpnd>, 3588 PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, 3589 MSA128DOpnd:$ws)>; 3590 3591class MSABitconvertPat<ValueType DstVT, ValueType SrcVT, 3592 RegisterClass DstRC, list<Predicate> preds = [HasMSA]> : 3593 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3594 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>; 3595 3596// These are endian-independent because the element size doesnt change 3597def : MSABitconvertPat<v8i16, v8f16, MSA128H>; 3598def : MSABitconvertPat<v4i32, v4f32, MSA128W>; 3599def : MSABitconvertPat<v2i64, v2f64, MSA128D>; 3600def : MSABitconvertPat<v8f16, v8i16, MSA128H>; 3601def : MSABitconvertPat<v4f32, v4i32, MSA128W>; 3602def : MSABitconvertPat<v2f64, v2i64, MSA128D>; 3603 3604// Little endian bitcasts are always no-ops 3605def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>; 3606def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>; 3607def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>; 3608def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>; 3609def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>; 3610def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>; 3611 3612def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>; 3613def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>; 3614def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>; 3615def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>; 3616def : MSABitconvertPat<v8i16, v2f64, MSA128H, [HasMSA, IsLE]>; 3617 3618def : MSABitconvertPat<v4i32, v16i8, MSA128W, [HasMSA, IsLE]>; 3619def : MSABitconvertPat<v4i32, v8i16, MSA128W, [HasMSA, IsLE]>; 3620def : MSABitconvertPat<v4i32, v2i64, MSA128W, [HasMSA, IsLE]>; 3621def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>; 3622def : MSABitconvertPat<v4i32, v2f64, MSA128W, [HasMSA, IsLE]>; 3623 3624def : MSABitconvertPat<v2i64, v16i8, MSA128D, [HasMSA, IsLE]>; 3625def : MSABitconvertPat<v2i64, v8i16, MSA128D, [HasMSA, IsLE]>; 3626def : MSABitconvertPat<v2i64, v4i32, MSA128D, [HasMSA, IsLE]>; 3627def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>; 3628def : MSABitconvertPat<v2i64, v4f32, MSA128D, [HasMSA, IsLE]>; 3629 3630def : MSABitconvertPat<v4f32, v16i8, MSA128W, [HasMSA, IsLE]>; 3631def : MSABitconvertPat<v4f32, v8i16, MSA128W, [HasMSA, IsLE]>; 3632def : MSABitconvertPat<v4f32, v2i64, MSA128W, [HasMSA, IsLE]>; 3633def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>; 3634def : MSABitconvertPat<v4f32, v2f64, MSA128W, [HasMSA, IsLE]>; 3635 3636def : MSABitconvertPat<v2f64, v16i8, MSA128D, [HasMSA, IsLE]>; 3637def : MSABitconvertPat<v2f64, v8i16, MSA128D, [HasMSA, IsLE]>; 3638def : MSABitconvertPat<v2f64, v4i32, MSA128D, [HasMSA, IsLE]>; 3639def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>; 3640def : MSABitconvertPat<v2f64, v4f32, MSA128D, [HasMSA, IsLE]>; 3641 3642// Big endian bitcasts expand to shuffle instructions. 3643// This is because bitcast is defined to be a store/load sequence and the 3644// vector store/load instructions are mixed-endian with respect to the vector 3645// as a whole (little endian with respect to element order, but big endian 3646// elements). 3647 3648class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT, 3649 RegisterClass DstRC, MSAInst Insn, 3650 RegisterClass ViaRC> : 3651 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3652 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27), 3653 DstRC), 3654 [HasMSA, IsBE]>; 3655 3656class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT, 3657 RegisterClass DstRC, MSAInst Insn, 3658 RegisterClass ViaRC> : 3659 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3660 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177), 3661 DstRC), 3662 [HasMSA, IsBE]>; 3663 3664class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT, 3665 RegisterClass DstRC> : 3666 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>; 3667 3668class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT, 3669 RegisterClass DstRC> : 3670 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>; 3671 3672class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT, 3673 RegisterClass DstRC> : 3674 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3675 (COPY_TO_REGCLASS 3676 (SHF_W 3677 (COPY_TO_REGCLASS 3678 (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27), 3679 MSA128W), 177), 3680 DstRC), 3681 [HasMSA, IsBE]>; 3682 3683class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT, 3684 RegisterClass DstRC> : 3685 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>; 3686 3687class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT, 3688 RegisterClass DstRC> : 3689 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>; 3690 3691class MSABitconvertReverseWInDPat<ValueType DstVT, ValueType SrcVT, 3692 RegisterClass DstRC> : 3693 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_W, MSA128W>; 3694 3695def : MSABitconvertReverseBInHPat<v8i16, v16i8, MSA128H>; 3696def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>; 3697def : MSABitconvertReverseBInWPat<v4i32, v16i8, MSA128W>; 3698def : MSABitconvertReverseBInWPat<v4f32, v16i8, MSA128W>; 3699def : MSABitconvertReverseBInDPat<v2i64, v16i8, MSA128D>; 3700def : MSABitconvertReverseBInDPat<v2f64, v16i8, MSA128D>; 3701 3702def : MSABitconvertReverseBInHPat<v16i8, v8i16, MSA128B>; 3703def : MSABitconvertReverseHInWPat<v4i32, v8i16, MSA128W>; 3704def : MSABitconvertReverseHInWPat<v4f32, v8i16, MSA128W>; 3705def : MSABitconvertReverseHInDPat<v2i64, v8i16, MSA128D>; 3706def : MSABitconvertReverseHInDPat<v2f64, v8i16, MSA128D>; 3707 3708def : MSABitconvertReverseBInHPat<v16i8, v8f16, MSA128B>; 3709def : MSABitconvertReverseHInWPat<v4i32, v8f16, MSA128W>; 3710def : MSABitconvertReverseHInWPat<v4f32, v8f16, MSA128W>; 3711def : MSABitconvertReverseHInDPat<v2i64, v8f16, MSA128D>; 3712def : MSABitconvertReverseHInDPat<v2f64, v8f16, MSA128D>; 3713 3714def : MSABitconvertReverseBInWPat<v16i8, v4i32, MSA128B>; 3715def : MSABitconvertReverseHInWPat<v8i16, v4i32, MSA128H>; 3716def : MSABitconvertReverseHInWPat<v8f16, v4i32, MSA128H>; 3717def : MSABitconvertReverseWInDPat<v2i64, v4i32, MSA128D>; 3718def : MSABitconvertReverseWInDPat<v2f64, v4i32, MSA128D>; 3719 3720def : MSABitconvertReverseBInWPat<v16i8, v4f32, MSA128B>; 3721def : MSABitconvertReverseHInWPat<v8i16, v4f32, MSA128H>; 3722def : MSABitconvertReverseHInWPat<v8f16, v4f32, MSA128H>; 3723def : MSABitconvertReverseWInDPat<v2i64, v4f32, MSA128D>; 3724def : MSABitconvertReverseWInDPat<v2f64, v4f32, MSA128D>; 3725 3726def : MSABitconvertReverseBInDPat<v16i8, v2i64, MSA128B>; 3727def : MSABitconvertReverseHInDPat<v8i16, v2i64, MSA128H>; 3728def : MSABitconvertReverseHInDPat<v8f16, v2i64, MSA128H>; 3729def : MSABitconvertReverseWInDPat<v4i32, v2i64, MSA128W>; 3730def : MSABitconvertReverseWInDPat<v4f32, v2i64, MSA128W>; 3731 3732def : MSABitconvertReverseBInDPat<v16i8, v2f64, MSA128B>; 3733def : MSABitconvertReverseHInDPat<v8i16, v2f64, MSA128H>; 3734def : MSABitconvertReverseHInDPat<v8f16, v2f64, MSA128H>; 3735def : MSABitconvertReverseWInDPat<v4i32, v2f64, MSA128W>; 3736def : MSABitconvertReverseWInDPat<v4f32, v2f64, MSA128W>; 3737 3738// Pseudos used to implement BNZ.df, and BZ.df 3739 3740class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode, 3741 RegisterClass RCWS, 3742 InstrItinClass itin = NoItinerary> : 3743 MipsPseudo<(outs GPR32:$dst), 3744 (ins RCWS:$ws), 3745 [(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> { 3746 bit usesCustomInserter = 1; 3747 bit hasNoSchedulingInfo = 1; 3748} 3749 3750def SNZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8, 3751 MSA128B, NoItinerary>; 3752def SNZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16, 3753 MSA128H, NoItinerary>; 3754def SNZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32, 3755 MSA128W, NoItinerary>; 3756def SNZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64, 3757 MSA128D, NoItinerary>; 3758def SNZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8, 3759 MSA128B, NoItinerary>; 3760 3761def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8, 3762 MSA128B, NoItinerary>; 3763def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16, 3764 MSA128H, NoItinerary>; 3765def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32, 3766 MSA128W, NoItinerary>; 3767def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64, 3768 MSA128D, NoItinerary>; 3769def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8, 3770 MSA128B, NoItinerary>; 3771 3772// Pseudoes used to implement transparent fp16 support. 3773 3774let ASEPredicate = [HasMSA] in { 3775 let usesCustomInserter = 1 in { 3776 def ST_F16 : 3777 MipsPseudo<(outs), (ins MSA128F16:$ws, mem_simm10:$addr), 3778 [(store (f16 MSA128F16:$ws), (addrimm10:$addr))]>; 3779 def LD_F16 : 3780 MipsPseudo<(outs MSA128F16:$ws), (ins mem_simm10:$addr), 3781 [(set MSA128F16:$ws, (f16 (load addrimm10:$addr)))]>; 3782 } 3783 3784 let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in { 3785 def MSA_FP_EXTEND_W_PSEUDO : 3786 MipsPseudo<(outs FGR32Opnd:$fd), (ins MSA128F16:$ws), 3787 [(set FGR32Opnd:$fd, (f32 (fpextend MSA128F16:$ws)))]>; 3788 def MSA_FP_ROUND_W_PSEUDO : 3789 MipsPseudo<(outs MSA128F16:$wd), (ins FGR32Opnd:$fs), 3790 [(set MSA128F16:$wd, (f16 (fpround FGR32Opnd:$fs)))]>; 3791 def MSA_FP_EXTEND_D_PSEUDO : 3792 MipsPseudo<(outs FGR64Opnd:$fd), (ins MSA128F16:$ws), 3793 [(set FGR64Opnd:$fd, (f64 (fpextend MSA128F16:$ws)))]>; 3794 def MSA_FP_ROUND_D_PSEUDO : 3795 MipsPseudo<(outs MSA128F16:$wd), (ins FGR64Opnd:$fs), 3796 [(set MSA128F16:$wd, (f16 (fpround FGR64Opnd:$fs)))]>; 3797 } 3798 3799 def : MipsPat<(MipsTruncIntFP MSA128F16:$ws), 3800 (TRUNC_W_D64 (MSA_FP_EXTEND_D_PSEUDO MSA128F16:$ws))>, 3801 ISA_MIPS1, ASE_MSA; 3802 3803 def : MipsPat<(MipsFPCmp MSA128F16:$ws, MSA128F16:$wt, imm:$cond), 3804 (FCMP_S32 (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$ws), 3805 (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$wt), imm:$cond)>, 3806 ISA_MIPS1_NOT_32R6_64R6, ASE_MSA; 3807} 3808 3809def vsplati64_imm_eq_63 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{ 3810 APInt Imm; 3811 SDNode *BV = N->getOperand(0).getNode(); 3812 EVT EltTy = N->getValueType(0).getVectorElementType(); 3813 3814 return selectVSplat(BV, Imm, EltTy.getSizeInBits()) && 3815 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 63; 3816}]>; 3817 3818def immi32Cst7 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 7;}]>; 3819def immi32Cst15 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 15;}]>; 3820def immi32Cst31 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 31;}]>; 3821 3822def vsplati8imm7 : PatFrag<(ops node:$wt), 3823 (and node:$wt, (vsplati8 immi32Cst7))>; 3824def vsplati16imm15 : PatFrag<(ops node:$wt), 3825 (and node:$wt, (vsplati16 immi32Cst15))>; 3826def vsplati32imm31 : PatFrag<(ops node:$wt), 3827 (and node:$wt, (vsplati32 immi32Cst31))>; 3828def vsplati64imm63 : PatFrag<(ops node:$wt), 3829 (and node:$wt, vsplati64_imm_eq_63)>; 3830 3831class MSAShiftPat<SDNode Node, ValueType VT, MSAInst Insn, dag Vec> : 3832 MSAPat<(VT (Node VT:$ws, (VT (and VT:$wt, Vec)))), 3833 (VT (Insn VT:$ws, VT:$wt))>; 3834 3835class MSABitPat<SDNode Node, ValueType VT, MSAInst Insn, PatFrag Frag> : 3836 MSAPat<(VT (Node VT:$ws, (shl vsplat_imm_eq_1, (Frag VT:$wt)))), 3837 (VT (Insn VT:$ws, VT:$wt))>; 3838 3839multiclass MSAShiftPats<SDNode Node, string Insn> { 3840 def : MSAShiftPat<Node, v16i8, !cast<MSAInst>(Insn#_B), 3841 (vsplati8 immi32Cst7)>; 3842 def : MSAShiftPat<Node, v8i16, !cast<MSAInst>(Insn#_H), 3843 (vsplati16 immi32Cst15)>; 3844 def : MSAShiftPat<Node, v4i32, !cast<MSAInst>(Insn#_W), 3845 (vsplati32 immi32Cst31)>; 3846 def : MSAPat<(v2i64 (Node v2i64:$ws, (v2i64 (and v2i64:$wt, 3847 vsplati64_imm_eq_63)))), 3848 (v2i64 (!cast<MSAInst>(Insn#_D) v2i64:$ws, v2i64:$wt))>; 3849} 3850 3851multiclass MSABitPats<SDNode Node, string Insn> { 3852 def : MSABitPat<Node, v16i8, !cast<MSAInst>(Insn#_B), vsplati8imm7>; 3853 def : MSABitPat<Node, v8i16, !cast<MSAInst>(Insn#_H), vsplati16imm15>; 3854 def : MSABitPat<Node, v4i32, !cast<MSAInst>(Insn#_W), vsplati32imm31>; 3855 def : MSAPat<(Node v2i64:$ws, (shl (v2i64 vsplati64_imm_eq_1), 3856 (vsplati64imm63 v2i64:$wt))), 3857 (v2i64 (!cast<MSAInst>(Insn#_D) v2i64:$ws, v2i64:$wt))>; 3858} 3859 3860defm : MSAShiftPats<shl, "SLL">; 3861defm : MSAShiftPats<srl, "SRL">; 3862defm : MSAShiftPats<sra, "SRA">; 3863defm : MSABitPats<xor, "BNEG">; 3864defm : MSABitPats<or, "BSET">; 3865 3866def : MSAPat<(and v16i8:$ws, (xor (shl vsplat_imm_eq_1, 3867 (vsplati8imm7 v16i8:$wt)), 3868 immAllOnesV)), 3869 (v16i8 (BCLR_B v16i8:$ws, v16i8:$wt))>; 3870def : MSAPat<(and v8i16:$ws, (xor (shl vsplat_imm_eq_1, 3871 (vsplati16imm15 v8i16:$wt)), 3872 immAllOnesV)), 3873 (v8i16 (BCLR_H v8i16:$ws, v8i16:$wt))>; 3874def : MSAPat<(and v4i32:$ws, (xor (shl vsplat_imm_eq_1, 3875 (vsplati32imm31 v4i32:$wt)), 3876 immAllOnesV)), 3877 (v4i32 (BCLR_W v4i32:$ws, v4i32:$wt))>; 3878def : MSAPat<(and v2i64:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1), 3879 (vsplati64imm63 v2i64:$wt)), 3880 (bitconvert (v4i32 immAllOnesV)))), 3881 (v2i64 (BCLR_D v2i64:$ws, v2i64:$wt))>; 3882 3883// Vector extraction with fixed index. 3884// 3885// Extracting 32-bit values on MSA32 should always use COPY_S_W rather than 3886// COPY_U_W, even for the zero-extended case. This is because our forward 3887// compatibility strategy is to consider registers to be infinitely 3888// sign-extended so that a MIPS64 can execute MIPS32 code without getting 3889// different register values. 3890def : MSAPat<(vextract_zext_i32 (v4i32 MSA128W:$ws), immZExt2Ptr:$idx), 3891 (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64; 3892def : MSAPat<(vextract_zext_i32 (v4f32 MSA128W:$ws), immZExt2Ptr:$idx), 3893 (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64; 3894 3895// Extracting 64-bit values on MSA64 should always use COPY_S_D rather than 3896// COPY_U_D, even for the zero-extended case. This is because our forward 3897// compatibility strategy is to consider registers to be infinitely 3898// sign-extended so that a hypothetical MIPS128 would be able to execute MIPS64 3899// code without getting different register values. 3900def : MSAPat<(vextract_zext_i64 (v2i64 MSA128D:$ws), immZExt1Ptr:$idx), 3901 (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64; 3902def : MSAPat<(vextract_zext_i64 (v2f64 MSA128D:$ws), immZExt1Ptr:$idx), 3903 (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64; 3904 3905// Vector extraction with variable index 3906def : MSAPat<(i32 (vextract_sext_i8 v16i8:$ws, i32:$idx)), 3907 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws, 3908 i32:$idx), 3909 sub_lo)), 3910 GPR32), (i32 24))>; 3911def : MSAPat<(i32 (vextract_sext_i16 v8i16:$ws, i32:$idx)), 3912 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws, 3913 i32:$idx), 3914 sub_lo)), 3915 GPR32), (i32 16))>; 3916def : MSAPat<(i32 (vextract_sext_i32 v4i32:$ws, i32:$idx)), 3917 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws, 3918 i32:$idx), 3919 sub_lo)), 3920 GPR32)>; 3921def : MSAPat<(i64 (vextract_sext_i64 v2i64:$ws, i32:$idx)), 3922 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws, 3923 i32:$idx), 3924 sub_64)), 3925 GPR64), [HasMSA, IsGP64bit]>; 3926 3927def : MSAPat<(i32 (vextract_zext_i8 v16i8:$ws, i32:$idx)), 3928 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws, 3929 i32:$idx), 3930 sub_lo)), 3931 GPR32), (i32 24))>; 3932def : MSAPat<(i32 (vextract_zext_i16 v8i16:$ws, i32:$idx)), 3933 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws, 3934 i32:$idx), 3935 sub_lo)), 3936 GPR32), (i32 16))>; 3937def : MSAPat<(i32 (vextract_zext_i32 v4i32:$ws, i32:$idx)), 3938 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws, 3939 i32:$idx), 3940 sub_lo)), 3941 GPR32)>; 3942def : MSAPat<(i64 (vextract_zext_i64 v2i64:$ws, i32:$idx)), 3943 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws, 3944 i32:$idx), 3945 sub_64)), 3946 GPR64), [HasMSA, IsGP64bit]>; 3947 3948def : MSAPat<(f32 (vector_extract v4f32:$ws, i32:$idx)), 3949 (f32 (EXTRACT_SUBREG (SPLAT_W v4f32:$ws, 3950 i32:$idx), 3951 sub_lo))>; 3952def : MSAPat<(f64 (vector_extract v2f64:$ws, i32:$idx)), 3953 (f64 (EXTRACT_SUBREG (SPLAT_D v2f64:$ws, 3954 i32:$idx), 3955 sub_64))>; 3956 3957// Vector extraction with variable index (N64 ABI) 3958def : MSAPat< 3959 (i32 (vextract_sext_i8 v16i8:$ws, i64:$idx)), 3960 (SRA (COPY_TO_REGCLASS 3961 (i32 (EXTRACT_SUBREG 3962 (SPLAT_B v16i8:$ws, 3963 (COPY_TO_REGCLASS 3964 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3965 sub_lo)), 3966 GPR32), 3967 (i32 24))>; 3968def : MSAPat< 3969 (i32 (vextract_sext_i16 v8i16:$ws, i64:$idx)), 3970 (SRA (COPY_TO_REGCLASS 3971 (i32 (EXTRACT_SUBREG 3972 (SPLAT_H v8i16:$ws, 3973 (COPY_TO_REGCLASS 3974 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3975 sub_lo)), 3976 GPR32), 3977 (i32 16))>; 3978def : MSAPat< 3979 (i32 (vextract_sext_i32 v4i32:$ws, i64:$idx)), 3980 (COPY_TO_REGCLASS 3981 (i32 (EXTRACT_SUBREG 3982 (SPLAT_W v4i32:$ws, 3983 (COPY_TO_REGCLASS 3984 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3985 sub_lo)), 3986 GPR32)>; 3987def : MSAPat< 3988 (i64 (vextract_sext_i64 v2i64:$ws, i64:$idx)), 3989 (COPY_TO_REGCLASS 3990 (i64 (EXTRACT_SUBREG 3991 (SPLAT_D v2i64:$ws, 3992 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3993 sub_64)), 3994 GPR64), [HasMSA, IsGP64bit]>; 3995 3996def : MSAPat< 3997 (i32 (vextract_zext_i8 v16i8:$ws, i64:$idx)), 3998 (SRL (COPY_TO_REGCLASS 3999 (i32 (EXTRACT_SUBREG 4000 (SPLAT_B v16i8:$ws, 4001 (COPY_TO_REGCLASS 4002 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4003 sub_lo)), 4004 GPR32), 4005 (i32 24))>; 4006def : MSAPat< 4007 (i32 (vextract_zext_i16 v8i16:$ws, i64:$idx)), 4008 (SRL (COPY_TO_REGCLASS 4009 (i32 (EXTRACT_SUBREG 4010 (SPLAT_H v8i16:$ws, 4011 (COPY_TO_REGCLASS 4012 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4013 sub_lo)), 4014 GPR32), 4015 (i32 16))>; 4016def : MSAPat< 4017 (i32 (vextract_zext_i32 v4i32:$ws, i64:$idx)), 4018 (COPY_TO_REGCLASS 4019 (i32 (EXTRACT_SUBREG 4020 (SPLAT_W v4i32:$ws, 4021 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4022 sub_lo)), 4023 GPR32)>; 4024def : MSAPat< 4025 (i64 (vextract_zext_i64 v2i64:$ws, i64:$idx)), 4026 (COPY_TO_REGCLASS 4027 (i64 (EXTRACT_SUBREG 4028 (SPLAT_D v2i64:$ws, 4029 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4030 sub_64)), 4031 GPR64), 4032 [HasMSA, IsGP64bit]>; 4033 4034def : MSAPat< 4035 (f32 (vector_extract v4f32:$ws, i64:$idx)), 4036 (f32 (EXTRACT_SUBREG 4037 (SPLAT_W v4f32:$ws, 4038 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4039 sub_lo))>; 4040def : MSAPat< 4041 (f64 (vector_extract v2f64:$ws, i64:$idx)), 4042 (f64 (EXTRACT_SUBREG 4043 (SPLAT_D v2f64:$ws, 4044 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4045 sub_64))>; 4046 4047def : MSAPat<(vfseteq_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b), 4048 (FCEQ_W MSA128WOpnd:$a, MSA128WOpnd:$b)>; 4049def : MSAPat<(vfseteq_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b), 4050 (FCEQ_D MSA128DOpnd:$a, MSA128DOpnd:$b)>; 4051def : MSAPat<(vfsetle_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b), 4052 (FCLE_W MSA128WOpnd:$a, MSA128WOpnd:$b)>; 4053def : MSAPat<(vfsetle_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b), 4054 (FCLE_D MSA128DOpnd:$a, MSA128DOpnd:$b)>; 4055def : MSAPat<(vfsetlt_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b), 4056 (FCLT_W MSA128WOpnd:$a, MSA128WOpnd:$b)>; 4057def : MSAPat<(vfsetlt_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b), 4058 (FCLT_D MSA128DOpnd:$a, MSA128DOpnd:$b)>; 4059def : MSAPat<(vfsetne_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b), 4060 (FCNE_W MSA128WOpnd:$a, MSA128WOpnd:$b)>; 4061def : MSAPat<(vfsetne_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b), 4062 (FCNE_D MSA128DOpnd:$a, MSA128DOpnd:$b)>; 4063