1//===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes Mips MSA ASE instructions. 10// 11//===----------------------------------------------------------------------===// 12 13def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>; 14def SDT_VSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>, 15 SDTCisInt<1>, 16 SDTCisSameAs<1, 2>, 17 SDTCisVT<3, OtherVT>]>; 18def SDT_VFSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>, 19 SDTCisFP<1>, 20 SDTCisSameAs<1, 2>, 21 SDTCisVT<3, OtherVT>]>; 22def SDT_VSHF : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>, 23 SDTCisInt<1>, SDTCisVec<1>, 24 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>; 25def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>, 26 SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>; 27def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>, 28 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>; 29def SDT_INSVE : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0, 1>, 30 SDTCisVT<2, i32>, SDTCisSameAs<0, 3>, 31 SDTCisVT<4, i32>]>; 32 33def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>; 34def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>; 35def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>; 36def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>; 37def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp, 38 [SDNPCommutative, SDNPAssociative]>; 39def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>; 40def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>; 41def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>; 42def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>; 43def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>; 44def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>; 45def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>; 46def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>; 47def MipsINSVE : SDNode<"MipsISD::INSVE", SDT_INSVE>; 48def MipsFMS : SDNode<"MipsISD::FMS", SDTFPTernaryOp>; 49 50def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>; 51def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>; 52 53def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT", 54 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>; 55def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT", 56 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>; 57 58def immZExt1Ptr : ImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>; 59def immZExt2Ptr : ImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>; 60def immZExt3Ptr : ImmLeaf<iPTR, [{return isUInt<3>(Imm);}]>; 61def immZExt4Ptr : ImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>; 62 63def timmZExt1Ptr : TImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>; 64def timmZExt2Ptr : TImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>; 65def timmZExt3Ptr : TImmLeaf<iPTR, [{return isUInt<3>(Imm);}]>; 66def timmZExt4Ptr : TImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>; 67 68// Operands 69 70def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>; 71 72// Pattern fragments 73def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx), 74 (MipsVExtractSExt node:$vec, node:$idx, i8)>; 75def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx), 76 (MipsVExtractSExt node:$vec, node:$idx, i16)>; 77def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx), 78 (MipsVExtractSExt node:$vec, node:$idx, i32)>; 79def vextract_sext_i64 : PatFrag<(ops node:$vec, node:$idx), 80 (MipsVExtractSExt node:$vec, node:$idx, i64)>; 81 82def vextract_zext_i8 : PatFrag<(ops node:$vec, node:$idx), 83 (MipsVExtractZExt node:$vec, node:$idx, i8)>; 84def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx), 85 (MipsVExtractZExt node:$vec, node:$idx, i16)>; 86def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx), 87 (MipsVExtractZExt node:$vec, node:$idx, i32)>; 88def vextract_zext_i64 : PatFrag<(ops node:$vec, node:$idx), 89 (MipsVExtractZExt node:$vec, node:$idx, i64)>; 90 91def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx), 92 (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>; 93def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx), 94 (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>; 95def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx), 96 (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>; 97def vinsert_v2i64 : PatFrag<(ops node:$vec, node:$val, node:$idx), 98 (v2i64 (vector_insert node:$vec, node:$val, node:$idx))>; 99 100def insve_v16i8 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 101 (v16i8 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 102def insve_v8i16 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 103 (v8i16 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 104def insve_v4i32 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 105 (v4i32 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 106def insve_v2i64 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 107 (v2i64 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 108 109class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> : 110 PatFrag<(ops node:$lhs, node:$rhs), 111 (ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>; 112 113// ISD::SETFALSE cannot occur 114def vfseteq_v4f32 : vfsetcc_type<v4i32, v4f32, SETEQ>; 115def vfseteq_v2f64 : vfsetcc_type<v2i64, v2f64, SETEQ>; 116def vfsetge_v4f32 : vfsetcc_type<v4i32, v4f32, SETGE>; 117def vfsetge_v2f64 : vfsetcc_type<v2i64, v2f64, SETGE>; 118def vfsetgt_v4f32 : vfsetcc_type<v4i32, v4f32, SETGT>; 119def vfsetgt_v2f64 : vfsetcc_type<v2i64, v2f64, SETGT>; 120def vfsetle_v4f32 : vfsetcc_type<v4i32, v4f32, SETLE>; 121def vfsetle_v2f64 : vfsetcc_type<v2i64, v2f64, SETLE>; 122def vfsetlt_v4f32 : vfsetcc_type<v4i32, v4f32, SETLT>; 123def vfsetlt_v2f64 : vfsetcc_type<v2i64, v2f64, SETLT>; 124def vfsetne_v4f32 : vfsetcc_type<v4i32, v4f32, SETNE>; 125def vfsetne_v2f64 : vfsetcc_type<v2i64, v2f64, SETNE>; 126def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>; 127def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>; 128def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>; 129def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>; 130def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>; 131def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>; 132def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>; 133def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>; 134def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>; 135def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>; 136def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>; 137def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>; 138def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>; 139def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>; 140def vfsetun_v4f32 : vfsetcc_type<v4i32, v4f32, SETUO>; 141def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>; 142def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>; 143def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>; 144def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>; 145def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>; 146def vfsetugt_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGT>; 147def vfsetugt_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGT>; 148def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>; 149def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>; 150def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>; 151def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>; 152def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>; 153def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>; 154// ISD::SETTRUE cannot occur 155// ISD::SETFALSE2 cannot occur 156// ISD::SETTRUE2 cannot occur 157 158class vsetcc_type<ValueType ResTy, CondCode CC> : 159 PatFrag<(ops node:$lhs, node:$rhs), 160 (ResTy (vsetcc node:$lhs, node:$rhs, CC))>; 161 162def vseteq_v16i8 : vsetcc_type<v16i8, SETEQ>; 163def vseteq_v8i16 : vsetcc_type<v8i16, SETEQ>; 164def vseteq_v4i32 : vsetcc_type<v4i32, SETEQ>; 165def vseteq_v2i64 : vsetcc_type<v2i64, SETEQ>; 166def vsetle_v16i8 : vsetcc_type<v16i8, SETLE>; 167def vsetle_v8i16 : vsetcc_type<v8i16, SETLE>; 168def vsetle_v4i32 : vsetcc_type<v4i32, SETLE>; 169def vsetle_v2i64 : vsetcc_type<v2i64, SETLE>; 170def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>; 171def vsetlt_v8i16 : vsetcc_type<v8i16, SETLT>; 172def vsetlt_v4i32 : vsetcc_type<v4i32, SETLT>; 173def vsetlt_v2i64 : vsetcc_type<v2i64, SETLT>; 174def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>; 175def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>; 176def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>; 177def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>; 178def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>; 179def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>; 180def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>; 181def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>; 182 183def vsplati8 : PatFrag<(ops node:$e0), 184 (v16i8 (build_vector node:$e0, node:$e0, 185 node:$e0, node:$e0, 186 node:$e0, node:$e0, 187 node:$e0, node:$e0, 188 node:$e0, node:$e0, 189 node:$e0, node:$e0, 190 node:$e0, node:$e0, 191 node:$e0, node:$e0))>; 192def vsplati16 : PatFrag<(ops node:$e0), 193 (v8i16 (build_vector node:$e0, node:$e0, 194 node:$e0, node:$e0, 195 node:$e0, node:$e0, 196 node:$e0, node:$e0))>; 197def vsplati32 : PatFrag<(ops node:$e0), 198 (v4i32 (build_vector node:$e0, node:$e0, 199 node:$e0, node:$e0))>; 200 201def vsplati64_imm_eq_1 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{ 202 APInt Imm; 203 SDNode *BV = N->getOperand(0).getNode(); 204 EVT EltTy = N->getValueType(0).getVectorElementType(); 205 206 return selectVSplat(BV, Imm, EltTy.getSizeInBits()) && 207 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; 208}]>; 209 210def vsplati64 : PatFrag<(ops node:$e0), 211 (v2i64 (build_vector node:$e0, node:$e0))>; 212 213def vsplati64_splat_d : PatFrag<(ops node:$e0), 214 (v2i64 (bitconvert 215 (v4i32 (and 216 (v4i32 (build_vector node:$e0, 217 node:$e0, 218 node:$e0, 219 node:$e0)), 220 vsplati64_imm_eq_1))))>; 221 222def vsplatf32 : PatFrag<(ops node:$e0), 223 (v4f32 (build_vector node:$e0, node:$e0, 224 node:$e0, node:$e0))>; 225def vsplatf64 : PatFrag<(ops node:$e0), 226 (v2f64 (build_vector node:$e0, node:$e0))>; 227 228def vsplati8_elt : PatFrag<(ops node:$v, node:$i), 229 (MipsVSHF (vsplati8 node:$i), node:$v, node:$v)>; 230def vsplati16_elt : PatFrag<(ops node:$v, node:$i), 231 (MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>; 232def vsplati32_elt : PatFrag<(ops node:$v, node:$i), 233 (MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>; 234def vsplati64_elt : PatFrag<(ops node:$v, node:$i), 235 (MipsVSHF (vsplati64_splat_d node:$i), 236 node:$v, node:$v)>; 237 238class SplatPatLeaf<Operand opclass, dag frag, code pred = [{}], 239 SDNodeXForm xform = NOOP_SDNodeXForm> 240 : PatLeaf<frag, pred, xform> { 241 Operand OpClass = opclass; 242} 243 244class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn, 245 list<SDNode> roots = [], 246 list<SDNodeProperty> props = []> : 247 ComplexPattern<ty, numops, fn, roots, props> { 248 Operand OpClass = opclass; 249} 250 251def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1, 252 "selectVSplatUimm3", 253 [build_vector, bitconvert]>; 254 255def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1, 256 "selectVSplatUimm4", 257 [build_vector, bitconvert]>; 258 259def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1, 260 "selectVSplatUimm5", 261 [build_vector, bitconvert]>; 262 263def vsplati8_uimm8 : SplatComplexPattern<vsplat_uimm8, v16i8, 1, 264 "selectVSplatUimm8", 265 [build_vector, bitconvert]>; 266 267def vsplati8_simm5 : SplatComplexPattern<vsplat_simm5, v16i8, 1, 268 "selectVSplatSimm5", 269 [build_vector, bitconvert]>; 270 271def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1, 272 "selectVSplatUimm3", 273 [build_vector, bitconvert]>; 274 275def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1, 276 "selectVSplatUimm4", 277 [build_vector, bitconvert]>; 278 279def vsplati16_uimm5 : SplatComplexPattern<vsplat_uimm5, v8i16, 1, 280 "selectVSplatUimm5", 281 [build_vector, bitconvert]>; 282 283def vsplati16_simm5 : SplatComplexPattern<vsplat_simm5, v8i16, 1, 284 "selectVSplatSimm5", 285 [build_vector, bitconvert]>; 286 287def vsplati32_uimm2 : SplatComplexPattern<vsplat_uimm2, v4i32, 1, 288 "selectVSplatUimm2", 289 [build_vector, bitconvert]>; 290 291def vsplati32_uimm5 : SplatComplexPattern<vsplat_uimm5, v4i32, 1, 292 "selectVSplatUimm5", 293 [build_vector, bitconvert]>; 294 295def vsplati32_simm5 : SplatComplexPattern<vsplat_simm5, v4i32, 1, 296 "selectVSplatSimm5", 297 [build_vector, bitconvert]>; 298 299def vsplati64_uimm1 : SplatComplexPattern<vsplat_uimm1, v2i64, 1, 300 "selectVSplatUimm1", 301 [build_vector, bitconvert]>; 302 303def vsplati64_uimm5 : SplatComplexPattern<vsplat_uimm5, v2i64, 1, 304 "selectVSplatUimm5", 305 [build_vector, bitconvert]>; 306 307def vsplati64_uimm6 : SplatComplexPattern<vsplat_uimm6, v2i64, 1, 308 "selectVSplatUimm6", 309 [build_vector, bitconvert]>; 310 311def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1, 312 "selectVSplatSimm5", 313 [build_vector, bitconvert]>; 314 315// Any build_vector that is a constant splat with a value that is an exact 316// power of 2 317def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2", 318 [build_vector, bitconvert]>; 319 320// Any build_vector that is a constant splat with a value that is the bitwise 321// inverse of an exact power of 2 322def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2", 323 [build_vector, bitconvert]>; 324 325// Any build_vector that is a constant splat with only a consecutive sequence 326// of left-most bits set. 327def vsplat_maskl_bits_uimm3 328 : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskL", 329 [build_vector, bitconvert]>; 330def vsplat_maskl_bits_uimm4 331 : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskL", 332 [build_vector, bitconvert]>; 333def vsplat_maskl_bits_uimm5 334 : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskL", 335 [build_vector, bitconvert]>; 336def vsplat_maskl_bits_uimm6 337 : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskL", 338 [build_vector, bitconvert]>; 339 340// Any build_vector that is a constant splat with only a consecutive sequence 341// of right-most bits set. 342def vsplat_maskr_bits_uimm3 343 : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskR", 344 [build_vector, bitconvert]>; 345def vsplat_maskr_bits_uimm4 346 : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskR", 347 [build_vector, bitconvert]>; 348def vsplat_maskr_bits_uimm5 349 : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskR", 350 [build_vector, bitconvert]>; 351def vsplat_maskr_bits_uimm6 352 : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskR", 353 [build_vector, bitconvert]>; 354 355// Any build_vector that is a constant splat with a value that equals 1 356// FIXME: These should be a ComplexPattern but we can't use them because the 357// ISel generator requires the uses to have a name, but providing a name 358// causes other errors ("used in pattern but not operand list") 359def vsplat_imm_eq_1 : PatLeaf<(build_vector), [{ 360 APInt Imm; 361 EVT EltTy = N->getValueType(0).getVectorElementType(); 362 363 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 364 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; 365}]>; 366 367def vbclr_b : PatFrag<(ops node:$ws, node:$wt), 368 (and node:$ws, (vnot (shl vsplat_imm_eq_1, node:$wt)))>; 369def vbclr_h : PatFrag<(ops node:$ws, node:$wt), 370 (and node:$ws, (vnot (shl vsplat_imm_eq_1, node:$wt)))>; 371def vbclr_w : PatFrag<(ops node:$ws, node:$wt), 372 (and node:$ws, (vnot (shl vsplat_imm_eq_1, node:$wt)))>; 373def vbclr_d : PatFrag<(ops node:$ws, node:$wt), 374 (and node:$ws, (vnot (shl (v2i64 vsplati64_imm_eq_1), 375 node:$wt)))>; 376 377def vbneg_b : PatFrag<(ops node:$ws, node:$wt), 378 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 379def vbneg_h : PatFrag<(ops node:$ws, node:$wt), 380 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 381def vbneg_w : PatFrag<(ops node:$ws, node:$wt), 382 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 383def vbneg_d : PatFrag<(ops node:$ws, node:$wt), 384 (xor node:$ws, (shl (v2i64 vsplati64_imm_eq_1), 385 node:$wt))>; 386 387def vbset_b : PatFrag<(ops node:$ws, node:$wt), 388 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 389def vbset_h : PatFrag<(ops node:$ws, node:$wt), 390 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 391def vbset_w : PatFrag<(ops node:$ws, node:$wt), 392 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 393def vbset_d : PatFrag<(ops node:$ws, node:$wt), 394 (or node:$ws, (shl (v2i64 vsplati64_imm_eq_1), 395 node:$wt))>; 396 397def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt), 398 (add node:$wd, (mul node:$ws, node:$wt))>; 399 400def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt), 401 (sub node:$wd, (mul node:$ws, node:$wt))>; 402 403def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt), 404 (fmul node:$ws, (fexp2 node:$wt))>; 405 406// Instruction encoding. 407class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>; 408class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>; 409class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>; 410class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>; 411 412class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>; 413class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>; 414class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>; 415class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>; 416 417class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>; 418class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>; 419class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>; 420class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>; 421 422class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>; 423class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>; 424class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>; 425class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>; 426 427class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>; 428class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>; 429class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>; 430class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>; 431 432class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>; 433class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>; 434class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>; 435class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>; 436 437class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>; 438 439class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>; 440 441class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>; 442class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>; 443class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>; 444class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>; 445 446class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>; 447class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>; 448class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>; 449class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>; 450 451class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>; 452class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>; 453class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>; 454class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>; 455 456class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>; 457class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>; 458class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>; 459class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>; 460 461class AVER_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010000>; 462class AVER_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010000>; 463class AVER_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010000>; 464class AVER_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010000>; 465 466class AVER_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010000>; 467class AVER_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010000>; 468class AVER_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010000>; 469class AVER_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010000>; 470 471class BCLR_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001101>; 472class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>; 473class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>; 474class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>; 475 476class BCLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001001>; 477class BCLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001001>; 478class BCLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001001>; 479class BCLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001001>; 480 481class BINSL_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001101>; 482class BINSL_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001101>; 483class BINSL_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001101>; 484class BINSL_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001101>; 485 486class BINSLI_B_ENC : MSA_BIT_B_FMT<0b110, 0b001001>; 487class BINSLI_H_ENC : MSA_BIT_H_FMT<0b110, 0b001001>; 488class BINSLI_W_ENC : MSA_BIT_W_FMT<0b110, 0b001001>; 489class BINSLI_D_ENC : MSA_BIT_D_FMT<0b110, 0b001001>; 490 491class BINSR_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001101>; 492class BINSR_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001101>; 493class BINSR_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001101>; 494class BINSR_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001101>; 495 496class BINSRI_B_ENC : MSA_BIT_B_FMT<0b111, 0b001001>; 497class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>; 498class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>; 499class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>; 500 501class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>; 502 503class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>; 504 505class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>; 506 507class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>; 508 509class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>; 510class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>; 511class BNEG_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001101>; 512class BNEG_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001101>; 513 514class BNEGI_B_ENC : MSA_BIT_B_FMT<0b101, 0b001001>; 515class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>; 516class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>; 517class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>; 518 519class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>; 520class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>; 521class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>; 522class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>; 523 524class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01111>; 525 526class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>; 527 528class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>; 529 530class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>; 531class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>; 532class BSET_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001101>; 533class BSET_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001101>; 534 535class BSETI_B_ENC : MSA_BIT_B_FMT<0b100, 0b001001>; 536class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>; 537class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>; 538class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>; 539 540class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>; 541class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>; 542class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>; 543class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>; 544 545class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>; 546 547class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>; 548class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>; 549class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>; 550class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>; 551 552class CEQI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000111>; 553class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>; 554class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>; 555class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>; 556 557class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>; 558 559class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>; 560class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>; 561class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>; 562class CLE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001111>; 563 564class CLE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001111>; 565class CLE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001111>; 566class CLE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001111>; 567class CLE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001111>; 568 569class CLEI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000111>; 570class CLEI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000111>; 571class CLEI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000111>; 572class CLEI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000111>; 573 574class CLEI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000111>; 575class CLEI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000111>; 576class CLEI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000111>; 577class CLEI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000111>; 578 579class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>; 580class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>; 581class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>; 582class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>; 583 584class CLT_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001111>; 585class CLT_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001111>; 586class CLT_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001111>; 587class CLT_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001111>; 588 589class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>; 590class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>; 591class CLTI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000111>; 592class CLTI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000111>; 593 594class CLTI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000111>; 595class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>; 596class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>; 597class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>; 598 599class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>; 600class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>; 601class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>; 602class COPY_S_D_ENC : MSA_ELM_COPY_D_FMT<0b0010, 0b011001>; 603 604class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>; 605class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>; 606class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>; 607 608class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>; 609 610class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>; 611class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>; 612class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>; 613class DIV_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010010>; 614 615class DIV_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010010>; 616class DIV_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010010>; 617class DIV_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010010>; 618class DIV_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010010>; 619 620class DOTP_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010011>; 621class DOTP_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010011>; 622class DOTP_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010011>; 623 624class DOTP_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010011>; 625class DOTP_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010011>; 626class DOTP_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010011>; 627 628class DPADD_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010011>; 629class DPADD_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010011>; 630class DPADD_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010011>; 631 632class DPADD_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010011>; 633class DPADD_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010011>; 634class DPADD_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010011>; 635 636class DPSUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010011>; 637class DPSUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010011>; 638class DPSUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010011>; 639 640class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>; 641class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>; 642class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>; 643 644class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>; 645class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>; 646 647class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>; 648class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>; 649 650class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>; 651class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>; 652 653class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>; 654class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>; 655 656class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>; 657class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>; 658 659class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>; 660class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>; 661 662class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>; 663class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>; 664 665class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>; 666class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>; 667 668class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>; 669class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>; 670 671class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>; 672class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>; 673 674class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>; 675class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>; 676 677class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>; 678class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>; 679 680class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>; 681class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>; 682 683class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>; 684class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>; 685 686class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>; 687class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>; 688 689class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>; 690class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>; 691 692class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>; 693class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>; 694 695class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>; 696class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>; 697 698class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>; 699class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>; 700 701class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>; 702class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>; 703 704class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>; 705class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>; 706 707class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>; 708class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>; 709 710class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>; 711class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>; 712class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>; 713class FILL_D_ENC : MSA_2R_FILL_D_FMT<0b11000000, 0b11, 0b011110>; 714 715class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>; 716class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>; 717 718class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>; 719class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>; 720 721class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>; 722class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>; 723 724class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>; 725class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>; 726 727class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>; 728class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>; 729 730class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>; 731class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>; 732 733class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>; 734class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>; 735 736class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>; 737class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>; 738 739class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>; 740class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>; 741 742class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>; 743class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>; 744 745class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>; 746class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>; 747 748class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>; 749class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>; 750 751class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>; 752class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>; 753 754class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>; 755class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>; 756 757class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>; 758class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>; 759 760class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>; 761class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>; 762 763class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>; 764class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>; 765 766class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>; 767class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>; 768 769class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>; 770class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>; 771 772class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>; 773class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>; 774 775class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>; 776class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>; 777 778class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>; 779class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>; 780 781class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>; 782class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>; 783 784class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>; 785class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>; 786 787class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>; 788class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>; 789 790class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>; 791class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>; 792 793class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>; 794class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>; 795 796class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>; 797class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>; 798 799class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>; 800class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>; 801 802class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>; 803class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>; 804class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>; 805 806class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>; 807class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>; 808class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>; 809 810class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>; 811class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>; 812class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>; 813 814class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>; 815class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>; 816class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>; 817 818class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>; 819class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>; 820class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>; 821class ILVEV_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010100>; 822 823class ILVL_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010100>; 824class ILVL_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010100>; 825class ILVL_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010100>; 826class ILVL_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010100>; 827 828class ILVOD_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010100>; 829class ILVOD_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010100>; 830class ILVOD_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010100>; 831class ILVOD_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010100>; 832 833class ILVR_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010100>; 834class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>; 835class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>; 836class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>; 837 838class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>; 839class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>; 840class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>; 841class INSERT_D_ENC : MSA_ELM_INSERT_D_FMT<0b0100, 0b011001>; 842 843class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>; 844class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>; 845class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>; 846class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>; 847 848class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>; 849class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>; 850class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>; 851class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>; 852 853class LDI_B_ENC : MSA_I10_FMT<0b110, 0b00, 0b000111>; 854class LDI_H_ENC : MSA_I10_FMT<0b110, 0b01, 0b000111>; 855class LDI_W_ENC : MSA_I10_FMT<0b110, 0b10, 0b000111>; 856class LDI_D_ENC : MSA_I10_FMT<0b110, 0b11, 0b000111>; 857 858class LSA_ENC : SPECIAL_LSA_FMT<0b000101>; 859class DLSA_ENC : SPECIAL_DLSA_FMT<0b010101>; 860 861class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>; 862class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>; 863 864class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>; 865class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>; 866 867class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>; 868class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>; 869class MADDV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010010>; 870class MADDV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010010>; 871 872class MAX_A_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001110>; 873class MAX_A_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001110>; 874class MAX_A_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001110>; 875class MAX_A_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001110>; 876 877class MAX_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001110>; 878class MAX_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001110>; 879class MAX_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001110>; 880class MAX_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001110>; 881 882class MAX_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001110>; 883class MAX_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001110>; 884class MAX_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001110>; 885class MAX_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001110>; 886 887class MAXI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000110>; 888class MAXI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000110>; 889class MAXI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000110>; 890class MAXI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000110>; 891 892class MAXI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000110>; 893class MAXI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000110>; 894class MAXI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000110>; 895class MAXI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000110>; 896 897class MIN_A_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001110>; 898class MIN_A_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001110>; 899class MIN_A_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001110>; 900class MIN_A_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001110>; 901 902class MIN_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001110>; 903class MIN_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001110>; 904class MIN_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001110>; 905class MIN_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001110>; 906 907class MIN_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001110>; 908class MIN_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001110>; 909class MIN_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001110>; 910class MIN_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001110>; 911 912class MINI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000110>; 913class MINI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000110>; 914class MINI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000110>; 915class MINI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000110>; 916 917class MINI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000110>; 918class MINI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000110>; 919class MINI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000110>; 920class MINI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000110>; 921 922class MOD_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010010>; 923class MOD_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010010>; 924class MOD_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010010>; 925class MOD_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010010>; 926 927class MOD_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010010>; 928class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>; 929class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>; 930class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>; 931 932class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>; 933 934class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>; 935class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>; 936 937class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>; 938class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>; 939 940class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>; 941class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>; 942class MSUBV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010010>; 943class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>; 944 945class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>; 946class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>; 947 948class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>; 949class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>; 950 951class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>; 952class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>; 953class MULV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010010>; 954class MULV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010010>; 955 956class NLOC_B_ENC : MSA_2R_FMT<0b11000010, 0b00, 0b011110>; 957class NLOC_H_ENC : MSA_2R_FMT<0b11000010, 0b01, 0b011110>; 958class NLOC_W_ENC : MSA_2R_FMT<0b11000010, 0b10, 0b011110>; 959class NLOC_D_ENC : MSA_2R_FMT<0b11000010, 0b11, 0b011110>; 960 961class NLZC_B_ENC : MSA_2R_FMT<0b11000011, 0b00, 0b011110>; 962class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>; 963class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>; 964class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>; 965 966class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>; 967 968class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>; 969 970class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>; 971 972class ORI_B_ENC : MSA_I8_FMT<0b01, 0b000000>; 973 974class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>; 975class PCKEV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010100>; 976class PCKEV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010100>; 977class PCKEV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010100>; 978 979class PCKOD_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010100>; 980class PCKOD_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010100>; 981class PCKOD_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010100>; 982class PCKOD_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010100>; 983 984class PCNT_B_ENC : MSA_2R_FMT<0b11000001, 0b00, 0b011110>; 985class PCNT_H_ENC : MSA_2R_FMT<0b11000001, 0b01, 0b011110>; 986class PCNT_W_ENC : MSA_2R_FMT<0b11000001, 0b10, 0b011110>; 987class PCNT_D_ENC : MSA_2R_FMT<0b11000001, 0b11, 0b011110>; 988 989class SAT_S_B_ENC : MSA_BIT_B_FMT<0b000, 0b001010>; 990class SAT_S_H_ENC : MSA_BIT_H_FMT<0b000, 0b001010>; 991class SAT_S_W_ENC : MSA_BIT_W_FMT<0b000, 0b001010>; 992class SAT_S_D_ENC : MSA_BIT_D_FMT<0b000, 0b001010>; 993 994class SAT_U_B_ENC : MSA_BIT_B_FMT<0b001, 0b001010>; 995class SAT_U_H_ENC : MSA_BIT_H_FMT<0b001, 0b001010>; 996class SAT_U_W_ENC : MSA_BIT_W_FMT<0b001, 0b001010>; 997class SAT_U_D_ENC : MSA_BIT_D_FMT<0b001, 0b001010>; 998 999class SHF_B_ENC : MSA_I8_FMT<0b00, 0b000010>; 1000class SHF_H_ENC : MSA_I8_FMT<0b01, 0b000010>; 1001class SHF_W_ENC : MSA_I8_FMT<0b10, 0b000010>; 1002 1003class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>; 1004class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>; 1005class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>; 1006class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>; 1007 1008class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>; 1009class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>; 1010class SLDI_W_ENC : MSA_ELM_W_FMT<0b0000, 0b011001>; 1011class SLDI_D_ENC : MSA_ELM_D_FMT<0b0000, 0b011001>; 1012 1013class SLL_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001101>; 1014class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>; 1015class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>; 1016class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>; 1017 1018class SLLI_B_ENC : MSA_BIT_B_FMT<0b000, 0b001001>; 1019class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>; 1020class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>; 1021class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>; 1022 1023class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>; 1024class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>; 1025class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>; 1026class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>; 1027 1028class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>; 1029class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>; 1030class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>; 1031class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>; 1032 1033class SRA_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001101>; 1034class SRA_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001101>; 1035class SRA_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001101>; 1036class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>; 1037 1038class SRAI_B_ENC : MSA_BIT_B_FMT<0b001, 0b001001>; 1039class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>; 1040class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>; 1041class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>; 1042 1043class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>; 1044class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>; 1045class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>; 1046class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>; 1047 1048class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>; 1049class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>; 1050class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>; 1051class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>; 1052 1053class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>; 1054class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>; 1055class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>; 1056class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>; 1057 1058class SRLI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001001>; 1059class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>; 1060class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>; 1061class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>; 1062 1063class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>; 1064class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>; 1065class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>; 1066class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>; 1067 1068class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>; 1069class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>; 1070class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>; 1071class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>; 1072 1073class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>; 1074class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>; 1075class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>; 1076class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>; 1077 1078class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>; 1079class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>; 1080class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>; 1081class SUBS_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010001>; 1082 1083class SUBS_U_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010001>; 1084class SUBS_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010001>; 1085class SUBS_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010001>; 1086class SUBS_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010001>; 1087 1088class SUBSUS_U_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010001>; 1089class SUBSUS_U_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010001>; 1090class SUBSUS_U_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010001>; 1091class SUBSUS_U_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010001>; 1092 1093class SUBSUU_S_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010001>; 1094class SUBSUU_S_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010001>; 1095class SUBSUU_S_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010001>; 1096class SUBSUU_S_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010001>; 1097 1098class SUBV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001110>; 1099class SUBV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001110>; 1100class SUBV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001110>; 1101class SUBV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001110>; 1102 1103class SUBVI_B_ENC : MSA_I5_FMT<0b001, 0b00, 0b000110>; 1104class SUBVI_H_ENC : MSA_I5_FMT<0b001, 0b01, 0b000110>; 1105class SUBVI_W_ENC : MSA_I5_FMT<0b001, 0b10, 0b000110>; 1106class SUBVI_D_ENC : MSA_I5_FMT<0b001, 0b11, 0b000110>; 1107 1108class VSHF_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010101>; 1109class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>; 1110class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>; 1111class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>; 1112 1113class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>; 1114 1115class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>; 1116 1117// Instruction desc. 1118class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1119 ComplexPattern Imm, RegisterOperand ROWD, 1120 RegisterOperand ROWS = ROWD, 1121 InstrItinClass itin = NoItinerary> { 1122 dag OutOperandList = (outs ROWD:$wd); 1123 dag InOperandList = (ins ROWS:$ws, vsplat_uimm3:$m); 1124 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1125 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1126 InstrItinClass Itinerary = itin; 1127} 1128 1129class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1130 ComplexPattern Imm, RegisterOperand ROWD, 1131 RegisterOperand ROWS = ROWD, 1132 InstrItinClass itin = NoItinerary> { 1133 dag OutOperandList = (outs ROWD:$wd); 1134 dag InOperandList = (ins ROWS:$ws, vsplat_uimm4:$m); 1135 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1136 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1137 InstrItinClass Itinerary = itin; 1138} 1139 1140class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1141 ComplexPattern Imm, RegisterOperand ROWD, 1142 RegisterOperand ROWS = ROWD, 1143 InstrItinClass itin = NoItinerary> { 1144 dag OutOperandList = (outs ROWD:$wd); 1145 dag InOperandList = (ins ROWS:$ws, vsplat_uimm5:$m); 1146 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1147 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1148 InstrItinClass Itinerary = itin; 1149} 1150 1151class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1152 ComplexPattern Imm, RegisterOperand ROWD, 1153 RegisterOperand ROWS = ROWD, 1154 InstrItinClass itin = NoItinerary> { 1155 dag OutOperandList = (outs ROWD:$wd); 1156 dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m); 1157 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1158 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1159 InstrItinClass Itinerary = itin; 1160} 1161 1162class MSA_BIT_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1163 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1164 RegisterOperand ROWS = ROWD, 1165 InstrItinClass itin = NoItinerary> { 1166 dag OutOperandList = (outs ROWD:$wd); 1167 dag InOperandList = (ins ROWS:$ws, ImmOp:$m); 1168 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1169 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1170 InstrItinClass Itinerary = itin; 1171} 1172 1173class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty, 1174 SplatComplexPattern Mask, RegisterOperand ROWD, 1175 RegisterOperand ROWS = ROWD, 1176 InstrItinClass itin = NoItinerary> { 1177 dag OutOperandList = (outs ROWD:$wd); 1178 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, Mask.OpClass:$m); 1179 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1180 // Note that binsxi and vselect treat the condition operand the opposite 1181 // way to each other. 1182 // (vselect cond, if_set, if_clear) 1183 // (BSEL_V cond, if_clear, if_set) 1184 list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$ws), 1185 ROWS:$wd_in))]; 1186 InstrItinClass Itinerary = itin; 1187 string Constraints = "$wd = $wd_in"; 1188} 1189 1190class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty, 1191 SplatComplexPattern ImmOp, RegisterOperand ROWD, 1192 RegisterOperand ROWS = ROWD, 1193 InstrItinClass itin = NoItinerary> : 1194 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>; 1195 1196class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty, 1197 SplatComplexPattern ImmOp, RegisterOperand ROWD, 1198 RegisterOperand ROWS = ROWD, 1199 InstrItinClass itin = NoItinerary> : 1200 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>; 1201 1202class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1203 SplatComplexPattern SplatImm, 1204 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1205 InstrItinClass itin = NoItinerary> { 1206 dag OutOperandList = (outs ROWD:$wd); 1207 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m); 1208 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1209 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))]; 1210 InstrItinClass Itinerary = itin; 1211} 1212 1213class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1214 ValueType VecTy, Operand ImmOp, ImmLeaf Imm, 1215 RegisterOperand ROD, RegisterOperand ROWS, 1216 InstrItinClass itin = NoItinerary> { 1217 dag OutOperandList = (outs ROD:$rd); 1218 dag InOperandList = (ins ROWS:$ws, ImmOp:$n); 1219 string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]"); 1220 list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), Imm:$n))]; 1221 InstrItinClass Itinerary = itin; 1222} 1223 1224class MSA_ELM_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1225 RegisterOperand ROWD, RegisterOperand ROWS, 1226 Operand ImmOp, ImmLeaf Imm, 1227 InstrItinClass itin = NoItinerary> { 1228 dag OutOperandList = (outs ROWD:$wd); 1229 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ImmOp:$n); 1230 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]"); 1231 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1232 Imm:$n))]; 1233 string Constraints = "$wd = $wd_in"; 1234 InstrItinClass Itinerary = itin; 1235} 1236 1237class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy, 1238 Operand ImmOp, ImmLeaf Imm, RegisterClass RCD, 1239 RegisterClass RCWS> : 1240 MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, ImmOp:$n), 1241 [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), Imm:$n))]> { 1242 bit usesCustomInserter = 1; 1243 bit hasNoSchedulingInfo = 1; 1244} 1245 1246class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1247 SplatComplexPattern SplatImm, RegisterOperand ROWD, 1248 RegisterOperand ROWS = ROWD, 1249 InstrItinClass itin = NoItinerary> { 1250 dag OutOperandList = (outs ROWD:$wd); 1251 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm); 1252 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm"); 1253 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))]; 1254 InstrItinClass Itinerary = itin; 1255} 1256 1257class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1258 SplatComplexPattern SplatImm, RegisterOperand ROWD, 1259 RegisterOperand ROWS = ROWD, 1260 InstrItinClass itin = NoItinerary> { 1261 dag OutOperandList = (outs ROWD:$wd); 1262 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8); 1263 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8"); 1264 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))]; 1265 InstrItinClass Itinerary = itin; 1266} 1267 1268class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1269 RegisterOperand ROWS = ROWD, 1270 InstrItinClass itin = NoItinerary> { 1271 dag OutOperandList = (outs ROWD:$wd); 1272 dag InOperandList = (ins ROWS:$ws, uimm8:$u8); 1273 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8"); 1274 list<dag> Pattern = [(set ROWD:$wd, (MipsSHF timmZExt8:$u8, ROWS:$ws))]; 1275 InstrItinClass Itinerary = itin; 1276} 1277 1278class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1279 InstrItinClass itin = NoItinerary> { 1280 dag OutOperandList = (outs ROWD:$wd); 1281 dag InOperandList = (ins vsplat_simm10:$s10); 1282 string AsmString = !strconcat(instr_asm, "\t$wd, $s10"); 1283 // LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp 1284 list<dag> Pattern = []; 1285 bit hasSideEffects = 0; 1286 bit isReMaterializable = 1; 1287 InstrItinClass Itinerary = itin; 1288} 1289 1290class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1291 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1292 InstrItinClass itin = NoItinerary> { 1293 dag OutOperandList = (outs ROWD:$wd); 1294 dag InOperandList = (ins ROWS:$ws); 1295 string AsmString = !strconcat(instr_asm, "\t$wd, $ws"); 1296 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))]; 1297 InstrItinClass Itinerary = itin; 1298} 1299 1300class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT, 1301 SDPatternOperator OpNode, RegisterOperand ROWD, 1302 RegisterOperand ROS = ROWD, 1303 InstrItinClass itin = NoItinerary> { 1304 dag OutOperandList = (outs ROWD:$wd); 1305 dag InOperandList = (ins ROS:$rs); 1306 string AsmString = !strconcat(instr_asm, "\t$wd, $rs"); 1307 list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))]; 1308 InstrItinClass Itinerary = itin; 1309} 1310 1311class MSA_2R_FILL_PSEUDO_BASE<SDPatternOperator OpNode, 1312 RegisterClass RCWD, RegisterClass RCWS> : 1313 MSAPseudo<(outs RCWD:$wd), (ins RCWS:$fs), 1314 [(set RCWD:$wd, (OpNode RCWS:$fs))]> { 1315 let usesCustomInserter = 1; 1316} 1317 1318class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1319 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1320 InstrItinClass itin = NoItinerary> { 1321 dag OutOperandList = (outs ROWD:$wd); 1322 dag InOperandList = (ins ROWS:$ws); 1323 string AsmString = !strconcat(instr_asm, "\t$wd, $ws"); 1324 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))]; 1325 InstrItinClass Itinerary = itin; 1326} 1327 1328class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1329 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1330 RegisterOperand ROWT = ROWD, 1331 InstrItinClass itin = NoItinerary> { 1332 dag OutOperandList = (outs ROWD:$wd); 1333 dag InOperandList = (ins ROWS:$ws, ROWT:$wt); 1334 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1335 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]; 1336 InstrItinClass Itinerary = itin; 1337} 1338 1339class MSA_3R_BINSX_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1340 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1341 RegisterOperand ROWT = ROWD, 1342 InstrItinClass itin = NoItinerary> { 1343 dag OutOperandList = (outs ROWD:$wd); 1344 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1345 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1346 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1347 ROWT:$wt))]; 1348 string Constraints = "$wd = $wd_in"; 1349 InstrItinClass Itinerary = itin; 1350} 1351 1352class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1353 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1354 InstrItinClass itin = NoItinerary> { 1355 dag OutOperandList = (outs ROWD:$wd); 1356 dag InOperandList = (ins ROWS:$ws, GPR32Opnd:$rt); 1357 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]"); 1358 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32Opnd:$rt))]; 1359 InstrItinClass Itinerary = itin; 1360} 1361 1362class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1363 RegisterOperand ROWS = ROWD, 1364 RegisterOperand ROWT = ROWD, 1365 InstrItinClass itin = NoItinerary> { 1366 dag OutOperandList = (outs ROWD:$wd); 1367 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1368 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1369 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws, 1370 ROWT:$wt))]; 1371 string Constraints = "$wd = $wd_in"; 1372 InstrItinClass Itinerary = itin; 1373} 1374 1375class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1376 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1377 InstrItinClass itin = NoItinerary> { 1378 dag OutOperandList = (outs ROWD:$wd); 1379 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, GPR32Opnd:$rt); 1380 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]"); 1381 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1382 GPR32Opnd:$rt))]; 1383 InstrItinClass Itinerary = itin; 1384 string Constraints = "$wd = $wd_in"; 1385} 1386 1387class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1388 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1389 RegisterOperand ROWT = ROWD, 1390 InstrItinClass itin = NoItinerary> { 1391 dag OutOperandList = (outs ROWD:$wd); 1392 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1393 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1394 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1395 ROWT:$wt))]; 1396 InstrItinClass Itinerary = itin; 1397 string Constraints = "$wd = $wd_in"; 1398} 1399 1400class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1401 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1402 RegisterOperand ROWT = ROWD, 1403 InstrItinClass itin = NoItinerary> : 1404 MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>; 1405 1406class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1407 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1408 RegisterOperand ROWT = ROWD, 1409 InstrItinClass itin = NoItinerary> : 1410 MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>; 1411 1412class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> { 1413 dag OutOperandList = (outs); 1414 dag InOperandList = (ins ROWD:$wt, brtarget:$offset); 1415 string AsmString = !strconcat(instr_asm, "\t$wt, $offset"); 1416 list<dag> Pattern = []; 1417 InstrItinClass Itinerary = NoItinerary; 1418 bit isBranch = 1; 1419 bit isTerminator = 1; 1420 bit hasDelaySlot = 1; 1421 list<Register> Defs = [AT]; 1422} 1423 1424class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1425 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1426 RegisterOperand ROS, 1427 InstrItinClass itin = NoItinerary> { 1428 dag OutOperandList = (outs ROWD:$wd); 1429 dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, ImmOp:$n); 1430 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs"); 1431 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROS:$rs, Imm:$n))]; 1432 InstrItinClass Itinerary = itin; 1433 string Constraints = "$wd = $wd_in"; 1434} 1435 1436class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty, 1437 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1438 RegisterOperand ROFS> : 1439 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ImmOp:$n, ROFS:$fs), 1440 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, Imm:$n))]> { 1441 bit usesCustomInserter = 1; 1442 string Constraints = "$wd = $wd_in"; 1443} 1444 1445class MSA_INSERT_VIDX_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty, 1446 RegisterOperand ROWD, RegisterOperand ROFS, 1447 RegisterOperand ROIdx> : 1448 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ROIdx:$n, ROFS:$fs), 1449 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, 1450 ROIdx:$n))]> { 1451 bit usesCustomInserter = 1; 1452 bit hasNoSchedulingInfo = 1; 1453 string Constraints = "$wd = $wd_in"; 1454} 1455 1456class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1457 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1458 RegisterOperand ROWS = ROWD, 1459 InstrItinClass itin = NoItinerary> { 1460 dag OutOperandList = (outs ROWD:$wd); 1461 dag InOperandList = (ins ROWD:$wd_in, ImmOp:$n, ROWS:$ws, uimmz:$n2); 1462 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[$n2]"); 1463 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, 1464 Imm:$n, 1465 ROWS:$ws, 1466 immz:$n2))]; 1467 InstrItinClass Itinerary = itin; 1468 string Constraints = "$wd = $wd_in"; 1469} 1470 1471class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1472 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1473 RegisterOperand ROWT = ROWD, 1474 InstrItinClass itin = NoItinerary> { 1475 dag OutOperandList = (outs ROWD:$wd); 1476 dag InOperandList = (ins ROWS:$ws, ROWT:$wt); 1477 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1478 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]; 1479 InstrItinClass Itinerary = itin; 1480} 1481 1482class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm, 1483 RegisterOperand ROWD, 1484 RegisterOperand ROWS = ROWD, 1485 InstrItinClass itin = NoItinerary> { 1486 dag OutOperandList = (outs ROWD:$wd); 1487 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n); 1488 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]"); 1489 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws, 1490 ROWS:$ws))]; 1491 InstrItinClass Itinerary = itin; 1492} 1493 1494class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD, 1495 RegisterOperand ROWS = ROWD, 1496 RegisterOperand ROWT = ROWD> : 1497 MSAPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt), 1498 [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>; 1499 1500class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>, 1501 IsCommutable; 1502class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>, 1503 IsCommutable; 1504class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>, 1505 IsCommutable; 1506class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>, 1507 IsCommutable; 1508 1509class ADDS_A_B_DESC : MSA_3R_DESC_BASE<"adds_a.b", int_mips_adds_a_b, 1510 MSA128BOpnd>, IsCommutable; 1511class ADDS_A_H_DESC : MSA_3R_DESC_BASE<"adds_a.h", int_mips_adds_a_h, 1512 MSA128HOpnd>, IsCommutable; 1513class ADDS_A_W_DESC : MSA_3R_DESC_BASE<"adds_a.w", int_mips_adds_a_w, 1514 MSA128WOpnd>, IsCommutable; 1515class ADDS_A_D_DESC : MSA_3R_DESC_BASE<"adds_a.d", int_mips_adds_a_d, 1516 MSA128DOpnd>, IsCommutable; 1517 1518class ADDS_S_B_DESC : MSA_3R_DESC_BASE<"adds_s.b", int_mips_adds_s_b, 1519 MSA128BOpnd>, IsCommutable; 1520class ADDS_S_H_DESC : MSA_3R_DESC_BASE<"adds_s.h", int_mips_adds_s_h, 1521 MSA128HOpnd>, IsCommutable; 1522class ADDS_S_W_DESC : MSA_3R_DESC_BASE<"adds_s.w", int_mips_adds_s_w, 1523 MSA128WOpnd>, IsCommutable; 1524class ADDS_S_D_DESC : MSA_3R_DESC_BASE<"adds_s.d", int_mips_adds_s_d, 1525 MSA128DOpnd>, IsCommutable; 1526 1527class ADDS_U_B_DESC : MSA_3R_DESC_BASE<"adds_u.b", int_mips_adds_u_b, 1528 MSA128BOpnd>, IsCommutable; 1529class ADDS_U_H_DESC : MSA_3R_DESC_BASE<"adds_u.h", int_mips_adds_u_h, 1530 MSA128HOpnd>, IsCommutable; 1531class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w, 1532 MSA128WOpnd>, IsCommutable; 1533class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d, 1534 MSA128DOpnd>, IsCommutable; 1535 1536class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable; 1537class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable; 1538class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable; 1539class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable; 1540 1541class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5, 1542 MSA128BOpnd>; 1543class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5, 1544 MSA128HOpnd>; 1545class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5, 1546 MSA128WOpnd>; 1547class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5, 1548 MSA128DOpnd>; 1549 1550class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>; 1551class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128HOpnd>; 1552class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128WOpnd>; 1553class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128DOpnd>; 1554 1555class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8, 1556 MSA128BOpnd>; 1557 1558class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b, 1559 MSA128BOpnd>; 1560class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h, 1561 MSA128HOpnd>; 1562class ASUB_S_W_DESC : MSA_3R_DESC_BASE<"asub_s.w", int_mips_asub_s_w, 1563 MSA128WOpnd>; 1564class ASUB_S_D_DESC : MSA_3R_DESC_BASE<"asub_s.d", int_mips_asub_s_d, 1565 MSA128DOpnd>; 1566 1567class ASUB_U_B_DESC : MSA_3R_DESC_BASE<"asub_u.b", int_mips_asub_u_b, 1568 MSA128BOpnd>; 1569class ASUB_U_H_DESC : MSA_3R_DESC_BASE<"asub_u.h", int_mips_asub_u_h, 1570 MSA128HOpnd>; 1571class ASUB_U_W_DESC : MSA_3R_DESC_BASE<"asub_u.w", int_mips_asub_u_w, 1572 MSA128WOpnd>; 1573class ASUB_U_D_DESC : MSA_3R_DESC_BASE<"asub_u.d", int_mips_asub_u_d, 1574 MSA128DOpnd>; 1575 1576class AVE_S_B_DESC : MSA_3R_DESC_BASE<"ave_s.b", int_mips_ave_s_b, MSA128BOpnd>, 1577 IsCommutable; 1578class AVE_S_H_DESC : MSA_3R_DESC_BASE<"ave_s.h", int_mips_ave_s_h, MSA128HOpnd>, 1579 IsCommutable; 1580class AVE_S_W_DESC : MSA_3R_DESC_BASE<"ave_s.w", int_mips_ave_s_w, MSA128WOpnd>, 1581 IsCommutable; 1582class AVE_S_D_DESC : MSA_3R_DESC_BASE<"ave_s.d", int_mips_ave_s_d, MSA128DOpnd>, 1583 IsCommutable; 1584 1585class AVE_U_B_DESC : MSA_3R_DESC_BASE<"ave_u.b", int_mips_ave_u_b, MSA128BOpnd>, 1586 IsCommutable; 1587class AVE_U_H_DESC : MSA_3R_DESC_BASE<"ave_u.h", int_mips_ave_u_h, MSA128HOpnd>, 1588 IsCommutable; 1589class AVE_U_W_DESC : MSA_3R_DESC_BASE<"ave_u.w", int_mips_ave_u_w, MSA128WOpnd>, 1590 IsCommutable; 1591class AVE_U_D_DESC : MSA_3R_DESC_BASE<"ave_u.d", int_mips_ave_u_d, MSA128DOpnd>, 1592 IsCommutable; 1593 1594class AVER_S_B_DESC : MSA_3R_DESC_BASE<"aver_s.b", int_mips_aver_s_b, 1595 MSA128BOpnd>, IsCommutable; 1596class AVER_S_H_DESC : MSA_3R_DESC_BASE<"aver_s.h", int_mips_aver_s_h, 1597 MSA128HOpnd>, IsCommutable; 1598class AVER_S_W_DESC : MSA_3R_DESC_BASE<"aver_s.w", int_mips_aver_s_w, 1599 MSA128WOpnd>, IsCommutable; 1600class AVER_S_D_DESC : MSA_3R_DESC_BASE<"aver_s.d", int_mips_aver_s_d, 1601 MSA128DOpnd>, IsCommutable; 1602 1603class AVER_U_B_DESC : MSA_3R_DESC_BASE<"aver_u.b", int_mips_aver_u_b, 1604 MSA128BOpnd>, IsCommutable; 1605class AVER_U_H_DESC : MSA_3R_DESC_BASE<"aver_u.h", int_mips_aver_u_h, 1606 MSA128HOpnd>, IsCommutable; 1607class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w, 1608 MSA128WOpnd>, IsCommutable; 1609class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d, 1610 MSA128DOpnd>, IsCommutable; 1611 1612class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", vbclr_b, MSA128BOpnd>; 1613class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", vbclr_h, MSA128HOpnd>; 1614class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", vbclr_w, MSA128WOpnd>; 1615class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", vbclr_d, MSA128DOpnd>; 1616 1617class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", and, vsplat_uimm_inv_pow2, 1618 MSA128BOpnd>; 1619class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", and, vsplat_uimm_inv_pow2, 1620 MSA128HOpnd>; 1621class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", and, vsplat_uimm_inv_pow2, 1622 MSA128WOpnd>; 1623class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", and, vsplat_uimm_inv_pow2, 1624 MSA128DOpnd>; 1625 1626class BINSL_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.b", int_mips_binsl_b, 1627 MSA128BOpnd>; 1628class BINSL_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.h", int_mips_binsl_h, 1629 MSA128HOpnd>; 1630class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w, 1631 MSA128WOpnd>; 1632class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d, 1633 MSA128DOpnd>; 1634 1635class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, vsplat_maskl_bits_uimm3, MSA128BOpnd>; 1636class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, vsplat_maskl_bits_uimm4, MSA128HOpnd>; 1637class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, vsplat_maskl_bits_uimm5, MSA128WOpnd>; 1638class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, vsplat_maskl_bits_uimm6, MSA128DOpnd>; 1639 1640class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b, 1641 MSA128BOpnd>; 1642class BINSR_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.h", int_mips_binsr_h, 1643 MSA128HOpnd>; 1644class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w, 1645 MSA128WOpnd>; 1646class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d, 1647 MSA128DOpnd>; 1648 1649class BINSRI_B_DESC 1650 : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, vsplat_maskr_bits_uimm3, 1651 MSA128BOpnd>; 1652class BINSRI_H_DESC 1653 : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, vsplat_maskr_bits_uimm4, 1654 MSA128HOpnd>; 1655class BINSRI_W_DESC 1656 : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, vsplat_maskr_bits_uimm5, 1657 MSA128WOpnd>; 1658class BINSRI_D_DESC 1659 : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, vsplat_maskr_bits_uimm6, 1660 MSA128DOpnd>; 1661 1662class BMNZ_V_DESC { 1663 dag OutOperandList = (outs MSA128BOpnd:$wd); 1664 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1665 MSA128BOpnd:$wt); 1666 string AsmString = "bmnz.v\t$wd, $ws, $wt"; 1667 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt, 1668 MSA128BOpnd:$ws, 1669 MSA128BOpnd:$wd_in))]; 1670 InstrItinClass Itinerary = NoItinerary; 1671 string Constraints = "$wd = $wd_in"; 1672} 1673 1674class BMNZI_B_DESC { 1675 dag OutOperandList = (outs MSA128BOpnd:$wd); 1676 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1677 vsplat_uimm8:$u8); 1678 string AsmString = "bmnzi.b\t$wd, $ws, $u8"; 1679 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8, 1680 MSA128BOpnd:$ws, 1681 MSA128BOpnd:$wd_in))]; 1682 InstrItinClass Itinerary = NoItinerary; 1683 string Constraints = "$wd = $wd_in"; 1684} 1685 1686class BMZ_V_DESC { 1687 dag OutOperandList = (outs MSA128BOpnd:$wd); 1688 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1689 MSA128BOpnd:$wt); 1690 string AsmString = "bmz.v\t$wd, $ws, $wt"; 1691 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt, 1692 MSA128BOpnd:$wd_in, 1693 MSA128BOpnd:$ws))]; 1694 InstrItinClass Itinerary = NoItinerary; 1695 string Constraints = "$wd = $wd_in"; 1696} 1697 1698class BMZI_B_DESC { 1699 dag OutOperandList = (outs MSA128BOpnd:$wd); 1700 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1701 vsplat_uimm8:$u8); 1702 string AsmString = "bmzi.b\t$wd, $ws, $u8"; 1703 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8, 1704 MSA128BOpnd:$wd_in, 1705 MSA128BOpnd:$ws))]; 1706 InstrItinClass Itinerary = NoItinerary; 1707 string Constraints = "$wd = $wd_in"; 1708} 1709 1710class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg_b, MSA128BOpnd>; 1711class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg_h, MSA128HOpnd>; 1712class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg_w, MSA128WOpnd>; 1713class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg_d, MSA128DOpnd>; 1714 1715class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", xor, vsplat_uimm_pow2, 1716 MSA128BOpnd>; 1717class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", xor, vsplat_uimm_pow2, 1718 MSA128HOpnd>; 1719class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", xor, vsplat_uimm_pow2, 1720 MSA128WOpnd>; 1721class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", xor, vsplat_uimm_pow2, 1722 MSA128DOpnd>; 1723 1724class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>; 1725class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>; 1726class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>; 1727class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>; 1728 1729class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>; 1730 1731class BSEL_V_DESC { 1732 dag OutOperandList = (outs MSA128BOpnd:$wd); 1733 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1734 MSA128BOpnd:$wt); 1735 string AsmString = "bsel.v\t$wd, $ws, $wt"; 1736 // Note that vselect and BSEL_V treat the condition operand the opposite way 1737 // from each other. 1738 // (vselect cond, if_set, if_clear) 1739 // (BSEL_V cond, if_clear, if_set) 1740 list<dag> Pattern = [(set MSA128BOpnd:$wd, 1741 (vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$wt, 1742 MSA128BOpnd:$ws))]; 1743 InstrItinClass Itinerary = NoItinerary; 1744 string Constraints = "$wd = $wd_in"; 1745} 1746 1747class BSELI_B_DESC { 1748 dag OutOperandList = (outs MSA128BOpnd:$wd); 1749 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1750 vsplat_uimm8:$u8); 1751 string AsmString = "bseli.b\t$wd, $ws, $u8"; 1752 // Note that vselect and BSEL_V treat the condition operand the opposite way 1753 // from each other. 1754 // (vselect cond, if_set, if_clear) 1755 // (BSEL_V cond, if_clear, if_set) 1756 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in, 1757 vsplati8_uimm8:$u8, 1758 MSA128BOpnd:$ws))]; 1759 InstrItinClass Itinerary = NoItinerary; 1760 string Constraints = "$wd = $wd_in"; 1761} 1762 1763class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", vbset_b, MSA128BOpnd>; 1764class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", vbset_h, MSA128HOpnd>; 1765class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", vbset_w, MSA128WOpnd>; 1766class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", vbset_d, MSA128DOpnd>; 1767 1768class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", or, vsplat_uimm_pow2, 1769 MSA128BOpnd>; 1770class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", or, vsplat_uimm_pow2, 1771 MSA128HOpnd>; 1772class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", or, vsplat_uimm_pow2, 1773 MSA128WOpnd>; 1774class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", or, vsplat_uimm_pow2, 1775 MSA128DOpnd>; 1776 1777class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>; 1778class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>; 1779class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>; 1780class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>; 1781 1782class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>; 1783 1784class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>, 1785 IsCommutable; 1786class CEQ_H_DESC : MSA_3R_DESC_BASE<"ceq.h", vseteq_v8i16, MSA128HOpnd>, 1787 IsCommutable; 1788class CEQ_W_DESC : MSA_3R_DESC_BASE<"ceq.w", vseteq_v4i32, MSA128WOpnd>, 1789 IsCommutable; 1790class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq.d", vseteq_v2i64, MSA128DOpnd>, 1791 IsCommutable; 1792 1793class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5, 1794 MSA128BOpnd>; 1795class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5, 1796 MSA128HOpnd>; 1797class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5, 1798 MSA128WOpnd>; 1799class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5, 1800 MSA128DOpnd>; 1801 1802class CFCMSA_DESC { 1803 dag OutOperandList = (outs GPR32Opnd:$rd); 1804 dag InOperandList = (ins MSA128CROpnd:$cs); 1805 string AsmString = "cfcmsa\t$rd, $cs"; 1806 InstrItinClass Itinerary = NoItinerary; 1807 bit hasSideEffects = 1; 1808 bit isMoveReg = 1; 1809} 1810 1811class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>; 1812class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", vsetle_v8i16, MSA128HOpnd>; 1813class CLE_S_W_DESC : MSA_3R_DESC_BASE<"cle_s.w", vsetle_v4i32, MSA128WOpnd>; 1814class CLE_S_D_DESC : MSA_3R_DESC_BASE<"cle_s.d", vsetle_v2i64, MSA128DOpnd>; 1815 1816class CLE_U_B_DESC : MSA_3R_DESC_BASE<"cle_u.b", vsetule_v16i8, MSA128BOpnd>; 1817class CLE_U_H_DESC : MSA_3R_DESC_BASE<"cle_u.h", vsetule_v8i16, MSA128HOpnd>; 1818class CLE_U_W_DESC : MSA_3R_DESC_BASE<"cle_u.w", vsetule_v4i32, MSA128WOpnd>; 1819class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>; 1820 1821class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8, 1822 vsplati8_simm5, MSA128BOpnd>; 1823class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16, 1824 vsplati16_simm5, MSA128HOpnd>; 1825class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32, 1826 vsplati32_simm5, MSA128WOpnd>; 1827class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64, 1828 vsplati64_simm5, MSA128DOpnd>; 1829 1830class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8, 1831 vsplati8_uimm5, MSA128BOpnd>; 1832class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16, 1833 vsplati16_uimm5, MSA128HOpnd>; 1834class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32, 1835 vsplati32_uimm5, MSA128WOpnd>; 1836class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64, 1837 vsplati64_uimm5, MSA128DOpnd>; 1838 1839class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>; 1840class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>; 1841class CLT_S_W_DESC : MSA_3R_DESC_BASE<"clt_s.w", vsetlt_v4i32, MSA128WOpnd>; 1842class CLT_S_D_DESC : MSA_3R_DESC_BASE<"clt_s.d", vsetlt_v2i64, MSA128DOpnd>; 1843 1844class CLT_U_B_DESC : MSA_3R_DESC_BASE<"clt_u.b", vsetult_v16i8, MSA128BOpnd>; 1845class CLT_U_H_DESC : MSA_3R_DESC_BASE<"clt_u.h", vsetult_v8i16, MSA128HOpnd>; 1846class CLT_U_W_DESC : MSA_3R_DESC_BASE<"clt_u.w", vsetult_v4i32, MSA128WOpnd>; 1847class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>; 1848 1849class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8, 1850 vsplati8_simm5, MSA128BOpnd>; 1851class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16, 1852 vsplati16_simm5, MSA128HOpnd>; 1853class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32, 1854 vsplati32_simm5, MSA128WOpnd>; 1855class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64, 1856 vsplati64_simm5, MSA128DOpnd>; 1857 1858class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8, 1859 vsplati8_uimm5, MSA128BOpnd>; 1860class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16, 1861 vsplati16_uimm5, MSA128HOpnd>; 1862class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32, 1863 vsplati32_uimm5, MSA128WOpnd>; 1864class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64, 1865 vsplati64_uimm5, MSA128DOpnd>; 1866 1867class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8, 1868 uimm4_ptr, immZExt4Ptr, GPR32Opnd, 1869 MSA128BOpnd>; 1870class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16, 1871 uimm3_ptr, immZExt3Ptr, GPR32Opnd, 1872 MSA128HOpnd>; 1873class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32, 1874 uimm2_ptr, immZExt2Ptr, GPR32Opnd, 1875 MSA128WOpnd>; 1876class COPY_S_D_DESC : MSA_COPY_DESC_BASE<"copy_s.d", vextract_sext_i64, v2i64, 1877 uimm1_ptr, immZExt1Ptr, GPR64Opnd, 1878 MSA128DOpnd>; 1879 1880class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8, 1881 uimm4_ptr, immZExt4Ptr, GPR32Opnd, 1882 MSA128BOpnd>; 1883class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16, 1884 uimm3_ptr, immZExt3Ptr, GPR32Opnd, 1885 MSA128HOpnd>; 1886class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32, 1887 uimm2_ptr, immZExt2Ptr, GPR32Opnd, 1888 MSA128WOpnd>; 1889 1890class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, 1891 uimm2_ptr, immZExt2Ptr, FGR32, 1892 MSA128W>; 1893class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64, 1894 uimm1_ptr, immZExt1Ptr, FGR64, 1895 MSA128D>; 1896 1897class CTCMSA_DESC { 1898 dag OutOperandList = (outs); 1899 dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs); 1900 string AsmString = "ctcmsa\t$cd, $rs"; 1901 InstrItinClass Itinerary = NoItinerary; 1902 bit hasSideEffects = 1; 1903 bit isMoveReg = 1; 1904} 1905 1906class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>; 1907class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128HOpnd>; 1908class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128WOpnd>; 1909class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128DOpnd>; 1910 1911class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128BOpnd>; 1912class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128HOpnd>; 1913class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128WOpnd>; 1914class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128DOpnd>; 1915 1916class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h, 1917 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>, 1918 IsCommutable; 1919class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w, 1920 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>, 1921 IsCommutable; 1922class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d, 1923 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>, 1924 IsCommutable; 1925 1926class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h, 1927 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>, 1928 IsCommutable; 1929class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w, 1930 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>, 1931 IsCommutable; 1932class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d, 1933 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>, 1934 IsCommutable; 1935 1936class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h, 1937 MSA128HOpnd, MSA128BOpnd, 1938 MSA128BOpnd>, IsCommutable; 1939class DPADD_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.w", int_mips_dpadd_s_w, 1940 MSA128WOpnd, MSA128HOpnd, 1941 MSA128HOpnd>, IsCommutable; 1942class DPADD_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.d", int_mips_dpadd_s_d, 1943 MSA128DOpnd, MSA128WOpnd, 1944 MSA128WOpnd>, IsCommutable; 1945 1946class DPADD_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.h", int_mips_dpadd_u_h, 1947 MSA128HOpnd, MSA128BOpnd, 1948 MSA128BOpnd>, IsCommutable; 1949class DPADD_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.w", int_mips_dpadd_u_w, 1950 MSA128WOpnd, MSA128HOpnd, 1951 MSA128HOpnd>, IsCommutable; 1952class DPADD_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.d", int_mips_dpadd_u_d, 1953 MSA128DOpnd, MSA128WOpnd, 1954 MSA128WOpnd>, IsCommutable; 1955 1956class DPSUB_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.h", int_mips_dpsub_s_h, 1957 MSA128HOpnd, MSA128BOpnd, 1958 MSA128BOpnd>; 1959class DPSUB_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.w", int_mips_dpsub_s_w, 1960 MSA128WOpnd, MSA128HOpnd, 1961 MSA128HOpnd>; 1962class DPSUB_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.d", int_mips_dpsub_s_d, 1963 MSA128DOpnd, MSA128WOpnd, 1964 MSA128WOpnd>; 1965 1966class DPSUB_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.h", int_mips_dpsub_u_h, 1967 MSA128HOpnd, MSA128BOpnd, 1968 MSA128BOpnd>; 1969class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w, 1970 MSA128WOpnd, MSA128HOpnd, 1971 MSA128HOpnd>; 1972class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d, 1973 MSA128DOpnd, MSA128WOpnd, 1974 MSA128WOpnd>; 1975 1976class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>, 1977 IsCommutable; 1978class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>, 1979 IsCommutable; 1980 1981class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>, 1982 IsCommutable; 1983class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>, 1984 IsCommutable; 1985 1986class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>, 1987 IsCommutable; 1988class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>, 1989 IsCommutable; 1990 1991class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w, 1992 MSA128WOpnd>; 1993class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d, 1994 MSA128DOpnd>; 1995 1996class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>; 1997class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>; 1998 1999class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>; 2000class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>; 2001 2002class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>, 2003 IsCommutable; 2004class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>, 2005 IsCommutable; 2006 2007class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>, 2008 IsCommutable; 2009class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>, 2010 IsCommutable; 2011 2012class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>, 2013 IsCommutable; 2014class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>, 2015 IsCommutable; 2016 2017class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>, 2018 IsCommutable; 2019class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>, 2020 IsCommutable; 2021 2022class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>, 2023 IsCommutable; 2024class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>, 2025 IsCommutable; 2026 2027class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>, 2028 IsCommutable; 2029class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>, 2030 IsCommutable; 2031 2032class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>, 2033 IsCommutable; 2034class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>, 2035 IsCommutable; 2036 2037class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>; 2038class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>; 2039 2040class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h, 2041 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>; 2042class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w, 2043 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>; 2044 2045// The fexp2.df instruction multiplies the first operand by 2 to the power of 2046// the second operand. We therefore need a pseudo-insn in order to invent the 2047// 1.0 when we only need to match ISD::FEXP2. 2048class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>; 2049class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>; 2050let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in { 2051 class FEXP2_W_1_PSEUDO_DESC : 2052 MSAPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws), 2053 [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>; 2054 class FEXP2_D_1_PSEUDO_DESC : 2055 MSAPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws), 2056 [(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>; 2057} 2058 2059class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w, 2060 MSA128WOpnd, MSA128HOpnd>; 2061class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d, 2062 MSA128DOpnd, MSA128WOpnd>; 2063 2064class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w, 2065 MSA128WOpnd, MSA128HOpnd>; 2066class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d, 2067 MSA128DOpnd, MSA128WOpnd>; 2068 2069class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>; 2070class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>; 2071 2072class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>; 2073class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>; 2074 2075class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w, 2076 MSA128WOpnd, MSA128HOpnd>; 2077class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d, 2078 MSA128DOpnd, MSA128WOpnd>; 2079 2080class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w, 2081 MSA128WOpnd, MSA128HOpnd>; 2082class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d, 2083 MSA128DOpnd, MSA128WOpnd>; 2084 2085class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8, 2086 MSA128BOpnd, GPR32Opnd>; 2087class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16, 2088 MSA128HOpnd, GPR32Opnd>; 2089class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32, 2090 MSA128WOpnd, GPR32Opnd>; 2091class FILL_D_DESC : MSA_2R_FILL_DESC_BASE<"fill.d", v2i64, vsplati64, 2092 MSA128DOpnd, GPR64Opnd>; 2093 2094class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<vsplatf32, MSA128W, FGR32>; 2095class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<vsplatf64, MSA128D, FGR64>; 2096 2097class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>; 2098class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>; 2099 2100class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>; 2101class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>; 2102 2103class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>; 2104class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>; 2105 2106class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w, 2107 MSA128WOpnd>; 2108class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d, 2109 MSA128DOpnd>; 2110 2111class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>; 2112class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>; 2113 2114class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w, 2115 MSA128WOpnd>; 2116class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d, 2117 MSA128DOpnd>; 2118 2119class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", MipsFMS, MSA128WOpnd>; 2120class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", MipsFMS, MSA128DOpnd>; 2121 2122class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>; 2123class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>; 2124 2125class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>; 2126class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>; 2127 2128class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>; 2129class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>; 2130 2131class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w, 2132 MSA128WOpnd>; 2133class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d, 2134 MSA128DOpnd>; 2135 2136class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>; 2137class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>; 2138 2139class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>; 2140class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>; 2141 2142class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>; 2143class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>; 2144 2145class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>; 2146class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>; 2147 2148class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>; 2149class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>; 2150 2151class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>; 2152class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>; 2153 2154class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>; 2155class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>; 2156 2157class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>; 2158class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>; 2159 2160class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w, 2161 MSA128WOpnd>; 2162class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d, 2163 MSA128DOpnd>; 2164 2165class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w, 2166 MSA128WOpnd>; 2167class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d, 2168 MSA128DOpnd>; 2169 2170class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w, 2171 MSA128WOpnd>; 2172class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d, 2173 MSA128DOpnd>; 2174 2175class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w, 2176 MSA128WOpnd>; 2177class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d, 2178 MSA128DOpnd>; 2179 2180class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w, 2181 MSA128WOpnd>; 2182class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d, 2183 MSA128DOpnd>; 2184 2185class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w, 2186 MSA128WOpnd>; 2187class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d, 2188 MSA128DOpnd>; 2189 2190class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w, 2191 MSA128WOpnd>; 2192class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d, 2193 MSA128DOpnd>; 2194 2195class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h, 2196 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>; 2197class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w, 2198 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>; 2199 2200class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint, 2201 MSA128WOpnd>; 2202class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint, 2203 MSA128DOpnd>; 2204 2205class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint, 2206 MSA128WOpnd>; 2207class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint, 2208 MSA128DOpnd>; 2209 2210class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h, 2211 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2212class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w, 2213 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2214class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d, 2215 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2216 2217class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h, 2218 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2219class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w, 2220 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2221class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d, 2222 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2223 2224class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h, 2225 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2226class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w, 2227 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2228class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d, 2229 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2230 2231class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h, 2232 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2233class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w, 2234 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2235class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d, 2236 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2237 2238class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", MipsILVEV, MSA128BOpnd>; 2239class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", MipsILVEV, MSA128HOpnd>; 2240class ILVEV_W_DESC : MSA_3R_DESC_BASE<"ilvev.w", MipsILVEV, MSA128WOpnd>; 2241class ILVEV_D_DESC : MSA_3R_DESC_BASE<"ilvev.d", MipsILVEV, MSA128DOpnd>; 2242 2243class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>; 2244class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>; 2245class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>; 2246class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>; 2247 2248class ILVOD_B_DESC : MSA_3R_DESC_BASE<"ilvod.b", MipsILVOD, MSA128BOpnd>; 2249class ILVOD_H_DESC : MSA_3R_DESC_BASE<"ilvod.h", MipsILVOD, MSA128HOpnd>; 2250class ILVOD_W_DESC : MSA_3R_DESC_BASE<"ilvod.w", MipsILVOD, MSA128WOpnd>; 2251class ILVOD_D_DESC : MSA_3R_DESC_BASE<"ilvod.d", MipsILVOD, MSA128DOpnd>; 2252 2253class ILVR_B_DESC : MSA_3R_DESC_BASE<"ilvr.b", MipsILVR, MSA128BOpnd>; 2254class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>; 2255class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>; 2256class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>; 2257 2258class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8, uimm4, 2259 immZExt4Ptr, MSA128BOpnd, GPR32Opnd>; 2260class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16, uimm3, 2261 immZExt3Ptr, MSA128HOpnd, GPR32Opnd>; 2262class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32, uimm2, 2263 immZExt2Ptr, MSA128WOpnd, GPR32Opnd>; 2264class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64, uimm1, 2265 immZExt1Ptr, MSA128DOpnd, GPR64Opnd>; 2266 2267class INSERT_B_VIDX_PSEUDO_DESC : 2268 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR32Opnd>; 2269class INSERT_H_VIDX_PSEUDO_DESC : 2270 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR32Opnd>; 2271class INSERT_W_VIDX_PSEUDO_DESC : 2272 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR32Opnd>; 2273class INSERT_D_VIDX_PSEUDO_DESC : 2274 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR32Opnd>; 2275 2276class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32, 2277 uimm2, immZExt2Ptr, 2278 MSA128WOpnd, FGR32Opnd>; 2279class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64, 2280 uimm1, immZExt1Ptr, 2281 MSA128DOpnd, FGR64Opnd>; 2282 2283class INSERT_FW_VIDX_PSEUDO_DESC : 2284 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR32Opnd>; 2285class INSERT_FD_VIDX_PSEUDO_DESC : 2286 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR32Opnd>; 2287 2288class INSERT_B_VIDX64_PSEUDO_DESC : 2289 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR64Opnd>; 2290class INSERT_H_VIDX64_PSEUDO_DESC : 2291 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR64Opnd>; 2292class INSERT_W_VIDX64_PSEUDO_DESC : 2293 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR64Opnd>; 2294class INSERT_D_VIDX64_PSEUDO_DESC : 2295 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR64Opnd>; 2296 2297class INSERT_FW_VIDX64_PSEUDO_DESC : 2298 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR64Opnd>; 2299class INSERT_FD_VIDX64_PSEUDO_DESC : 2300 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR64Opnd>; 2301 2302class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8, uimm4, timmZExt4, 2303 MSA128BOpnd>; 2304class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", insve_v8i16, uimm3, timmZExt3, 2305 MSA128HOpnd>; 2306class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", insve_v4i32, uimm2, timmZExt2, 2307 MSA128WOpnd>; 2308class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64, uimm1, timmZExt1, 2309 MSA128DOpnd>; 2310 2311class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 2312 ValueType TyNode, RegisterOperand ROWD, 2313 Operand MemOpnd, ComplexPattern Addr = addrimm10, 2314 InstrItinClass itin = NoItinerary> { 2315 dag OutOperandList = (outs ROWD:$wd); 2316 dag InOperandList = (ins MemOpnd:$addr); 2317 string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); 2318 list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))]; 2319 InstrItinClass Itinerary = itin; 2320 string DecoderMethod = "DecodeMSA128Mem"; 2321} 2322 2323class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd, mem_simm10>; 2324class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd, 2325 mem_simm10_lsl1, addrimm10lsl1>; 2326class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd, 2327 mem_simm10_lsl2, addrimm10lsl2>; 2328class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd, 2329 mem_simm10_lsl3, addrimm10lsl3>; 2330 2331class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>; 2332class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>; 2333class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>; 2334class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>; 2335 2336class MSA_LOAD_PSEUDO_BASE<SDPatternOperator intrinsic, RegisterOperand RO> : 2337 PseudoSE<(outs RO:$dst), (ins PtrRC:$ptr, GPR32:$imm), 2338 [(set RO:$dst, (intrinsic iPTR:$ptr, GPR32:$imm))]> { 2339 let hasNoSchedulingInfo = 1; 2340 let usesCustomInserter = 1; 2341} 2342 2343def LDR_D : MSA_LOAD_PSEUDO_BASE<int_mips_ldr_d, MSA128DOpnd>; 2344def LDR_W : MSA_LOAD_PSEUDO_BASE<int_mips_ldr_w, MSA128WOpnd>; 2345 2346class LSA_DESC_BASE<string instr_asm, RegisterOperand RORD, 2347 InstrItinClass itin = NoItinerary> { 2348 dag OutOperandList = (outs RORD:$rd); 2349 dag InOperandList = (ins RORD:$rs, RORD:$rt, uimm2_plus1:$sa); 2350 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $sa"); 2351 list<dag> Pattern = [(set RORD:$rd, (add RORD:$rt, 2352 (shl RORD:$rs, 2353 immZExt2Lsa:$sa)))]; 2354 InstrItinClass Itinerary = itin; 2355} 2356 2357class LSA_DESC : LSA_DESC_BASE<"lsa", GPR32Opnd, II_LSA>; 2358class DLSA_DESC : LSA_DESC_BASE<"dlsa", GPR64Opnd, II_DLSA>; 2359 2360class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h, 2361 MSA128HOpnd>; 2362class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w, 2363 MSA128WOpnd>; 2364 2365class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h, 2366 MSA128HOpnd>; 2367class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w, 2368 MSA128WOpnd>; 2369 2370class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", muladd, MSA128BOpnd>; 2371class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", muladd, MSA128HOpnd>; 2372class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", muladd, MSA128WOpnd>; 2373class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", muladd, MSA128DOpnd>; 2374 2375class MAX_A_B_DESC : MSA_3R_DESC_BASE<"max_a.b", int_mips_max_a_b, MSA128BOpnd>; 2376class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>; 2377class MAX_A_W_DESC : MSA_3R_DESC_BASE<"max_a.w", int_mips_max_a_w, MSA128WOpnd>; 2378class MAX_A_D_DESC : MSA_3R_DESC_BASE<"max_a.d", int_mips_max_a_d, MSA128DOpnd>; 2379 2380class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", smax, MSA128BOpnd>; 2381class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", smax, MSA128HOpnd>; 2382class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", smax, MSA128WOpnd>; 2383class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", smax, MSA128DOpnd>; 2384 2385class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", umax, MSA128BOpnd>; 2386class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", umax, MSA128HOpnd>; 2387class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", umax, MSA128WOpnd>; 2388class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", umax, MSA128DOpnd>; 2389 2390class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", smax, vsplati8_simm5, 2391 MSA128BOpnd>; 2392class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", smax, vsplati16_simm5, 2393 MSA128HOpnd>; 2394class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", smax, vsplati32_simm5, 2395 MSA128WOpnd>; 2396class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", smax, vsplati64_simm5, 2397 MSA128DOpnd>; 2398 2399class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", umax, vsplati8_uimm5, 2400 MSA128BOpnd>; 2401class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", umax, vsplati16_uimm5, 2402 MSA128HOpnd>; 2403class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", umax, vsplati32_uimm5, 2404 MSA128WOpnd>; 2405class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", umax, vsplati64_uimm5, 2406 MSA128DOpnd>; 2407 2408class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>; 2409class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>; 2410class MIN_A_W_DESC : MSA_3R_DESC_BASE<"min_a.w", int_mips_min_a_w, MSA128WOpnd>; 2411class MIN_A_D_DESC : MSA_3R_DESC_BASE<"min_a.d", int_mips_min_a_d, MSA128DOpnd>; 2412 2413class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", smin, MSA128BOpnd>; 2414class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", smin, MSA128HOpnd>; 2415class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", smin, MSA128WOpnd>; 2416class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", smin, MSA128DOpnd>; 2417 2418class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", umin, MSA128BOpnd>; 2419class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", umin, MSA128HOpnd>; 2420class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", umin, MSA128WOpnd>; 2421class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", umin, MSA128DOpnd>; 2422 2423class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", smin, vsplati8_simm5, 2424 MSA128BOpnd>; 2425class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", smin, vsplati16_simm5, 2426 MSA128HOpnd>; 2427class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", smin, vsplati32_simm5, 2428 MSA128WOpnd>; 2429class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", smin, vsplati64_simm5, 2430 MSA128DOpnd>; 2431 2432class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", umin, vsplati8_uimm5, 2433 MSA128BOpnd>; 2434class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", umin, vsplati16_uimm5, 2435 MSA128HOpnd>; 2436class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", umin, vsplati32_uimm5, 2437 MSA128WOpnd>; 2438class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", umin, vsplati64_uimm5, 2439 MSA128DOpnd>; 2440 2441class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", srem, MSA128BOpnd>; 2442class MOD_S_H_DESC : MSA_3R_DESC_BASE<"mod_s.h", srem, MSA128HOpnd>; 2443class MOD_S_W_DESC : MSA_3R_DESC_BASE<"mod_s.w", srem, MSA128WOpnd>; 2444class MOD_S_D_DESC : MSA_3R_DESC_BASE<"mod_s.d", srem, MSA128DOpnd>; 2445 2446class MOD_U_B_DESC : MSA_3R_DESC_BASE<"mod_u.b", urem, MSA128BOpnd>; 2447class MOD_U_H_DESC : MSA_3R_DESC_BASE<"mod_u.h", urem, MSA128HOpnd>; 2448class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", urem, MSA128WOpnd>; 2449class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", urem, MSA128DOpnd>; 2450 2451class MOVE_V_DESC { 2452 dag OutOperandList = (outs MSA128BOpnd:$wd); 2453 dag InOperandList = (ins MSA128BOpnd:$ws); 2454 string AsmString = "move.v\t$wd, $ws"; 2455 list<dag> Pattern = []; 2456 InstrItinClass Itinerary = NoItinerary; 2457 bit isMoveReg = 1; 2458} 2459 2460class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h, 2461 MSA128HOpnd>; 2462class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w, 2463 MSA128WOpnd>; 2464 2465class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h, 2466 MSA128HOpnd>; 2467class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w, 2468 MSA128WOpnd>; 2469 2470class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", mulsub, MSA128BOpnd>; 2471class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", mulsub, MSA128HOpnd>; 2472class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", mulsub, MSA128WOpnd>; 2473class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", mulsub, MSA128DOpnd>; 2474 2475class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h, 2476 MSA128HOpnd>; 2477class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w, 2478 MSA128WOpnd>; 2479 2480class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h, 2481 MSA128HOpnd>; 2482class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w, 2483 MSA128WOpnd>; 2484 2485class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128BOpnd>; 2486class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128HOpnd>; 2487class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", mul, MSA128WOpnd>; 2488class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", mul, MSA128DOpnd>; 2489 2490class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>; 2491class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>; 2492class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>; 2493class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>; 2494 2495class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", ctlz, MSA128BOpnd>; 2496class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128HOpnd>; 2497class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128WOpnd>; 2498class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128DOpnd>; 2499 2500class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128BOpnd>; 2501class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128HOpnd>; 2502class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128WOpnd>; 2503class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128DOpnd>; 2504 2505class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8, 2506 MSA128BOpnd>; 2507 2508class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128BOpnd>; 2509class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128HOpnd>; 2510class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128WOpnd>; 2511class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128DOpnd>; 2512 2513class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>; 2514 2515class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128BOpnd>; 2516class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128HOpnd>; 2517class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", MipsPCKEV, MSA128WOpnd>; 2518class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", MipsPCKEV, MSA128DOpnd>; 2519 2520class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", MipsPCKOD, MSA128BOpnd>; 2521class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", MipsPCKOD, MSA128HOpnd>; 2522class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>; 2523class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>; 2524 2525class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>; 2526class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>; 2527class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>; 2528class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>; 2529 2530class SAT_S_B_DESC : MSA_BIT_X_DESC_BASE<"sat_s.b", int_mips_sat_s_b, uimm3, 2531 timmZExt3, MSA128BOpnd>; 2532class SAT_S_H_DESC : MSA_BIT_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h, uimm4, 2533 timmZExt4, MSA128HOpnd>; 2534class SAT_S_W_DESC : MSA_BIT_X_DESC_BASE<"sat_s.w", int_mips_sat_s_w, uimm5, 2535 timmZExt5, MSA128WOpnd>; 2536class SAT_S_D_DESC : MSA_BIT_X_DESC_BASE<"sat_s.d", int_mips_sat_s_d, uimm6, 2537 timmZExt6, MSA128DOpnd>; 2538 2539class SAT_U_B_DESC : MSA_BIT_X_DESC_BASE<"sat_u.b", int_mips_sat_u_b, uimm3, 2540 timmZExt3, MSA128BOpnd>; 2541class SAT_U_H_DESC : MSA_BIT_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h, uimm4, 2542 timmZExt4, MSA128HOpnd>; 2543class SAT_U_W_DESC : MSA_BIT_X_DESC_BASE<"sat_u.w", int_mips_sat_u_w, uimm5, 2544 timmZExt5, MSA128WOpnd>; 2545class SAT_U_D_DESC : MSA_BIT_X_DESC_BASE<"sat_u.d", int_mips_sat_u_d, uimm6, 2546 timmZExt6, MSA128DOpnd>; 2547 2548class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>; 2549class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>; 2550class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>; 2551 2552class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>; 2553class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>; 2554class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>; 2555class SLD_D_DESC : MSA_3R_SLD_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>; 2556 2557class SLDI_B_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.b", int_mips_sldi_b, 2558 MSA128BOpnd, MSA128BOpnd, uimm4, 2559 timmZExt4>; 2560class SLDI_H_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.h", int_mips_sldi_h, 2561 MSA128HOpnd, MSA128HOpnd, uimm3, 2562 timmZExt3>; 2563class SLDI_W_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.w", int_mips_sldi_w, 2564 MSA128WOpnd, MSA128WOpnd, uimm2, 2565 timmZExt2>; 2566class SLDI_D_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.d", int_mips_sldi_d, 2567 MSA128DOpnd, MSA128DOpnd, uimm1, 2568 timmZExt1>; 2569 2570class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128BOpnd>; 2571class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128HOpnd>; 2572class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>; 2573class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>; 2574 2575class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3, 2576 MSA128BOpnd>; 2577class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4, 2578 MSA128HOpnd>; 2579class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5, 2580 MSA128WOpnd>; 2581class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6, 2582 MSA128DOpnd>; 2583 2584class SPLAT_B_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.b", vsplati8_elt, 2585 MSA128BOpnd>; 2586class SPLAT_H_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.h", vsplati16_elt, 2587 MSA128HOpnd>; 2588class SPLAT_W_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.w", vsplati32_elt, 2589 MSA128WOpnd>; 2590class SPLAT_D_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.d", vsplati64_elt, 2591 MSA128DOpnd>; 2592 2593class SPLATI_B_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.b", vsplati8_uimm4, 2594 MSA128BOpnd>; 2595class SPLATI_H_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.h", vsplati16_uimm3, 2596 MSA128HOpnd>; 2597class SPLATI_W_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.w", vsplati32_uimm2, 2598 MSA128WOpnd>; 2599class SPLATI_D_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.d", vsplati64_uimm1, 2600 MSA128DOpnd>; 2601 2602class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>; 2603class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>; 2604class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>; 2605class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>; 2606 2607class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3, 2608 MSA128BOpnd>; 2609class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4, 2610 MSA128HOpnd>; 2611class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5, 2612 MSA128WOpnd>; 2613class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6, 2614 MSA128DOpnd>; 2615 2616class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>; 2617class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>; 2618class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>; 2619class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>; 2620 2621class SRARI_B_DESC : MSA_BIT_X_DESC_BASE<"srari.b", int_mips_srari_b, uimm3, 2622 timmZExt3, MSA128BOpnd>; 2623class SRARI_H_DESC : MSA_BIT_X_DESC_BASE<"srari.h", int_mips_srari_h, uimm4, 2624 timmZExt4, MSA128HOpnd>; 2625class SRARI_W_DESC : MSA_BIT_X_DESC_BASE<"srari.w", int_mips_srari_w, uimm5, 2626 timmZExt5, MSA128WOpnd>; 2627class SRARI_D_DESC : MSA_BIT_X_DESC_BASE<"srari.d", int_mips_srari_d, uimm6, 2628 timmZExt6, MSA128DOpnd>; 2629 2630class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>; 2631class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>; 2632class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>; 2633class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>; 2634 2635class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3, 2636 MSA128BOpnd>; 2637class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4, 2638 MSA128HOpnd>; 2639class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5, 2640 MSA128WOpnd>; 2641class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6, 2642 MSA128DOpnd>; 2643 2644class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>; 2645class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>; 2646class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>; 2647class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>; 2648 2649class SRLRI_B_DESC : MSA_BIT_X_DESC_BASE<"srlri.b", int_mips_srlri_b, uimm3, 2650 timmZExt3, MSA128BOpnd>; 2651class SRLRI_H_DESC : MSA_BIT_X_DESC_BASE<"srlri.h", int_mips_srlri_h, uimm4, 2652 timmZExt4, MSA128HOpnd>; 2653class SRLRI_W_DESC : MSA_BIT_X_DESC_BASE<"srlri.w", int_mips_srlri_w, uimm5, 2654 timmZExt5, MSA128WOpnd>; 2655class SRLRI_D_DESC : MSA_BIT_X_DESC_BASE<"srlri.d", int_mips_srlri_d, uimm6, 2656 timmZExt6, MSA128DOpnd>; 2657 2658class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 2659 ValueType TyNode, RegisterOperand ROWD, 2660 Operand MemOpnd, ComplexPattern Addr = addrimm10, 2661 InstrItinClass itin = NoItinerary> { 2662 dag OutOperandList = (outs); 2663 dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr); 2664 string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); 2665 list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)]; 2666 InstrItinClass Itinerary = itin; 2667 string DecoderMethod = "DecodeMSA128Mem"; 2668} 2669 2670class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd, mem_simm10>; 2671class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd, 2672 mem_simm10_lsl1, addrimm10lsl1>; 2673class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd, 2674 mem_simm10_lsl2, addrimm10lsl2>; 2675class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd, 2676 mem_simm10_lsl3, addrimm10lsl3>; 2677 2678class MSA_STORE_PSEUDO_BASE<SDPatternOperator intrinsic, RegisterOperand RO> : 2679 PseudoSE<(outs), (ins RO:$dst, PtrRC:$ptr, GPR32:$imm), 2680 [(intrinsic RO:$dst, iPTR:$ptr, GPR32:$imm)]> { 2681 let hasNoSchedulingInfo = 1; 2682 let usesCustomInserter = 1; 2683} 2684 2685def STR_D : MSA_STORE_PSEUDO_BASE<int_mips_str_d, MSA128DOpnd>; 2686def STR_W : MSA_STORE_PSEUDO_BASE<int_mips_str_w, MSA128WOpnd>; 2687 2688class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b, 2689 MSA128BOpnd>; 2690class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h, 2691 MSA128HOpnd>; 2692class SUBS_S_W_DESC : MSA_3R_DESC_BASE<"subs_s.w", int_mips_subs_s_w, 2693 MSA128WOpnd>; 2694class SUBS_S_D_DESC : MSA_3R_DESC_BASE<"subs_s.d", int_mips_subs_s_d, 2695 MSA128DOpnd>; 2696 2697class SUBS_U_B_DESC : MSA_3R_DESC_BASE<"subs_u.b", int_mips_subs_u_b, 2698 MSA128BOpnd>; 2699class SUBS_U_H_DESC : MSA_3R_DESC_BASE<"subs_u.h", int_mips_subs_u_h, 2700 MSA128HOpnd>; 2701class SUBS_U_W_DESC : MSA_3R_DESC_BASE<"subs_u.w", int_mips_subs_u_w, 2702 MSA128WOpnd>; 2703class SUBS_U_D_DESC : MSA_3R_DESC_BASE<"subs_u.d", int_mips_subs_u_d, 2704 MSA128DOpnd>; 2705 2706class SUBSUS_U_B_DESC : MSA_3R_DESC_BASE<"subsus_u.b", int_mips_subsus_u_b, 2707 MSA128BOpnd>; 2708class SUBSUS_U_H_DESC : MSA_3R_DESC_BASE<"subsus_u.h", int_mips_subsus_u_h, 2709 MSA128HOpnd>; 2710class SUBSUS_U_W_DESC : MSA_3R_DESC_BASE<"subsus_u.w", int_mips_subsus_u_w, 2711 MSA128WOpnd>; 2712class SUBSUS_U_D_DESC : MSA_3R_DESC_BASE<"subsus_u.d", int_mips_subsus_u_d, 2713 MSA128DOpnd>; 2714 2715class SUBSUU_S_B_DESC : MSA_3R_DESC_BASE<"subsuu_s.b", int_mips_subsuu_s_b, 2716 MSA128BOpnd>; 2717class SUBSUU_S_H_DESC : MSA_3R_DESC_BASE<"subsuu_s.h", int_mips_subsuu_s_h, 2718 MSA128HOpnd>; 2719class SUBSUU_S_W_DESC : MSA_3R_DESC_BASE<"subsuu_s.w", int_mips_subsuu_s_w, 2720 MSA128WOpnd>; 2721class SUBSUU_S_D_DESC : MSA_3R_DESC_BASE<"subsuu_s.d", int_mips_subsuu_s_d, 2722 MSA128DOpnd>; 2723 2724class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", sub, MSA128BOpnd>; 2725class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", sub, MSA128HOpnd>; 2726class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128WOpnd>; 2727class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128DOpnd>; 2728 2729class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5, 2730 MSA128BOpnd>; 2731class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5, 2732 MSA128HOpnd>; 2733class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5, 2734 MSA128WOpnd>; 2735class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5, 2736 MSA128DOpnd>; 2737 2738class VSHF_B_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.b", MSA128BOpnd>; 2739class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>; 2740class VSHF_W_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.w", MSA128WOpnd>; 2741class VSHF_D_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.d", MSA128DOpnd>; 2742 2743class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128BOpnd>; 2744class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128HOpnd>; 2745class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128WOpnd>; 2746class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128DOpnd>; 2747 2748class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8, 2749 MSA128BOpnd>; 2750 2751// Instruction defs. 2752def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC; 2753def ADD_A_H : ADD_A_H_ENC, ADD_A_H_DESC; 2754def ADD_A_W : ADD_A_W_ENC, ADD_A_W_DESC; 2755def ADD_A_D : ADD_A_D_ENC, ADD_A_D_DESC; 2756 2757def ADDS_A_B : ADDS_A_B_ENC, ADDS_A_B_DESC; 2758def ADDS_A_H : ADDS_A_H_ENC, ADDS_A_H_DESC; 2759def ADDS_A_W : ADDS_A_W_ENC, ADDS_A_W_DESC; 2760def ADDS_A_D : ADDS_A_D_ENC, ADDS_A_D_DESC; 2761 2762def ADDS_S_B : ADDS_S_B_ENC, ADDS_S_B_DESC; 2763def ADDS_S_H : ADDS_S_H_ENC, ADDS_S_H_DESC; 2764def ADDS_S_W : ADDS_S_W_ENC, ADDS_S_W_DESC; 2765def ADDS_S_D : ADDS_S_D_ENC, ADDS_S_D_DESC; 2766 2767def ADDS_U_B : ADDS_U_B_ENC, ADDS_U_B_DESC; 2768def ADDS_U_H : ADDS_U_H_ENC, ADDS_U_H_DESC; 2769def ADDS_U_W : ADDS_U_W_ENC, ADDS_U_W_DESC; 2770def ADDS_U_D : ADDS_U_D_ENC, ADDS_U_D_DESC; 2771 2772def ADDV_B : ADDV_B_ENC, ADDV_B_DESC; 2773def ADDV_H : ADDV_H_ENC, ADDV_H_DESC; 2774def ADDV_W : ADDV_W_ENC, ADDV_W_DESC; 2775def ADDV_D : ADDV_D_ENC, ADDV_D_DESC; 2776 2777def ADDVI_B : ADDVI_B_ENC, ADDVI_B_DESC; 2778def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC; 2779def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC; 2780def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC; 2781 2782def AND_V : AND_V_ENC, AND_V_DESC; 2783def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC, 2784 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2785 MSA128BOpnd:$ws, 2786 MSA128BOpnd:$wt)>; 2787def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC, 2788 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2789 MSA128BOpnd:$ws, 2790 MSA128BOpnd:$wt)>; 2791def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC, 2792 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2793 MSA128BOpnd:$ws, 2794 MSA128BOpnd:$wt)>; 2795 2796def ANDI_B : ANDI_B_ENC, ANDI_B_DESC; 2797 2798def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC; 2799def ASUB_S_H : ASUB_S_H_ENC, ASUB_S_H_DESC; 2800def ASUB_S_W : ASUB_S_W_ENC, ASUB_S_W_DESC; 2801def ASUB_S_D : ASUB_S_D_ENC, ASUB_S_D_DESC; 2802 2803def ASUB_U_B : ASUB_U_B_ENC, ASUB_U_B_DESC; 2804def ASUB_U_H : ASUB_U_H_ENC, ASUB_U_H_DESC; 2805def ASUB_U_W : ASUB_U_W_ENC, ASUB_U_W_DESC; 2806def ASUB_U_D : ASUB_U_D_ENC, ASUB_U_D_DESC; 2807 2808def AVE_S_B : AVE_S_B_ENC, AVE_S_B_DESC; 2809def AVE_S_H : AVE_S_H_ENC, AVE_S_H_DESC; 2810def AVE_S_W : AVE_S_W_ENC, AVE_S_W_DESC; 2811def AVE_S_D : AVE_S_D_ENC, AVE_S_D_DESC; 2812 2813def AVE_U_B : AVE_U_B_ENC, AVE_U_B_DESC; 2814def AVE_U_H : AVE_U_H_ENC, AVE_U_H_DESC; 2815def AVE_U_W : AVE_U_W_ENC, AVE_U_W_DESC; 2816def AVE_U_D : AVE_U_D_ENC, AVE_U_D_DESC; 2817 2818def AVER_S_B : AVER_S_B_ENC, AVER_S_B_DESC; 2819def AVER_S_H : AVER_S_H_ENC, AVER_S_H_DESC; 2820def AVER_S_W : AVER_S_W_ENC, AVER_S_W_DESC; 2821def AVER_S_D : AVER_S_D_ENC, AVER_S_D_DESC; 2822 2823def AVER_U_B : AVER_U_B_ENC, AVER_U_B_DESC; 2824def AVER_U_H : AVER_U_H_ENC, AVER_U_H_DESC; 2825def AVER_U_W : AVER_U_W_ENC, AVER_U_W_DESC; 2826def AVER_U_D : AVER_U_D_ENC, AVER_U_D_DESC; 2827 2828def BCLR_B : BCLR_B_ENC, BCLR_B_DESC; 2829def BCLR_H : BCLR_H_ENC, BCLR_H_DESC; 2830def BCLR_W : BCLR_W_ENC, BCLR_W_DESC; 2831def BCLR_D : BCLR_D_ENC, BCLR_D_DESC; 2832 2833def BCLRI_B : BCLRI_B_ENC, BCLRI_B_DESC; 2834def BCLRI_H : BCLRI_H_ENC, BCLRI_H_DESC; 2835def BCLRI_W : BCLRI_W_ENC, BCLRI_W_DESC; 2836def BCLRI_D : BCLRI_D_ENC, BCLRI_D_DESC; 2837 2838def BINSL_B : BINSL_B_ENC, BINSL_B_DESC; 2839def BINSL_H : BINSL_H_ENC, BINSL_H_DESC; 2840def BINSL_W : BINSL_W_ENC, BINSL_W_DESC; 2841def BINSL_D : BINSL_D_ENC, BINSL_D_DESC; 2842 2843def BINSLI_B : BINSLI_B_ENC, BINSLI_B_DESC; 2844def BINSLI_H : BINSLI_H_ENC, BINSLI_H_DESC; 2845def BINSLI_W : BINSLI_W_ENC, BINSLI_W_DESC; 2846def BINSLI_D : BINSLI_D_ENC, BINSLI_D_DESC; 2847 2848def BINSR_B : BINSR_B_ENC, BINSR_B_DESC; 2849def BINSR_H : BINSR_H_ENC, BINSR_H_DESC; 2850def BINSR_W : BINSR_W_ENC, BINSR_W_DESC; 2851def BINSR_D : BINSR_D_ENC, BINSR_D_DESC; 2852 2853def BINSRI_B : BINSRI_B_ENC, BINSRI_B_DESC; 2854def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC; 2855def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC; 2856def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC; 2857 2858def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC; 2859 2860def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC; 2861 2862def BMZ_V : BMZ_V_ENC, BMZ_V_DESC; 2863 2864def BMZI_B : BMZI_B_ENC, BMZI_B_DESC; 2865 2866def BNEG_B : BNEG_B_ENC, BNEG_B_DESC; 2867def BNEG_H : BNEG_H_ENC, BNEG_H_DESC; 2868def BNEG_W : BNEG_W_ENC, BNEG_W_DESC; 2869def BNEG_D : BNEG_D_ENC, BNEG_D_DESC; 2870 2871def BNEGI_B : BNEGI_B_ENC, BNEGI_B_DESC; 2872def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC; 2873def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC; 2874def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC; 2875 2876def BNZ_B : BNZ_B_ENC, BNZ_B_DESC; 2877def BNZ_H : BNZ_H_ENC, BNZ_H_DESC; 2878def BNZ_W : BNZ_W_ENC, BNZ_W_DESC; 2879def BNZ_D : BNZ_D_ENC, BNZ_D_DESC; 2880 2881def BNZ_V : BNZ_V_ENC, BNZ_V_DESC; 2882 2883def BSEL_V : BSEL_V_ENC, BSEL_V_DESC; 2884 2885class MSA_BSEL_PSEUDO_BASE<RegisterOperand RO, ValueType Ty> : 2886 MSAPseudo<(outs RO:$wd), (ins RO:$wd_in, RO:$ws, RO:$wt), 2887 [(set RO:$wd, (Ty (vselect RO:$wd_in, RO:$wt, RO:$ws)))]>, 2888 // Note that vselect and BSEL_V treat the condition operand the opposite way 2889 // from each other. 2890 // (vselect cond, if_set, if_clear) 2891 // (BSEL_V cond, if_clear, if_set) 2892 PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in, 2893 MSA128BOpnd:$ws, MSA128BOpnd:$wt)> { 2894 let Constraints = "$wd_in = $wd"; 2895} 2896 2897def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128HOpnd, v8i16>; 2898def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4i32>; 2899def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2i64>; 2900def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4f32>; 2901def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2f64>; 2902 2903def BSELI_B : BSELI_B_ENC, BSELI_B_DESC; 2904 2905def BSET_B : BSET_B_ENC, BSET_B_DESC; 2906def BSET_H : BSET_H_ENC, BSET_H_DESC; 2907def BSET_W : BSET_W_ENC, BSET_W_DESC; 2908def BSET_D : BSET_D_ENC, BSET_D_DESC; 2909 2910def BSETI_B : BSETI_B_ENC, BSETI_B_DESC; 2911def BSETI_H : BSETI_H_ENC, BSETI_H_DESC; 2912def BSETI_W : BSETI_W_ENC, BSETI_W_DESC; 2913def BSETI_D : BSETI_D_ENC, BSETI_D_DESC; 2914 2915def BZ_B : BZ_B_ENC, BZ_B_DESC; 2916def BZ_H : BZ_H_ENC, BZ_H_DESC; 2917def BZ_W : BZ_W_ENC, BZ_W_DESC; 2918def BZ_D : BZ_D_ENC, BZ_D_DESC; 2919 2920def BZ_V : BZ_V_ENC, BZ_V_DESC; 2921 2922def CEQ_B : CEQ_B_ENC, CEQ_B_DESC; 2923def CEQ_H : CEQ_H_ENC, CEQ_H_DESC; 2924def CEQ_W : CEQ_W_ENC, CEQ_W_DESC; 2925def CEQ_D : CEQ_D_ENC, CEQ_D_DESC; 2926 2927def CEQI_B : CEQI_B_ENC, CEQI_B_DESC; 2928def CEQI_H : CEQI_H_ENC, CEQI_H_DESC; 2929def CEQI_W : CEQI_W_ENC, CEQI_W_DESC; 2930def CEQI_D : CEQI_D_ENC, CEQI_D_DESC; 2931 2932def CFCMSA : CFCMSA_ENC, CFCMSA_DESC; 2933 2934def CLE_S_B : CLE_S_B_ENC, CLE_S_B_DESC; 2935def CLE_S_H : CLE_S_H_ENC, CLE_S_H_DESC; 2936def CLE_S_W : CLE_S_W_ENC, CLE_S_W_DESC; 2937def CLE_S_D : CLE_S_D_ENC, CLE_S_D_DESC; 2938 2939def CLE_U_B : CLE_U_B_ENC, CLE_U_B_DESC; 2940def CLE_U_H : CLE_U_H_ENC, CLE_U_H_DESC; 2941def CLE_U_W : CLE_U_W_ENC, CLE_U_W_DESC; 2942def CLE_U_D : CLE_U_D_ENC, CLE_U_D_DESC; 2943 2944def CLEI_S_B : CLEI_S_B_ENC, CLEI_S_B_DESC; 2945def CLEI_S_H : CLEI_S_H_ENC, CLEI_S_H_DESC; 2946def CLEI_S_W : CLEI_S_W_ENC, CLEI_S_W_DESC; 2947def CLEI_S_D : CLEI_S_D_ENC, CLEI_S_D_DESC; 2948 2949def CLEI_U_B : CLEI_U_B_ENC, CLEI_U_B_DESC; 2950def CLEI_U_H : CLEI_U_H_ENC, CLEI_U_H_DESC; 2951def CLEI_U_W : CLEI_U_W_ENC, CLEI_U_W_DESC; 2952def CLEI_U_D : CLEI_U_D_ENC, CLEI_U_D_DESC; 2953 2954def CLT_S_B : CLT_S_B_ENC, CLT_S_B_DESC; 2955def CLT_S_H : CLT_S_H_ENC, CLT_S_H_DESC; 2956def CLT_S_W : CLT_S_W_ENC, CLT_S_W_DESC; 2957def CLT_S_D : CLT_S_D_ENC, CLT_S_D_DESC; 2958 2959def CLT_U_B : CLT_U_B_ENC, CLT_U_B_DESC; 2960def CLT_U_H : CLT_U_H_ENC, CLT_U_H_DESC; 2961def CLT_U_W : CLT_U_W_ENC, CLT_U_W_DESC; 2962def CLT_U_D : CLT_U_D_ENC, CLT_U_D_DESC; 2963 2964def CLTI_S_B : CLTI_S_B_ENC, CLTI_S_B_DESC; 2965def CLTI_S_H : CLTI_S_H_ENC, CLTI_S_H_DESC; 2966def CLTI_S_W : CLTI_S_W_ENC, CLTI_S_W_DESC; 2967def CLTI_S_D : CLTI_S_D_ENC, CLTI_S_D_DESC; 2968 2969def CLTI_U_B : CLTI_U_B_ENC, CLTI_U_B_DESC; 2970def CLTI_U_H : CLTI_U_H_ENC, CLTI_U_H_DESC; 2971def CLTI_U_W : CLTI_U_W_ENC, CLTI_U_W_DESC; 2972def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC; 2973 2974def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC; 2975def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC; 2976def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC; 2977def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC, ASE_MSA64; 2978 2979def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC; 2980def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC; 2981def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC, ASE_MSA64; 2982 2983def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC; 2984def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC; 2985 2986def CTCMSA : CTCMSA_ENC, CTCMSA_DESC; 2987 2988def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC; 2989def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC; 2990def DIV_S_W : DIV_S_W_ENC, DIV_S_W_DESC; 2991def DIV_S_D : DIV_S_D_ENC, DIV_S_D_DESC; 2992 2993def DIV_U_B : DIV_U_B_ENC, DIV_U_B_DESC; 2994def DIV_U_H : DIV_U_H_ENC, DIV_U_H_DESC; 2995def DIV_U_W : DIV_U_W_ENC, DIV_U_W_DESC; 2996def DIV_U_D : DIV_U_D_ENC, DIV_U_D_DESC; 2997 2998def DOTP_S_H : DOTP_S_H_ENC, DOTP_S_H_DESC; 2999def DOTP_S_W : DOTP_S_W_ENC, DOTP_S_W_DESC; 3000def DOTP_S_D : DOTP_S_D_ENC, DOTP_S_D_DESC; 3001 3002def DOTP_U_H : DOTP_U_H_ENC, DOTP_U_H_DESC; 3003def DOTP_U_W : DOTP_U_W_ENC, DOTP_U_W_DESC; 3004def DOTP_U_D : DOTP_U_D_ENC, DOTP_U_D_DESC; 3005 3006def DPADD_S_H : DPADD_S_H_ENC, DPADD_S_H_DESC; 3007def DPADD_S_W : DPADD_S_W_ENC, DPADD_S_W_DESC; 3008def DPADD_S_D : DPADD_S_D_ENC, DPADD_S_D_DESC; 3009 3010def DPADD_U_H : DPADD_U_H_ENC, DPADD_U_H_DESC; 3011def DPADD_U_W : DPADD_U_W_ENC, DPADD_U_W_DESC; 3012def DPADD_U_D : DPADD_U_D_ENC, DPADD_U_D_DESC; 3013 3014def DPSUB_S_H : DPSUB_S_H_ENC, DPSUB_S_H_DESC; 3015def DPSUB_S_W : DPSUB_S_W_ENC, DPSUB_S_W_DESC; 3016def DPSUB_S_D : DPSUB_S_D_ENC, DPSUB_S_D_DESC; 3017 3018def DPSUB_U_H : DPSUB_U_H_ENC, DPSUB_U_H_DESC; 3019def DPSUB_U_W : DPSUB_U_W_ENC, DPSUB_U_W_DESC; 3020def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC; 3021 3022def FADD_W : FADD_W_ENC, FADD_W_DESC; 3023def FADD_D : FADD_D_ENC, FADD_D_DESC; 3024 3025def FCAF_W : FCAF_W_ENC, FCAF_W_DESC; 3026def FCAF_D : FCAF_D_ENC, FCAF_D_DESC; 3027 3028def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC; 3029def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC; 3030 3031def FCLE_W : FCLE_W_ENC, FCLE_W_DESC; 3032def FCLE_D : FCLE_D_ENC, FCLE_D_DESC; 3033 3034def FCLT_W : FCLT_W_ENC, FCLT_W_DESC; 3035def FCLT_D : FCLT_D_ENC, FCLT_D_DESC; 3036 3037def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC; 3038def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC; 3039 3040def FCNE_W : FCNE_W_ENC, FCNE_W_DESC; 3041def FCNE_D : FCNE_D_ENC, FCNE_D_DESC; 3042 3043def FCOR_W : FCOR_W_ENC, FCOR_W_DESC; 3044def FCOR_D : FCOR_D_ENC, FCOR_D_DESC; 3045 3046def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC; 3047def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC; 3048 3049def FCULE_W : FCULE_W_ENC, FCULE_W_DESC; 3050def FCULE_D : FCULE_D_ENC, FCULE_D_DESC; 3051 3052def FCULT_W : FCULT_W_ENC, FCULT_W_DESC; 3053def FCULT_D : FCULT_D_ENC, FCULT_D_DESC; 3054 3055def FCUN_W : FCUN_W_ENC, FCUN_W_DESC; 3056def FCUN_D : FCUN_D_ENC, FCUN_D_DESC; 3057 3058def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC; 3059def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC; 3060 3061def FDIV_W : FDIV_W_ENC, FDIV_W_DESC; 3062def FDIV_D : FDIV_D_ENC, FDIV_D_DESC; 3063 3064def FEXDO_H : FEXDO_H_ENC, FEXDO_H_DESC; 3065def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC; 3066 3067def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC; 3068def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC; 3069def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC; 3070def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC; 3071 3072def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC; 3073def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC; 3074 3075def FEXUPR_W : FEXUPR_W_ENC, FEXUPR_W_DESC; 3076def FEXUPR_D : FEXUPR_D_ENC, FEXUPR_D_DESC; 3077 3078def FFINT_S_W : FFINT_S_W_ENC, FFINT_S_W_DESC; 3079def FFINT_S_D : FFINT_S_D_ENC, FFINT_S_D_DESC; 3080 3081def FFINT_U_W : FFINT_U_W_ENC, FFINT_U_W_DESC; 3082def FFINT_U_D : FFINT_U_D_ENC, FFINT_U_D_DESC; 3083 3084def FFQL_W : FFQL_W_ENC, FFQL_W_DESC; 3085def FFQL_D : FFQL_D_ENC, FFQL_D_DESC; 3086 3087def FFQR_W : FFQR_W_ENC, FFQR_W_DESC; 3088def FFQR_D : FFQR_D_ENC, FFQR_D_DESC; 3089 3090def FILL_B : FILL_B_ENC, FILL_B_DESC; 3091def FILL_H : FILL_H_ENC, FILL_H_DESC; 3092def FILL_W : FILL_W_ENC, FILL_W_DESC; 3093def FILL_D : FILL_D_ENC, FILL_D_DESC, ASE_MSA64; 3094def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC; 3095def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC; 3096 3097def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC; 3098def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC; 3099 3100def FMADD_W : FMADD_W_ENC, FMADD_W_DESC; 3101def FMADD_D : FMADD_D_ENC, FMADD_D_DESC; 3102 3103def FMAX_W : FMAX_W_ENC, FMAX_W_DESC; 3104def FMAX_D : FMAX_D_ENC, FMAX_D_DESC; 3105 3106def FMAX_A_W : FMAX_A_W_ENC, FMAX_A_W_DESC; 3107def FMAX_A_D : FMAX_A_D_ENC, FMAX_A_D_DESC; 3108 3109def FMIN_W : FMIN_W_ENC, FMIN_W_DESC; 3110def FMIN_D : FMIN_D_ENC, FMIN_D_DESC; 3111 3112def FMIN_A_W : FMIN_A_W_ENC, FMIN_A_W_DESC; 3113def FMIN_A_D : FMIN_A_D_ENC, FMIN_A_D_DESC; 3114 3115def FMSUB_W : FMSUB_W_ENC, FMSUB_W_DESC; 3116def FMSUB_D : FMSUB_D_ENC, FMSUB_D_DESC; 3117 3118def FMUL_W : FMUL_W_ENC, FMUL_W_DESC; 3119def FMUL_D : FMUL_D_ENC, FMUL_D_DESC; 3120 3121def FRINT_W : FRINT_W_ENC, FRINT_W_DESC; 3122def FRINT_D : FRINT_D_ENC, FRINT_D_DESC; 3123 3124def FRCP_W : FRCP_W_ENC, FRCP_W_DESC; 3125def FRCP_D : FRCP_D_ENC, FRCP_D_DESC; 3126 3127def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC; 3128def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC; 3129 3130def FSAF_W : FSAF_W_ENC, FSAF_W_DESC; 3131def FSAF_D : FSAF_D_ENC, FSAF_D_DESC; 3132 3133def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC; 3134def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC; 3135 3136def FSLE_W : FSLE_W_ENC, FSLE_W_DESC; 3137def FSLE_D : FSLE_D_ENC, FSLE_D_DESC; 3138 3139def FSLT_W : FSLT_W_ENC, FSLT_W_DESC; 3140def FSLT_D : FSLT_D_ENC, FSLT_D_DESC; 3141 3142def FSNE_W : FSNE_W_ENC, FSNE_W_DESC; 3143def FSNE_D : FSNE_D_ENC, FSNE_D_DESC; 3144 3145def FSOR_W : FSOR_W_ENC, FSOR_W_DESC; 3146def FSOR_D : FSOR_D_ENC, FSOR_D_DESC; 3147 3148def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC; 3149def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC; 3150 3151def FSUB_W : FSUB_W_ENC, FSUB_W_DESC; 3152def FSUB_D : FSUB_D_ENC, FSUB_D_DESC; 3153 3154def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC; 3155def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC; 3156 3157def FSULE_W : FSULE_W_ENC, FSULE_W_DESC; 3158def FSULE_D : FSULE_D_ENC, FSULE_D_DESC; 3159 3160def FSULT_W : FSULT_W_ENC, FSULT_W_DESC; 3161def FSULT_D : FSULT_D_ENC, FSULT_D_DESC; 3162 3163def FSUN_W : FSUN_W_ENC, FSUN_W_DESC; 3164def FSUN_D : FSUN_D_ENC, FSUN_D_DESC; 3165 3166def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC; 3167def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC; 3168 3169def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC; 3170def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC; 3171 3172def FTINT_U_W : FTINT_U_W_ENC, FTINT_U_W_DESC; 3173def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC; 3174 3175def FTQ_H : FTQ_H_ENC, FTQ_H_DESC; 3176def FTQ_W : FTQ_W_ENC, FTQ_W_DESC; 3177 3178def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC; 3179def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC; 3180 3181def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC; 3182def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC; 3183 3184def : MipsPat<(fsub MSA128WOpnd:$wd, (fmul MSA128WOpnd:$ws, MSA128WOpnd:$wt)), 3185 (FMSUB_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, MSA128WOpnd:$wt)>, 3186 ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST; 3187def : MipsPat<(fsub MSA128DOpnd:$wd, (fmul MSA128DOpnd:$ws, MSA128DOpnd:$wt)), 3188 (FMSUB_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, MSA128DOpnd:$wt)>, 3189 ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST; 3190 3191def : MipsPat<(fadd MSA128WOpnd:$wd, (fmul MSA128WOpnd:$ws, MSA128WOpnd:$wt)), 3192 (FMADD_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, MSA128WOpnd:$wt)>, 3193 ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST; 3194def : MipsPat<(fadd MSA128DOpnd:$wd, (fmul MSA128DOpnd:$ws, MSA128DOpnd:$wt)), 3195 (FMADD_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, MSA128DOpnd:$wt)>, 3196 ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST; 3197 3198def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC; 3199def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC; 3200def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC; 3201 3202def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC; 3203def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC; 3204def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC; 3205 3206def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC; 3207def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC; 3208def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC; 3209 3210def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC; 3211def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC; 3212def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC; 3213 3214def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC; 3215def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC; 3216def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC; 3217def ILVEV_D : ILVEV_D_ENC, ILVEV_D_DESC; 3218 3219def ILVL_B : ILVL_B_ENC, ILVL_B_DESC; 3220def ILVL_H : ILVL_H_ENC, ILVL_H_DESC; 3221def ILVL_W : ILVL_W_ENC, ILVL_W_DESC; 3222def ILVL_D : ILVL_D_ENC, ILVL_D_DESC; 3223 3224def ILVOD_B : ILVOD_B_ENC, ILVOD_B_DESC; 3225def ILVOD_H : ILVOD_H_ENC, ILVOD_H_DESC; 3226def ILVOD_W : ILVOD_W_ENC, ILVOD_W_DESC; 3227def ILVOD_D : ILVOD_D_ENC, ILVOD_D_DESC; 3228 3229def ILVR_B : ILVR_B_ENC, ILVR_B_DESC; 3230def ILVR_H : ILVR_H_ENC, ILVR_H_DESC; 3231def ILVR_W : ILVR_W_ENC, ILVR_W_DESC; 3232def ILVR_D : ILVR_D_ENC, ILVR_D_DESC; 3233 3234def INSERT_B : INSERT_B_ENC, INSERT_B_DESC; 3235def INSERT_H : INSERT_H_ENC, INSERT_H_DESC; 3236def INSERT_W : INSERT_W_ENC, INSERT_W_DESC; 3237def INSERT_D : INSERT_D_ENC, INSERT_D_DESC, ASE_MSA64; 3238 3239// INSERT_FW_PSEUDO defined after INSVE_W 3240// INSERT_FD_PSEUDO defined after INSVE_D 3241 3242// There is a fourth operand that is not present in the encoding. Use a 3243// custom decoder to get a chance to add it. 3244let DecoderMethod = "DecodeINSVE_DF" in { 3245 def INSVE_B : INSVE_B_ENC, INSVE_B_DESC; 3246 def INSVE_H : INSVE_H_ENC, INSVE_H_DESC; 3247 def INSVE_W : INSVE_W_ENC, INSVE_W_DESC; 3248 def INSVE_D : INSVE_D_ENC, INSVE_D_DESC; 3249} 3250 3251def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC; 3252def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC; 3253 3254def INSERT_B_VIDX_PSEUDO : INSERT_B_VIDX_PSEUDO_DESC; 3255def INSERT_H_VIDX_PSEUDO : INSERT_H_VIDX_PSEUDO_DESC; 3256def INSERT_W_VIDX_PSEUDO : INSERT_W_VIDX_PSEUDO_DESC; 3257def INSERT_D_VIDX_PSEUDO : INSERT_D_VIDX_PSEUDO_DESC; 3258def INSERT_FW_VIDX_PSEUDO : INSERT_FW_VIDX_PSEUDO_DESC; 3259def INSERT_FD_VIDX_PSEUDO : INSERT_FD_VIDX_PSEUDO_DESC; 3260 3261def INSERT_B_VIDX64_PSEUDO : INSERT_B_VIDX64_PSEUDO_DESC; 3262def INSERT_H_VIDX64_PSEUDO : INSERT_H_VIDX64_PSEUDO_DESC; 3263def INSERT_W_VIDX64_PSEUDO : INSERT_W_VIDX64_PSEUDO_DESC; 3264def INSERT_D_VIDX64_PSEUDO : INSERT_D_VIDX64_PSEUDO_DESC; 3265def INSERT_FW_VIDX64_PSEUDO : INSERT_FW_VIDX64_PSEUDO_DESC; 3266def INSERT_FD_VIDX64_PSEUDO : INSERT_FD_VIDX64_PSEUDO_DESC; 3267 3268def LD_B: LD_B_ENC, LD_B_DESC; 3269def LD_H: LD_H_ENC, LD_H_DESC; 3270def LD_W: LD_W_ENC, LD_W_DESC; 3271def LD_D: LD_D_ENC, LD_D_DESC; 3272 3273def LDI_B : LDI_B_ENC, LDI_B_DESC; 3274def LDI_H : LDI_H_ENC, LDI_H_DESC; 3275def LDI_W : LDI_W_ENC, LDI_W_DESC; 3276def LDI_D : LDI_D_ENC, LDI_D_DESC; 3277 3278def LSA : LSA_ENC, LSA_DESC; 3279def DLSA : DLSA_ENC, DLSA_DESC, ASE_MSA64; 3280 3281def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC; 3282def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC; 3283 3284def MADDR_Q_H : MADDR_Q_H_ENC, MADDR_Q_H_DESC; 3285def MADDR_Q_W : MADDR_Q_W_ENC, MADDR_Q_W_DESC; 3286 3287def MADDV_B : MADDV_B_ENC, MADDV_B_DESC; 3288def MADDV_H : MADDV_H_ENC, MADDV_H_DESC; 3289def MADDV_W : MADDV_W_ENC, MADDV_W_DESC; 3290def MADDV_D : MADDV_D_ENC, MADDV_D_DESC; 3291 3292def MAX_A_B : MAX_A_B_ENC, MAX_A_B_DESC; 3293def MAX_A_H : MAX_A_H_ENC, MAX_A_H_DESC; 3294def MAX_A_W : MAX_A_W_ENC, MAX_A_W_DESC; 3295def MAX_A_D : MAX_A_D_ENC, MAX_A_D_DESC; 3296 3297def MAX_S_B : MAX_S_B_ENC, MAX_S_B_DESC; 3298def MAX_S_H : MAX_S_H_ENC, MAX_S_H_DESC; 3299def MAX_S_W : MAX_S_W_ENC, MAX_S_W_DESC; 3300def MAX_S_D : MAX_S_D_ENC, MAX_S_D_DESC; 3301 3302def MAX_U_B : MAX_U_B_ENC, MAX_U_B_DESC; 3303def MAX_U_H : MAX_U_H_ENC, MAX_U_H_DESC; 3304def MAX_U_W : MAX_U_W_ENC, MAX_U_W_DESC; 3305def MAX_U_D : MAX_U_D_ENC, MAX_U_D_DESC; 3306 3307def MAXI_S_B : MAXI_S_B_ENC, MAXI_S_B_DESC; 3308def MAXI_S_H : MAXI_S_H_ENC, MAXI_S_H_DESC; 3309def MAXI_S_W : MAXI_S_W_ENC, MAXI_S_W_DESC; 3310def MAXI_S_D : MAXI_S_D_ENC, MAXI_S_D_DESC; 3311 3312def MAXI_U_B : MAXI_U_B_ENC, MAXI_U_B_DESC; 3313def MAXI_U_H : MAXI_U_H_ENC, MAXI_U_H_DESC; 3314def MAXI_U_W : MAXI_U_W_ENC, MAXI_U_W_DESC; 3315def MAXI_U_D : MAXI_U_D_ENC, MAXI_U_D_DESC; 3316 3317def MIN_A_B : MIN_A_B_ENC, MIN_A_B_DESC; 3318def MIN_A_H : MIN_A_H_ENC, MIN_A_H_DESC; 3319def MIN_A_W : MIN_A_W_ENC, MIN_A_W_DESC; 3320def MIN_A_D : MIN_A_D_ENC, MIN_A_D_DESC; 3321 3322def MIN_S_B : MIN_S_B_ENC, MIN_S_B_DESC; 3323def MIN_S_H : MIN_S_H_ENC, MIN_S_H_DESC; 3324def MIN_S_W : MIN_S_W_ENC, MIN_S_W_DESC; 3325def MIN_S_D : MIN_S_D_ENC, MIN_S_D_DESC; 3326 3327def MIN_U_B : MIN_U_B_ENC, MIN_U_B_DESC; 3328def MIN_U_H : MIN_U_H_ENC, MIN_U_H_DESC; 3329def MIN_U_W : MIN_U_W_ENC, MIN_U_W_DESC; 3330def MIN_U_D : MIN_U_D_ENC, MIN_U_D_DESC; 3331 3332def MINI_S_B : MINI_S_B_ENC, MINI_S_B_DESC; 3333def MINI_S_H : MINI_S_H_ENC, MINI_S_H_DESC; 3334def MINI_S_W : MINI_S_W_ENC, MINI_S_W_DESC; 3335def MINI_S_D : MINI_S_D_ENC, MINI_S_D_DESC; 3336 3337def MINI_U_B : MINI_U_B_ENC, MINI_U_B_DESC; 3338def MINI_U_H : MINI_U_H_ENC, MINI_U_H_DESC; 3339def MINI_U_W : MINI_U_W_ENC, MINI_U_W_DESC; 3340def MINI_U_D : MINI_U_D_ENC, MINI_U_D_DESC; 3341 3342def MOD_S_B : MOD_S_B_ENC, MOD_S_B_DESC; 3343def MOD_S_H : MOD_S_H_ENC, MOD_S_H_DESC; 3344def MOD_S_W : MOD_S_W_ENC, MOD_S_W_DESC; 3345def MOD_S_D : MOD_S_D_ENC, MOD_S_D_DESC; 3346 3347def MOD_U_B : MOD_U_B_ENC, MOD_U_B_DESC; 3348def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC; 3349def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC; 3350def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC; 3351 3352def MOVE_V : MOVE_V_ENC, MOVE_V_DESC; 3353 3354def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC; 3355def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC; 3356 3357def MSUBR_Q_H : MSUBR_Q_H_ENC, MSUBR_Q_H_DESC; 3358def MSUBR_Q_W : MSUBR_Q_W_ENC, MSUBR_Q_W_DESC; 3359 3360def MSUBV_B : MSUBV_B_ENC, MSUBV_B_DESC; 3361def MSUBV_H : MSUBV_H_ENC, MSUBV_H_DESC; 3362def MSUBV_W : MSUBV_W_ENC, MSUBV_W_DESC; 3363def MSUBV_D : MSUBV_D_ENC, MSUBV_D_DESC; 3364 3365def MUL_Q_H : MUL_Q_H_ENC, MUL_Q_H_DESC; 3366def MUL_Q_W : MUL_Q_W_ENC, MUL_Q_W_DESC; 3367 3368def MULR_Q_H : MULR_Q_H_ENC, MULR_Q_H_DESC; 3369def MULR_Q_W : MULR_Q_W_ENC, MULR_Q_W_DESC; 3370 3371def MULV_B : MULV_B_ENC, MULV_B_DESC; 3372def MULV_H : MULV_H_ENC, MULV_H_DESC; 3373def MULV_W : MULV_W_ENC, MULV_W_DESC; 3374def MULV_D : MULV_D_ENC, MULV_D_DESC; 3375 3376def NLOC_B : NLOC_B_ENC, NLOC_B_DESC; 3377def NLOC_H : NLOC_H_ENC, NLOC_H_DESC; 3378def NLOC_W : NLOC_W_ENC, NLOC_W_DESC; 3379def NLOC_D : NLOC_D_ENC, NLOC_D_DESC; 3380 3381def NLZC_B : NLZC_B_ENC, NLZC_B_DESC; 3382def NLZC_H : NLZC_H_ENC, NLZC_H_DESC; 3383def NLZC_W : NLZC_W_ENC, NLZC_W_DESC; 3384def NLZC_D : NLZC_D_ENC, NLZC_D_DESC; 3385 3386def NOR_V : NOR_V_ENC, NOR_V_DESC; 3387def NOR_V_H_PSEUDO : NOR_V_H_PSEUDO_DESC, 3388 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3389 MSA128BOpnd:$ws, 3390 MSA128BOpnd:$wt)>; 3391def NOR_V_W_PSEUDO : NOR_V_W_PSEUDO_DESC, 3392 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3393 MSA128BOpnd:$ws, 3394 MSA128BOpnd:$wt)>; 3395def NOR_V_D_PSEUDO : NOR_V_D_PSEUDO_DESC, 3396 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3397 MSA128BOpnd:$ws, 3398 MSA128BOpnd:$wt)>; 3399 3400def NORI_B : NORI_B_ENC, NORI_B_DESC; 3401 3402def OR_V : OR_V_ENC, OR_V_DESC; 3403def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC, 3404 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3405 MSA128BOpnd:$ws, 3406 MSA128BOpnd:$wt)>; 3407def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC, 3408 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3409 MSA128BOpnd:$ws, 3410 MSA128BOpnd:$wt)>; 3411def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC, 3412 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3413 MSA128BOpnd:$ws, 3414 MSA128BOpnd:$wt)>; 3415 3416def ORI_B : ORI_B_ENC, ORI_B_DESC; 3417 3418def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC; 3419def PCKEV_H : PCKEV_H_ENC, PCKEV_H_DESC; 3420def PCKEV_W : PCKEV_W_ENC, PCKEV_W_DESC; 3421def PCKEV_D : PCKEV_D_ENC, PCKEV_D_DESC; 3422 3423def PCKOD_B : PCKOD_B_ENC, PCKOD_B_DESC; 3424def PCKOD_H : PCKOD_H_ENC, PCKOD_H_DESC; 3425def PCKOD_W : PCKOD_W_ENC, PCKOD_W_DESC; 3426def PCKOD_D : PCKOD_D_ENC, PCKOD_D_DESC; 3427 3428def PCNT_B : PCNT_B_ENC, PCNT_B_DESC; 3429def PCNT_H : PCNT_H_ENC, PCNT_H_DESC; 3430def PCNT_W : PCNT_W_ENC, PCNT_W_DESC; 3431def PCNT_D : PCNT_D_ENC, PCNT_D_DESC; 3432 3433def SAT_S_B : SAT_S_B_ENC, SAT_S_B_DESC; 3434def SAT_S_H : SAT_S_H_ENC, SAT_S_H_DESC; 3435def SAT_S_W : SAT_S_W_ENC, SAT_S_W_DESC; 3436def SAT_S_D : SAT_S_D_ENC, SAT_S_D_DESC; 3437 3438def SAT_U_B : SAT_U_B_ENC, SAT_U_B_DESC; 3439def SAT_U_H : SAT_U_H_ENC, SAT_U_H_DESC; 3440def SAT_U_W : SAT_U_W_ENC, SAT_U_W_DESC; 3441def SAT_U_D : SAT_U_D_ENC, SAT_U_D_DESC; 3442 3443def SHF_B : SHF_B_ENC, SHF_B_DESC; 3444def SHF_H : SHF_H_ENC, SHF_H_DESC; 3445def SHF_W : SHF_W_ENC, SHF_W_DESC; 3446 3447def SLD_B : SLD_B_ENC, SLD_B_DESC; 3448def SLD_H : SLD_H_ENC, SLD_H_DESC; 3449def SLD_W : SLD_W_ENC, SLD_W_DESC; 3450def SLD_D : SLD_D_ENC, SLD_D_DESC; 3451 3452def SLDI_B : SLDI_B_ENC, SLDI_B_DESC; 3453def SLDI_H : SLDI_H_ENC, SLDI_H_DESC; 3454def SLDI_W : SLDI_W_ENC, SLDI_W_DESC; 3455def SLDI_D : SLDI_D_ENC, SLDI_D_DESC; 3456 3457def SLL_B : SLL_B_ENC, SLL_B_DESC; 3458def SLL_H : SLL_H_ENC, SLL_H_DESC; 3459def SLL_W : SLL_W_ENC, SLL_W_DESC; 3460def SLL_D : SLL_D_ENC, SLL_D_DESC; 3461 3462def SLLI_B : SLLI_B_ENC, SLLI_B_DESC; 3463def SLLI_H : SLLI_H_ENC, SLLI_H_DESC; 3464def SLLI_W : SLLI_W_ENC, SLLI_W_DESC; 3465def SLLI_D : SLLI_D_ENC, SLLI_D_DESC; 3466 3467def SPLAT_B : SPLAT_B_ENC, SPLAT_B_DESC; 3468def SPLAT_H : SPLAT_H_ENC, SPLAT_H_DESC; 3469def SPLAT_W : SPLAT_W_ENC, SPLAT_W_DESC; 3470def SPLAT_D : SPLAT_D_ENC, SPLAT_D_DESC; 3471 3472def SPLATI_B : SPLATI_B_ENC, SPLATI_B_DESC; 3473def SPLATI_H : SPLATI_H_ENC, SPLATI_H_DESC; 3474def SPLATI_W : SPLATI_W_ENC, SPLATI_W_DESC; 3475def SPLATI_D : SPLATI_D_ENC, SPLATI_D_DESC; 3476 3477def SRA_B : SRA_B_ENC, SRA_B_DESC; 3478def SRA_H : SRA_H_ENC, SRA_H_DESC; 3479def SRA_W : SRA_W_ENC, SRA_W_DESC; 3480def SRA_D : SRA_D_ENC, SRA_D_DESC; 3481 3482def SRAI_B : SRAI_B_ENC, SRAI_B_DESC; 3483def SRAI_H : SRAI_H_ENC, SRAI_H_DESC; 3484def SRAI_W : SRAI_W_ENC, SRAI_W_DESC; 3485def SRAI_D : SRAI_D_ENC, SRAI_D_DESC; 3486 3487def SRAR_B : SRAR_B_ENC, SRAR_B_DESC; 3488def SRAR_H : SRAR_H_ENC, SRAR_H_DESC; 3489def SRAR_W : SRAR_W_ENC, SRAR_W_DESC; 3490def SRAR_D : SRAR_D_ENC, SRAR_D_DESC; 3491 3492def SRARI_B : SRARI_B_ENC, SRARI_B_DESC; 3493def SRARI_H : SRARI_H_ENC, SRARI_H_DESC; 3494def SRARI_W : SRARI_W_ENC, SRARI_W_DESC; 3495def SRARI_D : SRARI_D_ENC, SRARI_D_DESC; 3496 3497def SRL_B : SRL_B_ENC, SRL_B_DESC; 3498def SRL_H : SRL_H_ENC, SRL_H_DESC; 3499def SRL_W : SRL_W_ENC, SRL_W_DESC; 3500def SRL_D : SRL_D_ENC, SRL_D_DESC; 3501 3502def SRLI_B : SRLI_B_ENC, SRLI_B_DESC; 3503def SRLI_H : SRLI_H_ENC, SRLI_H_DESC; 3504def SRLI_W : SRLI_W_ENC, SRLI_W_DESC; 3505def SRLI_D : SRLI_D_ENC, SRLI_D_DESC; 3506 3507def SRLR_B : SRLR_B_ENC, SRLR_B_DESC; 3508def SRLR_H : SRLR_H_ENC, SRLR_H_DESC; 3509def SRLR_W : SRLR_W_ENC, SRLR_W_DESC; 3510def SRLR_D : SRLR_D_ENC, SRLR_D_DESC; 3511 3512def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC; 3513def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC; 3514def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC; 3515def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC; 3516 3517def ST_B: ST_B_ENC, ST_B_DESC; 3518def ST_H: ST_H_ENC, ST_H_DESC; 3519def ST_W: ST_W_ENC, ST_W_DESC; 3520def ST_D: ST_D_ENC, ST_D_DESC; 3521 3522def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC; 3523def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC; 3524def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC; 3525def SUBS_S_D : SUBS_S_D_ENC, SUBS_S_D_DESC; 3526 3527def SUBS_U_B : SUBS_U_B_ENC, SUBS_U_B_DESC; 3528def SUBS_U_H : SUBS_U_H_ENC, SUBS_U_H_DESC; 3529def SUBS_U_W : SUBS_U_W_ENC, SUBS_U_W_DESC; 3530def SUBS_U_D : SUBS_U_D_ENC, SUBS_U_D_DESC; 3531 3532def SUBSUS_U_B : SUBSUS_U_B_ENC, SUBSUS_U_B_DESC; 3533def SUBSUS_U_H : SUBSUS_U_H_ENC, SUBSUS_U_H_DESC; 3534def SUBSUS_U_W : SUBSUS_U_W_ENC, SUBSUS_U_W_DESC; 3535def SUBSUS_U_D : SUBSUS_U_D_ENC, SUBSUS_U_D_DESC; 3536 3537def SUBSUU_S_B : SUBSUU_S_B_ENC, SUBSUU_S_B_DESC; 3538def SUBSUU_S_H : SUBSUU_S_H_ENC, SUBSUU_S_H_DESC; 3539def SUBSUU_S_W : SUBSUU_S_W_ENC, SUBSUU_S_W_DESC; 3540def SUBSUU_S_D : SUBSUU_S_D_ENC, SUBSUU_S_D_DESC; 3541 3542def SUBV_B : SUBV_B_ENC, SUBV_B_DESC; 3543def SUBV_H : SUBV_H_ENC, SUBV_H_DESC; 3544def SUBV_W : SUBV_W_ENC, SUBV_W_DESC; 3545def SUBV_D : SUBV_D_ENC, SUBV_D_DESC; 3546 3547def SUBVI_B : SUBVI_B_ENC, SUBVI_B_DESC; 3548def SUBVI_H : SUBVI_H_ENC, SUBVI_H_DESC; 3549def SUBVI_W : SUBVI_W_ENC, SUBVI_W_DESC; 3550def SUBVI_D : SUBVI_D_ENC, SUBVI_D_DESC; 3551 3552def VSHF_B : VSHF_B_ENC, VSHF_B_DESC; 3553def VSHF_H : VSHF_H_ENC, VSHF_H_DESC; 3554def VSHF_W : VSHF_W_ENC, VSHF_W_DESC; 3555def VSHF_D : VSHF_D_ENC, VSHF_D_DESC; 3556 3557def XOR_V : XOR_V_ENC, XOR_V_DESC; 3558def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC, 3559 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3560 MSA128BOpnd:$ws, 3561 MSA128BOpnd:$wt)>; 3562def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC, 3563 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3564 MSA128BOpnd:$ws, 3565 MSA128BOpnd:$wt)>; 3566def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC, 3567 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3568 MSA128BOpnd:$ws, 3569 MSA128BOpnd:$wt)>; 3570 3571def XORI_B : XORI_B_ENC, XORI_B_DESC; 3572 3573// Patterns. 3574class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> : 3575 Pat<pattern, result>, Requires<pred>; 3576 3577def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx), 3578 (COPY_S_W MSA128W:$ws, immZExt4:$idx)>; 3579 3580def : MSAPat<(v8f16 (load addrimm10lsl1:$addr)), (LD_H addrimm10lsl1:$addr)>; 3581def : MSAPat<(v4f32 (load addrimm10lsl2:$addr)), (LD_W addrimm10lsl2:$addr)>; 3582def : MSAPat<(v2f64 (load addrimm10lsl3:$addr)), (LD_D addrimm10lsl3:$addr)>; 3583 3584def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10lsl1:$addr), 3585 (ST_H MSA128H:$ws, addrimm10lsl1:$addr)>; 3586def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrimm10lsl2:$addr), 3587 (ST_W MSA128W:$ws, addrimm10lsl2:$addr)>; 3588def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrimm10lsl3:$addr), 3589 (ST_D MSA128D:$ws, addrimm10lsl3:$addr)>; 3590 3591class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD, 3592 RegisterOperand ROWS = ROWD, 3593 InstrItinClass itin = NoItinerary> : 3594 MSAPseudo<(outs ROWD:$wd), 3595 (ins ROWS:$ws), 3596 [(set ROWD:$wd, (fabs ROWS:$ws))]> { 3597 InstrItinClass Itinerary = itin; 3598} 3599def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>, 3600 PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, 3601 MSA128WOpnd:$ws)>; 3602def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128DOpnd>, 3603 PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, 3604 MSA128DOpnd:$ws)>; 3605 3606class MSABitconvertPat<ValueType DstVT, ValueType SrcVT, 3607 RegisterClass DstRC, list<Predicate> preds = [HasMSA]> : 3608 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3609 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>; 3610 3611// These are endian-independent because the element size doesnt change 3612def : MSABitconvertPat<v8i16, v8f16, MSA128H>; 3613def : MSABitconvertPat<v4i32, v4f32, MSA128W>; 3614def : MSABitconvertPat<v2i64, v2f64, MSA128D>; 3615def : MSABitconvertPat<v8f16, v8i16, MSA128H>; 3616def : MSABitconvertPat<v4f32, v4i32, MSA128W>; 3617def : MSABitconvertPat<v2f64, v2i64, MSA128D>; 3618 3619// Little endian bitcasts are always no-ops 3620def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>; 3621def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>; 3622def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>; 3623def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>; 3624def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>; 3625def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>; 3626 3627def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>; 3628def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>; 3629def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>; 3630def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>; 3631def : MSABitconvertPat<v8i16, v2f64, MSA128H, [HasMSA, IsLE]>; 3632 3633def : MSABitconvertPat<v4i32, v16i8, MSA128W, [HasMSA, IsLE]>; 3634def : MSABitconvertPat<v4i32, v8i16, MSA128W, [HasMSA, IsLE]>; 3635def : MSABitconvertPat<v4i32, v2i64, MSA128W, [HasMSA, IsLE]>; 3636def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>; 3637def : MSABitconvertPat<v4i32, v2f64, MSA128W, [HasMSA, IsLE]>; 3638 3639def : MSABitconvertPat<v2i64, v16i8, MSA128D, [HasMSA, IsLE]>; 3640def : MSABitconvertPat<v2i64, v8i16, MSA128D, [HasMSA, IsLE]>; 3641def : MSABitconvertPat<v2i64, v4i32, MSA128D, [HasMSA, IsLE]>; 3642def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>; 3643def : MSABitconvertPat<v2i64, v4f32, MSA128D, [HasMSA, IsLE]>; 3644 3645def : MSABitconvertPat<v4f32, v16i8, MSA128W, [HasMSA, IsLE]>; 3646def : MSABitconvertPat<v4f32, v8i16, MSA128W, [HasMSA, IsLE]>; 3647def : MSABitconvertPat<v4f32, v2i64, MSA128W, [HasMSA, IsLE]>; 3648def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>; 3649def : MSABitconvertPat<v4f32, v2f64, MSA128W, [HasMSA, IsLE]>; 3650 3651def : MSABitconvertPat<v2f64, v16i8, MSA128D, [HasMSA, IsLE]>; 3652def : MSABitconvertPat<v2f64, v8i16, MSA128D, [HasMSA, IsLE]>; 3653def : MSABitconvertPat<v2f64, v4i32, MSA128D, [HasMSA, IsLE]>; 3654def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>; 3655def : MSABitconvertPat<v2f64, v4f32, MSA128D, [HasMSA, IsLE]>; 3656 3657// Big endian bitcasts expand to shuffle instructions. 3658// This is because bitcast is defined to be a store/load sequence and the 3659// vector store/load instructions are mixed-endian with respect to the vector 3660// as a whole (little endian with respect to element order, but big endian 3661// elements). 3662 3663class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT, 3664 RegisterClass DstRC, MSAInst Insn, 3665 RegisterClass ViaRC> : 3666 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3667 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27), 3668 DstRC), 3669 [HasMSA, IsBE]>; 3670 3671class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT, 3672 RegisterClass DstRC, MSAInst Insn, 3673 RegisterClass ViaRC> : 3674 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3675 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177), 3676 DstRC), 3677 [HasMSA, IsBE]>; 3678 3679class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT, 3680 RegisterClass DstRC> : 3681 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>; 3682 3683class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT, 3684 RegisterClass DstRC> : 3685 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>; 3686 3687class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT, 3688 RegisterClass DstRC> : 3689 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3690 (COPY_TO_REGCLASS 3691 (SHF_W 3692 (COPY_TO_REGCLASS 3693 (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27), 3694 MSA128W), 177), 3695 DstRC), 3696 [HasMSA, IsBE]>; 3697 3698class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT, 3699 RegisterClass DstRC> : 3700 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>; 3701 3702class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT, 3703 RegisterClass DstRC> : 3704 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>; 3705 3706class MSABitconvertReverseWInDPat<ValueType DstVT, ValueType SrcVT, 3707 RegisterClass DstRC> : 3708 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_W, MSA128W>; 3709 3710def : MSABitconvertReverseBInHPat<v8i16, v16i8, MSA128H>; 3711def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>; 3712def : MSABitconvertReverseBInWPat<v4i32, v16i8, MSA128W>; 3713def : MSABitconvertReverseBInWPat<v4f32, v16i8, MSA128W>; 3714def : MSABitconvertReverseBInDPat<v2i64, v16i8, MSA128D>; 3715def : MSABitconvertReverseBInDPat<v2f64, v16i8, MSA128D>; 3716 3717def : MSABitconvertReverseBInHPat<v16i8, v8i16, MSA128B>; 3718def : MSABitconvertReverseHInWPat<v4i32, v8i16, MSA128W>; 3719def : MSABitconvertReverseHInWPat<v4f32, v8i16, MSA128W>; 3720def : MSABitconvertReverseHInDPat<v2i64, v8i16, MSA128D>; 3721def : MSABitconvertReverseHInDPat<v2f64, v8i16, MSA128D>; 3722 3723def : MSABitconvertReverseBInHPat<v16i8, v8f16, MSA128B>; 3724def : MSABitconvertReverseHInWPat<v4i32, v8f16, MSA128W>; 3725def : MSABitconvertReverseHInWPat<v4f32, v8f16, MSA128W>; 3726def : MSABitconvertReverseHInDPat<v2i64, v8f16, MSA128D>; 3727def : MSABitconvertReverseHInDPat<v2f64, v8f16, MSA128D>; 3728 3729def : MSABitconvertReverseBInWPat<v16i8, v4i32, MSA128B>; 3730def : MSABitconvertReverseHInWPat<v8i16, v4i32, MSA128H>; 3731def : MSABitconvertReverseHInWPat<v8f16, v4i32, MSA128H>; 3732def : MSABitconvertReverseWInDPat<v2i64, v4i32, MSA128D>; 3733def : MSABitconvertReverseWInDPat<v2f64, v4i32, MSA128D>; 3734 3735def : MSABitconvertReverseBInWPat<v16i8, v4f32, MSA128B>; 3736def : MSABitconvertReverseHInWPat<v8i16, v4f32, MSA128H>; 3737def : MSABitconvertReverseHInWPat<v8f16, v4f32, MSA128H>; 3738def : MSABitconvertReverseWInDPat<v2i64, v4f32, MSA128D>; 3739def : MSABitconvertReverseWInDPat<v2f64, v4f32, MSA128D>; 3740 3741def : MSABitconvertReverseBInDPat<v16i8, v2i64, MSA128B>; 3742def : MSABitconvertReverseHInDPat<v8i16, v2i64, MSA128H>; 3743def : MSABitconvertReverseHInDPat<v8f16, v2i64, MSA128H>; 3744def : MSABitconvertReverseWInDPat<v4i32, v2i64, MSA128W>; 3745def : MSABitconvertReverseWInDPat<v4f32, v2i64, MSA128W>; 3746 3747def : MSABitconvertReverseBInDPat<v16i8, v2f64, MSA128B>; 3748def : MSABitconvertReverseHInDPat<v8i16, v2f64, MSA128H>; 3749def : MSABitconvertReverseHInDPat<v8f16, v2f64, MSA128H>; 3750def : MSABitconvertReverseWInDPat<v4i32, v2f64, MSA128W>; 3751def : MSABitconvertReverseWInDPat<v4f32, v2f64, MSA128W>; 3752 3753// Pseudos used to implement BNZ.df, and BZ.df 3754 3755class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode, 3756 RegisterClass RCWS> : 3757 MipsPseudo<(outs GPR32:$dst), 3758 (ins RCWS:$ws), 3759 [(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> { 3760 bit usesCustomInserter = 1; 3761 bit hasNoSchedulingInfo = 1; 3762} 3763 3764def SNZ_B_PSEUDO 3765 : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8, MSA128B>; 3766def SNZ_H_PSEUDO 3767 : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16, MSA128H>; 3768def SNZ_W_PSEUDO 3769 : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32, MSA128W>; 3770def SNZ_D_PSEUDO 3771 : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64, MSA128D>; 3772def SNZ_V_PSEUDO 3773 : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8, MSA128B>; 3774 3775def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8, MSA128B>; 3776def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16, MSA128H>; 3777def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32, MSA128W>; 3778def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64, MSA128D>; 3779def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8, MSA128B>; 3780 3781// Pseudoes used to implement transparent fp16 support. 3782 3783let ASEPredicate = [HasMSA] in { 3784 let usesCustomInserter = 1 in { 3785 def ST_F16 : 3786 MipsPseudo<(outs), (ins MSA128F16:$ws, mem_simm10:$addr), 3787 [(store (f16 MSA128F16:$ws), (addrimm10:$addr))]>; 3788 def LD_F16 : 3789 MipsPseudo<(outs MSA128F16:$ws), (ins mem_simm10:$addr), 3790 [(set MSA128F16:$ws, (f16 (load addrimm10:$addr)))]>; 3791 } 3792 3793 let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in { 3794 def MSA_FP_EXTEND_W_PSEUDO : 3795 MipsPseudo<(outs FGR32Opnd:$fd), (ins MSA128F16:$ws), 3796 [(set FGR32Opnd:$fd, (f32 (fpextend MSA128F16:$ws)))]>; 3797 def MSA_FP_ROUND_W_PSEUDO : 3798 MipsPseudo<(outs MSA128F16:$wd), (ins FGR32Opnd:$fs), 3799 [(set MSA128F16:$wd, (f16 (fpround FGR32Opnd:$fs)))]>; 3800 def MSA_FP_EXTEND_D_PSEUDO : 3801 MipsPseudo<(outs FGR64Opnd:$fd), (ins MSA128F16:$ws), 3802 [(set FGR64Opnd:$fd, (f64 (fpextend MSA128F16:$ws)))]>; 3803 def MSA_FP_ROUND_D_PSEUDO : 3804 MipsPseudo<(outs MSA128F16:$wd), (ins FGR64Opnd:$fs), 3805 [(set MSA128F16:$wd, (f16 (fpround FGR64Opnd:$fs)))]>; 3806 } 3807 3808 def : MipsPat<(MipsTruncIntFP MSA128F16:$ws), 3809 (TRUNC_W_D64 (MSA_FP_EXTEND_D_PSEUDO MSA128F16:$ws))>, 3810 ISA_MIPS1, ASE_MSA; 3811 3812 def : MipsPat<(MipsFPCmp MSA128F16:$ws, MSA128F16:$wt, imm:$cond), 3813 (FCMP_S32 (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$ws), 3814 (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$wt), imm:$cond)>, 3815 ISA_MIPS1_NOT_32R6_64R6, ASE_MSA; 3816} 3817 3818def vsplati64_imm_eq_63 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{ 3819 APInt Imm; 3820 SDNode *BV = N->getOperand(0).getNode(); 3821 EVT EltTy = N->getValueType(0).getVectorElementType(); 3822 3823 return selectVSplat(BV, Imm, EltTy.getSizeInBits()) && 3824 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 63; 3825}]>; 3826 3827def immi32Cst7 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 7;}]>; 3828def immi32Cst15 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 15;}]>; 3829def immi32Cst31 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 31;}]>; 3830 3831def vsplati8imm7 : PatFrag<(ops node:$wt), 3832 (and node:$wt, (vsplati8 immi32Cst7))>; 3833def vsplati16imm15 : PatFrag<(ops node:$wt), 3834 (and node:$wt, (vsplati16 immi32Cst15))>; 3835def vsplati32imm31 : PatFrag<(ops node:$wt), 3836 (and node:$wt, (vsplati32 immi32Cst31))>; 3837def vsplati64imm63 : PatFrag<(ops node:$wt), 3838 (and node:$wt, vsplati64_imm_eq_63)>; 3839 3840class MSAShiftPat<SDNode Node, ValueType VT, MSAInst Insn, dag Vec> : 3841 MSAPat<(VT (Node VT:$ws, (VT (and VT:$wt, Vec)))), 3842 (VT (Insn VT:$ws, VT:$wt))>; 3843 3844class MSABitPat<SDNode Node, ValueType VT, MSAInst Insn, PatFrag Frag> : 3845 MSAPat<(VT (Node VT:$ws, (shl vsplat_imm_eq_1, (Frag VT:$wt)))), 3846 (VT (Insn VT:$ws, VT:$wt))>; 3847 3848multiclass MSAShiftPats<SDNode Node, string Insn> { 3849 def : MSAShiftPat<Node, v16i8, !cast<MSAInst>(Insn#_B), 3850 (vsplati8 immi32Cst7)>; 3851 def : MSAShiftPat<Node, v8i16, !cast<MSAInst>(Insn#_H), 3852 (vsplati16 immi32Cst15)>; 3853 def : MSAShiftPat<Node, v4i32, !cast<MSAInst>(Insn#_W), 3854 (vsplati32 immi32Cst31)>; 3855 def : MSAPat<(v2i64 (Node v2i64:$ws, (v2i64 (and v2i64:$wt, 3856 vsplati64_imm_eq_63)))), 3857 (v2i64 (!cast<MSAInst>(Insn#_D) v2i64:$ws, v2i64:$wt))>; 3858} 3859 3860multiclass MSABitPats<SDNode Node, string Insn> { 3861 def : MSABitPat<Node, v16i8, !cast<MSAInst>(Insn#_B), vsplati8imm7>; 3862 def : MSABitPat<Node, v8i16, !cast<MSAInst>(Insn#_H), vsplati16imm15>; 3863 def : MSABitPat<Node, v4i32, !cast<MSAInst>(Insn#_W), vsplati32imm31>; 3864 def : MSAPat<(Node v2i64:$ws, (shl (v2i64 vsplati64_imm_eq_1), 3865 (vsplati64imm63 v2i64:$wt))), 3866 (v2i64 (!cast<MSAInst>(Insn#_D) v2i64:$ws, v2i64:$wt))>; 3867} 3868 3869defm : MSAShiftPats<shl, "SLL">; 3870defm : MSAShiftPats<srl, "SRL">; 3871defm : MSAShiftPats<sra, "SRA">; 3872defm : MSABitPats<xor, "BNEG">; 3873defm : MSABitPats<or, "BSET">; 3874 3875def : MSAPat<(and v16i8:$ws, (vnot (shl vsplat_imm_eq_1, 3876 (vsplati8imm7 v16i8:$wt)))), 3877 (v16i8 (BCLR_B v16i8:$ws, v16i8:$wt))>; 3878def : MSAPat<(and v8i16:$ws, (vnot (shl vsplat_imm_eq_1, 3879 (vsplati16imm15 v8i16:$wt)))), 3880 (v8i16 (BCLR_H v8i16:$ws, v8i16:$wt))>; 3881def : MSAPat<(and v4i32:$ws, (vnot (shl vsplat_imm_eq_1, 3882 (vsplati32imm31 v4i32:$wt)))), 3883 (v4i32 (BCLR_W v4i32:$ws, v4i32:$wt))>; 3884def : MSAPat<(and v2i64:$ws, (vnot (shl (v2i64 vsplati64_imm_eq_1), 3885 (vsplati64imm63 v2i64:$wt)))), 3886 (v2i64 (BCLR_D v2i64:$ws, v2i64:$wt))>; 3887 3888// Vector extraction with fixed index. 3889// 3890// Extracting 32-bit values on MSA32 should always use COPY_S_W rather than 3891// COPY_U_W, even for the zero-extended case. This is because our forward 3892// compatibility strategy is to consider registers to be infinitely 3893// sign-extended so that a MIPS64 can execute MIPS32 code without getting 3894// different register values. 3895def : MSAPat<(vextract_zext_i32 (v4i32 MSA128W:$ws), immZExt2Ptr:$idx), 3896 (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64; 3897def : MSAPat<(vextract_zext_i32 (v4f32 MSA128W:$ws), immZExt2Ptr:$idx), 3898 (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64; 3899 3900// Extracting 64-bit values on MSA64 should always use COPY_S_D rather than 3901// COPY_U_D, even for the zero-extended case. This is because our forward 3902// compatibility strategy is to consider registers to be infinitely 3903// sign-extended so that a hypothetical MIPS128 would be able to execute MIPS64 3904// code without getting different register values. 3905def : MSAPat<(vextract_zext_i64 (v2i64 MSA128D:$ws), immZExt1Ptr:$idx), 3906 (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64; 3907def : MSAPat<(vextract_zext_i64 (v2f64 MSA128D:$ws), immZExt1Ptr:$idx), 3908 (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64; 3909 3910// Vector extraction with variable index 3911def : MSAPat<(i32 (vextract_sext_i8 v16i8:$ws, i32:$idx)), 3912 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws, 3913 i32:$idx), 3914 sub_lo)), 3915 GPR32), (i32 24))>; 3916def : MSAPat<(i32 (vextract_sext_i16 v8i16:$ws, i32:$idx)), 3917 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws, 3918 i32:$idx), 3919 sub_lo)), 3920 GPR32), (i32 16))>; 3921def : MSAPat<(i32 (vextract_sext_i32 v4i32:$ws, i32:$idx)), 3922 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws, 3923 i32:$idx), 3924 sub_lo)), 3925 GPR32)>; 3926def : MSAPat<(i64 (vextract_sext_i64 v2i64:$ws, i32:$idx)), 3927 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws, 3928 i32:$idx), 3929 sub_64)), 3930 GPR64), [HasMSA, IsGP64bit]>; 3931 3932def : MSAPat<(i32 (vextract_zext_i8 v16i8:$ws, i32:$idx)), 3933 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws, 3934 i32:$idx), 3935 sub_lo)), 3936 GPR32), (i32 24))>; 3937def : MSAPat<(i32 (vextract_zext_i16 v8i16:$ws, i32:$idx)), 3938 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws, 3939 i32:$idx), 3940 sub_lo)), 3941 GPR32), (i32 16))>; 3942def : MSAPat<(i32 (vextract_zext_i32 v4i32:$ws, i32:$idx)), 3943 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws, 3944 i32:$idx), 3945 sub_lo)), 3946 GPR32)>; 3947def : MSAPat<(i64 (vextract_zext_i64 v2i64:$ws, i32:$idx)), 3948 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws, 3949 i32:$idx), 3950 sub_64)), 3951 GPR64), [HasMSA, IsGP64bit]>; 3952 3953def : MSAPat<(f32 (vector_extract v4f32:$ws, i32:$idx)), 3954 (f32 (EXTRACT_SUBREG (SPLAT_W v4f32:$ws, 3955 i32:$idx), 3956 sub_lo))>; 3957def : MSAPat<(f64 (vector_extract v2f64:$ws, i32:$idx)), 3958 (f64 (EXTRACT_SUBREG (SPLAT_D v2f64:$ws, 3959 i32:$idx), 3960 sub_64))>; 3961 3962// Vector extraction with variable index (N64 ABI) 3963def : MSAPat< 3964 (i32 (vextract_sext_i8 v16i8:$ws, i64:$idx)), 3965 (SRA (COPY_TO_REGCLASS 3966 (i32 (EXTRACT_SUBREG 3967 (SPLAT_B v16i8:$ws, 3968 (COPY_TO_REGCLASS 3969 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3970 sub_lo)), 3971 GPR32), 3972 (i32 24))>; 3973def : MSAPat< 3974 (i32 (vextract_sext_i16 v8i16:$ws, i64:$idx)), 3975 (SRA (COPY_TO_REGCLASS 3976 (i32 (EXTRACT_SUBREG 3977 (SPLAT_H v8i16:$ws, 3978 (COPY_TO_REGCLASS 3979 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3980 sub_lo)), 3981 GPR32), 3982 (i32 16))>; 3983def : MSAPat< 3984 (i32 (vextract_sext_i32 v4i32:$ws, i64:$idx)), 3985 (COPY_TO_REGCLASS 3986 (i32 (EXTRACT_SUBREG 3987 (SPLAT_W v4i32:$ws, 3988 (COPY_TO_REGCLASS 3989 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3990 sub_lo)), 3991 GPR32)>; 3992def : MSAPat< 3993 (i64 (vextract_sext_i64 v2i64:$ws, i64:$idx)), 3994 (COPY_TO_REGCLASS 3995 (i64 (EXTRACT_SUBREG 3996 (SPLAT_D v2i64:$ws, 3997 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3998 sub_64)), 3999 GPR64), [HasMSA, IsGP64bit]>; 4000 4001def : MSAPat< 4002 (i32 (vextract_zext_i8 v16i8:$ws, i64:$idx)), 4003 (SRL (COPY_TO_REGCLASS 4004 (i32 (EXTRACT_SUBREG 4005 (SPLAT_B v16i8:$ws, 4006 (COPY_TO_REGCLASS 4007 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4008 sub_lo)), 4009 GPR32), 4010 (i32 24))>; 4011def : MSAPat< 4012 (i32 (vextract_zext_i16 v8i16:$ws, i64:$idx)), 4013 (SRL (COPY_TO_REGCLASS 4014 (i32 (EXTRACT_SUBREG 4015 (SPLAT_H v8i16:$ws, 4016 (COPY_TO_REGCLASS 4017 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4018 sub_lo)), 4019 GPR32), 4020 (i32 16))>; 4021def : MSAPat< 4022 (i32 (vextract_zext_i32 v4i32:$ws, i64:$idx)), 4023 (COPY_TO_REGCLASS 4024 (i32 (EXTRACT_SUBREG 4025 (SPLAT_W v4i32:$ws, 4026 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4027 sub_lo)), 4028 GPR32)>; 4029def : MSAPat< 4030 (i64 (vextract_zext_i64 v2i64:$ws, i64:$idx)), 4031 (COPY_TO_REGCLASS 4032 (i64 (EXTRACT_SUBREG 4033 (SPLAT_D v2i64:$ws, 4034 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4035 sub_64)), 4036 GPR64), 4037 [HasMSA, IsGP64bit]>; 4038 4039def : MSAPat< 4040 (f32 (vector_extract v4f32:$ws, i64:$idx)), 4041 (f32 (EXTRACT_SUBREG 4042 (SPLAT_W v4f32:$ws, 4043 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4044 sub_lo))>; 4045def : MSAPat< 4046 (f64 (vector_extract v2f64:$ws, i64:$idx)), 4047 (f64 (EXTRACT_SUBREG 4048 (SPLAT_D v2f64:$ws, 4049 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4050 sub_64))>; 4051 4052def : MSAPat<(vfseteq_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b), 4053 (FCEQ_W MSA128WOpnd:$a, MSA128WOpnd:$b)>; 4054def : MSAPat<(vfseteq_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b), 4055 (FCEQ_D MSA128DOpnd:$a, MSA128DOpnd:$b)>; 4056def : MSAPat<(vfsetle_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b), 4057 (FCLE_W MSA128WOpnd:$a, MSA128WOpnd:$b)>; 4058def : MSAPat<(vfsetle_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b), 4059 (FCLE_D MSA128DOpnd:$a, MSA128DOpnd:$b)>; 4060def : MSAPat<(vfsetlt_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b), 4061 (FCLT_W MSA128WOpnd:$a, MSA128WOpnd:$b)>; 4062def : MSAPat<(vfsetlt_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b), 4063 (FCLT_D MSA128DOpnd:$a, MSA128DOpnd:$b)>; 4064def : MSAPat<(vfsetne_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b), 4065 (FCNE_W MSA128WOpnd:$a, MSA128WOpnd:$b)>; 4066def : MSAPat<(vfsetne_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b), 4067 (FCNE_D MSA128DOpnd:$a, MSA128DOpnd:$b)>; 4068