1 //===- MipsLegalizerInfo.cpp ------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements the targeting of the Machinelegalizer class for Mips. 10 /// \todo This should be generated by TableGen. 11 //===----------------------------------------------------------------------===// 12 13 #include "MipsLegalizerInfo.h" 14 #include "MipsTargetMachine.h" 15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h" 16 #include "llvm/IR/IntrinsicsMips.h" 17 18 using namespace llvm; 19 20 struct TypesAndMemOps { 21 LLT ValTy; 22 LLT PtrTy; 23 unsigned MemSize; 24 bool SystemSupportsUnalignedAccess; 25 }; 26 27 // Assumes power of 2 memory size. Subtargets that have only naturally-aligned 28 // memory access need to perform additional legalization here. 29 static bool isUnalignedMemmoryAccess(uint64_t MemSize, uint64_t AlignInBits) { 30 assert(isPowerOf2_64(MemSize) && "Expected power of 2 memory size"); 31 assert(isPowerOf2_64(AlignInBits) && "Expected power of 2 align"); 32 if (MemSize > AlignInBits) 33 return true; 34 return false; 35 } 36 37 static bool 38 CheckTy0Ty1MemSizeAlign(const LegalityQuery &Query, 39 std::initializer_list<TypesAndMemOps> SupportedValues) { 40 unsigned QueryMemSize = Query.MMODescrs[0].SizeInBits; 41 42 // Non power of two memory access is never legal. 43 if (!isPowerOf2_64(QueryMemSize)) 44 return false; 45 46 for (auto &Val : SupportedValues) { 47 if (Val.ValTy != Query.Types[0]) 48 continue; 49 if (Val.PtrTy != Query.Types[1]) 50 continue; 51 if (Val.MemSize != QueryMemSize) 52 continue; 53 if (!Val.SystemSupportsUnalignedAccess && 54 isUnalignedMemmoryAccess(QueryMemSize, Query.MMODescrs[0].AlignInBits)) 55 return false; 56 return true; 57 } 58 return false; 59 } 60 61 static bool CheckTyN(unsigned N, const LegalityQuery &Query, 62 std::initializer_list<LLT> SupportedValues) { 63 for (auto &Val : SupportedValues) 64 if (Val == Query.Types[N]) 65 return true; 66 return false; 67 } 68 69 MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) { 70 using namespace TargetOpcode; 71 72 const LLT s1 = LLT::scalar(1); 73 const LLT s32 = LLT::scalar(32); 74 const LLT s64 = LLT::scalar(64); 75 const LLT v16s8 = LLT::vector(16, 8); 76 const LLT v8s16 = LLT::vector(8, 16); 77 const LLT v4s32 = LLT::vector(4, 32); 78 const LLT v2s64 = LLT::vector(2, 64); 79 const LLT p0 = LLT::pointer(0, 32); 80 81 getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL}) 82 .legalIf([=, &ST](const LegalityQuery &Query) { 83 if (CheckTyN(0, Query, {s32})) 84 return true; 85 if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64})) 86 return true; 87 return false; 88 }) 89 .clampScalar(0, s32, s32); 90 91 getActionDefinitionsBuilder({G_UADDO, G_UADDE, G_USUBO, G_USUBE, G_UMULO}) 92 .lowerFor({{s32, s1}}); 93 94 getActionDefinitionsBuilder(G_UMULH) 95 .legalFor({s32}) 96 .maxScalar(0, s32); 97 98 // MIPS32r6 does not have alignment restrictions for memory access. 99 // For MIPS32r5 and older memory access must be naturally-aligned i.e. aligned 100 // to at least a multiple of its own size. There is however a two instruction 101 // combination that performs 4 byte unaligned access (lwr/lwl and swl/swr) 102 // therefore 4 byte load and store are legal and will use NoAlignRequirements. 103 bool NoAlignRequirements = true; 104 105 getActionDefinitionsBuilder({G_LOAD, G_STORE}) 106 .legalIf([=, &ST](const LegalityQuery &Query) { 107 if (CheckTy0Ty1MemSizeAlign( 108 Query, {{s32, p0, 8, NoAlignRequirements}, 109 {s32, p0, 16, ST.systemSupportsUnalignedAccess()}, 110 {s32, p0, 32, NoAlignRequirements}, 111 {p0, p0, 32, NoAlignRequirements}, 112 {s64, p0, 64, ST.systemSupportsUnalignedAccess()}})) 113 return true; 114 if (ST.hasMSA() && CheckTy0Ty1MemSizeAlign( 115 Query, {{v16s8, p0, 128, NoAlignRequirements}, 116 {v8s16, p0, 128, NoAlignRequirements}, 117 {v4s32, p0, 128, NoAlignRequirements}, 118 {v2s64, p0, 128, NoAlignRequirements}})) 119 return true; 120 return false; 121 }) 122 // Custom lower scalar memory access, up to 8 bytes, for: 123 // - non-power-of-2 MemSizes 124 // - unaligned 2 or 8 byte MemSizes for MIPS32r5 and older 125 .customIf([=, &ST](const LegalityQuery &Query) { 126 if (!Query.Types[0].isScalar() || Query.Types[1] != p0 || 127 Query.Types[0] == s1) 128 return false; 129 130 unsigned Size = Query.Types[0].getSizeInBits(); 131 unsigned QueryMemSize = Query.MMODescrs[0].SizeInBits; 132 assert(QueryMemSize <= Size && "Scalar can't hold MemSize"); 133 134 if (Size > 64 || QueryMemSize > 64) 135 return false; 136 137 if (!isPowerOf2_64(Query.MMODescrs[0].SizeInBits)) 138 return true; 139 140 if (!ST.systemSupportsUnalignedAccess() && 141 isUnalignedMemmoryAccess(QueryMemSize, 142 Query.MMODescrs[0].AlignInBits)) { 143 assert(QueryMemSize != 32 && "4 byte load and store are legal"); 144 return true; 145 } 146 147 return false; 148 }) 149 .minScalar(0, s32); 150 151 getActionDefinitionsBuilder(G_IMPLICIT_DEF) 152 .legalFor({s32, s64}); 153 154 getActionDefinitionsBuilder(G_UNMERGE_VALUES) 155 .legalFor({{s32, s64}}); 156 157 getActionDefinitionsBuilder(G_MERGE_VALUES) 158 .legalFor({{s64, s32}}); 159 160 getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD}) 161 .legalForTypesWithMemDesc({{s32, p0, 8, 8}, 162 {s32, p0, 16, 8}}) 163 .clampScalar(0, s32, s32); 164 165 getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT}) 166 .legalIf([](const LegalityQuery &Query) { return false; }) 167 .maxScalar(0, s32); 168 169 getActionDefinitionsBuilder(G_TRUNC) 170 .legalIf([](const LegalityQuery &Query) { return false; }) 171 .maxScalar(1, s32); 172 173 getActionDefinitionsBuilder(G_SELECT) 174 .legalForCartesianProduct({p0, s32, s64}, {s32}) 175 .minScalar(0, s32) 176 .minScalar(1, s32); 177 178 getActionDefinitionsBuilder(G_BRCOND) 179 .legalFor({s32}) 180 .minScalar(0, s32); 181 182 getActionDefinitionsBuilder(G_BRJT) 183 .legalFor({{p0, s32}}); 184 185 getActionDefinitionsBuilder(G_BRINDIRECT) 186 .legalFor({p0}); 187 188 getActionDefinitionsBuilder(G_PHI) 189 .legalFor({p0, s32, s64}) 190 .minScalar(0, s32); 191 192 getActionDefinitionsBuilder({G_AND, G_OR, G_XOR}) 193 .legalFor({s32}) 194 .clampScalar(0, s32, s32); 195 196 getActionDefinitionsBuilder({G_SDIV, G_SREM, G_UDIV, G_UREM}) 197 .legalIf([=, &ST](const LegalityQuery &Query) { 198 if (CheckTyN(0, Query, {s32})) 199 return true; 200 if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64})) 201 return true; 202 return false; 203 }) 204 .minScalar(0, s32) 205 .libcallFor({s64}); 206 207 getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR}) 208 .legalFor({{s32, s32}}) 209 .clampScalar(1, s32, s32) 210 .clampScalar(0, s32, s32); 211 212 getActionDefinitionsBuilder(G_ICMP) 213 .legalForCartesianProduct({s32}, {s32, p0}) 214 .clampScalar(1, s32, s32) 215 .minScalar(0, s32); 216 217 getActionDefinitionsBuilder(G_CONSTANT) 218 .legalFor({s32}) 219 .clampScalar(0, s32, s32); 220 221 getActionDefinitionsBuilder({G_PTR_ADD, G_INTTOPTR}) 222 .legalFor({{p0, s32}}); 223 224 getActionDefinitionsBuilder(G_PTRTOINT) 225 .legalFor({{s32, p0}}); 226 227 getActionDefinitionsBuilder(G_FRAME_INDEX) 228 .legalFor({p0}); 229 230 getActionDefinitionsBuilder({G_GLOBAL_VALUE, G_JUMP_TABLE}) 231 .legalFor({p0}); 232 233 getActionDefinitionsBuilder(G_DYN_STACKALLOC) 234 .lowerFor({{p0, s32}}); 235 236 getActionDefinitionsBuilder(G_VASTART) 237 .legalFor({p0}); 238 239 getActionDefinitionsBuilder(G_BSWAP) 240 .legalIf([=, &ST](const LegalityQuery &Query) { 241 if (ST.hasMips32r2() && CheckTyN(0, Query, {s32})) 242 return true; 243 return false; 244 }) 245 .lowerIf([=, &ST](const LegalityQuery &Query) { 246 if (!ST.hasMips32r2() && CheckTyN(0, Query, {s32})) 247 return true; 248 return false; 249 }) 250 .maxScalar(0, s32); 251 252 getActionDefinitionsBuilder(G_BITREVERSE) 253 .lowerFor({s32}) 254 .maxScalar(0, s32); 255 256 getActionDefinitionsBuilder(G_CTLZ) 257 .legalFor({{s32, s32}}) 258 .maxScalar(0, s32) 259 .maxScalar(1, s32); 260 getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF) 261 .lowerFor({{s32, s32}}); 262 263 getActionDefinitionsBuilder(G_CTTZ) 264 .lowerFor({{s32, s32}}) 265 .maxScalar(0, s32) 266 .maxScalar(1, s32); 267 getActionDefinitionsBuilder(G_CTTZ_ZERO_UNDEF) 268 .lowerFor({{s32, s32}, {s64, s64}}); 269 270 getActionDefinitionsBuilder(G_CTPOP) 271 .lowerFor({{s32, s32}}) 272 .clampScalar(0, s32, s32) 273 .clampScalar(1, s32, s32); 274 275 // FP instructions 276 getActionDefinitionsBuilder(G_FCONSTANT) 277 .legalFor({s32, s64}); 278 279 getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FABS, G_FSQRT}) 280 .legalIf([=, &ST](const LegalityQuery &Query) { 281 if (CheckTyN(0, Query, {s32, s64})) 282 return true; 283 if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64})) 284 return true; 285 return false; 286 }); 287 288 getActionDefinitionsBuilder(G_FCMP) 289 .legalFor({{s32, s32}, {s32, s64}}) 290 .minScalar(0, s32); 291 292 getActionDefinitionsBuilder({G_FCEIL, G_FFLOOR}) 293 .libcallFor({s32, s64}); 294 295 getActionDefinitionsBuilder(G_FPEXT) 296 .legalFor({{s64, s32}}); 297 298 getActionDefinitionsBuilder(G_FPTRUNC) 299 .legalFor({{s32, s64}}); 300 301 // FP to int conversion instructions 302 getActionDefinitionsBuilder(G_FPTOSI) 303 .legalForCartesianProduct({s32}, {s64, s32}) 304 .libcallForCartesianProduct({s64}, {s64, s32}) 305 .minScalar(0, s32); 306 307 getActionDefinitionsBuilder(G_FPTOUI) 308 .libcallForCartesianProduct({s64}, {s64, s32}) 309 .lowerForCartesianProduct({s32}, {s64, s32}) 310 .minScalar(0, s32); 311 312 // Int to FP conversion instructions 313 getActionDefinitionsBuilder(G_SITOFP) 314 .legalForCartesianProduct({s64, s32}, {s32}) 315 .libcallForCartesianProduct({s64, s32}, {s64}) 316 .minScalar(1, s32); 317 318 getActionDefinitionsBuilder(G_UITOFP) 319 .libcallForCartesianProduct({s64, s32}, {s64}) 320 .customForCartesianProduct({s64, s32}, {s32}) 321 .minScalar(1, s32); 322 323 getActionDefinitionsBuilder(G_SEXT_INREG).lower(); 324 325 getActionDefinitionsBuilder({G_MEMCPY, G_MEMMOVE, G_MEMSET}).libcall(); 326 327 computeTables(); 328 verify(*ST.getInstrInfo()); 329 } 330 331 bool MipsLegalizerInfo::legalizeCustom(LegalizerHelper &Helper, 332 MachineInstr &MI) const { 333 using namespace TargetOpcode; 334 335 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder; 336 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); 337 338 const LLT s32 = LLT::scalar(32); 339 const LLT s64 = LLT::scalar(64); 340 341 switch (MI.getOpcode()) { 342 case G_LOAD: 343 case G_STORE: { 344 unsigned MemSize = (**MI.memoperands_begin()).getSize(); 345 Register Val = MI.getOperand(0).getReg(); 346 unsigned Size = MRI.getType(Val).getSizeInBits(); 347 348 MachineMemOperand *MMOBase = *MI.memoperands_begin(); 349 350 assert(MemSize <= 8 && "MemSize is too large"); 351 assert(Size <= 64 && "Scalar size is too large"); 352 353 // Split MemSize into two, P2HalfMemSize is largest power of two smaller 354 // then MemSize. e.g. 8 = 4 + 4 , 6 = 4 + 2, 3 = 2 + 1. 355 unsigned P2HalfMemSize, RemMemSize; 356 if (isPowerOf2_64(MemSize)) { 357 P2HalfMemSize = RemMemSize = MemSize / 2; 358 } else { 359 P2HalfMemSize = 1 << Log2_32(MemSize); 360 RemMemSize = MemSize - P2HalfMemSize; 361 } 362 363 Register BaseAddr = MI.getOperand(1).getReg(); 364 LLT PtrTy = MRI.getType(BaseAddr); 365 MachineFunction &MF = MIRBuilder.getMF(); 366 367 auto P2HalfMemOp = MF.getMachineMemOperand(MMOBase, 0, P2HalfMemSize); 368 auto RemMemOp = MF.getMachineMemOperand(MMOBase, P2HalfMemSize, RemMemSize); 369 370 if (MI.getOpcode() == G_STORE) { 371 // Widen Val to s32 or s64 in order to create legal G_LSHR or G_UNMERGE. 372 if (Size < 32) 373 Val = MIRBuilder.buildAnyExt(s32, Val).getReg(0); 374 if (Size > 32 && Size < 64) 375 Val = MIRBuilder.buildAnyExt(s64, Val).getReg(0); 376 377 auto C_P2HalfMemSize = MIRBuilder.buildConstant(s32, P2HalfMemSize); 378 auto Addr = MIRBuilder.buildPtrAdd(PtrTy, BaseAddr, C_P2HalfMemSize); 379 380 if (MI.getOpcode() == G_STORE && MemSize <= 4) { 381 MIRBuilder.buildStore(Val, BaseAddr, *P2HalfMemOp); 382 auto C_P2Half_InBits = MIRBuilder.buildConstant(s32, P2HalfMemSize * 8); 383 auto Shift = MIRBuilder.buildLShr(s32, Val, C_P2Half_InBits); 384 MIRBuilder.buildStore(Shift, Addr, *RemMemOp); 385 } else { 386 auto Unmerge = MIRBuilder.buildUnmerge(s32, Val); 387 MIRBuilder.buildStore(Unmerge.getReg(0), BaseAddr, *P2HalfMemOp); 388 MIRBuilder.buildStore(Unmerge.getReg(1), Addr, *RemMemOp); 389 } 390 } 391 392 if (MI.getOpcode() == G_LOAD) { 393 394 if (MemSize <= 4) { 395 // This is anyextending load, use 4 byte lwr/lwl. 396 auto *Load4MMO = MF.getMachineMemOperand(MMOBase, 0, 4); 397 398 if (Size == 32) 399 MIRBuilder.buildLoad(Val, BaseAddr, *Load4MMO); 400 else { 401 auto Load = MIRBuilder.buildLoad(s32, BaseAddr, *Load4MMO); 402 MIRBuilder.buildTrunc(Val, Load.getReg(0)); 403 } 404 405 } else { 406 auto C_P2HalfMemSize = MIRBuilder.buildConstant(s32, P2HalfMemSize); 407 auto Addr = MIRBuilder.buildPtrAdd(PtrTy, BaseAddr, C_P2HalfMemSize); 408 409 auto Load_P2Half = MIRBuilder.buildLoad(s32, BaseAddr, *P2HalfMemOp); 410 auto Load_Rem = MIRBuilder.buildLoad(s32, Addr, *RemMemOp); 411 412 if (Size == 64) 413 MIRBuilder.buildMerge(Val, {Load_P2Half, Load_Rem}); 414 else { 415 auto Merge = MIRBuilder.buildMerge(s64, {Load_P2Half, Load_Rem}); 416 MIRBuilder.buildTrunc(Val, Merge); 417 } 418 } 419 } 420 MI.eraseFromParent(); 421 break; 422 } 423 case G_UITOFP: { 424 Register Dst = MI.getOperand(0).getReg(); 425 Register Src = MI.getOperand(1).getReg(); 426 LLT DstTy = MRI.getType(Dst); 427 LLT SrcTy = MRI.getType(Src); 428 429 if (SrcTy != s32) 430 return false; 431 if (DstTy != s32 && DstTy != s64) 432 return false; 433 434 // Let 0xABCDEFGH be given unsigned in MI.getOperand(1). First let's convert 435 // unsigned to double. Mantissa has 52 bits so we use following trick: 436 // First make floating point bit mask 0x43300000ABCDEFGH. 437 // Mask represents 2^52 * 0x1.00000ABCDEFGH i.e. 0x100000ABCDEFGH.0 . 438 // Next, subtract 2^52 * 0x1.0000000000000 i.e. 0x10000000000000.0 from it. 439 // Done. Trunc double to float if needed. 440 441 auto C_HiMask = MIRBuilder.buildConstant(s32, UINT32_C(0x43300000)); 442 auto Bitcast = MIRBuilder.buildMerge(s64, {Src, C_HiMask.getReg(0)}); 443 444 MachineInstrBuilder TwoP52FP = MIRBuilder.buildFConstant( 445 s64, BitsToDouble(UINT64_C(0x4330000000000000))); 446 447 if (DstTy == s64) 448 MIRBuilder.buildFSub(Dst, Bitcast, TwoP52FP); 449 else { 450 MachineInstrBuilder ResF64 = MIRBuilder.buildFSub(s64, Bitcast, TwoP52FP); 451 MIRBuilder.buildFPTrunc(Dst, ResF64); 452 } 453 454 MI.eraseFromParent(); 455 break; 456 } 457 default: 458 return false; 459 } 460 461 return true; 462 } 463 464 static bool SelectMSA3OpIntrinsic(MachineInstr &MI, unsigned Opcode, 465 MachineIRBuilder &MIRBuilder, 466 const MipsSubtarget &ST) { 467 assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA."); 468 if (!MIRBuilder.buildInstr(Opcode) 469 .add(MI.getOperand(0)) 470 .add(MI.getOperand(2)) 471 .add(MI.getOperand(3)) 472 .constrainAllUses(MIRBuilder.getTII(), *ST.getRegisterInfo(), 473 *ST.getRegBankInfo())) 474 return false; 475 MI.eraseFromParent(); 476 return true; 477 } 478 479 static bool MSA3OpIntrinsicToGeneric(MachineInstr &MI, unsigned Opcode, 480 MachineIRBuilder &MIRBuilder, 481 const MipsSubtarget &ST) { 482 assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA."); 483 MIRBuilder.buildInstr(Opcode) 484 .add(MI.getOperand(0)) 485 .add(MI.getOperand(2)) 486 .add(MI.getOperand(3)); 487 MI.eraseFromParent(); 488 return true; 489 } 490 491 static bool MSA2OpIntrinsicToGeneric(MachineInstr &MI, unsigned Opcode, 492 MachineIRBuilder &MIRBuilder, 493 const MipsSubtarget &ST) { 494 assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA."); 495 MIRBuilder.buildInstr(Opcode) 496 .add(MI.getOperand(0)) 497 .add(MI.getOperand(2)); 498 MI.eraseFromParent(); 499 return true; 500 } 501 502 bool MipsLegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper, 503 MachineInstr &MI) const { 504 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder; 505 const MipsSubtarget &ST = 506 static_cast<const MipsSubtarget &>(MI.getMF()->getSubtarget()); 507 const MipsInstrInfo &TII = *ST.getInstrInfo(); 508 const MipsRegisterInfo &TRI = *ST.getRegisterInfo(); 509 const RegisterBankInfo &RBI = *ST.getRegBankInfo(); 510 511 switch (MI.getIntrinsicID()) { 512 case Intrinsic::trap: { 513 MachineInstr *Trap = MIRBuilder.buildInstr(Mips::TRAP); 514 MI.eraseFromParent(); 515 return constrainSelectedInstRegOperands(*Trap, TII, TRI, RBI); 516 } 517 case Intrinsic::vacopy: { 518 MachinePointerInfo MPO; 519 auto Tmp = 520 MIRBuilder.buildLoad(LLT::pointer(0, 32), MI.getOperand(2), 521 *MI.getMF()->getMachineMemOperand( 522 MPO, MachineMemOperand::MOLoad, 4, Align(4))); 523 MIRBuilder.buildStore(Tmp, MI.getOperand(1), 524 *MI.getMF()->getMachineMemOperand( 525 MPO, MachineMemOperand::MOStore, 4, Align(4))); 526 MI.eraseFromParent(); 527 return true; 528 } 529 case Intrinsic::mips_addv_b: 530 case Intrinsic::mips_addv_h: 531 case Intrinsic::mips_addv_w: 532 case Intrinsic::mips_addv_d: 533 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_ADD, MIRBuilder, ST); 534 case Intrinsic::mips_addvi_b: 535 return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_B, MIRBuilder, ST); 536 case Intrinsic::mips_addvi_h: 537 return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_H, MIRBuilder, ST); 538 case Intrinsic::mips_addvi_w: 539 return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_W, MIRBuilder, ST); 540 case Intrinsic::mips_addvi_d: 541 return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_D, MIRBuilder, ST); 542 case Intrinsic::mips_subv_b: 543 case Intrinsic::mips_subv_h: 544 case Intrinsic::mips_subv_w: 545 case Intrinsic::mips_subv_d: 546 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_SUB, MIRBuilder, ST); 547 case Intrinsic::mips_subvi_b: 548 return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_B, MIRBuilder, ST); 549 case Intrinsic::mips_subvi_h: 550 return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_H, MIRBuilder, ST); 551 case Intrinsic::mips_subvi_w: 552 return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_W, MIRBuilder, ST); 553 case Intrinsic::mips_subvi_d: 554 return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_D, MIRBuilder, ST); 555 case Intrinsic::mips_mulv_b: 556 case Intrinsic::mips_mulv_h: 557 case Intrinsic::mips_mulv_w: 558 case Intrinsic::mips_mulv_d: 559 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_MUL, MIRBuilder, ST); 560 case Intrinsic::mips_div_s_b: 561 case Intrinsic::mips_div_s_h: 562 case Intrinsic::mips_div_s_w: 563 case Intrinsic::mips_div_s_d: 564 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_SDIV, MIRBuilder, ST); 565 case Intrinsic::mips_mod_s_b: 566 case Intrinsic::mips_mod_s_h: 567 case Intrinsic::mips_mod_s_w: 568 case Intrinsic::mips_mod_s_d: 569 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_SREM, MIRBuilder, ST); 570 case Intrinsic::mips_div_u_b: 571 case Intrinsic::mips_div_u_h: 572 case Intrinsic::mips_div_u_w: 573 case Intrinsic::mips_div_u_d: 574 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_UDIV, MIRBuilder, ST); 575 case Intrinsic::mips_mod_u_b: 576 case Intrinsic::mips_mod_u_h: 577 case Intrinsic::mips_mod_u_w: 578 case Intrinsic::mips_mod_u_d: 579 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_UREM, MIRBuilder, ST); 580 case Intrinsic::mips_fadd_w: 581 case Intrinsic::mips_fadd_d: 582 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_FADD, MIRBuilder, ST); 583 case Intrinsic::mips_fsub_w: 584 case Intrinsic::mips_fsub_d: 585 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_FSUB, MIRBuilder, ST); 586 case Intrinsic::mips_fmul_w: 587 case Intrinsic::mips_fmul_d: 588 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_FMUL, MIRBuilder, ST); 589 case Intrinsic::mips_fdiv_w: 590 case Intrinsic::mips_fdiv_d: 591 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_FDIV, MIRBuilder, ST); 592 case Intrinsic::mips_fmax_a_w: 593 return SelectMSA3OpIntrinsic(MI, Mips::FMAX_A_W, MIRBuilder, ST); 594 case Intrinsic::mips_fmax_a_d: 595 return SelectMSA3OpIntrinsic(MI, Mips::FMAX_A_D, MIRBuilder, ST); 596 case Intrinsic::mips_fsqrt_w: 597 return MSA2OpIntrinsicToGeneric(MI, TargetOpcode::G_FSQRT, MIRBuilder, ST); 598 case Intrinsic::mips_fsqrt_d: 599 return MSA2OpIntrinsicToGeneric(MI, TargetOpcode::G_FSQRT, MIRBuilder, ST); 600 default: 601 break; 602 } 603 return true; 604 } 605