1 //===- MipsLegalizerInfo.cpp ------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements the targeting of the Machinelegalizer class for Mips. 10 /// \todo This should be generated by TableGen. 11 //===----------------------------------------------------------------------===// 12 13 #include "MipsLegalizerInfo.h" 14 #include "MipsTargetMachine.h" 15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h" 16 #include "llvm/IR/IntrinsicsMips.h" 17 18 using namespace llvm; 19 20 struct TypesAndMemOps { 21 LLT ValTy; 22 LLT PtrTy; 23 unsigned MemSize; 24 bool SystemSupportsUnalignedAccess; 25 }; 26 27 // Assumes power of 2 memory size. Subtargets that have only naturally-aligned 28 // memory access need to perform additional legalization here. 29 static bool isUnalignedMemmoryAccess(uint64_t MemSize, uint64_t AlignInBits) { 30 assert(isPowerOf2_64(MemSize) && "Expected power of 2 memory size"); 31 assert(isPowerOf2_64(AlignInBits) && "Expected power of 2 align"); 32 if (MemSize > AlignInBits) 33 return true; 34 return false; 35 } 36 37 static bool 38 CheckTy0Ty1MemSizeAlign(const LegalityQuery &Query, 39 std::initializer_list<TypesAndMemOps> SupportedValues) { 40 unsigned QueryMemSize = Query.MMODescrs[0].SizeInBits; 41 42 // Non power of two memory access is never legal. 43 if (!isPowerOf2_64(QueryMemSize)) 44 return false; 45 46 for (auto &Val : SupportedValues) { 47 if (Val.ValTy != Query.Types[0]) 48 continue; 49 if (Val.PtrTy != Query.Types[1]) 50 continue; 51 if (Val.MemSize != QueryMemSize) 52 continue; 53 if (!Val.SystemSupportsUnalignedAccess && 54 isUnalignedMemmoryAccess(QueryMemSize, Query.MMODescrs[0].AlignInBits)) 55 return false; 56 return true; 57 } 58 return false; 59 } 60 61 static bool CheckTyN(unsigned N, const LegalityQuery &Query, 62 std::initializer_list<LLT> SupportedValues) { 63 for (auto &Val : SupportedValues) 64 if (Val == Query.Types[N]) 65 return true; 66 return false; 67 } 68 69 MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) { 70 using namespace TargetOpcode; 71 72 const LLT s1 = LLT::scalar(1); 73 const LLT s32 = LLT::scalar(32); 74 const LLT s64 = LLT::scalar(64); 75 const LLT v16s8 = LLT::vector(16, 8); 76 const LLT v8s16 = LLT::vector(8, 16); 77 const LLT v4s32 = LLT::vector(4, 32); 78 const LLT v2s64 = LLT::vector(2, 64); 79 const LLT p0 = LLT::pointer(0, 32); 80 81 getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL}) 82 .legalIf([=, &ST](const LegalityQuery &Query) { 83 if (CheckTyN(0, Query, {s32})) 84 return true; 85 if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64})) 86 return true; 87 return false; 88 }) 89 .clampScalar(0, s32, s32); 90 91 getActionDefinitionsBuilder({G_UADDO, G_UADDE, G_USUBO, G_USUBE, G_UMULO}) 92 .lowerFor({{s32, s1}}); 93 94 getActionDefinitionsBuilder(G_UMULH) 95 .legalFor({s32}) 96 .maxScalar(0, s32); 97 98 // MIPS32r6 does not have alignment restrictions for memory access. 99 // For MIPS32r5 and older memory access must be naturally-aligned i.e. aligned 100 // to at least a multiple of its own size. There is however a two instruction 101 // combination that performs 4 byte unaligned access (lwr/lwl and swl/swr) 102 // therefore 4 byte load and store are legal and will use NoAlignRequirements. 103 bool NoAlignRequirements = true; 104 105 getActionDefinitionsBuilder({G_LOAD, G_STORE}) 106 .legalIf([=, &ST](const LegalityQuery &Query) { 107 if (CheckTy0Ty1MemSizeAlign( 108 Query, {{s32, p0, 8, NoAlignRequirements}, 109 {s32, p0, 16, ST.systemSupportsUnalignedAccess()}, 110 {s32, p0, 32, NoAlignRequirements}, 111 {p0, p0, 32, NoAlignRequirements}, 112 {s64, p0, 64, ST.systemSupportsUnalignedAccess()}})) 113 return true; 114 if (ST.hasMSA() && CheckTy0Ty1MemSizeAlign( 115 Query, {{v16s8, p0, 128, NoAlignRequirements}, 116 {v8s16, p0, 128, NoAlignRequirements}, 117 {v4s32, p0, 128, NoAlignRequirements}, 118 {v2s64, p0, 128, NoAlignRequirements}})) 119 return true; 120 return false; 121 }) 122 // Custom lower scalar memory access, up to 8 bytes, for: 123 // - non-power-of-2 MemSizes 124 // - unaligned 2 or 8 byte MemSizes for MIPS32r5 and older 125 .customIf([=, &ST](const LegalityQuery &Query) { 126 if (!Query.Types[0].isScalar() || Query.Types[1] != p0 || 127 Query.Types[0] == s1) 128 return false; 129 130 unsigned Size = Query.Types[0].getSizeInBits(); 131 unsigned QueryMemSize = Query.MMODescrs[0].SizeInBits; 132 assert(QueryMemSize <= Size && "Scalar can't hold MemSize"); 133 134 if (Size > 64 || QueryMemSize > 64) 135 return false; 136 137 if (!isPowerOf2_64(Query.MMODescrs[0].SizeInBits)) 138 return true; 139 140 if (!ST.systemSupportsUnalignedAccess() && 141 isUnalignedMemmoryAccess(QueryMemSize, 142 Query.MMODescrs[0].AlignInBits)) { 143 assert(QueryMemSize != 32 && "4 byte load and store are legal"); 144 return true; 145 } 146 147 return false; 148 }) 149 .minScalar(0, s32); 150 151 getActionDefinitionsBuilder(G_IMPLICIT_DEF) 152 .legalFor({s32, s64}); 153 154 getActionDefinitionsBuilder(G_UNMERGE_VALUES) 155 .legalFor({{s32, s64}}); 156 157 getActionDefinitionsBuilder(G_MERGE_VALUES) 158 .legalFor({{s64, s32}}); 159 160 getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD}) 161 .legalForTypesWithMemDesc({{s32, p0, 8, 8}, 162 {s32, p0, 16, 8}}) 163 .clampScalar(0, s32, s32); 164 165 getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT}) 166 .legalIf([](const LegalityQuery &Query) { return false; }) 167 .maxScalar(0, s32); 168 169 getActionDefinitionsBuilder(G_TRUNC) 170 .legalIf([](const LegalityQuery &Query) { return false; }) 171 .maxScalar(1, s32); 172 173 getActionDefinitionsBuilder(G_SELECT) 174 .legalForCartesianProduct({p0, s32, s64}, {s32}) 175 .minScalar(0, s32) 176 .minScalar(1, s32); 177 178 getActionDefinitionsBuilder(G_BRCOND) 179 .legalFor({s32}) 180 .minScalar(0, s32); 181 182 getActionDefinitionsBuilder(G_BRJT) 183 .legalFor({{p0, s32}}); 184 185 getActionDefinitionsBuilder(G_BRINDIRECT) 186 .legalFor({p0}); 187 188 getActionDefinitionsBuilder(G_PHI) 189 .legalFor({p0, s32, s64}) 190 .minScalar(0, s32); 191 192 getActionDefinitionsBuilder({G_AND, G_OR, G_XOR}) 193 .legalFor({s32}) 194 .clampScalar(0, s32, s32); 195 196 getActionDefinitionsBuilder({G_SDIV, G_SREM, G_UDIV, G_UREM}) 197 .legalIf([=, &ST](const LegalityQuery &Query) { 198 if (CheckTyN(0, Query, {s32})) 199 return true; 200 if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64})) 201 return true; 202 return false; 203 }) 204 .minScalar(0, s32) 205 .libcallFor({s64}); 206 207 getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR}) 208 .legalFor({{s32, s32}}) 209 .clampScalar(1, s32, s32) 210 .clampScalar(0, s32, s32); 211 212 getActionDefinitionsBuilder(G_ICMP) 213 .legalForCartesianProduct({s32}, {s32, p0}) 214 .clampScalar(1, s32, s32) 215 .minScalar(0, s32); 216 217 getActionDefinitionsBuilder(G_CONSTANT) 218 .legalFor({s32}) 219 .clampScalar(0, s32, s32); 220 221 getActionDefinitionsBuilder({G_PTR_ADD, G_INTTOPTR}) 222 .legalFor({{p0, s32}}); 223 224 getActionDefinitionsBuilder(G_PTRTOINT) 225 .legalFor({{s32, p0}}); 226 227 getActionDefinitionsBuilder(G_FRAME_INDEX) 228 .legalFor({p0}); 229 230 getActionDefinitionsBuilder({G_GLOBAL_VALUE, G_JUMP_TABLE}) 231 .legalFor({p0}); 232 233 getActionDefinitionsBuilder(G_DYN_STACKALLOC) 234 .lowerFor({{p0, s32}}); 235 236 getActionDefinitionsBuilder(G_VASTART) 237 .legalFor({p0}); 238 239 getActionDefinitionsBuilder(G_BSWAP) 240 .legalIf([=, &ST](const LegalityQuery &Query) { 241 if (ST.hasMips32r2() && CheckTyN(0, Query, {s32})) 242 return true; 243 return false; 244 }) 245 .lowerIf([=, &ST](const LegalityQuery &Query) { 246 if (!ST.hasMips32r2() && CheckTyN(0, Query, {s32})) 247 return true; 248 return false; 249 }) 250 .maxScalar(0, s32); 251 252 getActionDefinitionsBuilder(G_BITREVERSE) 253 .lowerFor({s32}) 254 .maxScalar(0, s32); 255 256 getActionDefinitionsBuilder(G_CTLZ) 257 .legalFor({{s32, s32}}) 258 .maxScalar(0, s32) 259 .maxScalar(1, s32); 260 getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF) 261 .lowerFor({{s32, s32}}); 262 263 getActionDefinitionsBuilder(G_CTTZ) 264 .lowerFor({{s32, s32}}) 265 .maxScalar(0, s32) 266 .maxScalar(1, s32); 267 getActionDefinitionsBuilder(G_CTTZ_ZERO_UNDEF) 268 .lowerFor({{s32, s32}, {s64, s64}}); 269 270 getActionDefinitionsBuilder(G_CTPOP) 271 .lowerFor({{s32, s32}}) 272 .clampScalar(0, s32, s32) 273 .clampScalar(1, s32, s32); 274 275 // FP instructions 276 getActionDefinitionsBuilder(G_FCONSTANT) 277 .legalFor({s32, s64}); 278 279 getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FABS, G_FSQRT}) 280 .legalIf([=, &ST](const LegalityQuery &Query) { 281 if (CheckTyN(0, Query, {s32, s64})) 282 return true; 283 if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64})) 284 return true; 285 return false; 286 }); 287 288 getActionDefinitionsBuilder(G_FCMP) 289 .legalFor({{s32, s32}, {s32, s64}}) 290 .minScalar(0, s32); 291 292 getActionDefinitionsBuilder({G_FCEIL, G_FFLOOR}) 293 .libcallFor({s32, s64}); 294 295 getActionDefinitionsBuilder(G_FPEXT) 296 .legalFor({{s64, s32}}); 297 298 getActionDefinitionsBuilder(G_FPTRUNC) 299 .legalFor({{s32, s64}}); 300 301 // FP to int conversion instructions 302 getActionDefinitionsBuilder(G_FPTOSI) 303 .legalForCartesianProduct({s32}, {s64, s32}) 304 .libcallForCartesianProduct({s64}, {s64, s32}) 305 .minScalar(0, s32); 306 307 getActionDefinitionsBuilder(G_FPTOUI) 308 .libcallForCartesianProduct({s64}, {s64, s32}) 309 .lowerForCartesianProduct({s32}, {s64, s32}) 310 .minScalar(0, s32); 311 312 // Int to FP conversion instructions 313 getActionDefinitionsBuilder(G_SITOFP) 314 .legalForCartesianProduct({s64, s32}, {s32}) 315 .libcallForCartesianProduct({s64, s32}, {s64}) 316 .minScalar(1, s32); 317 318 getActionDefinitionsBuilder(G_UITOFP) 319 .libcallForCartesianProduct({s64, s32}, {s64}) 320 .customForCartesianProduct({s64, s32}, {s32}) 321 .minScalar(1, s32); 322 323 getActionDefinitionsBuilder(G_SEXT_INREG).lower(); 324 325 computeTables(); 326 verify(*ST.getInstrInfo()); 327 } 328 329 bool MipsLegalizerInfo::legalizeCustom(LegalizerHelper &Helper, 330 MachineInstr &MI) const { 331 using namespace TargetOpcode; 332 333 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder; 334 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); 335 336 const LLT s32 = LLT::scalar(32); 337 const LLT s64 = LLT::scalar(64); 338 339 switch (MI.getOpcode()) { 340 case G_LOAD: 341 case G_STORE: { 342 unsigned MemSize = (**MI.memoperands_begin()).getSize(); 343 Register Val = MI.getOperand(0).getReg(); 344 unsigned Size = MRI.getType(Val).getSizeInBits(); 345 346 MachineMemOperand *MMOBase = *MI.memoperands_begin(); 347 348 assert(MemSize <= 8 && "MemSize is too large"); 349 assert(Size <= 64 && "Scalar size is too large"); 350 351 // Split MemSize into two, P2HalfMemSize is largest power of two smaller 352 // then MemSize. e.g. 8 = 4 + 4 , 6 = 4 + 2, 3 = 2 + 1. 353 unsigned P2HalfMemSize, RemMemSize; 354 if (isPowerOf2_64(MemSize)) { 355 P2HalfMemSize = RemMemSize = MemSize / 2; 356 } else { 357 P2HalfMemSize = 1 << Log2_32(MemSize); 358 RemMemSize = MemSize - P2HalfMemSize; 359 } 360 361 Register BaseAddr = MI.getOperand(1).getReg(); 362 LLT PtrTy = MRI.getType(BaseAddr); 363 MachineFunction &MF = MIRBuilder.getMF(); 364 365 auto P2HalfMemOp = MF.getMachineMemOperand(MMOBase, 0, P2HalfMemSize); 366 auto RemMemOp = MF.getMachineMemOperand(MMOBase, P2HalfMemSize, RemMemSize); 367 368 if (MI.getOpcode() == G_STORE) { 369 // Widen Val to s32 or s64 in order to create legal G_LSHR or G_UNMERGE. 370 if (Size < 32) 371 Val = MIRBuilder.buildAnyExt(s32, Val).getReg(0); 372 if (Size > 32 && Size < 64) 373 Val = MIRBuilder.buildAnyExt(s64, Val).getReg(0); 374 375 auto C_P2HalfMemSize = MIRBuilder.buildConstant(s32, P2HalfMemSize); 376 auto Addr = MIRBuilder.buildPtrAdd(PtrTy, BaseAddr, C_P2HalfMemSize); 377 378 if (MI.getOpcode() == G_STORE && MemSize <= 4) { 379 MIRBuilder.buildStore(Val, BaseAddr, *P2HalfMemOp); 380 auto C_P2Half_InBits = MIRBuilder.buildConstant(s32, P2HalfMemSize * 8); 381 auto Shift = MIRBuilder.buildLShr(s32, Val, C_P2Half_InBits); 382 MIRBuilder.buildStore(Shift, Addr, *RemMemOp); 383 } else { 384 auto Unmerge = MIRBuilder.buildUnmerge(s32, Val); 385 MIRBuilder.buildStore(Unmerge.getReg(0), BaseAddr, *P2HalfMemOp); 386 MIRBuilder.buildStore(Unmerge.getReg(1), Addr, *RemMemOp); 387 } 388 } 389 390 if (MI.getOpcode() == G_LOAD) { 391 392 if (MemSize <= 4) { 393 // This is anyextending load, use 4 byte lwr/lwl. 394 auto *Load4MMO = MF.getMachineMemOperand(MMOBase, 0, 4); 395 396 if (Size == 32) 397 MIRBuilder.buildLoad(Val, BaseAddr, *Load4MMO); 398 else { 399 auto Load = MIRBuilder.buildLoad(s32, BaseAddr, *Load4MMO); 400 MIRBuilder.buildTrunc(Val, Load.getReg(0)); 401 } 402 403 } else { 404 auto C_P2HalfMemSize = MIRBuilder.buildConstant(s32, P2HalfMemSize); 405 auto Addr = MIRBuilder.buildPtrAdd(PtrTy, BaseAddr, C_P2HalfMemSize); 406 407 auto Load_P2Half = MIRBuilder.buildLoad(s32, BaseAddr, *P2HalfMemOp); 408 auto Load_Rem = MIRBuilder.buildLoad(s32, Addr, *RemMemOp); 409 410 if (Size == 64) 411 MIRBuilder.buildMerge(Val, {Load_P2Half, Load_Rem}); 412 else { 413 auto Merge = MIRBuilder.buildMerge(s64, {Load_P2Half, Load_Rem}); 414 MIRBuilder.buildTrunc(Val, Merge); 415 } 416 } 417 } 418 MI.eraseFromParent(); 419 break; 420 } 421 case G_UITOFP: { 422 Register Dst = MI.getOperand(0).getReg(); 423 Register Src = MI.getOperand(1).getReg(); 424 LLT DstTy = MRI.getType(Dst); 425 LLT SrcTy = MRI.getType(Src); 426 427 if (SrcTy != s32) 428 return false; 429 if (DstTy != s32 && DstTy != s64) 430 return false; 431 432 // Let 0xABCDEFGH be given unsigned in MI.getOperand(1). First let's convert 433 // unsigned to double. Mantissa has 52 bits so we use following trick: 434 // First make floating point bit mask 0x43300000ABCDEFGH. 435 // Mask represents 2^52 * 0x1.00000ABCDEFGH i.e. 0x100000ABCDEFGH.0 . 436 // Next, subtract 2^52 * 0x1.0000000000000 i.e. 0x10000000000000.0 from it. 437 // Done. Trunc double to float if needed. 438 439 auto C_HiMask = MIRBuilder.buildConstant(s32, UINT32_C(0x43300000)); 440 auto Bitcast = MIRBuilder.buildMerge(s64, {Src, C_HiMask.getReg(0)}); 441 442 MachineInstrBuilder TwoP52FP = MIRBuilder.buildFConstant( 443 s64, BitsToDouble(UINT64_C(0x4330000000000000))); 444 445 if (DstTy == s64) 446 MIRBuilder.buildFSub(Dst, Bitcast, TwoP52FP); 447 else { 448 MachineInstrBuilder ResF64 = MIRBuilder.buildFSub(s64, Bitcast, TwoP52FP); 449 MIRBuilder.buildFPTrunc(Dst, ResF64); 450 } 451 452 MI.eraseFromParent(); 453 break; 454 } 455 default: 456 return false; 457 } 458 459 return true; 460 } 461 462 static bool SelectMSA3OpIntrinsic(MachineInstr &MI, unsigned Opcode, 463 MachineIRBuilder &MIRBuilder, 464 const MipsSubtarget &ST) { 465 assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA."); 466 if (!MIRBuilder.buildInstr(Opcode) 467 .add(MI.getOperand(0)) 468 .add(MI.getOperand(2)) 469 .add(MI.getOperand(3)) 470 .constrainAllUses(MIRBuilder.getTII(), *ST.getRegisterInfo(), 471 *ST.getRegBankInfo())) 472 return false; 473 MI.eraseFromParent(); 474 return true; 475 } 476 477 static bool MSA3OpIntrinsicToGeneric(MachineInstr &MI, unsigned Opcode, 478 MachineIRBuilder &MIRBuilder, 479 const MipsSubtarget &ST) { 480 assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA."); 481 MIRBuilder.buildInstr(Opcode) 482 .add(MI.getOperand(0)) 483 .add(MI.getOperand(2)) 484 .add(MI.getOperand(3)); 485 MI.eraseFromParent(); 486 return true; 487 } 488 489 static bool MSA2OpIntrinsicToGeneric(MachineInstr &MI, unsigned Opcode, 490 MachineIRBuilder &MIRBuilder, 491 const MipsSubtarget &ST) { 492 assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA."); 493 MIRBuilder.buildInstr(Opcode) 494 .add(MI.getOperand(0)) 495 .add(MI.getOperand(2)); 496 MI.eraseFromParent(); 497 return true; 498 } 499 500 bool MipsLegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper, 501 MachineInstr &MI) const { 502 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder; 503 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); 504 const MipsSubtarget &ST = 505 static_cast<const MipsSubtarget &>(MI.getMF()->getSubtarget()); 506 const MipsInstrInfo &TII = *ST.getInstrInfo(); 507 const MipsRegisterInfo &TRI = *ST.getRegisterInfo(); 508 const RegisterBankInfo &RBI = *ST.getRegBankInfo(); 509 510 switch (MI.getIntrinsicID()) { 511 case Intrinsic::memcpy: 512 case Intrinsic::memset: 513 case Intrinsic::memmove: 514 if (createMemLibcall(MIRBuilder, MRI, MI) == 515 LegalizerHelper::UnableToLegalize) 516 return false; 517 MI.eraseFromParent(); 518 return true; 519 case Intrinsic::trap: { 520 MachineInstr *Trap = MIRBuilder.buildInstr(Mips::TRAP); 521 MI.eraseFromParent(); 522 return constrainSelectedInstRegOperands(*Trap, TII, TRI, RBI); 523 } 524 case Intrinsic::vacopy: { 525 MachinePointerInfo MPO; 526 auto Tmp = 527 MIRBuilder.buildLoad(LLT::pointer(0, 32), MI.getOperand(2), 528 *MI.getMF()->getMachineMemOperand( 529 MPO, MachineMemOperand::MOLoad, 4, Align(4))); 530 MIRBuilder.buildStore(Tmp, MI.getOperand(1), 531 *MI.getMF()->getMachineMemOperand( 532 MPO, MachineMemOperand::MOStore, 4, Align(4))); 533 MI.eraseFromParent(); 534 return true; 535 } 536 case Intrinsic::mips_addv_b: 537 case Intrinsic::mips_addv_h: 538 case Intrinsic::mips_addv_w: 539 case Intrinsic::mips_addv_d: 540 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_ADD, MIRBuilder, ST); 541 case Intrinsic::mips_addvi_b: 542 return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_B, MIRBuilder, ST); 543 case Intrinsic::mips_addvi_h: 544 return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_H, MIRBuilder, ST); 545 case Intrinsic::mips_addvi_w: 546 return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_W, MIRBuilder, ST); 547 case Intrinsic::mips_addvi_d: 548 return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_D, MIRBuilder, ST); 549 case Intrinsic::mips_subv_b: 550 case Intrinsic::mips_subv_h: 551 case Intrinsic::mips_subv_w: 552 case Intrinsic::mips_subv_d: 553 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_SUB, MIRBuilder, ST); 554 case Intrinsic::mips_subvi_b: 555 return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_B, MIRBuilder, ST); 556 case Intrinsic::mips_subvi_h: 557 return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_H, MIRBuilder, ST); 558 case Intrinsic::mips_subvi_w: 559 return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_W, MIRBuilder, ST); 560 case Intrinsic::mips_subvi_d: 561 return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_D, MIRBuilder, ST); 562 case Intrinsic::mips_mulv_b: 563 case Intrinsic::mips_mulv_h: 564 case Intrinsic::mips_mulv_w: 565 case Intrinsic::mips_mulv_d: 566 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_MUL, MIRBuilder, ST); 567 case Intrinsic::mips_div_s_b: 568 case Intrinsic::mips_div_s_h: 569 case Intrinsic::mips_div_s_w: 570 case Intrinsic::mips_div_s_d: 571 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_SDIV, MIRBuilder, ST); 572 case Intrinsic::mips_mod_s_b: 573 case Intrinsic::mips_mod_s_h: 574 case Intrinsic::mips_mod_s_w: 575 case Intrinsic::mips_mod_s_d: 576 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_SREM, MIRBuilder, ST); 577 case Intrinsic::mips_div_u_b: 578 case Intrinsic::mips_div_u_h: 579 case Intrinsic::mips_div_u_w: 580 case Intrinsic::mips_div_u_d: 581 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_UDIV, MIRBuilder, ST); 582 case Intrinsic::mips_mod_u_b: 583 case Intrinsic::mips_mod_u_h: 584 case Intrinsic::mips_mod_u_w: 585 case Intrinsic::mips_mod_u_d: 586 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_UREM, MIRBuilder, ST); 587 case Intrinsic::mips_fadd_w: 588 case Intrinsic::mips_fadd_d: 589 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_FADD, MIRBuilder, ST); 590 case Intrinsic::mips_fsub_w: 591 case Intrinsic::mips_fsub_d: 592 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_FSUB, MIRBuilder, ST); 593 case Intrinsic::mips_fmul_w: 594 case Intrinsic::mips_fmul_d: 595 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_FMUL, MIRBuilder, ST); 596 case Intrinsic::mips_fdiv_w: 597 case Intrinsic::mips_fdiv_d: 598 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_FDIV, MIRBuilder, ST); 599 case Intrinsic::mips_fmax_a_w: 600 return SelectMSA3OpIntrinsic(MI, Mips::FMAX_A_W, MIRBuilder, ST); 601 case Intrinsic::mips_fmax_a_d: 602 return SelectMSA3OpIntrinsic(MI, Mips::FMAX_A_D, MIRBuilder, ST); 603 case Intrinsic::mips_fsqrt_w: 604 return MSA2OpIntrinsicToGeneric(MI, TargetOpcode::G_FSQRT, MIRBuilder, ST); 605 case Intrinsic::mips_fsqrt_d: 606 return MSA2OpIntrinsicToGeneric(MI, TargetOpcode::G_FSQRT, MIRBuilder, ST); 607 default: 608 break; 609 } 610 return true; 611 } 612