1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file contains the Mips implementation of the TargetInstrInfo class. 10// 11//===----------------------------------------------------------------------===// 12 13 14//===----------------------------------------------------------------------===// 15// Mips profiles and nodes 16//===----------------------------------------------------------------------===// 17 18def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 19def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 20 SDTCisSameAs<1, 2>, 21 SDTCisSameAs<3, 4>, 22 SDTCisInt<4>]>; 23def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 24def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 25def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>; 26def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 27 SDTCisInt<1>, SDTCisSameAs<1, 2>]>; 28def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>, 29 SDTCisSameAs<1, 2>]>; 30def SDT_MipsMAddMSub : SDTypeProfile<1, 3, 31 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, 32 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 33def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 34 35def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 36 37def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 38 39def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 40 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 41def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 42 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 43 SDTCisSameAs<0, 4>]>; 44 45def SDTMipsLoadLR : SDTypeProfile<1, 2, 46 [SDTCisInt<0>, SDTCisPtrTy<1>, 47 SDTCisSameAs<0, 2>]>; 48 49// Call 50def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 51 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 52 SDNPVariadic]>; 53 54// Tail call 55def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 56 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 57 58// Hi and Lo nodes are used to handle global addresses. Used on 59// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 60// static model. (nothing to do with Mips Registers Hi and Lo) 61 62// Hi is the odd node out, on MIPS64 it can expand to either daddiu when 63// using static relocations with 64 bit symbols, or lui when using 32 bit 64// symbols. 65def MipsHigher : SDNode<"MipsISD::Higher", SDTIntUnaryOp>; 66def MipsHighest : SDNode<"MipsISD::Highest", SDTIntUnaryOp>; 67def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 68def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 69 70def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 71 72// Hi node for accessing the GOT. 73def MipsGotHi : SDNode<"MipsISD::GotHi", SDTIntUnaryOp>; 74 75// Hi node for handling TLS offsets 76def MipsTlsHi : SDNode<"MipsISD::TlsHi", SDTIntUnaryOp>; 77 78// Thread pointer 79def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 80 81// Return 82def MipsRet : SDNode<"MipsISD::Ret", SDTNone, 83 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 84 85def MipsERet : SDNode<"MipsISD::ERet", SDTNone, 86 [SDNPHasChain, SDNPOptInGlue, SDNPSideEffect]>; 87 88// These are target-independent nodes, but have target-specific formats. 89def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 90 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 91def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 92 [SDNPHasChain, SDNPSideEffect, 93 SDNPOptInGlue, SDNPOutGlue]>; 94 95// Nodes used to extract LO/HI registers. 96def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>; 97def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>; 98 99// Node used to insert 32-bit integers to LOHI register pair. 100def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>; 101 102// Mult nodes. 103def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>; 104def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>; 105 106// MAdd*/MSub* nodes 107def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>; 108def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>; 109def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>; 110def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>; 111 112// DivRem(u) nodes 113def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>; 114def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>; 115def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16, 116 [SDNPOutGlue]>; 117def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16, 118 [SDNPOutGlue]>; 119 120// Target constant nodes that are not part of any isel patterns and remain 121// unchanged can cause instructions with illegal operands to be emitted. 122// Wrapper node patterns give the instruction selector a chance to replace 123// target constant nodes that would otherwise remain unchanged with ADDiu 124// nodes. Without these wrapper node patterns, the following conditional move 125// instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 126// compiled: 127// movn %got(d)($gp), %got(c)($gp), $4 128// This instruction is illegal since movn can take only register operands. 129 130def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 131 132def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 133 134def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 135def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 136def MipsCIns : SDNode<"MipsISD::CIns", SDT_Ext>; 137 138def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 139 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 140def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 141 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 142def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 143 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 144def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 145 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 146def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 147 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 148def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 149 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 150def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 151 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 152def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 153 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 154 155//===----------------------------------------------------------------------===// 156// Mips Instruction Predicate Definitions. 157//===----------------------------------------------------------------------===// 158def HasMips2 : Predicate<"Subtarget->hasMips2()">, 159 AssemblerPredicate<"FeatureMips2">; 160def HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">, 161 AssemblerPredicate<"FeatureMips3_32">; 162def HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">, 163 AssemblerPredicate<"FeatureMips3_32r2">; 164def HasMips3 : Predicate<"Subtarget->hasMips3()">, 165 AssemblerPredicate<"FeatureMips3">; 166def NotMips3 : Predicate<"!Subtarget->hasMips3()">, 167 AssemblerPredicate<"!FeatureMips3">; 168def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">, 169 AssemblerPredicate<"FeatureMips4_32">; 170def NotMips4_32 : Predicate<"!Subtarget->hasMips4_32()">, 171 AssemblerPredicate<"!FeatureMips4_32">; 172def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">, 173 AssemblerPredicate<"FeatureMips4_32r2">; 174def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">, 175 AssemblerPredicate<"FeatureMips5_32r2">; 176def HasMips32 : Predicate<"Subtarget->hasMips32()">, 177 AssemblerPredicate<"FeatureMips32">; 178def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">, 179 AssemblerPredicate<"FeatureMips32r2">; 180def HasMips32r5 : Predicate<"Subtarget->hasMips32r5()">, 181 AssemblerPredicate<"FeatureMips32r5">; 182def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">, 183 AssemblerPredicate<"FeatureMips32r6">; 184def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">, 185 AssemblerPredicate<"!FeatureMips32r6">; 186def IsGP64bit : Predicate<"Subtarget->isGP64bit()">, 187 AssemblerPredicate<"FeatureGP64Bit">; 188def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">, 189 AssemblerPredicate<"!FeatureGP64Bit">; 190def IsPTR64bit : Predicate<"Subtarget->isABI_N64()">, 191 AssemblerPredicate<"FeaturePTR64Bit">; 192def IsPTR32bit : Predicate<"!Subtarget->isABI_N64()">, 193 AssemblerPredicate<"!FeaturePTR64Bit">; 194def HasMips64 : Predicate<"Subtarget->hasMips64()">, 195 AssemblerPredicate<"FeatureMips64">; 196def NotMips64 : Predicate<"!Subtarget->hasMips64()">, 197 AssemblerPredicate<"!FeatureMips64">; 198def HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">, 199 AssemblerPredicate<"FeatureMips64r2">; 200def HasMips64r5 : Predicate<"Subtarget->hasMips64r5()">, 201 AssemblerPredicate<"FeatureMips64r5">; 202def HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">, 203 AssemblerPredicate<"FeatureMips64r6">; 204def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">, 205 AssemblerPredicate<"!FeatureMips64r6">; 206def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">, 207 AssemblerPredicate<"FeatureMips16">; 208def NotInMips16Mode : Predicate<"!Subtarget->inMips16Mode()">, 209 AssemblerPredicate<"!FeatureMips16">; 210def HasCnMips : Predicate<"Subtarget->hasCnMips()">, 211 AssemblerPredicate<"FeatureCnMips">; 212def NotCnMips : Predicate<"!Subtarget->hasCnMips()">, 213 AssemblerPredicate<"!FeatureCnMips">; 214def HasCnMipsP : Predicate<"Subtarget->hasCnMipsP()">, 215 AssemblerPredicate<"FeatureCnMipsP">; 216def NotCnMipsP : Predicate<"!Subtarget->hasCnMipsP()">, 217 AssemblerPredicate<"!FeatureCnMipsP">; 218def IsSym32 : Predicate<"Subtarget->hasSym32()">, 219 AssemblerPredicate<"FeatureSym32">; 220def IsSym64 : Predicate<"!Subtarget->hasSym32()">, 221 AssemblerPredicate<"!FeatureSym32">; 222def IsN64 : Predicate<"Subtarget->isABI_N64()">; 223def IsNotN64 : Predicate<"!Subtarget->isABI_N64()">; 224def RelocNotPIC : Predicate<"!TM.isPositionIndependent()">; 225def RelocPIC : Predicate<"TM.isPositionIndependent()">; 226def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">; 227def UseAbs : Predicate<"Subtarget->inAbs2008Mode() ||" 228 "TM.Options.NoNaNsFPMath">; 229def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">, 230 AssemblerPredicate<"!FeatureMips16">; 231def NotDSP : Predicate<"!Subtarget->hasDSP()">; 232def InMicroMips : Predicate<"Subtarget->inMicroMipsMode()">, 233 AssemblerPredicate<"FeatureMicroMips">; 234def NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">, 235 AssemblerPredicate<"!FeatureMicroMips">; 236def IsLE : Predicate<"Subtarget->isLittle()">; 237def IsBE : Predicate<"!Subtarget->isLittle()">; 238def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; 239def UseTCCInDIV : AssemblerPredicate<"FeatureUseTCCInDIV">; 240def HasEVA : Predicate<"Subtarget->hasEVA()">, 241 AssemblerPredicate<"FeatureEVA">; 242def HasMSA : Predicate<"Subtarget->hasMSA()">, 243 AssemblerPredicate<"FeatureMSA">; 244def HasMadd4 : Predicate<"!Subtarget->disableMadd4()">, 245 AssemblerPredicate<"!FeatureMadd4">; 246def HasMT : Predicate<"Subtarget->hasMT()">, 247 AssemblerPredicate<"FeatureMT">; 248def UseIndirectJumpsHazard : Predicate<"Subtarget->useIndirectJumpsHazard()">, 249 AssemblerPredicate<"FeatureUseIndirectJumpsHazard">; 250def NoIndirectJumpGuards : Predicate<"!Subtarget->useIndirectJumpsHazard()">, 251 AssemblerPredicate<"!FeatureUseIndirectJumpsHazard">; 252def HasCRC : Predicate<"Subtarget->hasCRC()">, 253 AssemblerPredicate<"FeatureCRC">; 254def HasVirt : Predicate<"Subtarget->hasVirt()">, 255 AssemblerPredicate<"FeatureVirt">; 256def HasGINV : Predicate<"Subtarget->hasGINV()">, 257 AssemblerPredicate<"FeatureGINV">; 258// TODO: Add support for FPOpFusion::Standard 259def AllowFPOpFusion : Predicate<"TM.Options.AllowFPOpFusion ==" 260 " FPOpFusion::Fast">; 261//===----------------------------------------------------------------------===// 262// Mips GPR size adjectives. 263// They are mutually exclusive. 264//===----------------------------------------------------------------------===// 265 266class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; } 267class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; } 268 269class PTR_32 { list<Predicate> PTRPredicates = [IsPTR32bit]; } 270class PTR_64 { list<Predicate> PTRPredicates = [IsPTR64bit]; } 271 272//===----------------------------------------------------------------------===// 273// Mips Symbol size adjectives. 274// They are mutally exculsive. 275//===----------------------------------------------------------------------===// 276 277class SYM_32 { list<Predicate> SYMPredicates = [IsSym32]; } 278class SYM_64 { list<Predicate> SYMPredicates = [IsSym64]; } 279 280//===----------------------------------------------------------------------===// 281// Mips ISA/ASE membership and instruction group membership adjectives. 282// They are mutually exclusive. 283//===----------------------------------------------------------------------===// 284 285// FIXME: I'd prefer to use additive predicates to build the instruction sets 286// but we are short on assembler feature bits at the moment. Using a 287// subtractive predicate will hopefully keep us under the 32 predicate 288// limit long enough to develop an alternative way to handle P1||P2 289// predicates. 290class ISA_MIPS1 { 291 list<Predicate> EncodingPredicates = [HasStdEnc]; 292} 293class ISA_MIPS1_NOT_MIPS3 { 294 list<Predicate> InsnPredicates = [NotMips3]; 295 list<Predicate> EncodingPredicates = [HasStdEnc]; 296} 297class ISA_MIPS1_NOT_4_32 { 298 list<Predicate> InsnPredicates = [NotMips4_32]; 299 list<Predicate> EncodingPredicates = [HasStdEnc]; 300} 301class ISA_MIPS1_NOT_32R6_64R6 { 302 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6]; 303 list<Predicate> EncodingPredicates = [HasStdEnc]; 304} 305class ISA_MIPS2 { 306 list<Predicate> InsnPredicates = [HasMips2]; 307 list<Predicate> EncodingPredicates = [HasStdEnc]; 308} 309class ISA_MIPS2_NOT_32R6_64R6 { 310 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6]; 311 list<Predicate> EncodingPredicates = [HasStdEnc]; 312} 313class ISA_MIPS3 { 314 list<Predicate> InsnPredicates = [HasMips3]; 315 list<Predicate> EncodingPredicates = [HasStdEnc]; 316} 317class ISA_MIPS3_NOT_32R6_64R6 { 318 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6]; 319 list<Predicate> EncodingPredicates = [HasStdEnc]; 320} 321class ISA_MIPS32 { 322 list<Predicate> InsnPredicates = [HasMips32]; 323 list<Predicate> EncodingPredicates = [HasStdEnc]; 324} 325class ISA_MIPS32_NOT_32R6_64R6 { 326 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6]; 327 list<Predicate> EncodingPredicates = [HasStdEnc]; 328} 329class ISA_MIPS32R2 { 330 list<Predicate> InsnPredicates = [HasMips32r2]; 331 list<Predicate> EncodingPredicates = [HasStdEnc]; 332} 333class ISA_MIPS32R2_NOT_32R6_64R6 { 334 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6]; 335 list<Predicate> EncodingPredicates = [HasStdEnc]; 336} 337class ISA_MIPS32R5 { 338 list<Predicate> InsnPredicates = [HasMips32r5]; 339 list<Predicate> EncodingPredicates = [HasStdEnc]; 340} 341class ISA_MIPS64 { 342 list<Predicate> InsnPredicates = [HasMips64]; 343 list<Predicate> EncodingPredicates = [HasStdEnc]; 344} 345class ISA_MIPS64_NOT_64R6 { 346 list<Predicate> InsnPredicates = [HasMips64, NotMips64r6]; 347 list<Predicate> EncodingPredicates = [HasStdEnc]; 348} 349class ISA_MIPS64R2 { 350 list<Predicate> InsnPredicates = [HasMips64r2]; 351 list<Predicate> EncodingPredicates = [HasStdEnc]; 352} 353class ISA_MIPS64R5 { 354 list<Predicate> InsnPredicates = [HasMips64r5]; 355 list<Predicate> EncodingPredicates = [HasStdEnc]; 356} 357class ISA_MIPS32R6 { 358 list<Predicate> InsnPredicates = [HasMips32r6]; 359 list<Predicate> EncodingPredicates = [HasStdEnc]; 360} 361class ISA_MIPS64R6 { 362 list<Predicate> InsnPredicates = [HasMips64r6]; 363 list<Predicate> EncodingPredicates = [HasStdEnc]; 364} 365class ISA_MICROMIPS { 366 list<Predicate> EncodingPredicates = [InMicroMips]; 367} 368class ISA_MICROMIPS32R5 { 369 list<Predicate> InsnPredicates = [HasMips32r5]; 370 list<Predicate> EncodingPredicates = [InMicroMips]; 371} 372class ISA_MICROMIPS32R6 { 373 list<Predicate> InsnPredicates = [HasMips32r6]; 374 list<Predicate> EncodingPredicates = [InMicroMips]; 375} 376class ISA_MICROMIPS64R6 { 377 list<Predicate> InsnPredicates = [HasMips64r6]; 378 list<Predicate> EncodingPredicates = [InMicroMips]; 379} 380class ISA_MICROMIPS32_NOT_MIPS32R6 { 381 list<Predicate> InsnPredicates = [NotMips32r6]; 382 list<Predicate> EncodingPredicates = [InMicroMips]; 383} 384class ASE_EVA { list<Predicate> ASEPredicate = [HasEVA]; } 385 386// The portions of MIPS-III that were also added to MIPS32 387class INSN_MIPS3_32 { 388 list<Predicate> InsnPredicates = [HasMips3_32]; 389 list<Predicate> EncodingPredicates = [HasStdEnc]; 390} 391 392// The portions of MIPS-III that were also added to MIPS32 but were removed in 393// MIPS32r6 and MIPS64r6. 394class INSN_MIPS3_32_NOT_32R6_64R6 { 395 list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6]; 396 list<Predicate> EncodingPredicates = [HasStdEnc]; 397} 398 399// The portions of MIPS-III that were also added to MIPS32 400class INSN_MIPS3_32R2 { 401 list<Predicate> InsnPredicates = [HasMips3_32r2]; 402 list<Predicate> EncodingPredicates = [HasStdEnc]; 403} 404 405// The portions of MIPS-IV that were also added to MIPS32. 406class INSN_MIPS4_32 { 407 list <Predicate> InsnPredicates = [HasMips4_32]; 408 list<Predicate> EncodingPredicates = [HasStdEnc]; 409} 410 411// The portions of MIPS-IV that were also added to MIPS32 but were removed in 412// MIPS32r6 and MIPS64r6. 413class INSN_MIPS4_32_NOT_32R6_64R6 { 414 list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6]; 415 list<Predicate> EncodingPredicates = [HasStdEnc]; 416} 417 418// The portions of MIPS-IV that were also added to MIPS32r2 but were removed in 419// MIPS32r6 and MIPS64r6. 420class INSN_MIPS4_32R2_NOT_32R6_64R6 { 421 list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6]; 422 list<Predicate> EncodingPredicates = [HasStdEnc]; 423} 424 425// The portions of MIPS-IV that were also added to MIPS32r2. 426class INSN_MIPS4_32R2 { 427 list<Predicate> InsnPredicates = [HasMips4_32r2]; 428 list<Predicate> EncodingPredicates = [HasStdEnc]; 429} 430 431// The portions of MIPS-V that were also added to MIPS32r2 but were removed in 432// MIPS32r6 and MIPS64r6. 433class INSN_MIPS5_32R2_NOT_32R6_64R6 { 434 list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6]; 435 list<Predicate> EncodingPredicates = [HasStdEnc]; 436} 437 438class ASE_CNMIPS { 439 list<Predicate> ASEPredicate = [HasCnMips]; 440} 441 442class NOT_ASE_CNMIPS { 443 list<Predicate> ASEPredicate = [NotCnMips]; 444} 445 446class ASE_CNMIPSP { 447 list<Predicate> ASEPredicate = [HasCnMipsP]; 448} 449 450class NOT_ASE_CNMIPSP { 451 list<Predicate> ASEPredicate = [NotCnMipsP]; 452} 453 454class ASE_MIPS64_CNMIPS { 455 list<Predicate> ASEPredicate = [HasMips64, HasCnMips]; 456} 457 458class ASE_MSA { 459 list<Predicate> ASEPredicate = [HasMSA]; 460} 461 462class ASE_MSA_NOT_MSA64 { 463 list<Predicate> ASEPredicate = [HasMSA, NotMips64]; 464} 465 466class ASE_MSA64 { 467 list<Predicate> ASEPredicate = [HasMSA, HasMips64]; 468} 469 470class ASE_MT { 471 list <Predicate> ASEPredicate = [HasMT]; 472} 473 474class ASE_CRC { 475 list <Predicate> ASEPredicate = [HasCRC]; 476} 477 478class ASE_VIRT { 479 list <Predicate> ASEPredicate = [HasVirt]; 480} 481 482class ASE_GINV { 483 list <Predicate> ASEPredicate = [HasGINV]; 484} 485 486// Class used for separating microMIPSr6 and microMIPS (r3) instruction. 487// It can be used only on instructions that doesn't inherit PredicateControl. 488class ISA_MICROMIPS_NOT_32R6 : PredicateControl { 489 let InsnPredicates = [NotMips32r6]; 490 let EncodingPredicates = [InMicroMips]; 491} 492 493class ASE_NOT_DSP { 494 list<Predicate> ASEPredicate = [NotDSP]; 495} 496 497class MADD4 { 498 list<Predicate> AdditionalPredicates = [HasMadd4]; 499} 500 501// Classses used for separating expansions that differ based on the ABI in 502// use. 503class ABI_N64 { 504 list<Predicate> AdditionalPredicates = [IsN64]; 505} 506 507class ABI_NOT_N64 { 508 list<Predicate> AdditionalPredicates = [IsNotN64]; 509} 510 511class FPOP_FUSION_FAST { 512 list <Predicate> AdditionalPredicates = [AllowFPOpFusion]; 513} 514 515//===----------------------------------------------------------------------===// 516 517class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl; 518 519class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> : 520 InstAlias<Asm, Result, Emit>, PredicateControl; 521 522class IsCommutable { 523 bit isCommutable = 1; 524} 525 526class IsBranch { 527 bit isBranch = 1; 528 bit isCTI = 1; 529} 530 531class IsReturn { 532 bit isReturn = 1; 533 bit isCTI = 1; 534} 535 536class IsCall { 537 bit isCall = 1; 538 bit isCTI = 1; 539} 540 541class IsTailCall { 542 bit isCall = 1; 543 bit isTerminator = 1; 544 bit isReturn = 1; 545 bit isBarrier = 1; 546 bit hasExtraSrcRegAllocReq = 1; 547 bit isCodeGenOnly = 1; 548 bit isCTI = 1; 549} 550 551class IsAsCheapAsAMove { 552 bit isAsCheapAsAMove = 1; 553} 554 555class NeverHasSideEffects { 556 bit hasSideEffects = 0; 557} 558 559//===----------------------------------------------------------------------===// 560// Instruction format superclass 561//===----------------------------------------------------------------------===// 562 563include "MipsInstrFormats.td" 564 565//===----------------------------------------------------------------------===// 566// Mips Operand, Complex Patterns and Transformations Definitions. 567//===----------------------------------------------------------------------===// 568 569class ConstantSImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = [], 570 int Offset = 0> : AsmOperandClass { 571 let Name = "ConstantSImm" # Bits # "_" # Offset; 572 let RenderMethod = "addConstantSImmOperands<" # Bits # ", " # Offset # ">"; 573 let PredicateMethod = "isConstantSImm<" # Bits # ", " # Offset # ">"; 574 let SuperClasses = Supers; 575 let DiagnosticType = "SImm" # Bits # "_" # Offset; 576} 577 578class SimmLslAsmOperandClass<int Bits, list<AsmOperandClass> Supers = [], 579 int Shift = 0> : AsmOperandClass { 580 let Name = "Simm" # Bits # "_Lsl" # Shift; 581 let RenderMethod = "addImmOperands"; 582 let PredicateMethod = "isScaledSImm<" # Bits # ", " # Shift # ">"; 583 let SuperClasses = Supers; 584 let DiagnosticType = "SImm" # Bits # "_Lsl" # Shift; 585} 586 587class ConstantUImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = [], 588 int Offset = 0> : AsmOperandClass { 589 let Name = "ConstantUImm" # Bits # "_" # Offset; 590 let RenderMethod = "addConstantUImmOperands<" # Bits # ", " # Offset # ">"; 591 let PredicateMethod = "isConstantUImm<" # Bits # ", " # Offset # ">"; 592 let SuperClasses = Supers; 593 let DiagnosticType = "UImm" # Bits # "_" # Offset; 594} 595 596class ConstantUImmRangeAsmOperandClass<int Bottom, int Top, 597 list<AsmOperandClass> Supers = []> 598 : AsmOperandClass { 599 let Name = "ConstantUImmRange" # Bottom # "_" # Top; 600 let RenderMethod = "addImmOperands"; 601 let PredicateMethod = "isConstantUImmRange<" # Bottom # ", " # Top # ">"; 602 let SuperClasses = Supers; 603 let DiagnosticType = "UImmRange" # Bottom # "_" # Top; 604} 605 606class SImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []> 607 : AsmOperandClass { 608 let Name = "SImm" # Bits; 609 let RenderMethod = "addSImmOperands<" # Bits # ">"; 610 let PredicateMethod = "isSImm<" # Bits # ">"; 611 let SuperClasses = Supers; 612 let DiagnosticType = "SImm" # Bits; 613} 614 615class UImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []> 616 : AsmOperandClass { 617 let Name = "UImm" # Bits; 618 let RenderMethod = "addUImmOperands<" # Bits # ">"; 619 let PredicateMethod = "isUImm<" # Bits # ">"; 620 let SuperClasses = Supers; 621 let DiagnosticType = "UImm" # Bits; 622} 623 624// Generic case - only to support certain assembly pseudo instructions. 625class UImmAnyAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []> 626 : AsmOperandClass { 627 let Name = "ImmAny"; 628 let RenderMethod = "addConstantUImmOperands<32>"; 629 let PredicateMethod = "isSImm<" # Bits # ">"; 630 let SuperClasses = Supers; 631 let DiagnosticType = "ImmAny"; 632} 633 634// AsmOperandClasses require a strict ordering which is difficult to manage 635// as a hierarchy. Instead, we use a linear ordering and impose an order that 636// is in some places arbitrary. 637// 638// Here the rules that are in use: 639// * Wider immediates are a superset of narrower immediates: 640// uimm4 < uimm5 < uimm6 641// * For the same bit-width, unsigned immediates are a superset of signed 642// immediates:: 643// simm4 < uimm4 < simm5 < uimm5 644// * For the same upper-bound, signed immediates are a superset of unsigned 645// immediates: 646// uimm3 < simm4 < uimm4 < simm4 647// * Modified immediates are a superset of ordinary immediates: 648// uimm5 < uimm5_plus1 (1..32) < uimm5_plus32 (32..63) < uimm6 649// The term 'superset' starts to break down here since the uimm5_plus* classes 650// are not true supersets of uimm5 (but they are still subsets of uimm6). 651// * 'Relaxed' immediates are supersets of the corresponding unsigned immediate. 652// uimm16 < uimm16_relaxed 653// * The codeGen pattern type is arbitrarily ordered. 654// uimm5 < uimm5_64, and uimm5 < vsplat_uimm5 655// This is entirely arbitrary. We need an ordering and what we pick is 656// unimportant since only one is possible for a given mnemonic. 657 658def UImm32CoercedAsmOperandClass : UImmAnyAsmOperandClass<33, []> { 659 let Name = "UImm32_Coerced"; 660 let DiagnosticType = "UImm32_Coerced"; 661} 662def SImm32RelaxedAsmOperandClass 663 : SImmAsmOperandClass<32, [UImm32CoercedAsmOperandClass]> { 664 let Name = "SImm32_Relaxed"; 665 let PredicateMethod = "isAnyImm<33>"; 666 let DiagnosticType = "SImm32_Relaxed"; 667} 668def SImm32AsmOperandClass 669 : SImmAsmOperandClass<32, [SImm32RelaxedAsmOperandClass]>; 670def ConstantUImm26AsmOperandClass 671 : ConstantUImmAsmOperandClass<26, [SImm32AsmOperandClass]>; 672def ConstantUImm20AsmOperandClass 673 : ConstantUImmAsmOperandClass<20, [ConstantUImm26AsmOperandClass]>; 674def ConstantSImm19Lsl2AsmOperandClass : AsmOperandClass { 675 let Name = "SImm19Lsl2"; 676 let RenderMethod = "addImmOperands"; 677 let PredicateMethod = "isScaledSImm<19, 2>"; 678 let SuperClasses = [ConstantUImm20AsmOperandClass]; 679 let DiagnosticType = "SImm19_Lsl2"; 680} 681def UImm16RelaxedAsmOperandClass 682 : UImmAsmOperandClass<16, [ConstantUImm20AsmOperandClass]> { 683 let Name = "UImm16_Relaxed"; 684 let PredicateMethod = "isAnyImm<16>"; 685 let DiagnosticType = "UImm16_Relaxed"; 686} 687// Similar to the relaxed classes which take an SImm and render it as 688// an UImm, this takes a UImm and renders it as an SImm. 689def UImm16AltRelaxedAsmOperandClass 690 : SImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]> { 691 let Name = "UImm16_AltRelaxed"; 692 let PredicateMethod = "isUImm<16>"; 693 let DiagnosticType = "UImm16_AltRelaxed"; 694} 695// FIXME: One of these should probably have UImm16AsmOperandClass as the 696// superclass instead of UImm16RelaxedasmOPerandClass. 697def UImm16AsmOperandClass 698 : UImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]>; 699def SImm16RelaxedAsmOperandClass 700 : SImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]> { 701 let Name = "SImm16_Relaxed"; 702 let PredicateMethod = "isAnyImm<16>"; 703 let DiagnosticType = "SImm16_Relaxed"; 704} 705def SImm16AsmOperandClass 706 : SImmAsmOperandClass<16, [SImm16RelaxedAsmOperandClass]>; 707def ConstantSImm10Lsl3AsmOperandClass : AsmOperandClass { 708 let Name = "SImm10Lsl3"; 709 let RenderMethod = "addImmOperands"; 710 let PredicateMethod = "isScaledSImm<10, 3>"; 711 let SuperClasses = [SImm16AsmOperandClass]; 712 let DiagnosticType = "SImm10_Lsl3"; 713} 714def ConstantSImm10Lsl2AsmOperandClass : AsmOperandClass { 715 let Name = "SImm10Lsl2"; 716 let RenderMethod = "addImmOperands"; 717 let PredicateMethod = "isScaledSImm<10, 2>"; 718 let SuperClasses = [ConstantSImm10Lsl3AsmOperandClass]; 719 let DiagnosticType = "SImm10_Lsl2"; 720} 721def ConstantSImm11AsmOperandClass 722 : ConstantSImmAsmOperandClass<11, [ConstantSImm10Lsl2AsmOperandClass]>; 723def ConstantSImm10Lsl1AsmOperandClass : AsmOperandClass { 724 let Name = "SImm10Lsl1"; 725 let RenderMethod = "addImmOperands"; 726 let PredicateMethod = "isScaledSImm<10, 1>"; 727 let SuperClasses = [ConstantSImm11AsmOperandClass]; 728 let DiagnosticType = "SImm10_Lsl1"; 729} 730def ConstantUImm10AsmOperandClass 731 : ConstantUImmAsmOperandClass<10, [ConstantSImm10Lsl1AsmOperandClass]>; 732def ConstantSImm10AsmOperandClass 733 : ConstantSImmAsmOperandClass<10, [ConstantUImm10AsmOperandClass]>; 734def ConstantSImm9AsmOperandClass 735 : ConstantSImmAsmOperandClass<9, [ConstantSImm10AsmOperandClass]>; 736def ConstantSImm7Lsl2AsmOperandClass : AsmOperandClass { 737 let Name = "SImm7Lsl2"; 738 let RenderMethod = "addImmOperands"; 739 let PredicateMethod = "isScaledSImm<7, 2>"; 740 let SuperClasses = [ConstantSImm9AsmOperandClass]; 741 let DiagnosticType = "SImm7_Lsl2"; 742} 743def ConstantUImm8AsmOperandClass 744 : ConstantUImmAsmOperandClass<8, [ConstantSImm7Lsl2AsmOperandClass]>; 745def ConstantUImm7Sub1AsmOperandClass 746 : ConstantUImmAsmOperandClass<7, [ConstantUImm8AsmOperandClass], -1> { 747 // Specify the names since the -1 offset causes invalid identifiers otherwise. 748 let Name = "UImm7_N1"; 749 let DiagnosticType = "UImm7_N1"; 750} 751def ConstantUImm7AsmOperandClass 752 : ConstantUImmAsmOperandClass<7, [ConstantUImm7Sub1AsmOperandClass]>; 753def ConstantUImm6Lsl2AsmOperandClass : AsmOperandClass { 754 let Name = "UImm6Lsl2"; 755 let RenderMethod = "addImmOperands"; 756 let PredicateMethod = "isScaledUImm<6, 2>"; 757 let SuperClasses = [ConstantUImm7AsmOperandClass]; 758 let DiagnosticType = "UImm6_Lsl2"; 759} 760def ConstantUImm6AsmOperandClass 761 : ConstantUImmAsmOperandClass<6, [ConstantUImm6Lsl2AsmOperandClass]>; 762def ConstantSImm6AsmOperandClass 763 : ConstantSImmAsmOperandClass<6, [ConstantUImm6AsmOperandClass]>; 764def ConstantUImm5Lsl2AsmOperandClass : AsmOperandClass { 765 let Name = "UImm5Lsl2"; 766 let RenderMethod = "addImmOperands"; 767 let PredicateMethod = "isScaledUImm<5, 2>"; 768 let SuperClasses = [ConstantSImm6AsmOperandClass]; 769 let DiagnosticType = "UImm5_Lsl2"; 770} 771def ConstantUImm5_Range2_64AsmOperandClass 772 : ConstantUImmRangeAsmOperandClass<2, 64, [ConstantUImm5Lsl2AsmOperandClass]>; 773def ConstantUImm5Plus33AsmOperandClass 774 : ConstantUImmAsmOperandClass<5, [ConstantUImm5_Range2_64AsmOperandClass], 775 33>; 776def ConstantUImm5ReportUImm6AsmOperandClass 777 : ConstantUImmAsmOperandClass<5, [ConstantUImm5Plus33AsmOperandClass]> { 778 let Name = "ConstantUImm5_0_Report_UImm6"; 779 let DiagnosticType = "UImm5_0_Report_UImm6"; 780} 781def ConstantUImm5Plus32AsmOperandClass 782 : ConstantUImmAsmOperandClass< 783 5, [ConstantUImm5ReportUImm6AsmOperandClass], 32>; 784def ConstantUImm5Plus32NormalizeAsmOperandClass 785 : ConstantUImmAsmOperandClass<5, [ConstantUImm5Plus32AsmOperandClass], 32> { 786 let Name = "ConstantUImm5_32_Norm"; 787 // We must also subtract 32 when we render the operand. 788 let RenderMethod = "addConstantUImmOperands<5, 32, -32>"; 789} 790def ConstantUImm5Plus1ReportUImm6AsmOperandClass 791 : ConstantUImmAsmOperandClass< 792 5, [ConstantUImm5Plus32NormalizeAsmOperandClass], 1>{ 793 let Name = "ConstantUImm5_Plus1_Report_UImm6"; 794} 795def ConstantUImm5Plus1AsmOperandClass 796 : ConstantUImmAsmOperandClass< 797 5, [ConstantUImm5Plus1ReportUImm6AsmOperandClass], 1>; 798def ConstantUImm5AsmOperandClass 799 : ConstantUImmAsmOperandClass<5, [ConstantUImm5Plus1AsmOperandClass]>; 800def ConstantSImm5AsmOperandClass 801 : ConstantSImmAsmOperandClass<5, [ConstantUImm5AsmOperandClass]>; 802def ConstantUImm4AsmOperandClass 803 : ConstantUImmAsmOperandClass<4, [ConstantSImm5AsmOperandClass]>; 804def ConstantSImm4AsmOperandClass 805 : ConstantSImmAsmOperandClass<4, [ConstantUImm4AsmOperandClass]>; 806def ConstantUImm3AsmOperandClass 807 : ConstantUImmAsmOperandClass<3, [ConstantSImm4AsmOperandClass]>; 808def ConstantUImm2Plus1AsmOperandClass 809 : ConstantUImmAsmOperandClass<2, [ConstantUImm3AsmOperandClass], 1>; 810def ConstantUImm2AsmOperandClass 811 : ConstantUImmAsmOperandClass<2, [ConstantUImm3AsmOperandClass]>; 812def ConstantUImm1AsmOperandClass 813 : ConstantUImmAsmOperandClass<1, [ConstantUImm2AsmOperandClass]>; 814def ConstantImmzAsmOperandClass : AsmOperandClass { 815 let Name = "ConstantImmz"; 816 let RenderMethod = "addConstantUImmOperands<1>"; 817 let PredicateMethod = "isConstantImmz"; 818 let SuperClasses = [ConstantUImm1AsmOperandClass]; 819 let DiagnosticType = "Immz"; 820} 821 822def Simm19Lsl2AsmOperand 823 : SimmLslAsmOperandClass<19, [], 2>; 824 825def MipsJumpTargetAsmOperand : AsmOperandClass { 826 let Name = "JumpTarget"; 827 let ParserMethod = "parseJumpTarget"; 828 let PredicateMethod = "isImm"; 829 let RenderMethod = "addImmOperands"; 830} 831 832// Instruction operand types 833def jmptarget : Operand<OtherVT> { 834 let EncoderMethod = "getJumpTargetOpValue"; 835 let ParserMatchClass = MipsJumpTargetAsmOperand; 836} 837def brtarget : Operand<OtherVT> { 838 let EncoderMethod = "getBranchTargetOpValue"; 839 let OperandType = "OPERAND_PCREL"; 840 let DecoderMethod = "DecodeBranchTarget"; 841 let ParserMatchClass = MipsJumpTargetAsmOperand; 842} 843def brtarget1SImm16 : Operand<OtherVT> { 844 let EncoderMethod = "getBranchTargetOpValue1SImm16"; 845 let OperandType = "OPERAND_PCREL"; 846 let DecoderMethod = "DecodeBranchTarget1SImm16"; 847 let ParserMatchClass = MipsJumpTargetAsmOperand; 848} 849def calltarget : Operand<iPTR> { 850 let EncoderMethod = "getJumpTargetOpValue"; 851 let ParserMatchClass = MipsJumpTargetAsmOperand; 852} 853 854def imm64: Operand<i64>; 855 856def simm19_lsl2 : Operand<i32> { 857 let EncoderMethod = "getSimm19Lsl2Encoding"; 858 let DecoderMethod = "DecodeSimm19Lsl2"; 859 let ParserMatchClass = Simm19Lsl2AsmOperand; 860} 861 862def simm18_lsl3 : Operand<i32> { 863 let EncoderMethod = "getSimm18Lsl3Encoding"; 864 let DecoderMethod = "DecodeSimm18Lsl3"; 865 let ParserMatchClass = MipsJumpTargetAsmOperand; 866} 867 868// Zero 869def uimmz : Operand<i32> { 870 let PrintMethod = "printUImm<0>"; 871 let ParserMatchClass = ConstantImmzAsmOperandClass; 872} 873 874// size operand of ins instruction 875def uimm_range_2_64 : Operand<i32> { 876 let PrintMethod = "printUImm<6, 2>"; 877 let EncoderMethod = "getSizeInsEncoding"; 878 let DecoderMethod = "DecodeInsSize"; 879 let ParserMatchClass = ConstantUImm5_Range2_64AsmOperandClass; 880} 881 882// Unsigned Operands 883foreach I = {1, 2, 3, 4, 5, 6, 7, 8, 10, 20, 26} in 884 def uimm # I : Operand<i32> { 885 let PrintMethod = "printUImm<" # I # ">"; 886 let ParserMatchClass = 887 !cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass"); 888 } 889 890def uimm2_plus1 : Operand<i32> { 891 let PrintMethod = "printUImm<2, 1>"; 892 let EncoderMethod = "getUImmWithOffsetEncoding<2, 1>"; 893 let DecoderMethod = "DecodeUImmWithOffset<2, 1>"; 894 let ParserMatchClass = ConstantUImm2Plus1AsmOperandClass; 895} 896 897def uimm5_plus1 : Operand<i32> { 898 let PrintMethod = "printUImm<5, 1>"; 899 let EncoderMethod = "getUImmWithOffsetEncoding<5, 1>"; 900 let DecoderMethod = "DecodeUImmWithOffset<5, 1>"; 901 let ParserMatchClass = ConstantUImm5Plus1AsmOperandClass; 902} 903 904def uimm5_plus1_report_uimm6 : Operand<i32> { 905 let PrintMethod = "printUImm<6, 1>"; 906 let EncoderMethod = "getUImmWithOffsetEncoding<5, 1>"; 907 let DecoderMethod = "DecodeUImmWithOffset<5, 1>"; 908 let ParserMatchClass = ConstantUImm5Plus1ReportUImm6AsmOperandClass; 909} 910 911def uimm5_plus32 : Operand<i32> { 912 let PrintMethod = "printUImm<5, 32>"; 913 let ParserMatchClass = ConstantUImm5Plus32AsmOperandClass; 914} 915 916def uimm5_plus33 : Operand<i32> { 917 let PrintMethod = "printUImm<5, 33>"; 918 let EncoderMethod = "getUImmWithOffsetEncoding<5, 1>"; 919 let DecoderMethod = "DecodeUImmWithOffset<5, 1>"; 920 let ParserMatchClass = ConstantUImm5Plus33AsmOperandClass; 921} 922 923def uimm5_inssize_plus1 : Operand<i32> { 924 let PrintMethod = "printUImm<6>"; 925 let ParserMatchClass = ConstantUImm5Plus1AsmOperandClass; 926 let EncoderMethod = "getSizeInsEncoding"; 927 let DecoderMethod = "DecodeInsSize"; 928} 929 930def uimm5_plus32_normalize : Operand<i32> { 931 let PrintMethod = "printUImm<5>"; 932 let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass; 933} 934 935def uimm5_lsl2 : Operand<OtherVT> { 936 let EncoderMethod = "getUImm5Lsl2Encoding"; 937 let DecoderMethod = "DecodeUImmWithOffsetAndScale<5, 0, 4>"; 938 let ParserMatchClass = ConstantUImm5Lsl2AsmOperandClass; 939} 940 941def uimm5_plus32_normalize_64 : Operand<i64> { 942 let PrintMethod = "printUImm<5>"; 943 let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass; 944} 945 946def uimm6_lsl2 : Operand<OtherVT> { 947 let EncoderMethod = "getUImm6Lsl2Encoding"; 948 let DecoderMethod = "DecodeUImmWithOffsetAndScale<6, 0, 4>"; 949 let ParserMatchClass = ConstantUImm6Lsl2AsmOperandClass; 950} 951 952foreach I = {16} in 953 def uimm # I : Operand<i32> { 954 let PrintMethod = "printUImm<" # I # ">"; 955 let ParserMatchClass = 956 !cast<AsmOperandClass>("UImm" # I # "AsmOperandClass"); 957 } 958 959// Like uimm16_64 but coerces simm16 to uimm16. 960def uimm16_relaxed : Operand<i32> { 961 let PrintMethod = "printUImm<16>"; 962 let ParserMatchClass = 963 !cast<AsmOperandClass>("UImm16RelaxedAsmOperandClass"); 964} 965 966foreach I = {5} in 967 def uimm # I # _64 : Operand<i64> { 968 let PrintMethod = "printUImm<" # I # ">"; 969 let ParserMatchClass = 970 !cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass"); 971 } 972 973foreach I = {16} in 974 def uimm # I # _64 : Operand<i64> { 975 let PrintMethod = "printUImm<" # I # ">"; 976 let ParserMatchClass = 977 !cast<AsmOperandClass>("UImm" # I # "AsmOperandClass"); 978 } 979 980// Like uimm16_64 but coerces simm16 to uimm16. 981def uimm16_64_relaxed : Operand<i64> { 982 let PrintMethod = "printUImm<16>"; 983 let ParserMatchClass = 984 !cast<AsmOperandClass>("UImm16RelaxedAsmOperandClass"); 985} 986 987def uimm16_altrelaxed : Operand<i32> { 988 let PrintMethod = "printUImm<16>"; 989 let ParserMatchClass = 990 !cast<AsmOperandClass>("UImm16AltRelaxedAsmOperandClass"); 991} 992// Like uimm5 but reports a less confusing error for 32-63 when 993// an instruction alias permits that. 994def uimm5_report_uimm6 : Operand<i32> { 995 let PrintMethod = "printUImm<6>"; 996 let ParserMatchClass = ConstantUImm5ReportUImm6AsmOperandClass; 997} 998 999// Like uimm5_64 but reports a less confusing error for 32-63 when 1000// an instruction alias permits that. 1001def uimm5_64_report_uimm6 : Operand<i64> { 1002 let PrintMethod = "printUImm<5>"; 1003 let ParserMatchClass = ConstantUImm5ReportUImm6AsmOperandClass; 1004} 1005 1006foreach I = {1, 2, 3, 4} in 1007 def uimm # I # _ptr : Operand<iPTR> { 1008 let PrintMethod = "printUImm<" # I # ">"; 1009 let ParserMatchClass = 1010 !cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass"); 1011 } 1012 1013foreach I = {1, 2, 3, 4, 5, 6, 8} in 1014 def vsplat_uimm # I : Operand<vAny> { 1015 let PrintMethod = "printUImm<" # I # ">"; 1016 let ParserMatchClass = 1017 !cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass"); 1018 } 1019 1020// Signed operands 1021foreach I = {4, 5, 6, 9, 10, 11} in 1022 def simm # I : Operand<i32> { 1023 let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ">"; 1024 let ParserMatchClass = 1025 !cast<AsmOperandClass>("ConstantSImm" # I # "AsmOperandClass"); 1026 } 1027 1028foreach I = {1, 2, 3} in 1029 def simm10_lsl # I : Operand<i32> { 1030 let DecoderMethod = "DecodeSImmWithOffsetAndScale<10, " # I # ">"; 1031 let ParserMatchClass = 1032 !cast<AsmOperandClass>("ConstantSImm10Lsl" # I # "AsmOperandClass"); 1033 } 1034 1035foreach I = {10} in 1036 def simm # I # _64 : Operand<i64> { 1037 let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ">"; 1038 let ParserMatchClass = 1039 !cast<AsmOperandClass>("ConstantSImm" # I # "AsmOperandClass"); 1040 } 1041 1042foreach I = {5, 10} in 1043 def vsplat_simm # I : Operand<vAny> { 1044 let ParserMatchClass = 1045 !cast<AsmOperandClass>("ConstantSImm" # I # "AsmOperandClass"); 1046 } 1047 1048def simm7_lsl2 : Operand<OtherVT> { 1049 let EncoderMethod = "getSImm7Lsl2Encoding"; 1050 let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ", 0, 4>"; 1051 let ParserMatchClass = ConstantSImm7Lsl2AsmOperandClass; 1052} 1053 1054foreach I = {16, 32} in 1055 def simm # I : Operand<i32> { 1056 let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ">"; 1057 let ParserMatchClass = !cast<AsmOperandClass>("SImm" # I # "AsmOperandClass"); 1058 } 1059 1060// Like simm16 but coerces uimm16 to simm16. 1061def simm16_relaxed : Operand<i32> { 1062 let DecoderMethod = "DecodeSImmWithOffsetAndScale<16>"; 1063 let ParserMatchClass = !cast<AsmOperandClass>("SImm16RelaxedAsmOperandClass"); 1064} 1065 1066def simm16_64 : Operand<i64> { 1067 let DecoderMethod = "DecodeSImmWithOffsetAndScale<16>"; 1068 let ParserMatchClass = !cast<AsmOperandClass>("SImm16AsmOperandClass"); 1069} 1070 1071// like simm32 but coerces simm32 to uimm32. 1072def uimm32_coerced : Operand<i32> { 1073 let ParserMatchClass = !cast<AsmOperandClass>("UImm32CoercedAsmOperandClass"); 1074} 1075// Like simm32 but coerces uimm32 to simm32. 1076def simm32_relaxed : Operand<i32> { 1077 let DecoderMethod = "DecodeSImmWithOffsetAndScale<32>"; 1078 let ParserMatchClass = !cast<AsmOperandClass>("SImm32RelaxedAsmOperandClass"); 1079} 1080 1081// This is almost the same as a uimm7 but 0x7f is interpreted as -1. 1082def li16_imm : Operand<i32> { 1083 let DecoderMethod = "DecodeLi16Imm"; 1084 let ParserMatchClass = ConstantUImm7Sub1AsmOperandClass; 1085} 1086 1087def MipsMemAsmOperand : AsmOperandClass { 1088 let Name = "Mem"; 1089 let ParserMethod = "parseMemOperand"; 1090} 1091 1092def MipsMemSimm9AsmOperand : AsmOperandClass { 1093 let Name = "MemOffsetSimm9"; 1094 let SuperClasses = [MipsMemAsmOperand]; 1095 let RenderMethod = "addMemOperands"; 1096 let ParserMethod = "parseMemOperand"; 1097 let PredicateMethod = "isMemWithSimmOffset<9>"; 1098 let DiagnosticType = "MemSImm9"; 1099} 1100 1101def MipsMemSimm10AsmOperand : AsmOperandClass { 1102 let Name = "MemOffsetSimm10"; 1103 let SuperClasses = [MipsMemAsmOperand]; 1104 let RenderMethod = "addMemOperands"; 1105 let ParserMethod = "parseMemOperand"; 1106 let PredicateMethod = "isMemWithSimmOffset<10>"; 1107 let DiagnosticType = "MemSImm10"; 1108} 1109 1110def MipsMemSimm12AsmOperand : AsmOperandClass { 1111 let Name = "MemOffsetSimm12"; 1112 let SuperClasses = [MipsMemAsmOperand]; 1113 let RenderMethod = "addMemOperands"; 1114 let ParserMethod = "parseMemOperand"; 1115 let PredicateMethod = "isMemWithSimmOffset<12>"; 1116 let DiagnosticType = "MemSImm12"; 1117} 1118 1119foreach I = {1, 2, 3} in 1120 def MipsMemSimm10Lsl # I # AsmOperand : AsmOperandClass { 1121 let Name = "MemOffsetSimm10_" # I; 1122 let SuperClasses = [MipsMemAsmOperand]; 1123 let RenderMethod = "addMemOperands"; 1124 let ParserMethod = "parseMemOperand"; 1125 let PredicateMethod = "isMemWithSimmOffset<10, " # I # ">"; 1126 let DiagnosticType = "MemSImm10Lsl" # I; 1127 } 1128 1129def MipsMemSimm11AsmOperand : AsmOperandClass { 1130 let Name = "MemOffsetSimm11"; 1131 let SuperClasses = [MipsMemAsmOperand]; 1132 let RenderMethod = "addMemOperands"; 1133 let ParserMethod = "parseMemOperand"; 1134 let PredicateMethod = "isMemWithSimmOffset<11>"; 1135 let DiagnosticType = "MemSImm11"; 1136} 1137 1138def MipsMemSimm16AsmOperand : AsmOperandClass { 1139 let Name = "MemOffsetSimm16"; 1140 let SuperClasses = [MipsMemAsmOperand]; 1141 let RenderMethod = "addMemOperands"; 1142 let ParserMethod = "parseMemOperand"; 1143 let PredicateMethod = "isMemWithSimmOffset<16>"; 1144 let DiagnosticType = "MemSImm16"; 1145} 1146 1147def MipsMemSimmPtrAsmOperand : AsmOperandClass { 1148 let Name = "MemOffsetSimmPtr"; 1149 let SuperClasses = [MipsMemAsmOperand]; 1150 let RenderMethod = "addMemOperands"; 1151 let ParserMethod = "parseMemOperand"; 1152 let PredicateMethod = "isMemWithPtrSizeOffset"; 1153 let DiagnosticType = "MemSImmPtr"; 1154} 1155 1156def MipsInvertedImmoperand : AsmOperandClass { 1157 let Name = "InvNum"; 1158 let RenderMethod = "addImmOperands"; 1159 let ParserMethod = "parseInvNum"; 1160} 1161 1162def InvertedImOperand : Operand<i32> { 1163 let ParserMatchClass = MipsInvertedImmoperand; 1164} 1165 1166def InvertedImOperand64 : Operand<i64> { 1167 let ParserMatchClass = MipsInvertedImmoperand; 1168} 1169 1170class mem_generic : Operand<iPTR> { 1171 let PrintMethod = "printMemOperand"; 1172 let MIOperandInfo = (ops ptr_rc, simm16); 1173 let EncoderMethod = "getMemEncoding"; 1174 let ParserMatchClass = MipsMemAsmOperand; 1175 let OperandType = "OPERAND_MEMORY"; 1176} 1177 1178// Address operand 1179def mem : mem_generic; 1180 1181// MSA specific address operand 1182def mem_msa : mem_generic { 1183 let MIOperandInfo = (ops ptr_rc, simm10); 1184 let EncoderMethod = "getMSAMemEncoding"; 1185} 1186 1187def simm12 : Operand<i32> { 1188 let DecoderMethod = "DecodeSimm12"; 1189} 1190 1191def mem_simm9 : mem_generic { 1192 let MIOperandInfo = (ops ptr_rc, simm9); 1193 let EncoderMethod = "getMemEncoding"; 1194 let ParserMatchClass = MipsMemSimm9AsmOperand; 1195} 1196 1197def mem_simm10 : mem_generic { 1198 let MIOperandInfo = (ops ptr_rc, simm10); 1199 let EncoderMethod = "getMemEncoding"; 1200 let ParserMatchClass = MipsMemSimm10AsmOperand; 1201} 1202 1203foreach I = {1, 2, 3} in 1204 def mem_simm10_lsl # I : mem_generic { 1205 let MIOperandInfo = (ops ptr_rc, !cast<Operand>("simm10_lsl" # I)); 1206 let EncoderMethod = "getMemEncoding<" # I # ">"; 1207 let ParserMatchClass = 1208 !cast<AsmOperandClass>("MipsMemSimm10Lsl" # I # "AsmOperand"); 1209 } 1210 1211def mem_simm11 : mem_generic { 1212 let MIOperandInfo = (ops ptr_rc, simm11); 1213 let EncoderMethod = "getMemEncoding"; 1214 let ParserMatchClass = MipsMemSimm11AsmOperand; 1215} 1216 1217def mem_simm12 : mem_generic { 1218 let MIOperandInfo = (ops ptr_rc, simm12); 1219 let EncoderMethod = "getMemEncoding"; 1220 let ParserMatchClass = MipsMemSimm12AsmOperand; 1221} 1222 1223def mem_simm16 : mem_generic { 1224 let MIOperandInfo = (ops ptr_rc, simm16); 1225 let EncoderMethod = "getMemEncoding"; 1226 let ParserMatchClass = MipsMemSimm16AsmOperand; 1227} 1228 1229def mem_simmptr : mem_generic { 1230 let ParserMatchClass = MipsMemSimmPtrAsmOperand; 1231} 1232 1233def mem_ea : Operand<iPTR> { 1234 let PrintMethod = "printMemOperandEA"; 1235 let MIOperandInfo = (ops ptr_rc, simm16); 1236 let EncoderMethod = "getMemEncoding"; 1237 let OperandType = "OPERAND_MEMORY"; 1238} 1239 1240def PtrRC : Operand<iPTR> { 1241 let MIOperandInfo = (ops ptr_rc); 1242 let DecoderMethod = "DecodePtrRegisterClass"; 1243 let ParserMatchClass = GPR32AsmOperand; 1244} 1245 1246// size operand of ins instruction 1247def size_ins : Operand<i32> { 1248 let EncoderMethod = "getSizeInsEncoding"; 1249 let DecoderMethod = "DecodeInsSize"; 1250} 1251 1252// Transformation Function - get the lower 16 bits. 1253def LO16 : SDNodeXForm<imm, [{ 1254 return getImm(N, N->getZExtValue() & 0xFFFF); 1255}]>; 1256 1257// Transformation Function - get the higher 16 bits. 1258def HI16 : SDNodeXForm<imm, [{ 1259 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 1260}]>; 1261 1262// Plus 1. 1263def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>; 1264 1265// Node immediate is zero (e.g. insve.d) 1266def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>; 1267 1268// Node immediate fits as 16-bit sign extended on target immediate. 1269// e.g. addi, andi 1270def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>; 1271 1272// Node immediate fits as 16-bit sign extended on target immediate. 1273// e.g. addi, andi 1274def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 1275 1276// Node immediate fits as 7-bit zero extended on target immediate. 1277def immZExt7 : PatLeaf<(imm), [{ return isUInt<7>(N->getZExtValue()); }]>; 1278 1279// Node immediate fits as 16-bit zero extended on target immediate. 1280// The LO16 param means that only the lower 16 bits of the node 1281// immediate are caught. 1282// e.g. addiu, sltiu 1283def immZExt16 : PatLeaf<(imm), [{ 1284 if (N->getValueType(0) == MVT::i32) 1285 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 1286 else 1287 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 1288}], LO16>; 1289 1290// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 1291def immSExt32Low16Zero : PatLeaf<(imm), [{ 1292 int64_t Val = N->getSExtValue(); 1293 return isInt<32>(Val) && !(Val & 0xffff); 1294}]>; 1295 1296// Zero-extended 32-bit unsigned int with lower 16-bit cleared. 1297def immZExt32Low16Zero : PatLeaf<(imm), [{ 1298 uint64_t Val = N->getZExtValue(); 1299 return isUInt<32>(Val) && !(Val & 0xffff); 1300}]>; 1301 1302// Note immediate fits as a 32 bit signed extended on target immediate. 1303def immSExt32 : PatLeaf<(imm), [{ return isInt<32>(N->getSExtValue()); }]>; 1304 1305// Note immediate fits as a 32 bit zero extended on target immediate. 1306def immZExt32 : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>; 1307 1308// shamt field must fit in 5 bits. 1309def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 1310 1311def immZExt5Plus1 : PatLeaf<(imm), [{ 1312 return isUInt<5>(N->getZExtValue() - 1); 1313}]>; 1314def immZExt5Plus32 : PatLeaf<(imm), [{ 1315 return isUInt<5>(N->getZExtValue() - 32); 1316}]>; 1317def immZExt5Plus33 : PatLeaf<(imm), [{ 1318 return isUInt<5>(N->getZExtValue() - 33); 1319}]>; 1320 1321def immZExt5To31 : SDNodeXForm<imm, [{ 1322 return getImm(N, 31 - N->getZExtValue()); 1323}]>; 1324 1325// True if (N + 1) fits in 16-bit field. 1326def immSExt16Plus1 : PatLeaf<(imm), [{ 1327 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1); 1328}]>; 1329 1330def immZExtRange2To64 : PatLeaf<(imm), [{ 1331 return isUInt<7>(N->getZExtValue()) && (N->getZExtValue() >= 2) && 1332 (N->getZExtValue() <= 64); 1333}]>; 1334 1335def ORiPred : PatLeaf<(imm), [{ 1336 return isUInt<16>(N->getZExtValue()) && !isInt<16>(N->getSExtValue()); 1337}], LO16>; 1338 1339def LUiPred : PatLeaf<(imm), [{ 1340 int64_t Val = N->getSExtValue(); 1341 return !isInt<16>(Val) && isInt<32>(Val) && !(Val & 0xffff); 1342}]>; 1343 1344def LUiORiPred : PatLeaf<(imm), [{ 1345 int64_t SVal = N->getSExtValue(); 1346 return isInt<32>(SVal) && (SVal & 0xffff); 1347}]>; 1348 1349// Mips Address Mode! SDNode frameindex could possibily be a match 1350// since load and store instructions from stack used it. 1351def addr : 1352 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>; 1353 1354def addrRegImm : 1355 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>; 1356 1357def addrDefault : 1358 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>; 1359 1360def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrSImm10", [frameindex]>; 1361def addrimm10lsl1 : ComplexPattern<iPTR, 2, "selectIntAddrSImm10Lsl1", 1362 [frameindex]>; 1363def addrimm10lsl2 : ComplexPattern<iPTR, 2, "selectIntAddrSImm10Lsl2", 1364 [frameindex]>; 1365def addrimm10lsl3 : ComplexPattern<iPTR, 2, "selectIntAddrSImm10Lsl3", 1366 [frameindex]>; 1367 1368//===----------------------------------------------------------------------===// 1369// Instructions specific format 1370//===----------------------------------------------------------------------===// 1371 1372// Arithmetic and logical instructions with 3 register operands. 1373class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, 1374 InstrItinClass Itin = NoItinerary, 1375 SDPatternOperator OpNode = null_frag>: 1376 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 1377 !strconcat(opstr, "\t$rd, $rs, $rt"), 1378 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> { 1379 let isCommutable = isComm; 1380 let isReMaterializable = 1; 1381 let TwoOperandAliasConstraint = "$rd = $rs"; 1382} 1383 1384// Arithmetic and logical instructions with 2 register operands. 1385class ArithLogicI<string opstr, Operand Od, RegisterOperand RO, 1386 InstrItinClass Itin = NoItinerary, 1387 SDPatternOperator imm_type = null_frag, 1388 SDPatternOperator OpNode = null_frag> : 1389 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), 1390 !strconcat(opstr, "\t$rt, $rs, $imm16"), 1391 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], 1392 Itin, FrmI, opstr> { 1393 let isReMaterializable = 1; 1394 let TwoOperandAliasConstraint = "$rs = $rt"; 1395} 1396 1397// Arithmetic Multiply ADD/SUB 1398class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> : 1399 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 1400 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> { 1401 let Defs = [HI0, LO0]; 1402 let Uses = [HI0, LO0]; 1403 let isCommutable = isComm; 1404} 1405 1406// Logical 1407class LogicNOR<string opstr, RegisterOperand RO>: 1408 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 1409 !strconcat(opstr, "\t$rd, $rs, $rt"), 1410 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> { 1411 let isCommutable = 1; 1412} 1413 1414// Shifts 1415class shift_rotate_imm<string opstr, Operand ImmOpnd, 1416 RegisterOperand RO, InstrItinClass itin, 1417 SDPatternOperator OpNode = null_frag, 1418 SDPatternOperator PF = null_frag> : 1419 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt), 1420 !strconcat(opstr, "\t$rd, $rt, $shamt"), 1421 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> { 1422 let TwoOperandAliasConstraint = "$rt = $rd"; 1423} 1424 1425class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin, 1426 SDPatternOperator OpNode = null_frag>: 1427 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs), 1428 !strconcat(opstr, "\t$rd, $rt, $rs"), 1429 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR, 1430 opstr>; 1431 1432// Load Upper Immediate 1433class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>: 1434 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 1435 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove { 1436 let hasSideEffects = 0; 1437 let isReMaterializable = 1; 1438} 1439 1440// Memory Load/Store 1441class LoadMemory<string opstr, DAGOperand RO, DAGOperand MO, 1442 SDPatternOperator OpNode = null_frag, 1443 InstrItinClass Itin = NoItinerary, 1444 ComplexPattern Addr = addr> : 1445 InstSE<(outs RO:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"), 1446 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> { 1447 let DecoderMethod = "DecodeMem"; 1448 let canFoldAsLoad = 1; 1449 string BaseOpcode = opstr; 1450 let mayLoad = 1; 1451} 1452 1453class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, 1454 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : 1455 LoadMemory<opstr, RO, mem, OpNode, Itin, Addr>; 1456 1457class StoreMemory<string opstr, DAGOperand RO, DAGOperand MO, 1458 SDPatternOperator OpNode = null_frag, 1459 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : 1460 InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"), 1461 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> { 1462 let DecoderMethod = "DecodeMem"; 1463 string BaseOpcode = opstr; 1464 let mayStore = 1; 1465} 1466 1467class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, 1468 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr, 1469 DAGOperand MO = mem> : 1470 StoreMemory<opstr, RO, MO, OpNode, Itin, Addr>; 1471 1472// Load/Store Left/Right 1473let canFoldAsLoad = 1 in 1474class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO, 1475 InstrItinClass Itin> : 1476 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src), 1477 !strconcat(opstr, "\t$rt, $addr"), 1478 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> { 1479 let DecoderMethod = "DecodeMem"; 1480 string Constraints = "$src = $rt"; 1481 let BaseOpcode = opstr; 1482} 1483 1484class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO, 1485 InstrItinClass Itin> : 1486 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 1487 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> { 1488 let DecoderMethod = "DecodeMem"; 1489 let BaseOpcode = opstr; 1490} 1491 1492// COP2 Load/Store 1493class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin, 1494 SDPatternOperator OpNode= null_frag> : 1495 InstSE<(outs RC:$rt), (ins mem_simm16:$addr), 1496 !strconcat(opstr, "\t$rt, $addr"), 1497 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> { 1498 let DecoderMethod = "DecodeFMem2"; 1499 let mayLoad = 1; 1500} 1501 1502class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin, 1503 SDPatternOperator OpNode= null_frag> : 1504 InstSE<(outs), (ins RC:$rt, mem_simm16:$addr), 1505 !strconcat(opstr, "\t$rt, $addr"), 1506 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> { 1507 let DecoderMethod = "DecodeFMem2"; 1508 let mayStore = 1; 1509} 1510 1511// COP3 Load/Store 1512class LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin, 1513 SDPatternOperator OpNode= null_frag> : 1514 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 1515 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> { 1516 let DecoderMethod = "DecodeFMem3"; 1517 let mayLoad = 1; 1518} 1519 1520class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin, 1521 SDPatternOperator OpNode= null_frag> : 1522 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 1523 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> { 1524 let DecoderMethod = "DecodeFMem3"; 1525 let mayStore = 1; 1526} 1527 1528// Conditional Branch 1529class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op, 1530 RegisterOperand RO> : 1531 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset), 1532 !strconcat(opstr, "\t$rs, $rt, $offset"), 1533 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], II_BCC, 1534 FrmI, opstr> { 1535 let isBranch = 1; 1536 let isTerminator = 1; 1537 let hasDelaySlot = 1; 1538 let Defs = [AT]; 1539 bit isCTI = 1; 1540} 1541 1542class CBranchLikely<string opstr, DAGOperand opnd, RegisterOperand RO> : 1543 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset), 1544 !strconcat(opstr, "\t$rs, $rt, $offset"), [], II_BCC, FrmI, opstr> { 1545 let isBranch = 1; 1546 let isTerminator = 1; 1547 let hasDelaySlot = 1; 1548 let Defs = [AT]; 1549 bit isCTI = 1; 1550} 1551 1552class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op, 1553 RegisterOperand RO> : 1554 InstSE<(outs), (ins RO:$rs, opnd:$offset), 1555 !strconcat(opstr, "\t$rs, $offset"), 1556 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], II_BCCZ, 1557 FrmI, opstr> { 1558 let isBranch = 1; 1559 let isTerminator = 1; 1560 let hasDelaySlot = 1; 1561 let Defs = [AT]; 1562 bit isCTI = 1; 1563} 1564 1565class CBranchZeroLikely<string opstr, DAGOperand opnd, RegisterOperand RO> : 1566 InstSE<(outs), (ins RO:$rs, opnd:$offset), 1567 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZ, FrmI, opstr> { 1568 let isBranch = 1; 1569 let isTerminator = 1; 1570 let hasDelaySlot = 1; 1571 let Defs = [AT]; 1572 bit isCTI = 1; 1573} 1574 1575// SetCC 1576class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> : 1577 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt), 1578 !strconcat(opstr, "\t$rd, $rs, $rt"), 1579 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))], 1580 II_SLT_SLTU, FrmR, opstr>; 1581 1582class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 1583 RegisterOperand RO>: 1584 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16), 1585 !strconcat(opstr, "\t$rt, $rs, $imm16"), 1586 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))], 1587 II_SLTI_SLTIU, FrmI, opstr>; 1588 1589// Jump 1590class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 1591 SDPatternOperator targetoperator, string bopstr> : 1592 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 1593 [(operator targetoperator:$target)], II_J, FrmJ, bopstr> { 1594 let isTerminator=1; 1595 let isBarrier=1; 1596 let hasDelaySlot = 1; 1597 let DecoderMethod = "DecodeJumpTarget"; 1598 let Defs = [AT]; 1599 bit isCTI = 1; 1600} 1601 1602// Unconditional branch 1603class UncondBranch<Instruction BEQInst, DAGOperand opnd> : 1604 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], II_B>, 1605 PseudoInstExpansion<(BEQInst ZERO, ZERO, opnd:$offset)> { 1606 let isBranch = 1; 1607 let isTerminator = 1; 1608 let isBarrier = 1; 1609 let hasDelaySlot = 1; 1610 let AdditionalPredicates = [RelocPIC]; 1611 let Defs = [AT]; 1612 bit isCTI = 1; 1613} 1614 1615// Base class for indirect branch and return instruction classes. 1616let isTerminator=1, isBarrier=1, hasDelaySlot = 1, isCTI = 1 in 1617class JumpFR<string opstr, RegisterOperand RO, 1618 SDPatternOperator operator = null_frag>: 1619 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], II_JR, 1620 FrmR, opstr>; 1621 1622// Indirect branch 1623class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> { 1624 let isBranch = 1; 1625 let isIndirectBranch = 1; 1626} 1627 1628// Jump and Link (Call) 1629let isCall=1, hasDelaySlot=1, isCTI=1, Defs = [RA] in { 1630 class JumpLink<string opstr, DAGOperand opnd> : 1631 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 1632 [(MipsJmpLink tglobaladdr:$target)], II_JAL, FrmJ, opstr> { 1633 let DecoderMethod = "DecodeJumpTarget"; 1634 } 1635 1636 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst, 1637 Register RetReg, RegisterOperand ResRO = RO>: 1638 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], II_JALR>, 1639 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)> { 1640 let hasPostISelHook = 1; 1641 } 1642 1643 class JumpLinkReg<string opstr, RegisterOperand RO>: 1644 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 1645 [], II_JALR, FrmR, opstr> { 1646 let hasPostISelHook = 1; 1647 } 1648 1649 class BGEZAL_FT<string opstr, DAGOperand opnd, 1650 RegisterOperand RO> : 1651 InstSE<(outs), (ins RO:$rs, opnd:$offset), 1652 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZAL, FrmI, opstr> { 1653 let hasDelaySlot = 1; 1654 } 1655 1656} 1657 1658let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1, 1659 hasExtraSrcRegAllocReq = 1, isCTI = 1, Defs = [AT] in { 1660 class TailCall<Instruction JumpInst, DAGOperand Opnd> : 1661 PseudoSE<(outs), (ins calltarget:$target), [], II_J>, 1662 PseudoInstExpansion<(JumpInst Opnd:$target)>; 1663 1664 class TailCallReg<Instruction JumpInst, RegisterOperand RO> : 1665 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>, 1666 PseudoInstExpansion<(JumpInst RO:$rs)> { 1667 let hasPostISelHook = 1; 1668 } 1669} 1670 1671class BAL_BR_Pseudo<Instruction RealInst, DAGOperand opnd> : 1672 PseudoSE<(outs), (ins opnd:$offset), [], II_BCCZAL>, 1673 PseudoInstExpansion<(RealInst ZERO, opnd:$offset)> { 1674 let isBranch = 1; 1675 let isTerminator = 1; 1676 let isBarrier = 1; 1677 let hasDelaySlot = 1; 1678 let Defs = [RA]; 1679 bit isCTI = 1; 1680} 1681 1682let isCTI = 1 in { 1683// Syscall 1684class SYS_FT<string opstr, Operand ImmOp, InstrItinClass itin = NoItinerary> : 1685 InstSE<(outs), (ins ImmOp:$code_), 1686 !strconcat(opstr, "\t$code_"), [], itin, FrmI, opstr>; 1687// Break 1688class BRK_FT<string opstr> : 1689 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2), 1690 !strconcat(opstr, "\t$code_1, $code_2"), [], II_BREAK, 1691 FrmOther, opstr>; 1692 1693// (D)Eret 1694class ER_FT<string opstr, InstrItinClass itin = NoItinerary> : 1695 InstSE<(outs), (ins), 1696 opstr, [], itin, FrmOther, opstr>; 1697 1698// Wait 1699class WAIT_FT<string opstr> : 1700 InstSE<(outs), (ins), opstr, [], II_WAIT, FrmOther, opstr>; 1701} 1702 1703// Interrupts 1704class DEI_FT<string opstr, RegisterOperand RO, 1705 InstrItinClass itin = NoItinerary> : 1706 InstSE<(outs RO:$rt), (ins), 1707 !strconcat(opstr, "\t$rt"), [], itin, FrmOther, opstr>; 1708 1709// Sync 1710let hasSideEffects = 1 in 1711class SYNC_FT<string opstr> : 1712 InstSE<(outs), (ins uimm5:$stype), "sync $stype", 1713 [(MipsSync immZExt5:$stype)], II_SYNC, FrmOther, opstr>; 1714 1715class SYNCI_FT<string opstr, DAGOperand MO> : 1716 InstSE<(outs), (ins MO:$addr), !strconcat(opstr, "\t$addr"), [], 1717 II_SYNCI, FrmOther, opstr> { 1718 let hasSideEffects = 1; 1719 let DecoderMethod = "DecodeSyncI"; 1720} 1721 1722let hasSideEffects = 1, isCTI = 1 in { 1723class TEQ_FT<string opstr, RegisterOperand RO, Operand ImmOp, 1724 InstrItinClass itin = NoItinerary> : 1725 InstSE<(outs), (ins RO:$rs, RO:$rt, ImmOp:$code_), 1726 !strconcat(opstr, "\t$rs, $rt, $code_"), [], itin, FrmI, opstr>; 1727 1728class TEQI_FT<string opstr, RegisterOperand RO, 1729 InstrItinClass itin = NoItinerary> : 1730 InstSE<(outs), (ins RO:$rs, simm16:$imm16), 1731 !strconcat(opstr, "\t$rs, $imm16"), [], itin, FrmOther, opstr>; 1732} 1733 1734// Mul, Div 1735class Mult<string opstr, InstrItinClass itin, RegisterOperand RO, 1736 list<Register> DefRegs> : 1737 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 1738 itin, FrmR, opstr> { 1739 let isCommutable = 1; 1740 let Defs = DefRegs; 1741 let hasSideEffects = 0; 1742} 1743 1744// Pseudo multiply/divide instruction with explicit accumulator register 1745// operands. 1746class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1, 1747 SDPatternOperator OpNode, InstrItinClass Itin, 1748 bit IsComm = 1, bit HasSideEffects = 0, 1749 bit UsesCustomInserter = 0> : 1750 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt), 1751 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>, 1752 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> { 1753 let isCommutable = IsComm; 1754 let hasSideEffects = HasSideEffects; 1755 let usesCustomInserter = UsesCustomInserter; 1756} 1757 1758// Pseudo multiply add/sub instruction with explicit accumulator register 1759// operands. 1760class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode, 1761 InstrItinClass itin> 1762 : PseudoSE<(outs ACC64:$ac), 1763 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin), 1764 [(set ACC64:$ac, 1765 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))], 1766 itin>, 1767 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> { 1768 string Constraints = "$acin = $ac"; 1769} 1770 1771class Div<string opstr, InstrItinClass itin, RegisterOperand RO, 1772 list<Register> DefRegs> : 1773 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"), 1774 [], itin, FrmR, opstr> { 1775 let Defs = DefRegs; 1776} 1777 1778// Move from Hi/Lo 1779class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> 1780 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo), 1781 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>; 1782 1783class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>: 1784 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO, 1785 FrmR, opstr> { 1786 let Uses = [UseReg]; 1787 let hasSideEffects = 0; 1788 let isMoveReg = 1; 1789} 1790 1791class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC> 1792 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi), 1793 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))], 1794 II_MTHI_MTLO>; 1795 1796class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>: 1797 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO, 1798 FrmR, opstr> { 1799 let Defs = DefRegs; 1800 let hasSideEffects = 0; 1801 let isMoveReg = 1; 1802} 1803 1804class EffectiveAddress<string opstr, RegisterOperand RO> : 1805 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"), 1806 [(set RO:$rt, addr:$addr)], II_ADDIU, FrmI, 1807 !strconcat(opstr, "_lea")> { 1808 let isCodeGenOnly = 1; 1809 let hasNoSchedulingInfo = 1; 1810 let DecoderMethod = "DecodeMem"; 1811} 1812 1813// Count Leading Ones/Zeros in Word 1814class CountLeading0<string opstr, RegisterOperand RO, 1815 InstrItinClass itin = NoItinerary>: 1816 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 1817 [(set RO:$rd, (ctlz RO:$rs))], itin, FrmR, opstr>; 1818 1819class CountLeading1<string opstr, RegisterOperand RO, 1820 InstrItinClass itin = NoItinerary>: 1821 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 1822 [(set RO:$rd, (ctlz (not RO:$rs)))], itin, FrmR, opstr>; 1823 1824// Sign Extend in Register. 1825class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO, 1826 InstrItinClass itin> : 1827 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), 1828 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>; 1829 1830// Subword Swap 1831class SubwordSwap<string opstr, RegisterOperand RO, 1832 InstrItinClass itin = NoItinerary>: 1833 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], itin, 1834 FrmR, opstr> { 1835 let hasSideEffects = 0; 1836} 1837 1838// Read Hardware 1839class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> : 1840 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd, uimm8:$sel), 1841 "rdhwr\t$rt, $rd, $sel", [], II_RDHWR, FrmR, "rdhwr">; 1842 1843// Ext and Ins 1844class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd, 1845 Operand SizeOpnd, PatFrag PosImm, PatFrag SizeImm, 1846 SDPatternOperator Op = null_frag> : 1847 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size), 1848 !strconcat(opstr, "\t$rt, $rs, $pos, $size"), 1849 [(set RO:$rt, (Op RO:$rs, PosImm:$pos, SizeImm:$size))], II_EXT, 1850 FrmR, opstr>; 1851 1852// 'ins' and its' 64 bit variants are matched by C++ code. 1853class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd, 1854 Operand SizeOpnd, PatFrag PosImm, PatFrag SizeImm>: 1855 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size, RO:$src), 1856 !strconcat(opstr, "\t$rt, $rs, $pos, $size"), 1857 [(set RO:$rt, (null_frag RO:$rs, PosImm:$pos, SizeImm:$size, 1858 RO:$src))], 1859 II_INS, FrmR, opstr> { 1860 let Constraints = "$src = $rt"; 1861} 1862 1863// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 1864class Atomic2Ops<PatFrag Op, RegisterClass DRC> : 1865 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr), 1866 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]> { 1867 let hasNoSchedulingInfo = 1; 1868} 1869 1870class Atomic2OpsPostRA<RegisterClass RC> : 1871 PseudoSE<(outs RC:$dst), (ins PtrRC:$ptr, RC:$incr), []> { 1872 let mayLoad = 1; 1873 let mayStore = 1; 1874} 1875 1876class Atomic2OpsSubwordPostRA<RegisterClass RC> : 1877 PseudoSE<(outs RC:$dst), (ins PtrRC:$ptr, RC:$incr, RC:$mask, RC:$mask2, 1878 RC:$shiftamnt), []>; 1879 1880// Atomic Compare & Swap. 1881// Atomic compare and swap is lowered into two stages. The first stage happens 1882// during ISelLowering, which produces the PostRA version of this instruction. 1883class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> : 1884 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap), 1885 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]> { 1886 let hasNoSchedulingInfo = 1; 1887} 1888 1889class AtomicCmpSwapPostRA<RegisterClass RC> : 1890 PseudoSE<(outs RC:$dst), (ins PtrRC:$ptr, RC:$cmp, RC:$swap), []> { 1891 let mayLoad = 1; 1892 let mayStore = 1; 1893} 1894 1895class AtomicCmpSwapSubwordPostRA<RegisterClass RC> : 1896 PseudoSE<(outs RC:$dst), (ins PtrRC:$ptr, RC:$mask, RC:$ShiftCmpVal, 1897 RC:$mask2, RC:$ShiftNewVal, RC:$ShiftAmt), []> { 1898 let mayLoad = 1; 1899 let mayStore = 1; 1900} 1901 1902class LLBase<string opstr, RegisterOperand RO, DAGOperand MO = mem> : 1903 InstSE<(outs RO:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"), 1904 [], II_LL, FrmI, opstr> { 1905 let DecoderMethod = "DecodeMem"; 1906 let mayLoad = 1; 1907} 1908 1909class SCBase<string opstr, RegisterOperand RO> : 1910 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr), 1911 !strconcat(opstr, "\t$rt, $addr"), [], II_SC, FrmI> { 1912 let DecoderMethod = "DecodeMem"; 1913 let mayStore = 1; 1914 let Constraints = "$rt = $dst"; 1915} 1916 1917class MFC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD, 1918 InstrItinClass itin> : 1919 InstSE<(outs RO:$rt), (ins RD:$rd, uimm3:$sel), 1920 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], itin, FrmFR> { 1921 let BaseOpcode = asmstr; 1922} 1923 1924class MTC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD, 1925 InstrItinClass itin> : 1926 InstSE<(outs RO:$rd), (ins RD:$rt, uimm3:$sel), 1927 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], itin, FrmFR> { 1928 let BaseOpcode = asmstr; 1929} 1930 1931class TrapBase<Instruction RealInst> 1932 : PseudoSE<(outs), (ins), [(trap)], II_TRAP>, 1933 PseudoInstExpansion<(RealInst 0, 0)> { 1934 let isBarrier = 1; 1935 let isTerminator = 1; 1936 let isCodeGenOnly = 1; 1937 let isCTI = 1; 1938} 1939 1940//===----------------------------------------------------------------------===// 1941// Pseudo instructions 1942//===----------------------------------------------------------------------===// 1943 1944// Return RA. 1945let isReturn=1, isTerminator=1, isBarrier=1, hasCtrlDep=1, isCTI=1 in { 1946 let hasDelaySlot=1 in 1947 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 1948 1949 let hasSideEffects=1 in 1950 def ERet : PseudoSE<(outs), (ins), [(MipsERet)]>; 1951} 1952 1953let Defs = [SP], Uses = [SP], hasSideEffects = 1, hasNoSchedulingInfo = 1 in { 1954def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 1955 [(callseq_start timm:$amt1, timm:$amt2)]>; 1956def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 1957 [(callseq_end timm:$amt1, timm:$amt2)]>; 1958} 1959 1960let usesCustomInserter = 1 in { 1961 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>; 1962 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>; 1963 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>; 1964 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>; 1965 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>; 1966 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>; 1967 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>; 1968 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>; 1969 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>; 1970 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>; 1971 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>; 1972 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>; 1973 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>; 1974 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>; 1975 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>; 1976 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>; 1977 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>; 1978 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>; 1979 1980 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>; 1981 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>; 1982 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>; 1983 1984 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>; 1985 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>; 1986 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>; 1987 1988} 1989 1990def ATOMIC_LOAD_ADD_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 1991def ATOMIC_LOAD_ADD_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 1992def ATOMIC_LOAD_ADD_I32_POSTRA : Atomic2OpsPostRA<GPR32>; 1993def ATOMIC_LOAD_SUB_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 1994def ATOMIC_LOAD_SUB_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 1995def ATOMIC_LOAD_SUB_I32_POSTRA : Atomic2OpsPostRA<GPR32>; 1996def ATOMIC_LOAD_AND_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 1997def ATOMIC_LOAD_AND_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 1998def ATOMIC_LOAD_AND_I32_POSTRA : Atomic2OpsPostRA<GPR32>; 1999def ATOMIC_LOAD_OR_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 2000def ATOMIC_LOAD_OR_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 2001def ATOMIC_LOAD_OR_I32_POSTRA : Atomic2OpsPostRA<GPR32>; 2002def ATOMIC_LOAD_XOR_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 2003def ATOMIC_LOAD_XOR_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 2004def ATOMIC_LOAD_XOR_I32_POSTRA : Atomic2OpsPostRA<GPR32>; 2005def ATOMIC_LOAD_NAND_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 2006def ATOMIC_LOAD_NAND_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 2007def ATOMIC_LOAD_NAND_I32_POSTRA : Atomic2OpsPostRA<GPR32>; 2008 2009def ATOMIC_SWAP_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 2010def ATOMIC_SWAP_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 2011def ATOMIC_SWAP_I32_POSTRA : Atomic2OpsPostRA<GPR32>; 2012 2013def ATOMIC_CMP_SWAP_I8_POSTRA : AtomicCmpSwapSubwordPostRA<GPR32>; 2014def ATOMIC_CMP_SWAP_I16_POSTRA : AtomicCmpSwapSubwordPostRA<GPR32>; 2015def ATOMIC_CMP_SWAP_I32_POSTRA : AtomicCmpSwapPostRA<GPR32>; 2016 2017/// Pseudo instructions for loading and storing accumulator registers. 2018let isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in { 2019 def LOAD_ACC64 : Load<"", ACC64>; 2020 def STORE_ACC64 : Store<"", ACC64>; 2021} 2022 2023// We need these two pseudo instructions to avoid offset calculation for long 2024// branches. See the comment in file MipsLongBranch.cpp for detailed 2025// explanation. 2026 2027// Expands to: lui $dst, %highest/%higher/%hi/%lo($tgt - $baltgt) 2028def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst), 2029 (ins brtarget:$tgt, brtarget:$baltgt), []> { 2030 bit hasNoSchedulingInfo = 1; 2031} 2032// Expands to: lui $dst, highest/%higher/%hi/%lo($tgt) 2033def LONG_BRANCH_LUi2Op : PseudoSE<(outs GPR32Opnd:$dst), 2034 (ins brtarget:$tgt), []> { 2035 bit hasNoSchedulingInfo = 1; 2036} 2037 2038// Expands to: addiu $dst, $src, %highest/%higher/%hi/%lo($tgt - $baltgt) 2039def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst), 2040 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []> { 2041 bit hasNoSchedulingInfo = 1; 2042} 2043// Expands to: addiu $dst, $src, %highest/%higher/%hi/%lo($tgt) 2044def LONG_BRANCH_ADDiu2Op : PseudoSE<(outs GPR32Opnd:$dst), 2045 (ins GPR32Opnd:$src, brtarget:$tgt), []> { 2046 bit hasNoSchedulingInfo = 1; 2047} 2048 2049//===----------------------------------------------------------------------===// 2050// Instruction definition 2051//===----------------------------------------------------------------------===// 2052//===----------------------------------------------------------------------===// 2053// MipsI Instructions 2054//===----------------------------------------------------------------------===// 2055 2056/// Arithmetic Instructions (ALU Immediate) 2057let AdditionalPredicates = [NotInMicroMips] in { 2058 def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16_relaxed, GPR32Opnd, 2059 II_ADDIU, immSExt16, add>, 2060 ADDI_FM<0x9>, IsAsCheapAsAMove, ISA_MIPS1; 2061 2062 def ANDi : MMRel, StdMMR6Rel, 2063 ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>, 2064 ADDI_FM<0xc>, ISA_MIPS1; 2065 def ORi : MMRel, StdMMR6Rel, 2066 ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>, 2067 ADDI_FM<0xd>, ISA_MIPS1; 2068 def XORi : MMRel, StdMMR6Rel, 2069 ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>, 2070 ADDI_FM<0xe>, ISA_MIPS1; 2071 def ADDi : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd, II_ADDI>, 2072 ADDI_FM<0x8>, ISA_MIPS1_NOT_32R6_64R6; 2073 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, 2074 SLTI_FM<0xa>, ISA_MIPS1; 2075 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, 2076 SLTI_FM<0xb>, ISA_MIPS1; 2077 2078 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM, 2079 ISA_MIPS1; 2080 2081 /// Arithmetic Instructions (3-Operand, R-Type) 2082 def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>, 2083 ADD_FM<0, 0x21>, ISA_MIPS1; 2084 def SUBu : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>, 2085 ADD_FM<0, 0x23>, ISA_MIPS1; 2086 2087 let Defs = [HI0, LO0] in 2088 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>, 2089 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6; 2090 2091 def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>, 2092 ADD_FM<0, 0x20>, ISA_MIPS1; 2093 def SUB : MMRel, StdMMR6Rel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>, 2094 ADD_FM<0, 0x22>, ISA_MIPS1; 2095 2096 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>, 2097 ISA_MIPS1; 2098 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>, 2099 ISA_MIPS1; 2100 def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>, 2101 ADD_FM<0, 0x24>, ISA_MIPS1; 2102 def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>, 2103 ADD_FM<0, 0x25>, ISA_MIPS1; 2104 def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>, 2105 ADD_FM<0, 0x26>, ISA_MIPS1; 2106 def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>, 2107 ISA_MIPS1; 2108} 2109 2110let AdditionalPredicates = [NotInMicroMips] in { 2111 /// Shift Instructions 2112 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl, 2113 immZExt5>, SRA_FM<0, 0>, ISA_MIPS1; 2114 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl, 2115 immZExt5>, SRA_FM<2, 0>, ISA_MIPS1; 2116 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra, 2117 immZExt5>, SRA_FM<3, 0>, ISA_MIPS1; 2118 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>, 2119 SRLV_FM<4, 0>, ISA_MIPS1; 2120 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>, 2121 SRLV_FM<6, 0>, ISA_MIPS1; 2122 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>, 2123 SRLV_FM<7, 0>, ISA_MIPS1; 2124 2125 // Rotate Instructions 2126 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr, 2127 immZExt5>, 2128 SRA_FM<2, 1>, ISA_MIPS32R2; 2129 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>, 2130 SRLV_FM<6, 1>, ISA_MIPS32R2; 2131} 2132 2133/// Load and Store Instructions 2134/// aligned 2135let AdditionalPredicates = [NotInMicroMips] in { 2136 def LB : LoadMemory<"lb", GPR32Opnd, mem_simmptr, sextloadi8, II_LB>, MMRel, 2137 LW_FM<0x20>, ISA_MIPS1; 2138 def LBu : LoadMemory<"lbu", GPR32Opnd, mem_simmptr, zextloadi8, II_LBU, 2139 addrDefault>, MMRel, LW_FM<0x24>, ISA_MIPS1; 2140 def LH : LoadMemory<"lh", GPR32Opnd, mem_simmptr, sextloadi16, II_LH, 2141 addrDefault>, MMRel, LW_FM<0x21>, ISA_MIPS1; 2142 def LHu : LoadMemory<"lhu", GPR32Opnd, mem_simmptr, zextloadi16, II_LHU>, 2143 MMRel, LW_FM<0x25>, ISA_MIPS1; 2144 def LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel, 2145 LW_FM<0x23>, ISA_MIPS1; 2146 def SB : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, 2147 LW_FM<0x28>, ISA_MIPS1; 2148 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>, 2149 ISA_MIPS1; 2150 def SW : StdMMR6Rel, Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>, ISA_MIPS1; 2151} 2152 2153/// load/store left/right 2154let AdditionalPredicates = [NotInMicroMips] in { 2155def LWL : MMRel, LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>, 2156 ISA_MIPS1_NOT_32R6_64R6; 2157def LWR : MMRel, LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>, 2158 ISA_MIPS1_NOT_32R6_64R6; 2159def SWL : MMRel, StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>, 2160 ISA_MIPS1_NOT_32R6_64R6; 2161def SWR : MMRel, StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>, 2162 ISA_MIPS1_NOT_32R6_64R6; 2163 2164// COP2 Memory Instructions 2165def LWC2 : StdMMR6Rel, LW_FT2<"lwc2", COP2Opnd, II_LWC2, load>, LW_FM<0x32>, 2166 ISA_MIPS1_NOT_32R6_64R6; 2167def SWC2 : StdMMR6Rel, SW_FT2<"swc2", COP2Opnd, II_SWC2, store>, 2168 LW_FM<0x3a>, ISA_MIPS1_NOT_32R6_64R6; 2169def LDC2 : StdMMR6Rel, LW_FT2<"ldc2", COP2Opnd, II_LDC2, load>, LW_FM<0x36>, 2170 ISA_MIPS2_NOT_32R6_64R6; 2171def SDC2 : StdMMR6Rel, SW_FT2<"sdc2", COP2Opnd, II_SDC2, store>, 2172 LW_FM<0x3e>, ISA_MIPS2_NOT_32R6_64R6; 2173 2174// COP3 Memory Instructions 2175let DecoderNamespace = "COP3_" in { 2176 def LWC3 : LW_FT3<"lwc3", COP3Opnd, II_LWC3, load>, LW_FM<0x33>, 2177 ISA_MIPS1_NOT_32R6_64R6, NOT_ASE_CNMIPS; 2178 def SWC3 : SW_FT3<"swc3", COP3Opnd, II_SWC3, store>, LW_FM<0x3b>, 2179 ISA_MIPS1_NOT_32R6_64R6, NOT_ASE_CNMIPS; 2180 def LDC3 : LW_FT3<"ldc3", COP3Opnd, II_LDC3, load>, LW_FM<0x37>, 2181 ISA_MIPS2, NOT_ASE_CNMIPS; 2182 def SDC3 : SW_FT3<"sdc3", COP3Opnd, II_SDC3, store>, LW_FM<0x3f>, 2183 ISA_MIPS2, NOT_ASE_CNMIPS; 2184} 2185 2186 def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS2; 2187 def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci", mem_simm16>, SYNCI_FM, 2188 ISA_MIPS32R2; 2189} 2190 2191let AdditionalPredicates = [NotInMicroMips] in { 2192 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm10, II_TEQ>, TEQ_FM<0x34>, 2193 ISA_MIPS2; 2194 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm10, II_TGE>, TEQ_FM<0x30>, 2195 ISA_MIPS2; 2196 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm10, II_TGEU>, TEQ_FM<0x31>, 2197 ISA_MIPS2; 2198 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm10, II_TLT>, TEQ_FM<0x32>, 2199 ISA_MIPS2; 2200 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm10, II_TLTU>, TEQ_FM<0x33>, 2201 ISA_MIPS2; 2202 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm10, II_TNE>, TEQ_FM<0x36>, 2203 ISA_MIPS2; 2204 2205 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd, II_TEQI>, TEQI_FM<0xc>, 2206 ISA_MIPS2_NOT_32R6_64R6; 2207 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd, II_TGEI>, TEQI_FM<0x8>, 2208 ISA_MIPS2_NOT_32R6_64R6; 2209 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd, II_TGEIU>, TEQI_FM<0x9>, 2210 ISA_MIPS2_NOT_32R6_64R6; 2211 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd, II_TLTI>, TEQI_FM<0xa>, 2212 ISA_MIPS2_NOT_32R6_64R6; 2213 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd, II_TTLTIU>, TEQI_FM<0xb>, 2214 ISA_MIPS2_NOT_32R6_64R6; 2215 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd, II_TNEI>, TEQI_FM<0xe>, 2216 ISA_MIPS2_NOT_32R6_64R6; 2217} 2218 2219let AdditionalPredicates = [NotInMicroMips] in { 2220 def BREAK : MMRel, StdMMR6Rel, BRK_FT<"break">, BRK_FM<0xd>, ISA_MIPS1; 2221 def SYSCALL : MMRel, SYS_FT<"syscall", uimm20, II_SYSCALL>, SYS_FM<0xc>, 2222 ISA_MIPS1; 2223 def TRAP : TrapBase<BREAK>, ISA_MIPS1; 2224 def SDBBP : MMRel, SYS_FT<"sdbbp", uimm20, II_SDBBP>, SDBBP_FM, 2225 ISA_MIPS32_NOT_32R6_64R6; 2226 2227 def ERET : MMRel, ER_FT<"eret", II_ERET>, ER_FM<0x18, 0x0>, INSN_MIPS3_32; 2228 def ERETNC : MMRel, ER_FT<"eretnc", II_ERETNC>, ER_FM<0x18, 0x1>, 2229 ISA_MIPS32R5; 2230 def DERET : MMRel, ER_FT<"deret", II_DERET>, ER_FM<0x1f, 0x0>, ISA_MIPS32; 2231 2232 def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd, II_EI>, EI_FM<1>, 2233 ISA_MIPS32R2; 2234 def DI : MMRel, StdMMR6Rel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM<0>, 2235 ISA_MIPS32R2; 2236 2237 def WAIT : MMRel, StdMMR6Rel, WAIT_FT<"wait">, WAIT_FM, INSN_MIPS3_32; 2238} 2239 2240let AdditionalPredicates = [NotInMicroMips] in { 2241/// Load-linked, Store-conditional 2242def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, PTR_32, ISA_MIPS2_NOT_32R6_64R6; 2243def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, PTR_32, ISA_MIPS2_NOT_32R6_64R6; 2244} 2245/// Jump and Branch Instructions 2246let AdditionalPredicates = [NotInMicroMips, RelocNotPIC] in 2247def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>, 2248 IsBranch, ISA_MIPS1; 2249 2250let AdditionalPredicates = [NotInMicroMips] in { 2251def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>, ISA_MIPS1_NOT_32R6_64R6; 2252def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>, 2253 ISA_MIPS1; 2254def BEQL : MMRel, CBranchLikely<"beql", brtarget, GPR32Opnd>, 2255 BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6; 2256def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>, 2257 ISA_MIPS1; 2258def BNEL : MMRel, CBranchLikely<"bnel", brtarget, GPR32Opnd>, 2259 BEQ_FM<21>, ISA_MIPS2_NOT_32R6_64R6; 2260def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>, 2261 BGEZ_FM<1, 1>, ISA_MIPS1; 2262def BGEZL : MMRel, CBranchZeroLikely<"bgezl", brtarget, GPR32Opnd>, 2263 BGEZ_FM<1, 3>, ISA_MIPS2_NOT_32R6_64R6; 2264def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>, 2265 BGEZ_FM<7, 0>, ISA_MIPS1; 2266def BGTZL : MMRel, CBranchZeroLikely<"bgtzl", brtarget, GPR32Opnd>, 2267 BGEZ_FM<23, 0>, ISA_MIPS2_NOT_32R6_64R6; 2268def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>, 2269 BGEZ_FM<6, 0>, ISA_MIPS1; 2270def BLEZL : MMRel, CBranchZeroLikely<"blezl", brtarget, GPR32Opnd>, 2271 BGEZ_FM<22, 0>, ISA_MIPS2_NOT_32R6_64R6; 2272def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>, 2273 BGEZ_FM<1, 0>, ISA_MIPS1; 2274def BLTZL : MMRel, CBranchZeroLikely<"bltzl", brtarget, GPR32Opnd>, 2275 BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6; 2276def B : UncondBranch<BEQ, brtarget>, ISA_MIPS1; 2277 2278def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>, ISA_MIPS1; 2279 2280} 2281 2282let AdditionalPredicates = [NotInMicroMips, NoIndirectJumpGuards] in { 2283 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM, ISA_MIPS1; 2284 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>, ISA_MIPS1; 2285} 2286 2287let AdditionalPredicates = [NotInMicroMips] in { 2288 def JALX : MMRel, JumpLink<"jalx", calltarget>, FJ<0x1D>, 2289 ISA_MIPS32_NOT_32R6_64R6; 2290 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>, 2291 ISA_MIPS1_NOT_32R6_64R6; 2292 def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd>, 2293 BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6; 2294 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>, 2295 ISA_MIPS1_NOT_32R6_64R6; 2296 def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd>, 2297 BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6; 2298 def BAL_BR : BAL_BR_Pseudo<BGEZAL, brtarget>, ISA_MIPS1; 2299} 2300let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips] in { 2301 def TAILCALL : TailCall<J, jmptarget>, ISA_MIPS1; 2302} 2303let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, 2304 NoIndirectJumpGuards] in 2305 def TAILCALLREG : TailCallReg<JR, GPR32Opnd>, ISA_MIPS1_NOT_32R6_64R6; 2306 2307// Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64 2308// then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA. 2309class PseudoIndirectBranchBase<Instruction JumpInst, RegisterOperand RO> : 2310 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)], 2311 II_IndirectBranchPseudo>, 2312 PseudoInstExpansion<(JumpInst RO:$rs)> { 2313 let isTerminator=1; 2314 let isBarrier=1; 2315 let hasDelaySlot = 1; 2316 let isBranch = 1; 2317 let isIndirectBranch = 1; 2318 bit isCTI = 1; 2319} 2320 2321let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, 2322 NoIndirectJumpGuards] in 2323 def PseudoIndirectBranch : PseudoIndirectBranchBase<JR, GPR32Opnd>, 2324 ISA_MIPS1_NOT_32R6_64R6; 2325 2326// Return instructions are matched as a RetRA instruction, then are expanded 2327// into PseudoReturn/PseudoReturn64 after register allocation. Finally, 2328// MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the 2329// ISA. 2330class PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs), 2331 [], II_ReturnPseudo> { 2332 let isTerminator = 1; 2333 let isBarrier = 1; 2334 let hasDelaySlot = 1; 2335 let isReturn = 1; 2336 let isCodeGenOnly = 1; 2337 let hasCtrlDep = 1; 2338 let hasExtraSrcRegAllocReq = 1; 2339 bit isCTI = 1; 2340} 2341 2342def PseudoReturn : PseudoReturnBase<GPR32Opnd>; 2343 2344// Exception handling related node and instructions. 2345// The conversion sequence is: 2346// ISD::EH_RETURN -> MipsISD::EH_RETURN -> 2347// MIPSeh_return -> (stack change + indirect branch) 2348// 2349// MIPSeh_return takes the place of regular return instruction 2350// but takes two arguments (V1, V0) which are used for storing 2351// the offset and return address respectively. 2352def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 2353 2354def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET, 2355 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 2356 2357let Uses = [V0, V1], isTerminator = 1, isReturn = 1, 2358 isBarrier = 1, isCTI = 1, hasNoSchedulingInfo = 1 in { 2359 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst), 2360 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>; 2361 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff, GPR64:$dst), 2362 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>; 2363} 2364 2365/// Multiply and Divide Instructions. 2366let AdditionalPredicates = [NotInMicroMips] in { 2367 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>, 2368 MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6; 2369 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>, 2370 MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6; 2371 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>, 2372 MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6; 2373 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>, 2374 MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6; 2375 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>, 2376 ISA_MIPS1_NOT_32R6_64R6; 2377 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>, 2378 ISA_MIPS1_NOT_32R6_64R6; 2379 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>, 2380 ISA_MIPS1_NOT_32R6_64R6; 2381 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>, 2382 ISA_MIPS1_NOT_32R6_64R6; 2383 2384 /// Sign Ext In Register Instructions. 2385 def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, 2386 SEB_FM<0x10, 0x20>, ISA_MIPS32R2; 2387 def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, 2388 SEB_FM<0x18, 0x20>, ISA_MIPS32R2; 2389 2390 /// Count Leading 2391 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM<0x20>, 2392 ISA_MIPS32_NOT_32R6_64R6; 2393 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM<0x21>, 2394 ISA_MIPS32_NOT_32R6_64R6; 2395 2396 /// Word Swap Bytes Within Halfwords 2397 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>, SEB_FM<2, 0x20>, 2398 ISA_MIPS32R2; 2399 2400 /// No operation. 2401 def NOP : PseudoSE<(outs), (ins), []>, 2402 PseudoInstExpansion<(SLL ZERO, ZERO, 0)>, ISA_MIPS1; 2403 2404 // FrameIndexes are legalized when they are operands from load/store 2405 // instructions. The same not happens for stack address copies, so an 2406 // add op with mem ComplexPattern is used and the stack address copy 2407 // can be matched. It's similar to Sparc LEA_ADDRi 2408 let AdditionalPredicates = [NotInMicroMips] in 2409 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>, ISA_MIPS1; 2410 2411 // MADD*/MSUB* 2412 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>, 2413 ISA_MIPS32_NOT_32R6_64R6; 2414 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>, 2415 ISA_MIPS32_NOT_32R6_64R6; 2416 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>, 2417 ISA_MIPS32_NOT_32R6_64R6; 2418 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>, 2419 ISA_MIPS32_NOT_32R6_64R6; 2420} 2421 2422let AdditionalPredicates = [NotDSP] in { 2423def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>, 2424 ISA_MIPS1_NOT_32R6_64R6; 2425def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>, 2426 ISA_MIPS1_NOT_32R6_64R6; 2427def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6; 2428def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6; 2429def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6; 2430def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>, 2431 ISA_MIPS32_NOT_32R6_64R6; 2432def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>, 2433 ISA_MIPS32_NOT_32R6_64R6; 2434def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>, 2435 ISA_MIPS32_NOT_32R6_64R6; 2436def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>, 2437 ISA_MIPS32_NOT_32R6_64R6; 2438} 2439 2440let AdditionalPredicates = [NotInMicroMips] in { 2441 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV, 2442 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6; 2443 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU, 2444 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6; 2445 def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM, ISA_MIPS1; 2446 // TODO: Add '0 < pos+size <= 32' constraint check to ext instruction 2447 def EXT : MMRel, StdMMR6Rel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, 2448 immZExt5, immZExt5Plus1, MipsExt>, 2449 EXT_FM<0>, ISA_MIPS32R2; 2450 def INS : MMRel, StdMMR6Rel, InsBase<"ins", GPR32Opnd, uimm5, 2451 uimm5_inssize_plus1, immZExt5, 2452 immZExt5Plus1>, 2453 EXT_FM<4>, ISA_MIPS32R2; 2454} 2455/// Move Control Registers From/To CPU Registers 2456let AdditionalPredicates = [NotInMicroMips] in { 2457 def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd, II_MTC0>, 2458 MFC3OP_FM<0x10, 4, 0>, ISA_MIPS1; 2459 def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd, II_MFC0>, 2460 MFC3OP_FM<0x10, 0, 0>, ISA_MIPS1; 2461 def MFC2 : MFC3OP<"mfc2", GPR32Opnd, COP2Opnd, II_MFC2>, 2462 MFC3OP_FM<0x12, 0, 0>, ISA_MIPS1; 2463 def MTC2 : MTC3OP<"mtc2", COP2Opnd, GPR32Opnd, II_MTC2>, 2464 MFC3OP_FM<0x12, 4, 0>, ISA_MIPS1; 2465} 2466 2467class Barrier<string asmstr, InstrItinClass itin = NoItinerary> : 2468 InstSE<(outs), (ins), asmstr, [], itin, FrmOther, asmstr>; 2469let AdditionalPredicates = [NotInMicroMips] in { 2470 def SSNOP : MMRel, StdMMR6Rel, Barrier<"ssnop", II_SSNOP>, BARRIER_FM<1>, 2471 ISA_MIPS1; 2472 def EHB : MMRel, Barrier<"ehb", II_EHB>, BARRIER_FM<3>, ISA_MIPS1; 2473 2474 let isCTI = 1 in 2475 def PAUSE : MMRel, StdMMR6Rel, Barrier<"pause", II_PAUSE>, BARRIER_FM<5>, 2476 ISA_MIPS32R2; 2477} 2478 2479// JR_HB and JALR_HB are defined here using the new style naming 2480// scheme because some of this code is shared with Mips32r6InstrInfo.td 2481// and because of that it doesn't follow the naming convention of the 2482// rest of the file. To avoid a mixture of old vs new style, the new 2483// style was chosen. 2484class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 2485 dag OutOperandList = (outs); 2486 dag InOperandList = (ins GPROpnd:$rs); 2487 string AsmString = !strconcat(instr_asm, "\t$rs"); 2488 list<dag> Pattern = []; 2489} 2490 2491class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 2492 dag OutOperandList = (outs GPROpnd:$rd); 2493 dag InOperandList = (ins GPROpnd:$rs); 2494 string AsmString = !strconcat(instr_asm, "\t$rd, $rs"); 2495 list<dag> Pattern = []; 2496} 2497 2498class JR_HB_DESC<RegisterOperand RO> : 2499 InstSE<(outs), (ins), "", [], II_JR_HB, FrmJ>, JR_HB_DESC_BASE<"jr.hb", RO> { 2500 let isBranch=1; 2501 let isIndirectBranch=1; 2502 let hasDelaySlot=1; 2503 let isTerminator=1; 2504 let isBarrier=1; 2505 bit isCTI = 1; 2506} 2507 2508class JALR_HB_DESC<RegisterOperand RO> : 2509 InstSE<(outs), (ins), "", [], II_JALR_HB, FrmJ>, JALR_HB_DESC_BASE<"jalr.hb", 2510 RO> { 2511 let isIndirectBranch=1; 2512 let hasDelaySlot=1; 2513 bit isCTI = 1; 2514} 2515 2516class JR_HB_ENC : JR_HB_FM<8>; 2517class JALR_HB_ENC : JALR_HB_FM<9>; 2518 2519def JR_HB : JR_HB_DESC<GPR32Opnd>, JR_HB_ENC, ISA_MIPS32R2_NOT_32R6_64R6; 2520def JALR_HB : JALR_HB_DESC<GPR32Opnd>, JALR_HB_ENC, ISA_MIPS32; 2521 2522let AdditionalPredicates = [NotInMicroMips, UseIndirectJumpsHazard] in 2523 def JALRHBPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR_HB, RA>; 2524 2525 2526let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, 2527 UseIndirectJumpsHazard] in { 2528 def TAILCALLREGHB : TailCallReg<JR_HB, GPR32Opnd>, ISA_MIPS32_NOT_32R6_64R6; 2529 def PseudoIndirectHazardBranch : PseudoIndirectBranchBase<JR_HB, GPR32Opnd>, 2530 ISA_MIPS32R2_NOT_32R6_64R6; 2531} 2532 2533class TLB<string asmstr, InstrItinClass itin = NoItinerary> : 2534 InstSE<(outs), (ins), asmstr, [], itin, FrmOther, asmstr>; 2535let AdditionalPredicates = [NotInMicroMips] in { 2536 def TLBP : MMRel, TLB<"tlbp", II_TLBP>, COP0_TLB_FM<0x08>, ISA_MIPS1; 2537 def TLBR : MMRel, TLB<"tlbr", II_TLBR>, COP0_TLB_FM<0x01>, ISA_MIPS1; 2538 def TLBWI : MMRel, TLB<"tlbwi", II_TLBWI>, COP0_TLB_FM<0x02>, ISA_MIPS1; 2539 def TLBWR : MMRel, TLB<"tlbwr", II_TLBWR>, COP0_TLB_FM<0x06>, ISA_MIPS1; 2540} 2541class CacheOp<string instr_asm, Operand MemOpnd, 2542 InstrItinClass itin = NoItinerary> : 2543 InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint), 2544 !strconcat(instr_asm, "\t$hint, $addr"), [], itin, FrmOther, 2545 instr_asm> { 2546 let DecoderMethod = "DecodeCacheOp"; 2547} 2548 2549let AdditionalPredicates = [NotInMicroMips] in { 2550 def CACHE : MMRel, CacheOp<"cache", mem, II_CACHE>, CACHEOP_FM<0b101111>, 2551 INSN_MIPS3_32_NOT_32R6_64R6; 2552 def PREF : MMRel, CacheOp<"pref", mem, II_PREF>, CACHEOP_FM<0b110011>, 2553 INSN_MIPS3_32_NOT_32R6_64R6; 2554} 2555// FIXME: We are missing the prefx instruction. 2556def ROL : MipsAsmPseudoInst<(outs), 2557 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd), 2558 "rol\t$rs, $rt, $rd">; 2559def ROLImm : MipsAsmPseudoInst<(outs), 2560 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 2561 "rol\t$rs, $rt, $imm">; 2562def : MipsInstAlias<"rol $rd, $rs", 2563 (ROL GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>; 2564def : MipsInstAlias<"rol $rd, $imm", 2565 (ROLImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>; 2566 2567def ROR : MipsAsmPseudoInst<(outs), 2568 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd), 2569 "ror\t$rs, $rt, $rd">; 2570def RORImm : MipsAsmPseudoInst<(outs), 2571 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 2572 "ror\t$rs, $rt, $imm">; 2573def : MipsInstAlias<"ror $rd, $rs", 2574 (ROR GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>; 2575def : MipsInstAlias<"ror $rd, $imm", 2576 (RORImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>; 2577 2578def DROL : MipsAsmPseudoInst<(outs), 2579 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd), 2580 "drol\t$rs, $rt, $rd">, ISA_MIPS64; 2581def DROLImm : MipsAsmPseudoInst<(outs), 2582 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 2583 "drol\t$rs, $rt, $imm">, ISA_MIPS64; 2584def : MipsInstAlias<"drol $rd, $rs", 2585 (DROL GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>, ISA_MIPS64; 2586def : MipsInstAlias<"drol $rd, $imm", 2587 (DROLImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>, ISA_MIPS64; 2588 2589def DROR : MipsAsmPseudoInst<(outs), 2590 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd), 2591 "dror\t$rs, $rt, $rd">, ISA_MIPS64; 2592def DRORImm : MipsAsmPseudoInst<(outs), 2593 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 2594 "dror\t$rs, $rt, $imm">, ISA_MIPS64; 2595def : MipsInstAlias<"dror $rd, $rs", 2596 (DROR GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>, ISA_MIPS64; 2597def : MipsInstAlias<"dror $rd, $imm", 2598 (DRORImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>, ISA_MIPS64; 2599 2600def ABSMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs), 2601 "abs\t$rd, $rs">; 2602 2603def SEQMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 2604 (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 2605 "seq $rd, $rs, $rt">, NOT_ASE_CNMIPS; 2606 2607def : MipsInstAlias<"seq $rd, $rs", 2608 (SEQMacro GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>, 2609 NOT_ASE_CNMIPS; 2610 2611def SEQIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 2612 (ins GPR32Opnd:$rs, simm32_relaxed:$imm), 2613 "seq $rd, $rs, $imm">, NOT_ASE_CNMIPS; 2614 2615def : MipsInstAlias<"seq $rd, $imm", 2616 (SEQIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, simm32:$imm), 0>, 2617 NOT_ASE_CNMIPS; 2618 2619def MULImmMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs, 2620 simm32_relaxed:$imm), 2621 "mul\t$rd, $rs, $imm">, 2622 ISA_MIPS1_NOT_32R6_64R6; 2623def MULOMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs, 2624 GPR32Opnd:$rt), 2625 "mulo\t$rd, $rs, $rt">, 2626 ISA_MIPS1_NOT_32R6_64R6; 2627def MULOUMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs, 2628 GPR32Opnd:$rt), 2629 "mulou\t$rd, $rs, $rt">, 2630 ISA_MIPS1_NOT_32R6_64R6; 2631 2632// Virtualization ASE 2633class HYPCALL_FT<string opstr> : 2634 InstSE<(outs), (ins uimm10:$code_), 2635 !strconcat(opstr, "\t$code_"), [], II_HYPCALL, FrmOther, opstr> { 2636 let BaseOpcode = opstr; 2637} 2638 2639let AdditionalPredicates = [NotInMicroMips] in { 2640 def MFGC0 : MMRel, MFC3OP<"mfgc0", GPR32Opnd, COP0Opnd, II_MFGC0>, 2641 MFC3OP_FM<0x10, 3, 0>, ISA_MIPS32R5, ASE_VIRT; 2642 def MTGC0 : MMRel, MTC3OP<"mtgc0", COP0Opnd, GPR32Opnd, II_MTGC0>, 2643 MFC3OP_FM<0x10, 3, 2>, ISA_MIPS32R5, ASE_VIRT; 2644 def MFHGC0 : MMRel, MFC3OP<"mfhgc0", GPR32Opnd, COP0Opnd, II_MFHGC0>, 2645 MFC3OP_FM<0x10, 3, 4>, ISA_MIPS32R5, ASE_VIRT; 2646 def MTHGC0 : MMRel, MTC3OP<"mthgc0", COP0Opnd, GPR32Opnd, II_MTHGC0>, 2647 MFC3OP_FM<0x10, 3, 6>, ISA_MIPS32R5, ASE_VIRT; 2648 def TLBGINV : MMRel, TLB<"tlbginv", II_TLBGINV>, COP0_TLB_FM<0b001011>, 2649 ISA_MIPS32R5, ASE_VIRT; 2650 def TLBGINVF : MMRel, TLB<"tlbginvf", II_TLBGINVF>, COP0_TLB_FM<0b001100>, 2651 ISA_MIPS32R5, ASE_VIRT; 2652 def TLBGP : MMRel, TLB<"tlbgp", II_TLBGP>, COP0_TLB_FM<0b010000>, 2653 ISA_MIPS32R5, ASE_VIRT; 2654 def TLBGR : MMRel, TLB<"tlbgr", II_TLBGR>, COP0_TLB_FM<0b001001>, 2655 ISA_MIPS32R5, ASE_VIRT; 2656 def TLBGWI : MMRel, TLB<"tlbgwi", II_TLBGWI>, COP0_TLB_FM<0b001010>, 2657 ISA_MIPS32R5, ASE_VIRT; 2658 def TLBGWR : MMRel, TLB<"tlbgwr", II_TLBGWR>, COP0_TLB_FM<0b001110>, 2659 ISA_MIPS32R5, ASE_VIRT; 2660 def HYPCALL : MMRel, HYPCALL_FT<"hypcall">, 2661 HYPCALL_FM<0b101000>, ISA_MIPS32R5, ASE_VIRT; 2662} 2663 2664//===----------------------------------------------------------------------===// 2665// Instruction aliases 2666//===----------------------------------------------------------------------===// 2667 2668multiclass OneOrTwoOperandMacroImmediateAlias<string Memnomic, 2669 Instruction Opcode, 2670 RegisterOperand RO = GPR32Opnd, 2671 Operand Imm = simm32_relaxed> { 2672 def : MipsInstAlias<!strconcat(Memnomic, " $rs, $rt, $imm"), 2673 (Opcode RO:$rs, 2674 RO:$rt, 2675 Imm:$imm), 0>; 2676 def : MipsInstAlias<!strconcat(Memnomic, " $rs, $imm"), 2677 (Opcode RO:$rs, 2678 RO:$rs, 2679 Imm:$imm), 0>; 2680} 2681 2682let AdditionalPredicates = [NotInMicroMips] in { 2683 def : MipsInstAlias<"move $dst, $src", 2684 (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>, 2685 GPR_32, ISA_MIPS1; 2686 def : MipsInstAlias<"move $dst, $src", 2687 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>, 2688 GPR_32, ISA_MIPS1; 2689 2690 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 1>, 2691 ISA_MIPS1_NOT_32R6_64R6; 2692 2693 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>, ISA_MIPS1; 2694 2695 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>; 2696 2697 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, 2698 ISA_MIPS32; 2699 2700 def : MipsInstAlias<"neg $rt, $rs", 2701 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS1; 2702 def : MipsInstAlias<"neg $rt", 2703 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>, ISA_MIPS1; 2704 def : MipsInstAlias<"negu $rt, $rs", 2705 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS1; 2706 def : MipsInstAlias<"negu $rt", 2707 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>, ISA_MIPS1; 2708 2709 def SGE : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 2710 (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 2711 "sge\t$rd, $rs, $rt">, ISA_MIPS1; 2712 def : MipsInstAlias<"sge $rs, $rt", 2713 (SGE GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>, 2714 ISA_MIPS1; 2715 def SGEImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 2716 (ins GPR32Opnd:$rs, simm32:$imm), 2717 "sge\t$rd, $rs, $imm">, GPR_32; 2718 def : MipsInstAlias<"sge $rs, $imm", (SGEImm GPR32Opnd:$rs, 2719 GPR32Opnd:$rs, 2720 simm32:$imm), 0>, 2721 GPR_32; 2722 2723 def SGEU : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 2724 (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 2725 "sgeu\t$rd, $rs, $rt">, ISA_MIPS1; 2726 def : MipsInstAlias<"sgeu $rs, $rt", 2727 (SGEU GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>, 2728 ISA_MIPS1; 2729 def SGEUImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 2730 (ins GPR32Opnd:$rs, uimm32_coerced:$imm), 2731 "sgeu\t$rd, $rs, $imm">, GPR_32; 2732 def : MipsInstAlias<"sgeu $rs, $imm", (SGEUImm GPR32Opnd:$rs, 2733 GPR32Opnd:$rs, 2734 uimm32_coerced:$imm), 0>, 2735 GPR_32; 2736 2737 def : MipsInstAlias< 2738 "sgt $rd, $rs, $rt", 2739 (SLT GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1; 2740 def : MipsInstAlias< 2741 "sgt $rs, $rt", 2742 (SLT GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1; 2743 2744 def SGTImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 2745 (ins GPR32Opnd:$rs, simm32:$imm), 2746 "sgt\t$rd, $rs, $imm">, GPR_32; 2747 def : MipsInstAlias<"sgt $rs, $imm", (SGTImm GPR32Opnd:$rs, 2748 GPR32Opnd:$rs, 2749 simm32:$imm), 0>, 2750 GPR_32; 2751 def : MipsInstAlias< 2752 "sgtu $rd, $rs, $rt", 2753 (SLTu GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1; 2754 def : MipsInstAlias< 2755 "sgtu $$rs, $rt", 2756 (SLTu GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1; 2757 2758 def SGTUImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 2759 (ins GPR32Opnd:$rs, uimm32_coerced:$imm), 2760 "sgtu\t$rd, $rs, $imm">, GPR_32; 2761 def : MipsInstAlias<"sgtu $rs, $imm", (SGTUImm GPR32Opnd:$rs, 2762 GPR32Opnd:$rs, 2763 uimm32_coerced:$imm), 0>, 2764 GPR_32; 2765 2766 def : MipsInstAlias< 2767 "not $rt, $rs", 2768 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>, ISA_MIPS1; 2769 def : MipsInstAlias< 2770 "not $rt", 2771 (NOR GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>, ISA_MIPS1; 2772 2773 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>, ISA_MIPS1; 2774 2775 defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi>, ISA_MIPS1_NOT_32R6_64R6; 2776 2777 defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu>, ISA_MIPS1; 2778 2779 defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi>, ISA_MIPS1, GPR_32; 2780 2781 defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi>, ISA_MIPS1, GPR_32; 2782 2783 defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi>, ISA_MIPS1, GPR_32; 2784 2785 defm : OneOrTwoOperandMacroImmediateAlias<"slt", SLTi>, ISA_MIPS1, GPR_32; 2786 2787 defm : OneOrTwoOperandMacroImmediateAlias<"sltu", SLTiu>, ISA_MIPS1, GPR_32; 2788 2789 def : MipsInstAlias<"mfgc0 $rt, $rd", 2790 (MFGC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>, 2791 ISA_MIPS32R5, ASE_VIRT; 2792 def : MipsInstAlias<"mtgc0 $rt, $rd", 2793 (MTGC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>, 2794 ISA_MIPS32R5, ASE_VIRT; 2795 def : MipsInstAlias<"mfhgc0 $rt, $rd", 2796 (MFHGC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>, 2797 ISA_MIPS32R5, ASE_VIRT; 2798 def : MipsInstAlias<"mthgc0 $rt, $rd", 2799 (MTHGC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>, 2800 ISA_MIPS32R5, ASE_VIRT; 2801 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>, 2802 ISA_MIPS1; 2803 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>, 2804 ISA_MIPS1; 2805 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, COP2Opnd:$rd, 0), 0>, 2806 ISA_MIPS1; 2807 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 COP2Opnd:$rd, GPR32Opnd:$rt, 0), 0>, 2808 ISA_MIPS1; 2809 2810 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>, 2811 ISA_MIPS1; 2812 2813 def : MipsInstAlias<"bnez $rs,$offset", 2814 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>, 2815 ISA_MIPS1; 2816 def : MipsInstAlias<"bnezl $rs, $offset", 2817 (BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset), 1>, 2818 ISA_MIPS2; 2819 def : MipsInstAlias<"beqz $rs,$offset", 2820 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>, 2821 ISA_MIPS1; 2822 def : MipsInstAlias<"beqzl $rs, $offset", 2823 (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 1>, 2824 ISA_MIPS2; 2825 2826 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>, ISA_MIPS1; 2827 2828 def : MipsInstAlias<"break", (BREAK 0, 0), 1>, ISA_MIPS1; 2829 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>, ISA_MIPS1; 2830 def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2; 2831 def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2; 2832 2833 def : MipsInstAlias<"teq $rs, $rt", 2834 (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; 2835 def : MipsInstAlias<"tge $rs, $rt", 2836 (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; 2837 def : MipsInstAlias<"tgeu $rs, $rt", 2838 (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; 2839 def : MipsInstAlias<"tlt $rs, $rt", 2840 (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; 2841 def : MipsInstAlias<"tltu $rs, $rt", 2842 (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; 2843 def : MipsInstAlias<"tne $rs, $rt", 2844 (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; 2845 def : MipsInstAlias<"rdhwr $rt, $rs", 2846 (RDHWR GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>, ISA_MIPS1; 2847 2848} 2849def : MipsInstAlias<"sub, $rd, $rs, $imm", 2850 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, 2851 InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6; 2852def : MipsInstAlias<"sub $rs, $imm", 2853 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm), 2854 0>, ISA_MIPS1_NOT_32R6_64R6; 2855def : MipsInstAlias<"subu, $rd, $rs, $imm", 2856 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, 2857 InvertedImOperand:$imm), 0>; 2858def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, 2859 InvertedImOperand:$imm), 0>; 2860let AdditionalPredicates = [NotInMicroMips] in { 2861 def : MipsInstAlias<"sll $rd, $rt, $rs", 2862 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; 2863 def : MipsInstAlias<"sra $rd, $rt, $rs", 2864 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; 2865 def : MipsInstAlias<"srl $rd, $rt, $rs", 2866 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; 2867 def : MipsInstAlias<"sll $rd, $rt", 2868 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>; 2869 def : MipsInstAlias<"sra $rd, $rt", 2870 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>; 2871 def : MipsInstAlias<"srl $rd, $rt", 2872 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>; 2873 def : MipsInstAlias<"seh $rd", (SEH GPR32Opnd:$rd, GPR32Opnd:$rd), 0>, 2874 ISA_MIPS32R2; 2875 def : MipsInstAlias<"seb $rd", (SEB GPR32Opnd:$rd, GPR32Opnd:$rd), 0>, 2876 ISA_MIPS32R2; 2877} 2878def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6; 2879let AdditionalPredicates = [NotInMicroMips] in 2880 def : MipsInstAlias<"sync", (SYNC 0), 1>, ISA_MIPS2; 2881 2882def : MipsInstAlias<"mulo $rs, $rt", 2883 (MULOMacro GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>, 2884 ISA_MIPS1_NOT_32R6_64R6; 2885def : MipsInstAlias<"mulou $rs, $rt", 2886 (MULOUMacro GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>, 2887 ISA_MIPS1_NOT_32R6_64R6; 2888 2889let AdditionalPredicates = [NotInMicroMips] in 2890 def : MipsInstAlias<"hypcall", (HYPCALL 0), 1>, ISA_MIPS32R5, ASE_VIRT; 2891 2892//===----------------------------------------------------------------------===// 2893// Assembler Pseudo Instructions 2894//===----------------------------------------------------------------------===// 2895 2896// We use uimm32_coerced to accept a 33 bit signed number that is rendered into 2897// a 32 bit number. 2898class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> : 2899 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 2900 !strconcat(instr_asm, "\t$rt, $imm32")> ; 2901def LoadImm32 : LoadImmediate32<"li", uimm32_coerced, GPR32Opnd>; 2902 2903class LoadAddressFromReg32<string instr_asm, Operand MemOpnd, 2904 RegisterOperand RO> : 2905 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), 2906 !strconcat(instr_asm, "\t$rt, $addr")> ; 2907def LoadAddrReg32 : LoadAddressFromReg32<"la", mem, GPR32Opnd>; 2908 2909class LoadAddressFromImm32<string instr_asm, Operand Od, RegisterOperand RO> : 2910 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 2911 !strconcat(instr_asm, "\t$rt, $imm32")> ; 2912def LoadAddrImm32 : LoadAddressFromImm32<"la", i32imm, GPR32Opnd>; 2913 2914def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs), 2915 "jal\t$rd, $rs"> ; 2916def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs), 2917 "jal\t$rs"> ; 2918 2919class NORIMM_DESC_BASE<RegisterOperand RO, DAGOperand Imm> : 2920 MipsAsmPseudoInst<(outs RO:$rs), (ins RO:$rt, Imm:$imm), 2921 "nor\t$rs, $rt, $imm">; 2922def NORImm : NORIMM_DESC_BASE<GPR32Opnd, simm32_relaxed>, GPR_32; 2923def : MipsInstAlias<"nor\t$rs, $imm", (NORImm GPR32Opnd:$rs, GPR32Opnd:$rs, 2924 simm32_relaxed:$imm)>, GPR_32; 2925 2926let hasDelaySlot = 1, isCTI = 1 in { 2927def BneImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), 2928 (ins imm64:$imm64, brtarget:$offset), 2929 "bne\t$rt, $imm64, $offset">; 2930def BeqImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), 2931 (ins imm64:$imm64, brtarget:$offset), 2932 "beq\t$rt, $imm64, $offset">; 2933 2934class CondBranchPseudo<string instr_asm> : 2935 MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, 2936 brtarget:$offset), 2937 !strconcat(instr_asm, "\t$rs, $rt, $offset")>; 2938} 2939 2940def BLT : CondBranchPseudo<"blt">; 2941def BLE : CondBranchPseudo<"ble">; 2942def BGE : CondBranchPseudo<"bge">; 2943def BGT : CondBranchPseudo<"bgt">; 2944def BLTU : CondBranchPseudo<"bltu">; 2945def BLEU : CondBranchPseudo<"bleu">; 2946def BGEU : CondBranchPseudo<"bgeu">; 2947def BGTU : CondBranchPseudo<"bgtu">; 2948def BLTL : CondBranchPseudo<"bltl">, ISA_MIPS2_NOT_32R6_64R6; 2949def BLEL : CondBranchPseudo<"blel">, ISA_MIPS2_NOT_32R6_64R6; 2950def BGEL : CondBranchPseudo<"bgel">, ISA_MIPS2_NOT_32R6_64R6; 2951def BGTL : CondBranchPseudo<"bgtl">, ISA_MIPS2_NOT_32R6_64R6; 2952def BLTUL: CondBranchPseudo<"bltul">, ISA_MIPS2_NOT_32R6_64R6; 2953def BLEUL: CondBranchPseudo<"bleul">, ISA_MIPS2_NOT_32R6_64R6; 2954def BGEUL: CondBranchPseudo<"bgeul">, ISA_MIPS2_NOT_32R6_64R6; 2955def BGTUL: CondBranchPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6; 2956 2957let isCTI = 1 in 2958class CondBranchImmPseudo<string instr_asm> : 2959 MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, imm64:$imm, brtarget:$offset), 2960 !strconcat(instr_asm, "\t$rs, $imm, $offset")>; 2961 2962def BEQLImmMacro : CondBranchImmPseudo<"beql">, ISA_MIPS2_NOT_32R6_64R6; 2963def BNELImmMacro : CondBranchImmPseudo<"bnel">, ISA_MIPS2_NOT_32R6_64R6; 2964 2965def BLTImmMacro : CondBranchImmPseudo<"blt">; 2966def BLEImmMacro : CondBranchImmPseudo<"ble">; 2967def BGEImmMacro : CondBranchImmPseudo<"bge">; 2968def BGTImmMacro : CondBranchImmPseudo<"bgt">; 2969def BLTUImmMacro : CondBranchImmPseudo<"bltu">; 2970def BLEUImmMacro : CondBranchImmPseudo<"bleu">; 2971def BGEUImmMacro : CondBranchImmPseudo<"bgeu">; 2972def BGTUImmMacro : CondBranchImmPseudo<"bgtu">; 2973def BLTLImmMacro : CondBranchImmPseudo<"bltl">, ISA_MIPS2_NOT_32R6_64R6; 2974def BLELImmMacro : CondBranchImmPseudo<"blel">, ISA_MIPS2_NOT_32R6_64R6; 2975def BGELImmMacro : CondBranchImmPseudo<"bgel">, ISA_MIPS2_NOT_32R6_64R6; 2976def BGTLImmMacro : CondBranchImmPseudo<"bgtl">, ISA_MIPS2_NOT_32R6_64R6; 2977def BLTULImmMacro : CondBranchImmPseudo<"bltul">, ISA_MIPS2_NOT_32R6_64R6; 2978def BLEULImmMacro : CondBranchImmPseudo<"bleul">, ISA_MIPS2_NOT_32R6_64R6; 2979def BGEULImmMacro : CondBranchImmPseudo<"bgeul">, ISA_MIPS2_NOT_32R6_64R6; 2980def BGTULImmMacro : CondBranchImmPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6; 2981 2982// FIXME: Predicates are removed because instructions are matched regardless of 2983// predicates, because PredicateControl was not in the hierarchy. This was 2984// done to emit more precise error message from expansion function. 2985// Once the tablegen-erated errors are made better, this needs to be fixed and 2986// predicates needs to be restored. 2987 2988def SDivMacro : MipsAsmPseudoInst<(outs GPR32NonZeroOpnd:$rd), 2989 (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 2990 "div\t$rd, $rs, $rt">, 2991 ISA_MIPS1_NOT_32R6_64R6; 2992def SDivIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 2993 (ins GPR32Opnd:$rs, simm32:$imm), 2994 "div\t$rd, $rs, $imm">, 2995 ISA_MIPS1_NOT_32R6_64R6; 2996def UDivMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 2997 (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 2998 "divu\t$rd, $rs, $rt">, 2999 ISA_MIPS1_NOT_32R6_64R6; 3000def UDivIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 3001 (ins GPR32Opnd:$rs, simm32:$imm), 3002 "divu\t$rd, $rs, $imm">, 3003 ISA_MIPS1_NOT_32R6_64R6; 3004 3005 3006def : MipsInstAlias<"div $rs, $rt", (SDIV GPR32ZeroOpnd:$rs, 3007 GPR32Opnd:$rt), 0>, 3008 ISA_MIPS1_NOT_32R6_64R6; 3009def : MipsInstAlias<"div $rs, $rt", (SDivMacro GPR32NonZeroOpnd:$rs, 3010 GPR32NonZeroOpnd:$rs, 3011 GPR32Opnd:$rt), 0>, 3012 ISA_MIPS1_NOT_32R6_64R6; 3013def : MipsInstAlias<"div $rd, $imm", (SDivIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, 3014 simm32:$imm), 0>, 3015 ISA_MIPS1_NOT_32R6_64R6; 3016 3017def : MipsInstAlias<"divu $rt, $rs", (UDIV GPR32ZeroOpnd:$rt, 3018 GPR32Opnd:$rs), 0>, 3019 ISA_MIPS1_NOT_32R6_64R6; 3020def : MipsInstAlias<"divu $rt, $rs", (UDivMacro GPR32NonZeroOpnd:$rt, 3021 GPR32NonZeroOpnd:$rt, 3022 GPR32Opnd:$rs), 0>, 3023 ISA_MIPS1_NOT_32R6_64R6; 3024 3025def : MipsInstAlias<"divu $rd, $imm", (UDivIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, 3026 simm32:$imm), 0>, 3027 ISA_MIPS1_NOT_32R6_64R6; 3028 3029def SRemMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 3030 (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 3031 "rem\t$rd, $rs, $rt">, 3032 ISA_MIPS1_NOT_32R6_64R6; 3033def SRemIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 3034 (ins GPR32Opnd:$rs, simm32_relaxed:$imm), 3035 "rem\t$rd, $rs, $imm">, 3036 ISA_MIPS1_NOT_32R6_64R6; 3037def URemMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 3038 (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 3039 "remu\t$rd, $rs, $rt">, 3040 ISA_MIPS1_NOT_32R6_64R6; 3041def URemIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 3042 (ins GPR32Opnd:$rs, simm32_relaxed:$imm), 3043 "remu\t$rd, $rs, $imm">, 3044 ISA_MIPS1_NOT_32R6_64R6; 3045 3046def : MipsInstAlias<"rem $rt, $rs", (SRemMacro GPR32Opnd:$rt, GPR32Opnd:$rt, 3047 GPR32Opnd:$rs), 0>, 3048 ISA_MIPS1_NOT_32R6_64R6; 3049def : MipsInstAlias<"rem $rd, $imm", (SRemIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, 3050 simm32_relaxed:$imm), 0>, 3051 ISA_MIPS1_NOT_32R6_64R6; 3052def : MipsInstAlias<"remu $rt, $rs", (URemMacro GPR32Opnd:$rt, GPR32Opnd:$rt, 3053 GPR32Opnd:$rs), 0>, 3054 ISA_MIPS1_NOT_32R6_64R6; 3055def : MipsInstAlias<"remu $rd, $imm", (URemIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, 3056 simm32_relaxed:$imm), 0>, 3057 ISA_MIPS1_NOT_32R6_64R6; 3058 3059def Ulh : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), 3060 "ulh\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6; 3061 3062def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), 3063 "ulhu\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6; 3064 3065def Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), 3066 "ulw\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6; 3067 3068def Ush : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), 3069 "ush\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6; 3070 3071def Usw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), 3072 "usw\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6; 3073 3074def LDMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), 3075 (ins mem_simm16:$addr), "ld $rt, $addr">, 3076 ISA_MIPS1_NOT_MIPS3; 3077def SDMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), 3078 (ins mem_simm16:$addr), "sd $rt, $addr">, 3079 ISA_MIPS1_NOT_MIPS3; 3080//===----------------------------------------------------------------------===// 3081// Arbitrary patterns that map to one or more instructions 3082//===----------------------------------------------------------------------===// 3083 3084// Load/store pattern templates. 3085class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> : 3086 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>; 3087 3088class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> : 3089 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>; 3090 3091// Materialize constants. 3092multiclass MaterializeImms<ValueType VT, Register ZEROReg, 3093 Instruction ADDiuOp, Instruction LUiOp, 3094 Instruction ORiOp> { 3095 3096// Constant synthesis previously relied on the ordering of the patterns below. 3097// By making the predicates they use non-overlapping, the patterns were 3098// reordered so that the effect of the newly introduced predicates can be 3099// observed. 3100 3101// Arbitrary immediates 3102def : MipsPat<(VT LUiORiPred:$imm), (ORiOp (LUiOp (HI16 imm:$imm)), (LO16 imm:$imm))>; 3103 3104// Bits 32-16 set, sign/zero extended. 3105def : MipsPat<(VT LUiPred:$imm), (LUiOp (HI16 imm:$imm))>; 3106 3107// Small immediates 3108def : MipsPat<(VT ORiPred:$imm), (ORiOp ZEROReg, imm:$imm)>; 3109def : MipsPat<(VT immSExt16:$imm), (ADDiuOp ZEROReg, imm:$imm)>; 3110} 3111 3112let AdditionalPredicates = [NotInMicroMips] in 3113 defm : MaterializeImms<i32, ZERO, ADDiu, LUi, ORi>, ISA_MIPS1; 3114 3115// Carry MipsPatterns 3116let AdditionalPredicates = [NotInMicroMips] in { 3117 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), 3118 (SUBu GPR32:$lhs, GPR32:$rhs)>, ISA_MIPS1; 3119} 3120def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs), 3121 (ADDu GPR32:$lhs, GPR32:$rhs)>, ISA_MIPS1, ASE_NOT_DSP; 3122def : MipsPat<(addc GPR32:$src, immSExt16:$imm), 3123 (ADDiu GPR32:$src, imm:$imm)>, ISA_MIPS1, ASE_NOT_DSP; 3124 3125// Support multiplication for pre-Mips32 targets that don't have 3126// the MUL instruction. 3127def : MipsPat<(mul GPR32:$lhs, GPR32:$rhs), 3128 (PseudoMFLO (PseudoMULT GPR32:$lhs, GPR32:$rhs))>, 3129 ISA_MIPS1_NOT_32R6_64R6; 3130 3131// SYNC 3132def : MipsPat<(MipsSync (i32 immz)), 3133 (SYNC 0)>, ISA_MIPS2; 3134 3135// Call 3136def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 3137 (JAL texternalsym:$dst)>, ISA_MIPS1; 3138//def : MipsPat<(MipsJmpLink GPR32:$dst), 3139// (JALR GPR32:$dst)>; 3140 3141// Tail call 3142let AdditionalPredicates = [NotInMicroMips] in { 3143 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 3144 (TAILCALL tglobaladdr:$dst)>, ISA_MIPS1; 3145 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 3146 (TAILCALL texternalsym:$dst)>, ISA_MIPS1; 3147} 3148// hi/lo relocs 3149multiclass MipsHiLoRelocs<Instruction Lui, Instruction Addiu, 3150 Register ZeroReg, RegisterOperand GPROpnd> { 3151 def : MipsPat<(MipsHi tglobaladdr:$in), (Lui tglobaladdr:$in)>; 3152 def : MipsPat<(MipsHi tblockaddress:$in), (Lui tblockaddress:$in)>; 3153 def : MipsPat<(MipsHi tjumptable:$in), (Lui tjumptable:$in)>; 3154 def : MipsPat<(MipsHi tconstpool:$in), (Lui tconstpool:$in)>; 3155 def : MipsPat<(MipsHi texternalsym:$in), (Lui texternalsym:$in)>; 3156 3157 def : MipsPat<(MipsLo tglobaladdr:$in), (Addiu ZeroReg, tglobaladdr:$in)>; 3158 def : MipsPat<(MipsLo tblockaddress:$in), 3159 (Addiu ZeroReg, tblockaddress:$in)>; 3160 def : MipsPat<(MipsLo tjumptable:$in), (Addiu ZeroReg, tjumptable:$in)>; 3161 def : MipsPat<(MipsLo tconstpool:$in), (Addiu ZeroReg, tconstpool:$in)>; 3162 def : MipsPat<(MipsLo tglobaltlsaddr:$in), 3163 (Addiu ZeroReg, tglobaltlsaddr:$in)>; 3164 def : MipsPat<(MipsLo texternalsym:$in), (Addiu ZeroReg, texternalsym:$in)>; 3165 3166 def : MipsPat<(add GPROpnd:$hi, (MipsLo tglobaladdr:$lo)), 3167 (Addiu GPROpnd:$hi, tglobaladdr:$lo)>; 3168 def : MipsPat<(add GPROpnd:$hi, (MipsLo tblockaddress:$lo)), 3169 (Addiu GPROpnd:$hi, tblockaddress:$lo)>; 3170 def : MipsPat<(add GPROpnd:$hi, (MipsLo tjumptable:$lo)), 3171 (Addiu GPROpnd:$hi, tjumptable:$lo)>; 3172 def : MipsPat<(add GPROpnd:$hi, (MipsLo tconstpool:$lo)), 3173 (Addiu GPROpnd:$hi, tconstpool:$lo)>; 3174 def : MipsPat<(add GPROpnd:$hi, (MipsLo tglobaltlsaddr:$lo)), 3175 (Addiu GPROpnd:$hi, tglobaltlsaddr:$lo)>; 3176 def : MipsPat<(add GPROpnd:$hi, (MipsLo texternalsym:$lo)), 3177 (Addiu GPROpnd:$hi, texternalsym:$lo)>; 3178} 3179 3180// wrapper_pic 3181class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 3182 MipsPat<(MipsWrapper RC:$gp, node:$in), (ADDiuOp RC:$gp, node:$in)>; 3183 3184let AdditionalPredicates = [NotInMicroMips] in { 3185 defm : MipsHiLoRelocs<LUi, ADDiu, ZERO, GPR32Opnd>, ISA_MIPS1; 3186 3187 def : MipsPat<(MipsGotHi tglobaladdr:$in), (LUi tglobaladdr:$in)>, ISA_MIPS1; 3188 def : MipsPat<(MipsGotHi texternalsym:$in), (LUi texternalsym:$in)>, 3189 ISA_MIPS1; 3190 3191 def : MipsPat<(MipsTlsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>, 3192 ISA_MIPS1; 3193 3194 // gp_rel relocs 3195 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)), 3196 (ADDiu GPR32:$gp, tglobaladdr:$in)>, ISA_MIPS1, ABI_NOT_N64; 3197 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)), 3198 (ADDiu GPR32:$gp, tconstpool:$in)>, ISA_MIPS1, ABI_NOT_N64; 3199 3200 def : WrapperPat<tglobaladdr, ADDiu, GPR32>, ISA_MIPS1; 3201 def : WrapperPat<tconstpool, ADDiu, GPR32>, ISA_MIPS1; 3202 def : WrapperPat<texternalsym, ADDiu, GPR32>, ISA_MIPS1; 3203 def : WrapperPat<tblockaddress, ADDiu, GPR32>, ISA_MIPS1; 3204 def : WrapperPat<tjumptable, ADDiu, GPR32>, ISA_MIPS1; 3205 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>, ISA_MIPS1; 3206 3207 // Mips does not have "not", so we expand our way 3208 def : MipsPat<(not GPR32:$in), 3209 (NOR GPR32Opnd:$in, ZERO)>, ISA_MIPS1; 3210} 3211 3212// extended loads 3213let AdditionalPredicates = [NotInMicroMips] in { 3214 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>, ISA_MIPS1; 3215 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>, ISA_MIPS1; 3216 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>, ISA_MIPS1; 3217 3218 // peepholes 3219 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>, ISA_MIPS1; 3220} 3221 3222// brcond patterns 3223multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BEQOp1, 3224 Instruction BNEOp, Instruction SLTOp, Instruction SLTuOp, 3225 Instruction SLTiOp, Instruction SLTiuOp, 3226 Register ZEROReg> { 3227def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 3228 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 3229def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 3230 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 3231 3232def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 3233 (BEQOp1 (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 3234def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 3235 (BEQOp1 (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 3236def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 3237 (BEQOp1 (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 3238def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 3239 (BEQOp1 (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 3240def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 3241 (BEQOp1 (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 3242def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 3243 (BEQOp1 (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 3244 3245def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 3246 (BEQOp1 (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 3247def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 3248 (BEQOp1 (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 3249 3250def : MipsPat<(brcond RC:$cond, bb:$dst), 3251 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 3252} 3253let AdditionalPredicates = [NotInMicroMips] in { 3254 defm : BrcondPats<GPR32, BEQ, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>, 3255 ISA_MIPS1; 3256 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst), 3257 (BLEZ i32:$lhs, bb:$dst)>, ISA_MIPS1; 3258 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst), 3259 (BGEZ i32:$lhs, bb:$dst)>, ISA_MIPS1; 3260} 3261 3262// setcc patterns 3263multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 3264 Instruction SLTuOp, Register ZEROReg> { 3265 def : MipsPat<(seteq RC:$lhs, 0), 3266 (SLTiuOp RC:$lhs, 1)>; 3267 def : MipsPat<(setne RC:$lhs, 0), 3268 (SLTuOp ZEROReg, RC:$lhs)>; 3269 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 3270 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 3271 def : MipsPat<(setne RC:$lhs, RC:$rhs), 3272 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 3273} 3274 3275multiclass SetlePats<RegisterClass RC, Instruction XORiOp, Instruction SLTOp, 3276 Instruction SLTuOp> { 3277 def : MipsPat<(setle RC:$lhs, RC:$rhs), 3278 (XORiOp (SLTOp RC:$rhs, RC:$lhs), 1)>; 3279 def : MipsPat<(setule RC:$lhs, RC:$rhs), 3280 (XORiOp (SLTuOp RC:$rhs, RC:$lhs), 1)>; 3281} 3282 3283multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 3284 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 3285 (SLTOp RC:$rhs, RC:$lhs)>; 3286 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 3287 (SLTuOp RC:$rhs, RC:$lhs)>; 3288} 3289 3290multiclass SetgePats<RegisterClass RC, Instruction XORiOp, Instruction SLTOp, 3291 Instruction SLTuOp> { 3292 def : MipsPat<(setge RC:$lhs, RC:$rhs), 3293 (XORiOp (SLTOp RC:$lhs, RC:$rhs), 1)>; 3294 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 3295 (XORiOp (SLTuOp RC:$lhs, RC:$rhs), 1)>; 3296} 3297 3298multiclass SetgeImmPats<RegisterClass RC, Instruction XORiOp, 3299 Instruction SLTiOp, Instruction SLTiuOp> { 3300 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 3301 (XORiOp (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 3302 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 3303 (XORiOp (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 3304} 3305 3306let AdditionalPredicates = [NotInMicroMips] in { 3307 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>, ISA_MIPS1; 3308 defm : SetlePats<GPR32, XORi, SLT, SLTu>, ISA_MIPS1; 3309 defm : SetgtPats<GPR32, SLT, SLTu>, ISA_MIPS1; 3310 defm : SetgePats<GPR32, XORi, SLT, SLTu>, ISA_MIPS1; 3311 defm : SetgeImmPats<GPR32, XORi, SLTi, SLTiu>, ISA_MIPS1; 3312 3313 // bswap pattern 3314 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>, ISA_MIPS32R2; 3315} 3316 3317// Load halfword/word patterns. 3318let AdditionalPredicates = [NotInMicroMips] in { 3319 let AddedComplexity = 40 in { 3320 def : LoadRegImmPat<LBu, i32, zextloadi8>, ISA_MIPS1; 3321 def : LoadRegImmPat<LHu, i32, zextloadi16>, ISA_MIPS1; 3322 def : LoadRegImmPat<LB, i32, sextloadi8>, ISA_MIPS1; 3323 def : LoadRegImmPat<LH, i32, sextloadi16>, ISA_MIPS1; 3324 def : LoadRegImmPat<LW, i32, load>, ISA_MIPS1; 3325 } 3326 3327 // Atomic load patterns. 3328 def : MipsPat<(atomic_load_8 addr:$a), (LB addr:$a)>, ISA_MIPS1; 3329 def : MipsPat<(atomic_load_16 addr:$a), (LH addr:$a)>, ISA_MIPS1; 3330 def : MipsPat<(atomic_load_32 addr:$a), (LW addr:$a)>, ISA_MIPS1; 3331 3332 // Atomic store patterns. 3333 def : MipsPat<(atomic_store_8 addr:$a, GPR32:$v), (SB GPR32:$v, addr:$a)>, 3334 ISA_MIPS1; 3335 def : MipsPat<(atomic_store_16 addr:$a, GPR32:$v), (SH GPR32:$v, addr:$a)>, 3336 ISA_MIPS1; 3337 def : MipsPat<(atomic_store_32 addr:$a, GPR32:$v), (SW GPR32:$v, addr:$a)>, 3338 ISA_MIPS1; 3339} 3340 3341//===----------------------------------------------------------------------===// 3342// Floating Point Support 3343//===----------------------------------------------------------------------===// 3344 3345include "MipsInstrFPU.td" 3346include "Mips64InstrInfo.td" 3347include "MipsCondMov.td" 3348 3349include "Mips32r6InstrInfo.td" 3350include "Mips64r6InstrInfo.td" 3351 3352// 3353// Mips16 3354 3355include "Mips16InstrFormats.td" 3356include "Mips16InstrInfo.td" 3357 3358// DSP 3359include "MipsDSPInstrFormats.td" 3360include "MipsDSPInstrInfo.td" 3361 3362// MSA 3363include "MipsMSAInstrFormats.td" 3364include "MipsMSAInstrInfo.td" 3365 3366// EVA 3367include "MipsEVAInstrFormats.td" 3368include "MipsEVAInstrInfo.td" 3369 3370// MT 3371include "MipsMTInstrFormats.td" 3372include "MipsMTInstrInfo.td" 3373 3374// Micromips 3375include "MicroMipsInstrFormats.td" 3376include "MicroMipsInstrInfo.td" 3377include "MicroMipsInstrFPU.td" 3378 3379// Micromips r6 3380include "MicroMips32r6InstrFormats.td" 3381include "MicroMips32r6InstrInfo.td" 3382 3383// Micromips DSP 3384include "MicroMipsDSPInstrFormats.td" 3385include "MicroMipsDSPInstrInfo.td" 3386