1//===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the Mips FPU instruction set. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Floating Point Instructions 15// ------------------------ 16// * 64bit fp: 17// - 32 64-bit registers (default mode) 18// - 16 even 32-bit registers (32-bit compatible mode) for 19// single and double access. 20// * 32bit fp: 21// - 16 even 32-bit registers - single and double (aliased) 22// - 32 32-bit registers (within single-only mode) 23//===----------------------------------------------------------------------===// 24 25// Floating Point Compare and Branch 26def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>, 27 SDTCisVT<1, i32>, 28 SDTCisVT<2, OtherVT>]>; 29def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>, 30 SDTCisVT<2, i32>]>; 31def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>, 32 SDTCisSameAs<1, 3>]>; 33def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>; 34def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, 35 SDTCisVT<1, i32>, 36 SDTCisSameAs<1, 2>]>; 37def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 38 SDTCisVT<1, f64>, 39 SDTCisVT<2, i32>]>; 40 41def SDT_MipsMTC1_D64 : SDTypeProfile<1, 1, [SDTCisVT<0, f64>, 42 SDTCisVT<1, i32>]>; 43 44def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>; 45def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>; 46def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>; 47def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond, 48 [SDNPHasChain, SDNPOptInGlue]>; 49def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>; 50def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>; 51def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64", 52 SDT_MipsExtractElementF64>; 53 54def MipsMTC1_D64 : SDNode<"MipsISD::MTC1_D64", SDT_MipsMTC1_D64>; 55 56// Operand for printing out a condition code. 57let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in 58 def condcode : Operand<i32>; 59 60//===----------------------------------------------------------------------===// 61// Feature predicates. 62//===----------------------------------------------------------------------===// 63 64def IsFP64bit : Predicate<"Subtarget->isFP64bit()">, 65 AssemblerPredicate<"FeatureFP64Bit">; 66def NotFP64bit : Predicate<"!Subtarget->isFP64bit()">, 67 AssemblerPredicate<"!FeatureFP64Bit">; 68def IsSingleFloat : Predicate<"Subtarget->isSingleFloat()">, 69 AssemblerPredicate<"FeatureSingleFloat">; 70def IsNotSingleFloat : Predicate<"!Subtarget->isSingleFloat()">, 71 AssemblerPredicate<"!FeatureSingleFloat">; 72def IsNotSoftFloat : Predicate<"!Subtarget->useSoftFloat()">, 73 AssemblerPredicate<"!FeatureSoftFloat">; 74 75//===----------------------------------------------------------------------===// 76// Mips FGR size adjectives. 77// They are mutually exclusive. 78//===----------------------------------------------------------------------===// 79 80class FGR_32 { list<Predicate> FGRPredicates = [NotFP64bit]; } 81class FGR_64 { list<Predicate> FGRPredicates = [IsFP64bit]; } 82class HARDFLOAT { list<Predicate> HardFloatPredicate = [IsNotSoftFloat]; } 83 84//===----------------------------------------------------------------------===// 85 86// FP immediate patterns. 87def fpimm0 : PatLeaf<(fpimm), [{ 88 return N->isExactlyValue(+0.0); 89}]>; 90 91def fpimm0neg : PatLeaf<(fpimm), [{ 92 return N->isExactlyValue(-0.0); 93}]>; 94 95//===----------------------------------------------------------------------===// 96// Instruction Class Templates 97// 98// A set of multiclasses is used to address the register usage. 99// 100// S32 - single precision in 16 32bit even fp registers 101// single precision in 32 32bit fp registers in SingleOnly mode 102// S64 - single precision in 32 64bit fp registers (In64BitMode) 103// D32 - double precision in 16 32bit even fp registers 104// D64 - double precision in 32 64bit fp registers (In64BitMode) 105// 106// Only S32 and D32 are supported right now. 107//===----------------------------------------------------------------------===// 108class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm, 109 SDPatternOperator OpNode= null_frag> : 110 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft), 111 !strconcat(opstr, "\t$fd, $fs, $ft"), 112 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>, 113 HARDFLOAT { 114 let isCommutable = IsComm; 115} 116 117multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm, 118 SDPatternOperator OpNode = null_frag> { 119 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, FGR_32; 120 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 { 121 string DecoderNamespace = "MipsFP64"; 122 } 123} 124 125class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 126 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 127 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"), 128 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, 129 HARDFLOAT, 130 NeverHasSideEffects; 131 132class CVT_PS_S_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 133 InstrItinClass Itin, bit IsComm, 134 SDPatternOperator OpNode = null_frag> : 135 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs, SrcRC:$ft), 136 !strconcat(opstr, "\t$fd, $fs, $ft"), 137 [(set DstRC:$fd, (OpNode SrcRC:$fs, SrcRC:$ft))], Itin, FrmFR, opstr>, 138 HARDFLOAT { 139 let isCommutable = IsComm; 140} 141 142multiclass ABSS_M<string opstr, InstrItinClass Itin, 143 SDPatternOperator OpNode= null_frag> { 144 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>, 145 FGR_32; 146 def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, 147 FGR_64 { 148 string DecoderNamespace = "MipsFP64"; 149 } 150} 151 152multiclass ROUND_M<string opstr, InstrItinClass Itin> { 153 def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>, FGR_32; 154 def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>, FGR_64 { 155 let DecoderNamespace = "MipsFP64"; 156 } 157} 158 159class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 160 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 161 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"), 162 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT { 163 let isMoveReg = 1; 164} 165 166class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 167 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 168 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"), 169 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>, HARDFLOAT { 170 let isMoveReg = 1; 171} 172 173class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 174 InstrItinClass Itin> : 175 InstSE<(outs DstRC:$fs), (ins DstRC:$fs_in, SrcRC:$rt), 176 !strconcat(opstr, "\t$rt, $fs"), [], Itin, FrmFR, opstr>, HARDFLOAT { 177 // $fs_in is part of a white lie to work around a widespread bug in the FPU 178 // implementation. See expandBuildPairF64 for details. 179 let Constraints = "$fs = $fs_in"; 180} 181 182class LW_FT<string opstr, RegisterOperand RC, DAGOperand MO, 183 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 184 InstSE<(outs RC:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"), 185 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr>, 186 HARDFLOAT { 187 let DecoderMethod = "DecodeFMem"; 188 let mayLoad = 1; 189} 190 191class SW_FT<string opstr, RegisterOperand RC, DAGOperand MO, 192 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 193 InstSE<(outs), (ins RC:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"), 194 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr>, HARDFLOAT { 195 let DecoderMethod = "DecodeFMem"; 196 let mayStore = 1; 197} 198 199class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 200 SDPatternOperator OpNode = null_frag> : 201 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 202 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 203 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, 204 FrmFR, opstr>, HARDFLOAT; 205 206class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 207 SDPatternOperator OpNode = null_frag> : 208 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 209 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 210 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))], 211 Itin, FrmFR, opstr>, HARDFLOAT; 212 213class LWXC1_FT<string opstr, RegisterOperand DRC, 214 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 215 InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index), 216 !strconcat(opstr, "\t$fd, ${index}(${base})"), 217 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin, 218 FrmFI, opstr>, HARDFLOAT { 219 let AddedComplexity = 20; 220} 221 222class SWXC1_FT<string opstr, RegisterOperand DRC, 223 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 224 InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index), 225 !strconcat(opstr, "\t$fs, ${index}(${base})"), 226 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin, 227 FrmFI, opstr>, HARDFLOAT { 228 let AddedComplexity = 20; 229} 230 231class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin, 232 SDPatternOperator Op = null_frag> : 233 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset), 234 !strconcat(opstr, "\t$fcc, $offset"), 235 [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin, 236 FrmFI, opstr>, HARDFLOAT { 237 let isBranch = 1; 238 let isTerminator = 1; 239 let hasDelaySlot = 1; 240 let Defs = [AT]; 241 let hasFCCRegOperand = 1; 242} 243 244class BC1XL_FT<string opstr, DAGOperand opnd, InstrItinClass Itin> : 245 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset), 246 !strconcat(opstr, "\t$fcc, $offset"), [], Itin, 247 FrmFI, opstr>, HARDFLOAT { 248 let isBranch = 1; 249 let isTerminator = 1; 250 let hasDelaySlot = 1; 251 let Defs = [AT]; 252 let hasFCCRegOperand = 1; 253} 254 255class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin, 256 SDPatternOperator OpNode = null_frag> : 257 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond), 258 !strconcat("c.$cond.", typestr, "\t$fs, $ft"), 259 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR, 260 !strconcat("c.$cond.", typestr)>, HARDFLOAT { 261 let Defs = [FCC0]; 262 let isCodeGenOnly = 1; 263 let hasFCCRegOperand = 1; 264} 265 266 267// Note: MIPS-IV introduced $fcc1-$fcc7 and renamed FCSR31[23] $fcc0. Rather 268// duplicating the instruction definition for MIPS1 - MIPS3, we expand 269// c.cond.ft if necessary, and reject it after constructing the 270// instruction if the ISA doesn't support it. 271class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC, 272 InstrItinClass itin> : 273 InstSE<(outs FCCRegsOpnd:$fcc), (ins RC:$fs, RC:$ft), 274 !strconcat("c.", CondStr, ".", Typestr, "\t$fcc, $fs, $ft"), [], itin, 275 FrmFR>, HARDFLOAT { 276 let isCompare = 1; 277 let hasFCCRegOperand = 1; 278} 279 280 281multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt, 282 InstrItinClass itin> { 283 def C_F_#NAME : MMRel, C_COND_FT<"f", TypeStr, RC, itin>, 284 C_COND_FM<fmt, 0> { 285 let BaseOpcode = "c.f."#NAME; 286 let isCommutable = 1; 287 } 288 def C_UN_#NAME : MMRel, C_COND_FT<"un", TypeStr, RC, itin>, 289 C_COND_FM<fmt, 1> { 290 let BaseOpcode = "c.un."#NAME; 291 let isCommutable = 1; 292 } 293 def C_EQ_#NAME : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>, 294 C_COND_FM<fmt, 2> { 295 let BaseOpcode = "c.eq."#NAME; 296 let isCommutable = 1; 297 } 298 def C_UEQ_#NAME : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>, 299 C_COND_FM<fmt, 3> { 300 let BaseOpcode = "c.ueq."#NAME; 301 let isCommutable = 1; 302 } 303 def C_OLT_#NAME : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>, 304 C_COND_FM<fmt, 4> { 305 let BaseOpcode = "c.olt."#NAME; 306 } 307 def C_ULT_#NAME : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>, 308 C_COND_FM<fmt, 5> { 309 let BaseOpcode = "c.ult."#NAME; 310 } 311 def C_OLE_#NAME : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>, 312 C_COND_FM<fmt, 6> { 313 let BaseOpcode = "c.ole."#NAME; 314 } 315 def C_ULE_#NAME : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>, 316 C_COND_FM<fmt, 7> { 317 let BaseOpcode = "c.ule."#NAME; 318 } 319 def C_SF_#NAME : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>, 320 C_COND_FM<fmt, 8> { 321 let BaseOpcode = "c.sf."#NAME; 322 let isCommutable = 1; 323 } 324 def C_NGLE_#NAME : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>, 325 C_COND_FM<fmt, 9> { 326 let BaseOpcode = "c.ngle."#NAME; 327 } 328 def C_SEQ_#NAME : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>, 329 C_COND_FM<fmt, 10> { 330 let BaseOpcode = "c.seq."#NAME; 331 let isCommutable = 1; 332 } 333 def C_NGL_#NAME : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>, 334 C_COND_FM<fmt, 11> { 335 let BaseOpcode = "c.ngl."#NAME; 336 } 337 def C_LT_#NAME : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>, 338 C_COND_FM<fmt, 12> { 339 let BaseOpcode = "c.lt."#NAME; 340 } 341 def C_NGE_#NAME : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>, 342 C_COND_FM<fmt, 13> { 343 let BaseOpcode = "c.nge."#NAME; 344 } 345 def C_LE_#NAME : MMRel, C_COND_FT<"le", TypeStr, RC, itin>, 346 C_COND_FM<fmt, 14> { 347 let BaseOpcode = "c.le."#NAME; 348 } 349 def C_NGT_#NAME : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>, 350 C_COND_FM<fmt, 15> { 351 let BaseOpcode = "c.ngt."#NAME; 352 } 353} 354 355let AdditionalPredicates = [NotInMicroMips] in { 356defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6; 357defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, 358 FGR_32; 359let DecoderNamespace = "MipsFP64" in 360defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, 361 FGR_64; 362} 363//===----------------------------------------------------------------------===// 364// Floating Point Instructions 365//===----------------------------------------------------------------------===// 366let AdditionalPredicates = [NotInMicroMips] in { 367 def ROUND_W_S : MMRel, StdMMR6Rel, 368 ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>, 369 ABSS_FM<0xc, 16>, ISA_MIPS2; 370 defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2; 371 def TRUNC_W_S : MMRel, StdMMR6Rel, 372 ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>, 373 ABSS_FM<0xd, 16>, ISA_MIPS2; 374 def CEIL_W_S : MMRel, StdMMR6Rel, 375 ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, 376 ABSS_FM<0xe, 16>, ISA_MIPS2; 377 def FLOOR_W_S : MMRel, StdMMR6Rel, 378 ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>, 379 ABSS_FM<0xf, 16>, ISA_MIPS2; 380 def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, 381 ABSS_FM<0x24, 16>, ISA_MIPS1; 382 383 defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2; 384 defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2; 385 defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2; 386 defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>, ISA_MIPS1; 387} 388 389let AdditionalPredicates = [NotInMicroMips] in { 390 def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>, 391 ABSS_FM<0b010101, 0x10>, INSN_MIPS4_32R2; 392 def RECIP_D32 : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd, II_RECIP_D>, 393 ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2, FGR_32 { 394 let BaseOpcode = "RECIP_D32"; 395 } 396 let DecoderNamespace = "MipsFP64" in 397 def RECIP_D64 : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd, 398 II_RECIP_D>, ABSS_FM<0b010101, 0x11>, 399 INSN_MIPS4_32R2, FGR_64; 400 def RSQRT_S : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, II_RSQRT_S>, 401 ABSS_FM<0b010110, 0x10>, INSN_MIPS4_32R2; 402 def RSQRT_D32 : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd, II_RSQRT_D>, 403 ABSS_FM<0b010110, 0x11>, INSN_MIPS4_32R2, FGR_32 { 404 let BaseOpcode = "RSQRT_D32"; 405 } 406 let DecoderNamespace = "MipsFP64" in 407 def RSQRT_D64 : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd, 408 II_RSQRT_D>, ABSS_FM<0b010110, 0x11>, 409 INSN_MIPS4_32R2, FGR_64; 410} 411let DecoderNamespace = "MipsFP64" in { 412 let AdditionalPredicates = [NotInMicroMips] in { 413 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>, 414 ABSS_FM<0x8, 16>, ISA_MIPS2, FGR_64; 415 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>, 416 ABSS_FM<0x8, 17>, INSN_MIPS3_32, FGR_64; 417 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>, 418 ABSS_FM<0x9, 16>, ISA_MIPS2, FGR_64; 419 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>, 420 ABSS_FM<0x9, 17>, INSN_MIPS3_32, FGR_64; 421 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, II_CEIL>, 422 ABSS_FM<0xa, 16>, ISA_MIPS2, FGR_64; 423 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, II_CEIL>, 424 ABSS_FM<0xa, 17>, INSN_MIPS3_32, FGR_64; 425 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>, 426 ABSS_FM<0xb, 16>, ISA_MIPS2, FGR_64; 427 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>, 428 ABSS_FM<0xb, 17>, INSN_MIPS3_32, FGR_64; 429 } 430} 431 432let AdditionalPredicates = [NotInMicroMips] in{ 433 def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>, 434 ABSS_FM<0x20, 20>, ISA_MIPS1; 435 def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, 436 ABSS_FM<0x25, 16>, INSN_MIPS3_32R2; 437 def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, 438 ABSS_FM<0x25, 17>, INSN_MIPS3_32R2; 439} 440 441let AdditionalPredicates = [NotInMicroMips] in { 442 def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, 443 ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_32; 444 def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, 445 ABSS_FM<0x21, 16>, ISA_MIPS1, FGR_32; 446 def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, 447 ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_32; 448} 449 450let DecoderNamespace = "MipsFP64" in { 451 let AdditionalPredicates = [NotInMicroMips] in { 452 def PLL_PS64 : ADDS_FT<"pll.ps", FGR64Opnd, II_CVT, 0>, 453 ADDS_FM<0x2C, 22>, 454 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 455 def PLU_PS64 : ADDS_FT<"plu.ps", FGR64Opnd, II_CVT, 0>, 456 ADDS_FM<0x2D, 22>, 457 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 458 459 def CVT_S_PU64 : ABSS_FT<"cvt.s.pu", FGR32Opnd, FGR64Opnd, II_CVT>, 460 ABSS_FM<0x20, 22>, 461 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 462 def CVT_S_PL64 : ABSS_FT<"cvt.s.pl", FGR32Opnd, FGR64Opnd, II_CVT>, 463 ABSS_FM<0x28, 22>, 464 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 465 466 def CVT_PS_S64 : CVT_PS_S_FT<"cvt.ps.s", FGR64Opnd, FGR32Opnd, II_CVT, 0>, 467 ADDS_FM<0x26, 16>, 468 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 469 } 470} 471 472let DecoderNamespace = "MipsFP64" in { 473 let AdditionalPredicates = [NotInMicroMips] in { 474 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>, 475 ABSS_FM<0x20, 21>, INSN_MIPS3_32R2, FGR_64; 476 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>, 477 ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_64; 478 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>, 479 ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_64; 480 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>, 481 ABSS_FM<0x21, 16>, ISA_MIPS1, FGR_64; 482 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>, 483 ABSS_FM<0x21, 21>, INSN_MIPS3_32R2, FGR_64; 484 } 485} 486 487let isPseudo = 1, isCodeGenOnly = 1 in { 488 def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>; 489 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>; 490 def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>; 491 def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>; 492 def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>; 493} 494 495let AdditionalPredicates = [NotInMicroMips, UseAbs] in { 496 def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>, 497 ABSS_FM<0x5, 16>, ISA_MIPS1; 498 defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>, ISA_MIPS1; 499} 500 501def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, 502 ABSS_FM<0x7, 16>, ISA_MIPS1; 503let AdditionalPredicates = [NotInMicroMips] in { 504 defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>, ISA_MIPS1; 505} 506 507let AdditionalPredicates = [NotInMicroMips] in { 508 def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, 509 II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2; 510 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2; 511} 512 513// The odd-numbered registers are only referenced when doing loads, 514// stores, and moves between floating-point and integer registers. 515// When defining instructions, we reference all 32-bit registers, 516// regardless of register aliasing. 517 518/// Move Control Registers From/To CPU Registers 519let AdditionalPredicates = [NotInMicroMips] in { 520 def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>, 521 ISA_MIPS1; 522 def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>, 523 ISA_MIPS1; 524 525 def MFC1 : MMRel, StdMMR6Rel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, 526 bitconvert>, MFC1_FM<0>, ISA_MIPS1; 527 def MFC1_D64 : MFC1_FT<"mfc1", GPR32Opnd, FGR64Opnd, II_MFC1>, MFC1_FM<0>, 528 ISA_MIPS1, FGR_64 { 529 let DecoderNamespace = "MipsFP64"; 530 } 531 def MTC1 : MMRel, StdMMR6Rel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, 532 bitconvert>, MFC1_FM<4>, ISA_MIPS1; 533 def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>, 534 ISA_MIPS1, FGR_64 { 535 let DecoderNamespace = "MipsFP64"; 536 } 537 538 def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, 539 MFC1_FM<3>, ISA_MIPS32R2, FGR_32; 540 def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>, 541 MFC1_FM<3>, ISA_MIPS32R2, FGR_64 { 542 let DecoderNamespace = "MipsFP64"; 543 } 544 545 def MTHC1_D32 : MMRel, StdMMR6Rel, 546 MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, 547 MFC1_FM<7>, ISA_MIPS32R2, FGR_32; 548 def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>, 549 MFC1_FM<7>, ISA_MIPS32R2, FGR_64 { 550 let DecoderNamespace = "MipsFP64"; 551 } 552 553 def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1, 554 bitconvert>, MFC1_FM<5>, ISA_MIPS3; 555 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1, 556 bitconvert>, MFC1_FM<1>, ISA_MIPS3; 557 let isMoveReg = 1 in { 558 def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, 559 ABSS_FM<0x6, 16>, ISA_MIPS1; 560 defm FMOV : ABSS_M<"mov.d", II_MOV_D>, ABSS_FM<0x6, 17>, ISA_MIPS1; 561 } // isMoveReg 562} 563 564/// Floating Point Memory Instructions 565let AdditionalPredicates = [NotInMicroMips] in { 566 def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_simm16, II_LWC1, load>, 567 LW_FM<0x31>, ISA_MIPS1; 568 def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, mem_simm16, II_SWC1, store>, 569 LW_FM<0x39>, ISA_MIPS1; 570} 571 572let DecoderNamespace = "MipsFP64", AdditionalPredicates = [NotInMicroMips] in { 573 def LDC164 : StdMMR6Rel, LW_FT<"ldc1", FGR64Opnd, mem_simm16, II_LDC1, load>, 574 LW_FM<0x35>, ISA_MIPS2, FGR_64 { 575 let BaseOpcode = "LDC164"; 576 } 577 def SDC164 : StdMMR6Rel, SW_FT<"sdc1", FGR64Opnd, mem_simm16, II_SDC1, store>, 578 LW_FM<0x3d>, ISA_MIPS2, FGR_64; 579} 580 581let AdditionalPredicates = [NotInMicroMips] in { 582 def LDC1 : MMRel, StdMMR6Rel, LW_FT<"ldc1", AFGR64Opnd, mem_simm16, II_LDC1, 583 load>, LW_FM<0x35>, ISA_MIPS2, FGR_32 { 584 let BaseOpcode = "LDC132"; 585 } 586 def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_simm16, II_SDC1, store>, 587 LW_FM<0x3d>, ISA_MIPS2, FGR_32; 588} 589 590// Indexed loads and stores. 591// Base register + offset register addressing mode (indicated by "x" in the 592// instruction mnemonic) is disallowed under NaCl. 593let AdditionalPredicates = [IsNotNaCl] in { 594 def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>, 595 INSN_MIPS4_32R2_NOT_32R6_64R6; 596 def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>, 597 INSN_MIPS4_32R2_NOT_32R6_64R6; 598} 599 600let AdditionalPredicates = [NotInMicroMips, IsNotNaCl] in { 601 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>, 602 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 603 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>, 604 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 605} 606 607let DecoderNamespace="MipsFP64" in { 608 def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>, 609 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 610 def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>, 611 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 612} 613 614// Load/store doubleword indexed unaligned. 615// FIXME: This instruction should not be defined for FGR_32. 616let AdditionalPredicates = [IsNotNaCl, NotInMicroMips] in { 617 def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>, 618 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32; 619 def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>, 620 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32; 621} 622 623let AdditionalPredicates = [IsNotNaCl, NotInMicroMips], 624 DecoderNamespace="MipsFP64" in { 625 def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>, 626 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64; 627 def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>, 628 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64; 629} 630 631/// Floating-point Arithmetic 632let AdditionalPredicates = [NotInMicroMips] in { 633 def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, 634 ADDS_FM<0x00, 16>, ISA_MIPS1; 635 defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>, 636 ISA_MIPS1; 637 def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>, 638 ADDS_FM<0x03, 16>, ISA_MIPS1; 639 defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>, 640 ISA_MIPS1; 641 def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>, 642 ADDS_FM<0x02, 16>, ISA_MIPS1; 643 defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>, 644 ISA_MIPS1; 645 def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, 646 ADDS_FM<0x01, 16>, ISA_MIPS1; 647 defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>, 648 ISA_MIPS1; 649} 650 651let AdditionalPredicates = [NotInMicroMips, HasMadd4] in { 652 def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, 653 MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; 654 def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, 655 MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; 656 657 def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>, 658 MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 659 def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>, 660 MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 661 662 let DecoderNamespace = "MipsFP64" in { 663 def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>, 664 MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 665 def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>, 666 MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 667 } 668} 669 670let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in { 671 def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>, 672 MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; 673 def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>, 674 MADDS_FM<7, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; 675 676 def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>, 677 MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 678 def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>, 679 MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 680 681 let DecoderNamespace = "MipsFP64" in { 682 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>, 683 MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 684 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>, 685 MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 686 } 687} 688//===----------------------------------------------------------------------===// 689// Floating Point Branch Codes 690//===----------------------------------------------------------------------===// 691// Mips branch codes. These correspond to condcode in MipsInstrInfo.h. 692// They must be kept in synch. 693def MIPS_BRANCH_F : PatLeaf<(i32 0)>; 694def MIPS_BRANCH_T : PatLeaf<(i32 1)>; 695 696let AdditionalPredicates = [NotInMicroMips] in { 697 def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>, 698 BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6; 699 def BC1FL : MMRel, BC1XL_FT<"bc1fl", brtarget, II_BC1FL>, 700 BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6; 701 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>, 702 BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6; 703 def BC1TL : MMRel, BC1XL_FT<"bc1tl", brtarget, II_BC1TL>, 704 BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6; 705 706/// Floating Point Compare 707 def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>, 708 ISA_MIPS1_NOT_32R6_64R6 { 709 710 // FIXME: This is a required to work around the fact that these instructions 711 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the 712 // fcc register set is used directly. 713 bits<3> fcc = 0; 714 } 715 def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, 716 ISA_MIPS1_NOT_32R6_64R6, FGR_32 { 717 // FIXME: This is a required to work around the fact that these instructions 718 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the 719 // fcc register set is used directly. 720 bits<3> fcc = 0; 721 } 722} 723let DecoderNamespace = "MipsFP64" in 724def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, 725 ISA_MIPS1_NOT_32R6_64R6, FGR_64 { 726 // FIXME: This is a required to work around the fact that thiese instructions 727 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the 728 // fcc register set is used directly. 729 bits<3> fcc = 0; 730} 731 732//===----------------------------------------------------------------------===// 733// Floating Point Pseudo-Instructions 734//===----------------------------------------------------------------------===// 735 736// This pseudo instr gets expanded into 2 mtc1 instrs after register 737// allocation. 738class BuildPairF64Base<RegisterOperand RO> : 739 PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi), 740 [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))], 741 II_MTC1>; 742 743def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT; 744def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>, FGR_64, HARDFLOAT; 745 746// This pseudo instr gets expanded into 2 mfc1 instrs after register 747// allocation. 748// if n is 0, lower part of src is extracted. 749// if n is 1, higher part of src is extracted. 750// This node has associated scheduling information as the pre RA scheduler 751// asserts otherwise. 752class ExtractElementF64Base<RegisterOperand RO> : 753 PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n), 754 [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))], 755 II_MFC1>; 756 757def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT; 758def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>, FGR_64, HARDFLOAT; 759 760def PseudoTRUNC_W_S : MipsAsmPseudoInst<(outs FGR32Opnd:$fd), 761 (ins FGR32Opnd:$fs, GPR32Opnd:$rs), 762 "trunc.w.s\t$fd, $fs, $rs">; 763 764def PseudoTRUNC_W_D32 : MipsAsmPseudoInst<(outs FGR32Opnd:$fd), 765 (ins AFGR64Opnd:$fs, GPR32Opnd:$rs), 766 "trunc.w.d\t$fd, $fs, $rs">, 767 FGR_32, HARDFLOAT; 768 769def PseudoTRUNC_W_D : MipsAsmPseudoInst<(outs FGR32Opnd:$fd), 770 (ins FGR64Opnd:$fs, GPR32Opnd:$rs), 771 "trunc.w.d\t$fd, $fs, $rs">, 772 FGR_64, HARDFLOAT; 773 774def LoadImmSingleGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 775 (ins imm64:$fpimm), 776 "li.s\t$rd, $fpimm">; 777 778def LoadImmSingleFGR : MipsAsmPseudoInst<(outs StrictlyFGR32Opnd:$rd), 779 (ins imm64:$fpimm), 780 "li.s\t$rd, $fpimm">, 781 HARDFLOAT; 782 783def LoadImmDoubleGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 784 (ins imm64:$fpimm), 785 "li.d\t$rd, $fpimm">; 786 787def LoadImmDoubleFGR_32 : MipsAsmPseudoInst<(outs StrictlyAFGR64Opnd:$rd), 788 (ins imm64:$fpimm), 789 "li.d\t$rd, $fpimm">, 790 FGR_32, HARDFLOAT; 791 792def LoadImmDoubleFGR : MipsAsmPseudoInst<(outs StrictlyFGR64Opnd:$rd), 793 (ins imm64:$fpimm), 794 "li.d\t$rd, $fpimm">, 795 FGR_64, HARDFLOAT; 796 797def SDC1_M1 : MipsAsmPseudoInst<(outs AFGR64Opnd:$fd), 798 (ins mem_simm16:$addr), 799 "s.d\t$fd, $addr">, 800 FGR_32, ISA_MIPS1, HARDFLOAT; 801 802//===----------------------------------------------------------------------===// 803// InstAliases. 804//===----------------------------------------------------------------------===// 805def : MipsInstAlias 806 <"s.s $fd, $addr", (SWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>, 807 ISA_MIPS2, HARDFLOAT; 808def : MipsInstAlias 809 <"s.d $fd, $addr", (SDC1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>, 810 FGR_32, ISA_MIPS2, HARDFLOAT; 811def : MipsInstAlias 812 <"s.d $fd, $addr", (SDC164 FGR64Opnd:$fd, mem_simm16:$addr), 0>, 813 FGR_64, ISA_MIPS2, HARDFLOAT; 814def : MipsInstAlias 815 <"s.d $fd, $addr", (SDC1_M1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>, 816 FGR_32, ISA_MIPS1, HARDFLOAT; 817 818def : MipsInstAlias 819 <"l.s $fd, $addr", (LWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>, 820 ISA_MIPS2, HARDFLOAT; 821def : MipsInstAlias 822 <"l.d $fd, $addr", (LDC1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>, 823 FGR_32, ISA_MIPS2, HARDFLOAT; 824def : MipsInstAlias 825 <"l.d $fd, $addr", (LDC164 FGR64Opnd:$fd, mem_simm16:$addr), 0>, 826 FGR_64, ISA_MIPS2, HARDFLOAT; 827 828multiclass C_COND_ALIASES<string TypeStr, RegisterOperand RC> { 829 def : MipsInstAlias<!strconcat("c.f.", TypeStr, " $fs, $ft"), 830 (!cast<Instruction>("C_F_"#NAME) FCC0, 831 RC:$fs, RC:$ft), 1>; 832 def : MipsInstAlias<!strconcat("c.un.", TypeStr, " $fs, $ft"), 833 (!cast<Instruction>("C_UN_"#NAME) FCC0, 834 RC:$fs, RC:$ft), 1>; 835 def : MipsInstAlias<!strconcat("c.eq.", TypeStr, " $fs, $ft"), 836 (!cast<Instruction>("C_EQ_"#NAME) FCC0, 837 RC:$fs, RC:$ft), 1>; 838 def : MipsInstAlias<!strconcat("c.ueq.", TypeStr, " $fs, $ft"), 839 (!cast<Instruction>("C_UEQ_"#NAME) FCC0, 840 RC:$fs, RC:$ft), 1>; 841 def : MipsInstAlias<!strconcat("c.olt.", TypeStr, " $fs, $ft"), 842 (!cast<Instruction>("C_OLT_"#NAME) FCC0, 843 RC:$fs, RC:$ft), 1>; 844 def : MipsInstAlias<!strconcat("c.ult.", TypeStr, " $fs, $ft"), 845 (!cast<Instruction>("C_ULT_"#NAME) FCC0, 846 RC:$fs, RC:$ft), 1>; 847 def : MipsInstAlias<!strconcat("c.ole.", TypeStr, " $fs, $ft"), 848 (!cast<Instruction>("C_OLE_"#NAME) FCC0, 849 RC:$fs, RC:$ft), 1>; 850 def : MipsInstAlias<!strconcat("c.ule.", TypeStr, " $fs, $ft"), 851 (!cast<Instruction>("C_ULE_"#NAME) FCC0, 852 RC:$fs, RC:$ft), 1>; 853 def : MipsInstAlias<!strconcat("c.sf.", TypeStr, " $fs, $ft"), 854 (!cast<Instruction>("C_SF_"#NAME) FCC0, 855 RC:$fs, RC:$ft), 1>; 856 def : MipsInstAlias<!strconcat("c.ngle.", TypeStr, " $fs, $ft"), 857 (!cast<Instruction>("C_NGLE_"#NAME) FCC0, 858 RC:$fs, RC:$ft), 1>; 859 def : MipsInstAlias<!strconcat("c.seq.", TypeStr, " $fs, $ft"), 860 (!cast<Instruction>("C_SEQ_"#NAME) FCC0, 861 RC:$fs, RC:$ft), 1>; 862 def : MipsInstAlias<!strconcat("c.ngl.", TypeStr, " $fs, $ft"), 863 (!cast<Instruction>("C_NGL_"#NAME) FCC0, 864 RC:$fs, RC:$ft), 1>; 865 def : MipsInstAlias<!strconcat("c.lt.", TypeStr, " $fs, $ft"), 866 (!cast<Instruction>("C_LT_"#NAME) FCC0, 867 RC:$fs, RC:$ft), 1>; 868 def : MipsInstAlias<!strconcat("c.nge.", TypeStr, " $fs, $ft"), 869 (!cast<Instruction>("C_NGE_"#NAME) FCC0, 870 RC:$fs, RC:$ft), 1>; 871 def : MipsInstAlias<!strconcat("c.le.", TypeStr, " $fs, $ft"), 872 (!cast<Instruction>("C_LE_"#NAME) FCC0, 873 RC:$fs, RC:$ft), 1>; 874 def : MipsInstAlias<!strconcat("c.ngt.", TypeStr, " $fs, $ft"), 875 (!cast<Instruction>("C_NGT_"#NAME) FCC0, 876 RC:$fs, RC:$ft), 1>; 877} 878 879multiclass BC1_ALIASES<Instruction BCTrue, string BCTrueString, 880 Instruction BCFalse, string BCFalseString> { 881 def : MipsInstAlias<!strconcat(BCTrueString, " $offset"), 882 (BCTrue FCC0, brtarget:$offset), 1>; 883 884 def : MipsInstAlias<!strconcat(BCFalseString, " $offset"), 885 (BCFalse FCC0, brtarget:$offset), 1>; 886} 887 888let AdditionalPredicates = [NotInMicroMips] in { 889 defm S : C_COND_ALIASES<"s", FGR32Opnd>, HARDFLOAT, 890 ISA_MIPS1_NOT_32R6_64R6; 891 defm D32 : C_COND_ALIASES<"d", AFGR64Opnd>, HARDFLOAT, 892 ISA_MIPS1_NOT_32R6_64R6, FGR_32; 893 defm D64 : C_COND_ALIASES<"d", FGR64Opnd>, HARDFLOAT, 894 ISA_MIPS1_NOT_32R6_64R6, FGR_64; 895 896 defm : BC1_ALIASES<BC1T, "bc1t", BC1F, "bc1f">, ISA_MIPS1_NOT_32R6_64R6, 897 HARDFLOAT; 898 defm : BC1_ALIASES<BC1TL, "bc1tl", BC1FL, "bc1fl">, ISA_MIPS2_NOT_32R6_64R6, 899 HARDFLOAT; 900} 901//===----------------------------------------------------------------------===// 902// Floating Point Patterns 903//===----------------------------------------------------------------------===// 904def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>, ISA_MIPS1; 905def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>, ISA_MIPS1; 906 907def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)), 908 (PseudoCVT_S_W GPR32Opnd:$src)>; 909def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), 910 (TRUNC_W_S FGR32Opnd:$src)>, ISA_MIPS1; 911 912def : MipsPat<(MipsMTC1_D64 GPR32Opnd:$src), 913 (MTC1_D64 GPR32Opnd:$src)>, ISA_MIPS1, FGR_64; 914 915def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), 916 (PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32; 917let AdditionalPredicates = [NotInMicroMips] in { 918 def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src), 919 (TRUNC_W_D32 AFGR64Opnd:$src)>, ISA_MIPS2, FGR_32; 920 def : MipsPat<(f32 (fpround AFGR64Opnd:$src)), 921 (CVT_S_D32 AFGR64Opnd:$src)>, ISA_MIPS1, FGR_32; 922 def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), 923 (CVT_D32_S FGR32Opnd:$src)>, ISA_MIPS1, FGR_32; 924} 925 926def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, ISA_MIPS3, GPR_64, FGR_64; 927def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, ISA_MIPS3, GPR_64, 928 FGR_64; 929 930def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), 931 (PseudoCVT_D64_W GPR32Opnd:$src)>, FGR_64; 932def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)), 933 (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>, FGR_64; 934def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)), 935 (PseudoCVT_D64_L GPR64Opnd:$src)>, FGR_64; 936 937def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), 938 (TRUNC_W_D64 FGR64Opnd:$src)>, ISA_MIPS2, FGR_64; 939def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), 940 (TRUNC_L_S FGR32Opnd:$src)>, ISA_MIPS2, FGR_64; 941def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), 942 (TRUNC_L_D64 FGR64Opnd:$src)>, ISA_MIPS2, FGR_64; 943 944let AdditionalPredicates = [NotInMicroMips] in { 945 def : MipsPat<(f32 (fpround FGR64Opnd:$src)), 946 (CVT_S_D64 FGR64Opnd:$src)>, ISA_MIPS1, FGR_64; 947 def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), 948 (CVT_D64_S FGR32Opnd:$src)>, ISA_MIPS1, FGR_64; 949} 950 951// To generate NMADD and NMSUB instructions when fneg node is present 952multiclass NMADD_NMSUB<Instruction Nmadd, Instruction Nmsub, RegisterOperand RC> { 953 def : MipsPat<(fneg (fadd (fmul RC:$fs, RC:$ft), RC:$fr)), 954 (Nmadd RC:$fr, RC:$fs, RC:$ft)>; 955 def : MipsPat<(fneg (fsub (fmul RC:$fs, RC:$ft), RC:$fr)), 956 (Nmsub RC:$fr, RC:$fs, RC:$ft)>; 957} 958 959let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in { 960 defm : NMADD_NMSUB<NMADD_S, NMSUB_S, FGR32Opnd>, 961 INSN_MIPS4_32R2_NOT_32R6_64R6; 962 defm : NMADD_NMSUB<NMADD_D32, NMSUB_D32, AFGR64Opnd>, 963 FGR_32, INSN_MIPS4_32R2_NOT_32R6_64R6; 964 defm : NMADD_NMSUB<NMADD_D64, NMSUB_D64, FGR64Opnd>, 965 FGR_64, INSN_MIPS4_32R2_NOT_32R6_64R6; 966} 967 968// Patterns for loads/stores with a reg+imm operand. 969let AdditionalPredicates = [NotInMicroMips] in { 970 let AddedComplexity = 40 in { 971 def : LoadRegImmPat<LWC1, f32, load>, ISA_MIPS1; 972 def : StoreRegImmPat<SWC1, f32>, ISA_MIPS1; 973 974 def : LoadRegImmPat<LDC164, f64, load>, ISA_MIPS1, FGR_64; 975 def : StoreRegImmPat<SDC164, f64>, ISA_MIPS1, FGR_64; 976 977 def : LoadRegImmPat<LDC1, f64, load>, ISA_MIPS1, FGR_32; 978 def : StoreRegImmPat<SDC1, f64>, ISA_MIPS1, FGR_32; 979 } 980} 981