1//===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the Mips FPU instruction set. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Floating Point Instructions 15// ------------------------ 16// * 64bit fp: 17// - 32 64-bit registers (default mode) 18// - 16 even 32-bit registers (32-bit compatible mode) for 19// single and double access. 20// * 32bit fp: 21// - 16 even 32-bit registers - single and double (aliased) 22// - 32 32-bit registers (within single-only mode) 23//===----------------------------------------------------------------------===// 24 25// Floating Point Compare and Branch 26def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>, 27 SDTCisVT<1, i32>, 28 SDTCisVT<2, OtherVT>]>; 29def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>, 30 SDTCisVT<2, i32>]>; 31def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>, 32 SDTCisSameAs<1, 3>]>; 33def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>; 34def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, 35 SDTCisVT<1, i32>, 36 SDTCisSameAs<1, 2>]>; 37def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 38 SDTCisVT<1, f64>, 39 SDTCisVT<2, i32>]>; 40 41def SDT_MipsMTC1_D64 : SDTypeProfile<1, 1, [SDTCisVT<0, f64>, 42 SDTCisVT<1, i32>]>; 43 44def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>; 45def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>; 46def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>; 47def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond, 48 [SDNPHasChain, SDNPOptInGlue]>; 49def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>; 50def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>; 51def : GINodeEquiv<G_MERGE_VALUES, MipsBuildPairF64>; 52def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64", 53 SDT_MipsExtractElementF64>; 54 55def MipsMTC1_D64 : SDNode<"MipsISD::MTC1_D64", SDT_MipsMTC1_D64>; 56 57// Operand for printing out a condition code. 58let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in 59 def condcode : Operand<i32>; 60 61//===----------------------------------------------------------------------===// 62// Feature predicates. 63//===----------------------------------------------------------------------===// 64 65def IsFP64bit : Predicate<"Subtarget->isFP64bit()">, 66 AssemblerPredicate<(all_of FeatureFP64Bit)>; 67def NotFP64bit : Predicate<"!Subtarget->isFP64bit()">, 68 AssemblerPredicate<(all_of (not FeatureFP64Bit))>; 69def IsSingleFloat : Predicate<"Subtarget->isSingleFloat()">, 70 AssemblerPredicate<(all_of FeatureSingleFloat)>; 71def IsNotSingleFloat : Predicate<"!Subtarget->isSingleFloat()">, 72 AssemblerPredicate<(all_of (not FeatureSingleFloat))>; 73def IsNotSoftFloat : Predicate<"!Subtarget->useSoftFloat()">, 74 AssemblerPredicate<(all_of (not FeatureSoftFloat))>; 75def HasMips3D : Predicate<"Subtarget->has3D()">, 76 AssemblerPredicate<(all_of FeatureMips3D)>; 77 78//===----------------------------------------------------------------------===// 79// Mips FGR size adjectives. 80// They are mutually exclusive. 81//===----------------------------------------------------------------------===// 82 83class FGR_32 { list<Predicate> FGRPredicates = [NotFP64bit]; } 84class FGR_64 { list<Predicate> FGRPredicates = [IsFP64bit]; } 85class HARDFLOAT { list<Predicate> HardFloatPredicate = [IsNotSoftFloat]; } 86 87//===----------------------------------------------------------------------===// 88 89// FP immediate patterns. 90def fpimm0 : PatLeaf<(fpimm), [{ 91 return N->isExactlyValue(+0.0); 92}]>; 93 94def fpimm0neg : PatLeaf<(fpimm), [{ 95 return N->isExactlyValue(-0.0); 96}]>; 97 98//===----------------------------------------------------------------------===// 99// Instruction Class Templates 100// 101// A set of multiclasses is used to address the register usage. 102// 103// S32 - single precision in 16 32bit even fp registers 104// single precision in 32 32bit fp registers in SingleOnly mode 105// S64 - single precision in 32 64bit fp registers (In64BitMode) 106// D32 - double precision in 16 32bit even fp registers 107// D64 - double precision in 32 64bit fp registers (In64BitMode) 108// 109// Only S32 and D32 are supported right now. 110//===----------------------------------------------------------------------===// 111class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm, 112 SDPatternOperator OpNode= null_frag> : 113 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft), 114 !strconcat(opstr, "\t$fd, $fs, $ft"), 115 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>, 116 HARDFLOAT { 117 let isCommutable = IsComm; 118} 119 120multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm, 121 SDPatternOperator OpNode = null_frag> { 122 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, FGR_32; 123 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 { 124 string DecoderNamespace = "MipsFP64"; 125 } 126} 127 128class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 129 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 130 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"), 131 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, 132 HARDFLOAT, 133 NeverHasSideEffects; 134 135class CVT_PS_S_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 136 InstrItinClass Itin, bit IsComm, 137 SDPatternOperator OpNode = null_frag> : 138 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs, SrcRC:$ft), 139 !strconcat(opstr, "\t$fd, $fs, $ft"), 140 [(set DstRC:$fd, (OpNode SrcRC:$fs, SrcRC:$ft))], Itin, FrmFR, opstr>, 141 HARDFLOAT { 142 let isCommutable = IsComm; 143} 144 145multiclass ABSS_M<string opstr, InstrItinClass Itin, 146 SDPatternOperator OpNode= null_frag> { 147 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>, 148 FGR_32; 149 def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, 150 FGR_64 { 151 string DecoderNamespace = "MipsFP64"; 152 } 153} 154 155multiclass ROUND_M<string opstr, InstrItinClass Itin> { 156 def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>, FGR_32; 157 def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>, FGR_64 { 158 let DecoderNamespace = "MipsFP64"; 159 } 160} 161 162class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 163 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 164 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"), 165 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT { 166 let isMoveReg = 1; 167} 168 169class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 170 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 171 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"), 172 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>, HARDFLOAT { 173 let isMoveReg = 1; 174} 175 176class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 177 InstrItinClass Itin> : 178 InstSE<(outs DstRC:$fs), (ins DstRC:$fs_in, SrcRC:$rt), 179 !strconcat(opstr, "\t$rt, $fs"), [], Itin, FrmFR, opstr>, HARDFLOAT { 180 // $fs_in is part of a white lie to work around a widespread bug in the FPU 181 // implementation. See expandBuildPairF64 for details. 182 let Constraints = "$fs = $fs_in"; 183} 184 185class LW_FT<string opstr, RegisterOperand RC, DAGOperand MO, 186 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 187 InstSE<(outs RC:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"), 188 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr>, 189 HARDFLOAT { 190 let DecoderMethod = "DecodeFMem"; 191 let mayLoad = 1; 192} 193 194class SW_FT<string opstr, RegisterOperand RC, DAGOperand MO, 195 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 196 InstSE<(outs), (ins RC:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"), 197 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr>, HARDFLOAT { 198 let DecoderMethod = "DecodeFMem"; 199 let mayStore = 1; 200} 201 202class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 203 SDPatternOperator OpNode = null_frag> : 204 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 205 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 206 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, 207 FrmFR, opstr>, HARDFLOAT; 208 209class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 210 SDPatternOperator OpNode = null_frag> : 211 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 212 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 213 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))], 214 Itin, FrmFR, opstr>, HARDFLOAT; 215 216class LWXC1_FT<string opstr, RegisterOperand DRC, 217 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 218 InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index), 219 !strconcat(opstr, "\t$fd, ${index}(${base})"), 220 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin, 221 FrmFI, opstr>, HARDFLOAT { 222 let AddedComplexity = 20; 223} 224 225class SWXC1_FT<string opstr, RegisterOperand DRC, 226 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 227 InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index), 228 !strconcat(opstr, "\t$fs, ${index}(${base})"), 229 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin, 230 FrmFI, opstr>, HARDFLOAT { 231 let AddedComplexity = 20; 232} 233 234class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin, 235 SDPatternOperator Op = null_frag> : 236 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset), 237 !strconcat(opstr, "\t$fcc, $offset"), 238 [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin, 239 FrmFI, opstr>, HARDFLOAT { 240 let isBranch = 1; 241 let isTerminator = 1; 242 let hasDelaySlot = 1; 243 let Defs = [AT]; 244 let hasFCCRegOperand = 1; 245} 246 247class BC1XL_FT<string opstr, DAGOperand opnd, InstrItinClass Itin> : 248 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset), 249 !strconcat(opstr, "\t$fcc, $offset"), [], Itin, 250 FrmFI, opstr>, HARDFLOAT { 251 let isBranch = 1; 252 let isTerminator = 1; 253 let hasDelaySlot = 1; 254 let Defs = [AT]; 255 let hasFCCRegOperand = 1; 256} 257 258class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin, 259 SDPatternOperator OpNode = null_frag> : 260 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond), 261 !strconcat("c.$cond.", typestr, "\t$fs, $ft"), 262 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR, 263 !strconcat("c.$cond.", typestr)>, HARDFLOAT { 264 let Defs = [FCC0]; 265 let isCodeGenOnly = 1; 266 let hasFCCRegOperand = 1; 267} 268 269 270// Note: MIPS-IV introduced $fcc1-$fcc7 and renamed FCSR31[23] $fcc0. Rather 271// duplicating the instruction definition for MIPS1 - MIPS3, we expand 272// c.cond.ft if necessary, and reject it after constructing the 273// instruction if the ISA doesn't support it. 274class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC, 275 InstrItinClass itin> : 276 InstSE<(outs FCCRegsOpnd:$fcc), (ins RC:$fs, RC:$ft), 277 !strconcat("c.", CondStr, ".", Typestr, "\t$fcc, $fs, $ft"), [], itin, 278 FrmFR>, HARDFLOAT { 279 let isCompare = 1; 280 let hasFCCRegOperand = 1; 281} 282 283 284multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt, 285 InstrItinClass itin> { 286 def C_F_#NAME : MMRel, C_COND_FT<"f", TypeStr, RC, itin>, 287 C_COND_FM<fmt, 0> { 288 let BaseOpcode = "c.f."#NAME; 289 let isCommutable = 1; 290 } 291 def C_UN_#NAME : MMRel, C_COND_FT<"un", TypeStr, RC, itin>, 292 C_COND_FM<fmt, 1> { 293 let BaseOpcode = "c.un."#NAME; 294 let isCommutable = 1; 295 } 296 def C_EQ_#NAME : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>, 297 C_COND_FM<fmt, 2> { 298 let BaseOpcode = "c.eq."#NAME; 299 let isCommutable = 1; 300 } 301 def C_UEQ_#NAME : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>, 302 C_COND_FM<fmt, 3> { 303 let BaseOpcode = "c.ueq."#NAME; 304 let isCommutable = 1; 305 } 306 def C_OLT_#NAME : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>, 307 C_COND_FM<fmt, 4> { 308 let BaseOpcode = "c.olt."#NAME; 309 } 310 def C_ULT_#NAME : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>, 311 C_COND_FM<fmt, 5> { 312 let BaseOpcode = "c.ult."#NAME; 313 } 314 def C_OLE_#NAME : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>, 315 C_COND_FM<fmt, 6> { 316 let BaseOpcode = "c.ole."#NAME; 317 } 318 def C_ULE_#NAME : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>, 319 C_COND_FM<fmt, 7> { 320 let BaseOpcode = "c.ule."#NAME; 321 } 322 def C_SF_#NAME : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>, 323 C_COND_FM<fmt, 8> { 324 let BaseOpcode = "c.sf."#NAME; 325 let isCommutable = 1; 326 } 327 def C_NGLE_#NAME : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>, 328 C_COND_FM<fmt, 9> { 329 let BaseOpcode = "c.ngle."#NAME; 330 } 331 def C_SEQ_#NAME : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>, 332 C_COND_FM<fmt, 10> { 333 let BaseOpcode = "c.seq."#NAME; 334 let isCommutable = 1; 335 } 336 def C_NGL_#NAME : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>, 337 C_COND_FM<fmt, 11> { 338 let BaseOpcode = "c.ngl."#NAME; 339 } 340 def C_LT_#NAME : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>, 341 C_COND_FM<fmt, 12> { 342 let BaseOpcode = "c.lt."#NAME; 343 } 344 def C_NGE_#NAME : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>, 345 C_COND_FM<fmt, 13> { 346 let BaseOpcode = "c.nge."#NAME; 347 } 348 def C_LE_#NAME : MMRel, C_COND_FT<"le", TypeStr, RC, itin>, 349 C_COND_FM<fmt, 14> { 350 let BaseOpcode = "c.le."#NAME; 351 } 352 def C_NGT_#NAME : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>, 353 C_COND_FM<fmt, 15> { 354 let BaseOpcode = "c.ngt."#NAME; 355 } 356} 357 358let AdditionalPredicates = [NotInMicroMips] in { 359defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6; 360defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, 361 FGR_32; 362let DecoderNamespace = "MipsFP64" in 363defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, 364 FGR_64; 365} 366//===----------------------------------------------------------------------===// 367// Floating Point Instructions 368//===----------------------------------------------------------------------===// 369let AdditionalPredicates = [NotInMicroMips] in { 370 def ROUND_W_S : MMRel, StdMMR6Rel, 371 ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>, 372 ABSS_FM<0xc, 16>, ISA_MIPS2; 373 defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2; 374 def TRUNC_W_S : MMRel, StdMMR6Rel, 375 ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>, 376 ABSS_FM<0xd, 16>, ISA_MIPS2; 377 def CEIL_W_S : MMRel, StdMMR6Rel, 378 ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, 379 ABSS_FM<0xe, 16>, ISA_MIPS2; 380 def FLOOR_W_S : MMRel, StdMMR6Rel, 381 ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>, 382 ABSS_FM<0xf, 16>, ISA_MIPS2; 383 def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, 384 ABSS_FM<0x24, 16>, ISA_MIPS1; 385 386 defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2; 387 defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2; 388 defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2; 389 defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>, ISA_MIPS1; 390} 391 392let AdditionalPredicates = [NotInMicroMips] in { 393 def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>, 394 ABSS_FM<0b010101, 0x10>, INSN_MIPS4_32R2; 395 def RECIP_D32 : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd, II_RECIP_D>, 396 ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2, FGR_32 { 397 let BaseOpcode = "RECIP_D32"; 398 } 399 let DecoderNamespace = "MipsFP64" in 400 def RECIP_D64 : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd, 401 II_RECIP_D>, ABSS_FM<0b010101, 0x11>, 402 INSN_MIPS4_32R2, FGR_64; 403 def RSQRT_S : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, II_RSQRT_S>, 404 ABSS_FM<0b010110, 0x10>, INSN_MIPS4_32R2; 405 def RSQRT_D32 : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd, II_RSQRT_D>, 406 ABSS_FM<0b010110, 0x11>, INSN_MIPS4_32R2, FGR_32 { 407 let BaseOpcode = "RSQRT_D32"; 408 } 409 let DecoderNamespace = "MipsFP64" in 410 def RSQRT_D64 : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd, 411 II_RSQRT_D>, ABSS_FM<0b010110, 0x11>, 412 INSN_MIPS4_32R2, FGR_64; 413} 414let DecoderNamespace = "MipsFP64" in { 415 let AdditionalPredicates = [NotInMicroMips] in { 416 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>, 417 ABSS_FM<0x8, 16>, ISA_MIPS2, FGR_64; 418 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>, 419 ABSS_FM<0x8, 17>, INSN_MIPS3_32, FGR_64; 420 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>, 421 ABSS_FM<0x9, 16>, ISA_MIPS2, FGR_64; 422 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>, 423 ABSS_FM<0x9, 17>, INSN_MIPS3_32, FGR_64; 424 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, II_CEIL>, 425 ABSS_FM<0xa, 16>, ISA_MIPS2, FGR_64; 426 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, II_CEIL>, 427 ABSS_FM<0xa, 17>, INSN_MIPS3_32, FGR_64; 428 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>, 429 ABSS_FM<0xb, 16>, ISA_MIPS2, FGR_64; 430 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>, 431 ABSS_FM<0xb, 17>, INSN_MIPS3_32, FGR_64; 432 } 433} 434 435let AdditionalPredicates = [NotInMicroMips] in{ 436 def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>, 437 ABSS_FM<0x20, 20>, ISA_MIPS1; 438 def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, 439 ABSS_FM<0x25, 16>, INSN_MIPS3_32R2; 440 def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, 441 ABSS_FM<0x25, 17>, INSN_MIPS3_32R2; 442} 443 444let AdditionalPredicates = [NotInMicroMips] in { 445 def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, 446 ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_32; 447 def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, 448 ABSS_FM<0x21, 16>, ISA_MIPS1, FGR_32; 449 def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, 450 ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_32; 451} 452 453let DecoderNamespace = "MipsFP64" in { 454 let AdditionalPredicates = [NotInMicroMips] in { 455 def FADD_PS64 : ADDS_FT<"add.ps", FGR64Opnd, II_ADD_PS, 0>, 456 ADDS_FM<0x0, 22>, 457 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 458 def FMUL_PS64 : ADDS_FT<"mul.ps", FGR64Opnd, II_MUL_PS, 0>, 459 ADDS_FM<0x2, 22>, 460 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 461 def PLL_PS64 : ADDS_FT<"pll.ps", FGR64Opnd, II_CVT, 0>, 462 ADDS_FM<0x2C, 22>, 463 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 464 def PLU_PS64 : ADDS_FT<"plu.ps", FGR64Opnd, II_CVT, 0>, 465 ADDS_FM<0x2D, 22>, 466 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 467 def PUL_PS64 : ADDS_FT<"pul.ps", FGR64Opnd, II_CVT, 0>, 468 ADDS_FM<0x2E, 22>, 469 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 470 def PUU_PS64 : ADDS_FT<"puu.ps", FGR64Opnd, II_CVT, 0>, 471 ADDS_FM<0x2F, 22>, 472 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 473 def FSUB_PS64 : ADDS_FT<"sub.ps", FGR64Opnd, II_SUB_PS, 0>, 474 ADDS_FM<0x1, 22>, 475 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 476 477 def CVT_S_PU64 : ABSS_FT<"cvt.s.pu", FGR32Opnd, FGR64Opnd, II_CVT>, 478 ABSS_FM<0x20, 22>, 479 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 480 def CVT_S_PL64 : ABSS_FT<"cvt.s.pl", FGR32Opnd, FGR64Opnd, II_CVT>, 481 ABSS_FM<0x28, 22>, 482 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 483 484 def CVT_PS_S64 : CVT_PS_S_FT<"cvt.ps.s", FGR64Opnd, FGR32Opnd, II_CVT, 0>, 485 ADDS_FM<0x26, 16>, 486 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 487 } 488} 489 490let DecoderNamespace = "MipsFP64" in { 491 let AdditionalPredicates = [HasMips3D] in { 492 def ADDR_PS64 : ADDS_FT<"addr.ps", FGR64Opnd, II_ADDR_PS, 0>, 493 ADDS_FM<0x18, 22>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 494 def MULR_PS64 : ADDS_FT<"mulr.ps", FGR64Opnd, II_MULR_PS, 0>, 495 ADDS_FM<0x1a, 22>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 496 def CVT_PS_PW64 : ABSS_FT<"cvt.ps.pw", FGR64Opnd, FGR64Opnd, II_CVT>, 497 ABSS_FM<0x26, 20>, 498 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 499 def CVT_PW_PS64 : ABSS_FT<"cvt.pw.ps", FGR64Opnd, FGR64Opnd, II_CVT>, 500 ABSS_FM<0x24, 22>, 501 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 502 } 503} 504 505let DecoderNamespace = "MipsFP64" in { 506 let AdditionalPredicates = [NotInMicroMips] in { 507 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>, 508 ABSS_FM<0x20, 21>, INSN_MIPS3_32R2, FGR_64; 509 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>, 510 ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_64; 511 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>, 512 ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_64; 513 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>, 514 ABSS_FM<0x21, 16>, ISA_MIPS1, FGR_64; 515 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>, 516 ABSS_FM<0x21, 21>, INSN_MIPS3_32R2, FGR_64; 517 } 518} 519 520let isPseudo = 1, isCodeGenOnly = 1 in { 521 def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>; 522 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>; 523 def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>; 524 def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>; 525 def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>; 526} 527 528let AdditionalPredicates = [NotInMicroMips, UseAbs] in { 529 def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>, 530 ABSS_FM<0x5, 16>, ISA_MIPS1; 531 defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>, ISA_MIPS1; 532} 533 534def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, 535 ABSS_FM<0x7, 16>, ISA_MIPS1; 536let AdditionalPredicates = [NotInMicroMips] in { 537 defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>, ISA_MIPS1; 538} 539 540let AdditionalPredicates = [NotInMicroMips] in { 541 def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, 542 II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2; 543 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2; 544} 545 546// The odd-numbered registers are only referenced when doing loads, 547// stores, and moves between floating-point and integer registers. 548// When defining instructions, we reference all 32-bit registers, 549// regardless of register aliasing. 550 551/// Move Control Registers From/To CPU Registers 552let AdditionalPredicates = [NotInMicroMips] in { 553 def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>, 554 ISA_MIPS1; 555 def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>, 556 ISA_MIPS1; 557 558 def MFC1 : MMRel, StdMMR6Rel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, 559 bitconvert>, MFC1_FM<0>, ISA_MIPS1; 560 def MFC1_D64 : MFC1_FT<"mfc1", GPR32Opnd, FGR64Opnd, II_MFC1>, MFC1_FM<0>, 561 ISA_MIPS1, FGR_64 { 562 let DecoderNamespace = "MipsFP64"; 563 } 564 def MTC1 : MMRel, StdMMR6Rel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, 565 bitconvert>, MFC1_FM<4>, ISA_MIPS1; 566 def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>, 567 ISA_MIPS1, FGR_64 { 568 let DecoderNamespace = "MipsFP64"; 569 } 570 571 def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, 572 MFC1_FM<3>, ISA_MIPS32R2, FGR_32; 573 def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>, 574 MFC1_FM<3>, ISA_MIPS32R2, FGR_64 { 575 let DecoderNamespace = "MipsFP64"; 576 } 577 578 def MTHC1_D32 : MMRel, StdMMR6Rel, 579 MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, 580 MFC1_FM<7>, ISA_MIPS32R2, FGR_32; 581 def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>, 582 MFC1_FM<7>, ISA_MIPS32R2, FGR_64 { 583 let DecoderNamespace = "MipsFP64"; 584 } 585 586 def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1, 587 bitconvert>, MFC1_FM<5>, ISA_MIPS3; 588 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1, 589 bitconvert>, MFC1_FM<1>, ISA_MIPS3; 590 let isMoveReg = 1 in { 591 def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, 592 ABSS_FM<0x6, 16>, ISA_MIPS1; 593 defm FMOV : ABSS_M<"mov.d", II_MOV_D>, ABSS_FM<0x6, 17>, ISA_MIPS1; 594 } // isMoveReg 595} 596 597/// Floating Point Memory Instructions 598let AdditionalPredicates = [NotInMicroMips] in { 599 def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_simm16, II_LWC1, load>, 600 LW_FM<0x31>, ISA_MIPS1; 601 def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, mem_simm16, II_SWC1, store>, 602 LW_FM<0x39>, ISA_MIPS1; 603} 604 605let DecoderNamespace = "MipsFP64", AdditionalPredicates = [NotInMicroMips] in { 606 def LDC164 : StdMMR6Rel, LW_FT<"ldc1", FGR64Opnd, mem_simm16, II_LDC1, load>, 607 LW_FM<0x35>, ISA_MIPS2, FGR_64 { 608 let BaseOpcode = "LDC164"; 609 } 610 def SDC164 : StdMMR6Rel, SW_FT<"sdc1", FGR64Opnd, mem_simm16, II_SDC1, store>, 611 LW_FM<0x3d>, ISA_MIPS2, FGR_64; 612} 613 614let AdditionalPredicates = [NotInMicroMips] in { 615 def LDC1 : MMRel, StdMMR6Rel, LW_FT<"ldc1", AFGR64Opnd, mem_simm16, II_LDC1, 616 load>, LW_FM<0x35>, ISA_MIPS2, FGR_32 { 617 let BaseOpcode = "LDC132"; 618 } 619 def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_simm16, II_SDC1, store>, 620 LW_FM<0x3d>, ISA_MIPS2, FGR_32; 621} 622 623// Indexed loads and stores. 624// Base register + offset register addressing mode (indicated by "x" in the 625// instruction mnemonic) is disallowed under NaCl. 626let AdditionalPredicates = [IsNotNaCl] in { 627 def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>, 628 INSN_MIPS4_32R2_NOT_32R6_64R6; 629 def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>, 630 INSN_MIPS4_32R2_NOT_32R6_64R6; 631} 632 633let AdditionalPredicates = [NotInMicroMips, IsNotNaCl] in { 634 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>, 635 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 636 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>, 637 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 638} 639 640let DecoderNamespace="MipsFP64" in { 641 def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>, 642 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 643 def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>, 644 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 645} 646 647// Load/store doubleword indexed unaligned. 648// FIXME: This instruction should not be defined for FGR_32. 649let AdditionalPredicates = [IsNotNaCl, NotInMicroMips] in { 650 def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>, 651 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32; 652 def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>, 653 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32; 654} 655 656let AdditionalPredicates = [IsNotNaCl, NotInMicroMips], 657 DecoderNamespace="MipsFP64" in { 658 def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>, 659 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64; 660 def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>, 661 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64; 662} 663 664/// Floating-point Arithmetic 665let AdditionalPredicates = [NotInMicroMips] in { 666 def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, 667 ADDS_FM<0x00, 16>, ISA_MIPS1; 668 defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>, 669 ISA_MIPS1; 670 def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>, 671 ADDS_FM<0x03, 16>, ISA_MIPS1; 672 defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>, 673 ISA_MIPS1; 674 def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>, 675 ADDS_FM<0x02, 16>, ISA_MIPS1; 676 defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>, 677 ISA_MIPS1; 678 def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, 679 ADDS_FM<0x01, 16>, ISA_MIPS1; 680 defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>, 681 ISA_MIPS1; 682} 683 684let AdditionalPredicates = [NotInMicroMips, HasMadd4] in { 685 def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, 686 MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; 687 def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, 688 MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; 689 690 def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>, 691 MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 692 def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>, 693 MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 694 695 let DecoderNamespace = "MipsFP64" in { 696 def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>, 697 MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 698 def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>, 699 MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 700 } 701} 702 703let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in { 704 def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>, 705 MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; 706 def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>, 707 MADDS_FM<7, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; 708 709 def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>, 710 MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 711 def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>, 712 MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 713 714 let DecoderNamespace = "MipsFP64" in { 715 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>, 716 MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 717 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>, 718 MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 719 } 720} 721//===----------------------------------------------------------------------===// 722// Floating Point Branch Codes 723//===----------------------------------------------------------------------===// 724// Mips branch codes. These correspond to condcode in MipsInstrInfo.h. 725// They must be kept in synch. 726def MIPS_BRANCH_F : PatLeaf<(i32 0)>; 727def MIPS_BRANCH_T : PatLeaf<(i32 1)>; 728 729let AdditionalPredicates = [NotInMicroMips] in { 730 def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>, 731 BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6; 732 def BC1FL : MMRel, BC1XL_FT<"bc1fl", brtarget, II_BC1FL>, 733 BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6; 734 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>, 735 BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6; 736 def BC1TL : MMRel, BC1XL_FT<"bc1tl", brtarget, II_BC1TL>, 737 BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6; 738 739/// Floating Point Compare 740 def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>, 741 ISA_MIPS1_NOT_32R6_64R6 { 742 743 // FIXME: This is a required to work around the fact that these instructions 744 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the 745 // fcc register set is used directly. 746 bits<3> fcc = 0; 747 } 748 def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, 749 ISA_MIPS1_NOT_32R6_64R6, FGR_32 { 750 // FIXME: This is a required to work around the fact that these instructions 751 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the 752 // fcc register set is used directly. 753 bits<3> fcc = 0; 754 } 755} 756let DecoderNamespace = "MipsFP64" in 757def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, 758 ISA_MIPS1_NOT_32R6_64R6, FGR_64 { 759 // FIXME: This is a required to work around the fact that thiese instructions 760 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the 761 // fcc register set is used directly. 762 bits<3> fcc = 0; 763} 764 765//===----------------------------------------------------------------------===// 766// Floating Point Pseudo-Instructions 767//===----------------------------------------------------------------------===// 768 769// This pseudo instr gets expanded into 2 mtc1 instrs after register 770// allocation. 771class BuildPairF64Base<RegisterOperand RO> : 772 PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi), 773 [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))], 774 II_MTC1>; 775 776def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT; 777def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>, FGR_64, HARDFLOAT; 778 779// This pseudo instr gets expanded into 2 mfc1 instrs after register 780// allocation. 781// if n is 0, lower part of src is extracted. 782// if n is 1, higher part of src is extracted. 783// This node has associated scheduling information as the pre RA scheduler 784// asserts otherwise. 785class ExtractElementF64Base<RegisterOperand RO> : 786 PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n), 787 [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))], 788 II_MFC1>; 789 790def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT; 791def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>, FGR_64, HARDFLOAT; 792 793def PseudoTRUNC_W_S : MipsAsmPseudoInst<(outs FGR32Opnd:$fd), 794 (ins FGR32Opnd:$fs, GPR32Opnd:$rs), 795 "trunc.w.s\t$fd, $fs, $rs">; 796 797def PseudoTRUNC_W_D32 : MipsAsmPseudoInst<(outs FGR32Opnd:$fd), 798 (ins AFGR64Opnd:$fs, GPR32Opnd:$rs), 799 "trunc.w.d\t$fd, $fs, $rs">, 800 FGR_32, HARDFLOAT; 801 802def PseudoTRUNC_W_D : MipsAsmPseudoInst<(outs FGR32Opnd:$fd), 803 (ins FGR64Opnd:$fs, GPR32Opnd:$rs), 804 "trunc.w.d\t$fd, $fs, $rs">, 805 FGR_64, HARDFLOAT; 806 807def LoadImmSingleGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 808 (ins imm64:$fpimm), 809 "li.s\t$rd, $fpimm">; 810 811def LoadImmSingleFGR : MipsAsmPseudoInst<(outs StrictlyFGR32Opnd:$rd), 812 (ins imm64:$fpimm), 813 "li.s\t$rd, $fpimm">, 814 HARDFLOAT; 815 816def LoadImmDoubleGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 817 (ins imm64:$fpimm), 818 "li.d\t$rd, $fpimm">; 819 820def LoadImmDoubleFGR_32 : MipsAsmPseudoInst<(outs StrictlyAFGR64Opnd:$rd), 821 (ins imm64:$fpimm), 822 "li.d\t$rd, $fpimm">, 823 FGR_32, HARDFLOAT; 824 825def LoadImmDoubleFGR : MipsAsmPseudoInst<(outs StrictlyFGR64Opnd:$rd), 826 (ins imm64:$fpimm), 827 "li.d\t$rd, $fpimm">, 828 FGR_64, HARDFLOAT; 829 830def SDC1_M1 : MipsAsmPseudoInst<(outs AFGR64Opnd:$fd), 831 (ins mem_simm16:$addr), 832 "s.d\t$fd, $addr">, 833 FGR_32, ISA_MIPS1, HARDFLOAT; 834 835//===----------------------------------------------------------------------===// 836// InstAliases. 837//===----------------------------------------------------------------------===// 838def : MipsInstAlias 839 <"s.s $fd, $addr", (SWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>, 840 ISA_MIPS2, HARDFLOAT; 841def : MipsInstAlias 842 <"s.d $fd, $addr", (SDC1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>, 843 FGR_32, ISA_MIPS2, HARDFLOAT; 844def : MipsInstAlias 845 <"s.d $fd, $addr", (SDC164 FGR64Opnd:$fd, mem_simm16:$addr), 0>, 846 FGR_64, ISA_MIPS2, HARDFLOAT; 847def : MipsInstAlias 848 <"s.d $fd, $addr", (SDC1_M1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>, 849 FGR_32, ISA_MIPS1, HARDFLOAT; 850 851def : MipsInstAlias 852 <"l.s $fd, $addr", (LWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>, 853 ISA_MIPS2, HARDFLOAT; 854def : MipsInstAlias 855 <"l.d $fd, $addr", (LDC1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>, 856 FGR_32, ISA_MIPS2, HARDFLOAT; 857def : MipsInstAlias 858 <"l.d $fd, $addr", (LDC164 FGR64Opnd:$fd, mem_simm16:$addr), 0>, 859 FGR_64, ISA_MIPS2, HARDFLOAT; 860 861multiclass C_COND_ALIASES<string TypeStr, RegisterOperand RC> { 862 def : MipsInstAlias<!strconcat("c.f.", TypeStr, " $fs, $ft"), 863 (!cast<Instruction>("C_F_"#NAME) FCC0, 864 RC:$fs, RC:$ft), 1>; 865 def : MipsInstAlias<!strconcat("c.un.", TypeStr, " $fs, $ft"), 866 (!cast<Instruction>("C_UN_"#NAME) FCC0, 867 RC:$fs, RC:$ft), 1>; 868 def : MipsInstAlias<!strconcat("c.eq.", TypeStr, " $fs, $ft"), 869 (!cast<Instruction>("C_EQ_"#NAME) FCC0, 870 RC:$fs, RC:$ft), 1>; 871 def : MipsInstAlias<!strconcat("c.ueq.", TypeStr, " $fs, $ft"), 872 (!cast<Instruction>("C_UEQ_"#NAME) FCC0, 873 RC:$fs, RC:$ft), 1>; 874 def : MipsInstAlias<!strconcat("c.olt.", TypeStr, " $fs, $ft"), 875 (!cast<Instruction>("C_OLT_"#NAME) FCC0, 876 RC:$fs, RC:$ft), 1>; 877 def : MipsInstAlias<!strconcat("c.ult.", TypeStr, " $fs, $ft"), 878 (!cast<Instruction>("C_ULT_"#NAME) FCC0, 879 RC:$fs, RC:$ft), 1>; 880 def : MipsInstAlias<!strconcat("c.ole.", TypeStr, " $fs, $ft"), 881 (!cast<Instruction>("C_OLE_"#NAME) FCC0, 882 RC:$fs, RC:$ft), 1>; 883 def : MipsInstAlias<!strconcat("c.ule.", TypeStr, " $fs, $ft"), 884 (!cast<Instruction>("C_ULE_"#NAME) FCC0, 885 RC:$fs, RC:$ft), 1>; 886 def : MipsInstAlias<!strconcat("c.sf.", TypeStr, " $fs, $ft"), 887 (!cast<Instruction>("C_SF_"#NAME) FCC0, 888 RC:$fs, RC:$ft), 1>; 889 def : MipsInstAlias<!strconcat("c.ngle.", TypeStr, " $fs, $ft"), 890 (!cast<Instruction>("C_NGLE_"#NAME) FCC0, 891 RC:$fs, RC:$ft), 1>; 892 def : MipsInstAlias<!strconcat("c.seq.", TypeStr, " $fs, $ft"), 893 (!cast<Instruction>("C_SEQ_"#NAME) FCC0, 894 RC:$fs, RC:$ft), 1>; 895 def : MipsInstAlias<!strconcat("c.ngl.", TypeStr, " $fs, $ft"), 896 (!cast<Instruction>("C_NGL_"#NAME) FCC0, 897 RC:$fs, RC:$ft), 1>; 898 def : MipsInstAlias<!strconcat("c.lt.", TypeStr, " $fs, $ft"), 899 (!cast<Instruction>("C_LT_"#NAME) FCC0, 900 RC:$fs, RC:$ft), 1>; 901 def : MipsInstAlias<!strconcat("c.nge.", TypeStr, " $fs, $ft"), 902 (!cast<Instruction>("C_NGE_"#NAME) FCC0, 903 RC:$fs, RC:$ft), 1>; 904 def : MipsInstAlias<!strconcat("c.le.", TypeStr, " $fs, $ft"), 905 (!cast<Instruction>("C_LE_"#NAME) FCC0, 906 RC:$fs, RC:$ft), 1>; 907 def : MipsInstAlias<!strconcat("c.ngt.", TypeStr, " $fs, $ft"), 908 (!cast<Instruction>("C_NGT_"#NAME) FCC0, 909 RC:$fs, RC:$ft), 1>; 910} 911 912multiclass BC1_ALIASES<Instruction BCTrue, string BCTrueString, 913 Instruction BCFalse, string BCFalseString> { 914 def : MipsInstAlias<!strconcat(BCTrueString, " $offset"), 915 (BCTrue FCC0, brtarget:$offset), 1>; 916 917 def : MipsInstAlias<!strconcat(BCFalseString, " $offset"), 918 (BCFalse FCC0, brtarget:$offset), 1>; 919} 920 921let AdditionalPredicates = [NotInMicroMips] in { 922 defm S : C_COND_ALIASES<"s", FGR32Opnd>, HARDFLOAT, 923 ISA_MIPS1_NOT_32R6_64R6; 924 defm D32 : C_COND_ALIASES<"d", AFGR64Opnd>, HARDFLOAT, 925 ISA_MIPS1_NOT_32R6_64R6, FGR_32; 926 defm D64 : C_COND_ALIASES<"d", FGR64Opnd>, HARDFLOAT, 927 ISA_MIPS1_NOT_32R6_64R6, FGR_64; 928 929 defm : BC1_ALIASES<BC1T, "bc1t", BC1F, "bc1f">, ISA_MIPS1_NOT_32R6_64R6, 930 HARDFLOAT; 931 defm : BC1_ALIASES<BC1TL, "bc1tl", BC1FL, "bc1fl">, ISA_MIPS2_NOT_32R6_64R6, 932 HARDFLOAT; 933} 934//===----------------------------------------------------------------------===// 935// Floating Point Patterns 936//===----------------------------------------------------------------------===// 937def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>, ISA_MIPS1; 938def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>, ISA_MIPS1; 939 940def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)), 941 (PseudoCVT_S_W GPR32Opnd:$src)>; 942def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), 943 (TRUNC_W_S FGR32Opnd:$src)>, ISA_MIPS1; 944 945def : MipsPat<(MipsMTC1_D64 GPR32Opnd:$src), 946 (MTC1_D64 GPR32Opnd:$src)>, ISA_MIPS1, FGR_64; 947 948def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), 949 (PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32; 950let AdditionalPredicates = [NotInMicroMips] in { 951 def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src), 952 (TRUNC_W_D32 AFGR64Opnd:$src)>, ISA_MIPS2, FGR_32; 953 def : MipsPat<(f32 (fpround AFGR64Opnd:$src)), 954 (CVT_S_D32 AFGR64Opnd:$src)>, ISA_MIPS1, FGR_32; 955 def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), 956 (CVT_D32_S FGR32Opnd:$src)>, ISA_MIPS1, FGR_32; 957} 958 959def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, ISA_MIPS3, GPR_64, FGR_64; 960def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, ISA_MIPS3, GPR_64, 961 FGR_64; 962 963def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), 964 (PseudoCVT_D64_W GPR32Opnd:$src)>, FGR_64; 965def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)), 966 (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>, FGR_64; 967def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)), 968 (PseudoCVT_D64_L GPR64Opnd:$src)>, FGR_64; 969 970def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), 971 (TRUNC_W_D64 FGR64Opnd:$src)>, ISA_MIPS2, FGR_64; 972def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), 973 (TRUNC_L_S FGR32Opnd:$src)>, ISA_MIPS2, FGR_64; 974def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), 975 (TRUNC_L_D64 FGR64Opnd:$src)>, ISA_MIPS2, FGR_64; 976 977let AdditionalPredicates = [NotInMicroMips] in { 978 def : MipsPat<(f32 (fpround FGR64Opnd:$src)), 979 (CVT_S_D64 FGR64Opnd:$src)>, ISA_MIPS1, FGR_64; 980 def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), 981 (CVT_D64_S FGR32Opnd:$src)>, ISA_MIPS1, FGR_64; 982} 983 984// To generate NMADD and NMSUB instructions when fneg node is present 985multiclass NMADD_NMSUB<Instruction Nmadd, Instruction Nmsub, RegisterOperand RC> { 986 def : MipsPat<(fneg (fadd (fmul RC:$fs, RC:$ft), RC:$fr)), 987 (Nmadd RC:$fr, RC:$fs, RC:$ft)>; 988 def : MipsPat<(fneg (fsub (fmul RC:$fs, RC:$ft), RC:$fr)), 989 (Nmsub RC:$fr, RC:$fs, RC:$ft)>; 990} 991 992let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in { 993 defm : NMADD_NMSUB<NMADD_S, NMSUB_S, FGR32Opnd>, 994 INSN_MIPS4_32R2_NOT_32R6_64R6; 995 defm : NMADD_NMSUB<NMADD_D32, NMSUB_D32, AFGR64Opnd>, 996 FGR_32, INSN_MIPS4_32R2_NOT_32R6_64R6; 997 defm : NMADD_NMSUB<NMADD_D64, NMSUB_D64, FGR64Opnd>, 998 FGR_64, INSN_MIPS4_32R2_NOT_32R6_64R6; 999} 1000 1001// Patterns for loads/stores with a reg+imm operand. 1002let AdditionalPredicates = [NotInMicroMips] in { 1003 let AddedComplexity = 40 in { 1004 def : LoadRegImmPat<LWC1, f32, load>, ISA_MIPS1; 1005 def : StoreRegImmPat<SWC1, f32>, ISA_MIPS1; 1006 1007 def : LoadRegImmPat<LDC164, f64, load>, ISA_MIPS1, FGR_64; 1008 def : StoreRegImmPat<SDC164, f64>, ISA_MIPS1, FGR_64; 1009 1010 def : LoadRegImmPat<LDC1, f64, load>, ISA_MIPS1, FGR_32; 1011 def : StoreRegImmPat<SDC1, f64>, ISA_MIPS1, FGR_32; 1012 } 1013} 1014