1 //===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that Mips uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "MipsISelLowering.h"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "MCTargetDesc/MipsInstPrinter.h"
17 #include "MCTargetDesc/MipsMCTargetDesc.h"
18 #include "MipsCCState.h"
19 #include "MipsInstrInfo.h"
20 #include "MipsMachineFunction.h"
21 #include "MipsRegisterInfo.h"
22 #include "MipsSubtarget.h"
23 #include "MipsTargetMachine.h"
24 #include "MipsTargetObjectFile.h"
25 #include "llvm/ADT/APFloat.h"
26 #include "llvm/ADT/ArrayRef.h"
27 #include "llvm/ADT/SmallVector.h"
28 #include "llvm/ADT/Statistic.h"
29 #include "llvm/ADT/StringRef.h"
30 #include "llvm/ADT/StringSwitch.h"
31 #include "llvm/CodeGen/CallingConvLower.h"
32 #include "llvm/CodeGen/FunctionLoweringInfo.h"
33 #include "llvm/CodeGen/ISDOpcodes.h"
34 #include "llvm/CodeGen/MachineBasicBlock.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineFunction.h"
37 #include "llvm/CodeGen/MachineInstr.h"
38 #include "llvm/CodeGen/MachineInstrBuilder.h"
39 #include "llvm/CodeGen/MachineJumpTableInfo.h"
40 #include "llvm/CodeGen/MachineMemOperand.h"
41 #include "llvm/CodeGen/MachineOperand.h"
42 #include "llvm/CodeGen/MachineRegisterInfo.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/CodeGen/SelectionDAGNodes.h"
45 #include "llvm/CodeGen/TargetFrameLowering.h"
46 #include "llvm/CodeGen/TargetInstrInfo.h"
47 #include "llvm/CodeGen/TargetRegisterInfo.h"
48 #include "llvm/CodeGen/ValueTypes.h"
49 #include "llvm/CodeGenTypes/MachineValueType.h"
50 #include "llvm/IR/CallingConv.h"
51 #include "llvm/IR/Constants.h"
52 #include "llvm/IR/DataLayout.h"
53 #include "llvm/IR/DebugLoc.h"
54 #include "llvm/IR/DerivedTypes.h"
55 #include "llvm/IR/Function.h"
56 #include "llvm/IR/GlobalValue.h"
57 #include "llvm/IR/Module.h"
58 #include "llvm/IR/Type.h"
59 #include "llvm/IR/Value.h"
60 #include "llvm/MC/MCContext.h"
61 #include "llvm/Support/Casting.h"
62 #include "llvm/Support/CodeGen.h"
63 #include "llvm/Support/CommandLine.h"
64 #include "llvm/Support/Compiler.h"
65 #include "llvm/Support/ErrorHandling.h"
66 #include "llvm/Support/MathExtras.h"
67 #include "llvm/Target/TargetMachine.h"
68 #include "llvm/Target/TargetOptions.h"
69 #include <algorithm>
70 #include <cassert>
71 #include <cctype>
72 #include <cstdint>
73 #include <deque>
74 #include <iterator>
75 #include <utility>
76 #include <vector>
77
78 using namespace llvm;
79
80 #define DEBUG_TYPE "mips-lower"
81
82 STATISTIC(NumTailCalls, "Number of tail calls");
83
84 static cl::opt<bool>
85 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
86 cl::desc("MIPS: Don't trap on integer division by zero."),
87 cl::init(false));
88
89 extern cl::opt<bool> EmitJalrReloc;
90
91 static const MCPhysReg Mips64DPRegs[8] = {
92 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
93 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
94 };
95
96 // The MIPS MSA ABI passes vector arguments in the integer register set.
97 // The number of integer registers used is dependant on the ABI used.
getRegisterTypeForCallingConv(LLVMContext & Context,CallingConv::ID CC,EVT VT) const98 MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
99 CallingConv::ID CC,
100 EVT VT) const {
101 if (!VT.isVector())
102 return getRegisterType(Context, VT);
103
104 if (VT.isPow2VectorType() && VT.getVectorElementType().isRound())
105 return Subtarget.isABI_O32() || VT.getSizeInBits() == 32 ? MVT::i32
106 : MVT::i64;
107 return getRegisterType(Context, VT.getVectorElementType());
108 }
109
getNumRegistersForCallingConv(LLVMContext & Context,CallingConv::ID CC,EVT VT) const110 unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
111 CallingConv::ID CC,
112 EVT VT) const {
113 if (VT.isVector()) {
114 if (VT.isPow2VectorType() && VT.getVectorElementType().isRound())
115 return divideCeil(VT.getSizeInBits(), Subtarget.isABI_O32() ? 32 : 64);
116 return VT.getVectorNumElements() *
117 getNumRegisters(Context, VT.getVectorElementType());
118 }
119 return MipsTargetLowering::getNumRegisters(Context, VT);
120 }
121
getVectorTypeBreakdownForCallingConv(LLVMContext & Context,CallingConv::ID CC,EVT VT,EVT & IntermediateVT,unsigned & NumIntermediates,MVT & RegisterVT) const122 unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv(
123 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
124 unsigned &NumIntermediates, MVT &RegisterVT) const {
125 if (VT.isPow2VectorType() && VT.getVectorElementType().isRound()) {
126 IntermediateVT = getRegisterTypeForCallingConv(Context, CC, VT);
127 RegisterVT = IntermediateVT.getSimpleVT();
128 NumIntermediates = getNumRegistersForCallingConv(Context, CC, VT);
129 return NumIntermediates;
130 }
131 IntermediateVT = VT.getVectorElementType();
132 NumIntermediates = VT.getVectorNumElements();
133 RegisterVT = getRegisterType(Context, IntermediateVT);
134 return NumIntermediates * getNumRegisters(Context, IntermediateVT);
135 }
136
getGlobalReg(SelectionDAG & DAG,EVT Ty) const137 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
138 MachineFunction &MF = DAG.getMachineFunction();
139 MipsFunctionInfo *FI = MF.getInfo<MipsFunctionInfo>();
140 return DAG.getRegister(FI->getGlobalBaseReg(MF), Ty);
141 }
142
getTargetNode(GlobalAddressSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flag) const143 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
144 SelectionDAG &DAG,
145 unsigned Flag) const {
146 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
147 }
148
getTargetNode(ExternalSymbolSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flag) const149 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
150 SelectionDAG &DAG,
151 unsigned Flag) const {
152 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
153 }
154
getTargetNode(BlockAddressSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flag) const155 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
156 SelectionDAG &DAG,
157 unsigned Flag) const {
158 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
159 }
160
getTargetNode(JumpTableSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flag) const161 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
162 SelectionDAG &DAG,
163 unsigned Flag) const {
164 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
165 }
166
getTargetNode(ConstantPoolSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flag) const167 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
168 SelectionDAG &DAG,
169 unsigned Flag) const {
170 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlign(),
171 N->getOffset(), Flag);
172 }
173
getTargetNodeName(unsigned Opcode) const174 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
175 switch ((MipsISD::NodeType)Opcode) {
176 case MipsISD::FIRST_NUMBER: break;
177 case MipsISD::JmpLink: return "MipsISD::JmpLink";
178 case MipsISD::TailCall: return "MipsISD::TailCall";
179 case MipsISD::Highest: return "MipsISD::Highest";
180 case MipsISD::Higher: return "MipsISD::Higher";
181 case MipsISD::Hi: return "MipsISD::Hi";
182 case MipsISD::Lo: return "MipsISD::Lo";
183 case MipsISD::GotHi: return "MipsISD::GotHi";
184 case MipsISD::TlsHi: return "MipsISD::TlsHi";
185 case MipsISD::GPRel: return "MipsISD::GPRel";
186 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
187 case MipsISD::Ret: return "MipsISD::Ret";
188 case MipsISD::ERet: return "MipsISD::ERet";
189 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
190 case MipsISD::FAbs: return "MipsISD::FAbs";
191 case MipsISD::FMS: return "MipsISD::FMS";
192 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
193 case MipsISD::FPCmp: return "MipsISD::FPCmp";
194 case MipsISD::FSELECT: return "MipsISD::FSELECT";
195 case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64";
196 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
197 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
198 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
199 case MipsISD::MFHI: return "MipsISD::MFHI";
200 case MipsISD::MFLO: return "MipsISD::MFLO";
201 case MipsISD::MTLOHI: return "MipsISD::MTLOHI";
202 case MipsISD::Mult: return "MipsISD::Mult";
203 case MipsISD::Multu: return "MipsISD::Multu";
204 case MipsISD::MAdd: return "MipsISD::MAdd";
205 case MipsISD::MAddu: return "MipsISD::MAddu";
206 case MipsISD::MSub: return "MipsISD::MSub";
207 case MipsISD::MSubu: return "MipsISD::MSubu";
208 case MipsISD::DivRem: return "MipsISD::DivRem";
209 case MipsISD::DivRemU: return "MipsISD::DivRemU";
210 case MipsISD::DivRem16: return "MipsISD::DivRem16";
211 case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
212 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
213 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
214 case MipsISD::Wrapper: return "MipsISD::Wrapper";
215 case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
216 case MipsISD::Sync: return "MipsISD::Sync";
217 case MipsISD::Ext: return "MipsISD::Ext";
218 case MipsISD::Ins: return "MipsISD::Ins";
219 case MipsISD::CIns: return "MipsISD::CIns";
220 case MipsISD::LWL: return "MipsISD::LWL";
221 case MipsISD::LWR: return "MipsISD::LWR";
222 case MipsISD::SWL: return "MipsISD::SWL";
223 case MipsISD::SWR: return "MipsISD::SWR";
224 case MipsISD::LDL: return "MipsISD::LDL";
225 case MipsISD::LDR: return "MipsISD::LDR";
226 case MipsISD::SDL: return "MipsISD::SDL";
227 case MipsISD::SDR: return "MipsISD::SDR";
228 case MipsISD::EXTP: return "MipsISD::EXTP";
229 case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
230 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
231 case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
232 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
233 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
234 case MipsISD::SHILO: return "MipsISD::SHILO";
235 case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
236 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH";
237 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL";
238 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR";
239 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL";
240 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR";
241 case MipsISD::DOUBLE_SELECT_I: return "MipsISD::DOUBLE_SELECT_I";
242 case MipsISD::DOUBLE_SELECT_I64: return "MipsISD::DOUBLE_SELECT_I64";
243 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL";
244 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR";
245 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL";
246 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR";
247 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH";
248 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH";
249 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W";
250 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W";
251 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH";
252 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH";
253 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH";
254 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH";
255 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH";
256 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH";
257 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH";
258 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH";
259 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH";
260 case MipsISD::MULT: return "MipsISD::MULT";
261 case MipsISD::MULTU: return "MipsISD::MULTU";
262 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
263 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
264 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
265 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
266 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
267 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
268 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
269 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
270 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
271 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO";
272 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
273 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
274 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
275 case MipsISD::VCEQ: return "MipsISD::VCEQ";
276 case MipsISD::VCLE_S: return "MipsISD::VCLE_S";
277 case MipsISD::VCLE_U: return "MipsISD::VCLE_U";
278 case MipsISD::VCLT_S: return "MipsISD::VCLT_S";
279 case MipsISD::VCLT_U: return "MipsISD::VCLT_U";
280 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
281 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
282 case MipsISD::VNOR: return "MipsISD::VNOR";
283 case MipsISD::VSHF: return "MipsISD::VSHF";
284 case MipsISD::SHF: return "MipsISD::SHF";
285 case MipsISD::ILVEV: return "MipsISD::ILVEV";
286 case MipsISD::ILVOD: return "MipsISD::ILVOD";
287 case MipsISD::ILVL: return "MipsISD::ILVL";
288 case MipsISD::ILVR: return "MipsISD::ILVR";
289 case MipsISD::PCKEV: return "MipsISD::PCKEV";
290 case MipsISD::PCKOD: return "MipsISD::PCKOD";
291 case MipsISD::INSVE: return "MipsISD::INSVE";
292 }
293 return nullptr;
294 }
295
MipsTargetLowering(const MipsTargetMachine & TM,const MipsSubtarget & STI)296 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
297 const MipsSubtarget &STI)
298 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
299 // Mips does not have i1 type, so use i32 for
300 // setcc operations results (slt, sgt, ...).
301 setBooleanContents(ZeroOrOneBooleanContent);
302 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
303 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
304 // does. Integer booleans still use 0 and 1.
305 if (Subtarget.hasMips32r6())
306 setBooleanContents(ZeroOrOneBooleanContent,
307 ZeroOrNegativeOneBooleanContent);
308
309 // Load extented operations for i1 types must be promoted
310 for (MVT VT : MVT::integer_valuetypes()) {
311 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
312 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
313 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
314 }
315
316 // MIPS doesn't have extending float->double load/store. Set LoadExtAction
317 // for f32, f16
318 for (MVT VT : MVT::fp_valuetypes()) {
319 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
320 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
321 }
322
323 // Set LoadExtAction for f16 vectors to Expand
324 for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) {
325 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements());
326 if (F16VT.isValid())
327 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand);
328 }
329
330 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
331 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
332
333 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
334
335 // Used by legalize types to correctly generate the setcc result.
336 // Without this, every float setcc comes with a AND/OR with the result,
337 // we don't want this, since the fpcmp result goes to a flag register,
338 // which is used implicitly by brcond and select operations.
339 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
340
341 // Mips Custom Operations
342 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
343 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
344 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
345 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
346 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
347 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
348 setOperationAction(ISD::SELECT, MVT::f32, Custom);
349 setOperationAction(ISD::SELECT, MVT::f64, Custom);
350 setOperationAction(ISD::SELECT, MVT::i32, Custom);
351 setOperationAction(ISD::SETCC, MVT::f32, Custom);
352 setOperationAction(ISD::SETCC, MVT::f64, Custom);
353 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
354 setOperationAction(ISD::FABS, MVT::f32, Custom);
355 setOperationAction(ISD::FABS, MVT::f64, Custom);
356 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
357 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
358 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
359
360 if (Subtarget.hasMips32r2() ||
361 getTargetMachine().getTargetTriple().isOSLinux())
362 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
363
364 // Lower fmin/fmax/fclass operations for MIPS R6.
365 if (Subtarget.hasMips32r6()) {
366 setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal);
367 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal);
368 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
369 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
370 setOperationAction(ISD::FMINNUM_IEEE, MVT::f64, Legal);
371 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal);
372 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
373 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
374 setOperationAction(ISD::IS_FPCLASS, MVT::f32, Legal);
375 setOperationAction(ISD::IS_FPCLASS, MVT::f64, Legal);
376 setOperationAction(ISD::FCANONICALIZE, MVT::f32, Legal);
377 setOperationAction(ISD::FCANONICALIZE, MVT::f64, Legal);
378 } else {
379 setOperationAction(ISD::FCANONICALIZE, MVT::f32, Custom);
380 setOperationAction(ISD::FCANONICALIZE, MVT::f64, Custom);
381 }
382
383 if (Subtarget.isGP64bit()) {
384 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
385 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
386 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
387 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
388 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
389 setOperationAction(ISD::SELECT, MVT::i64, Custom);
390 if (Subtarget.hasMips64r6()) {
391 setOperationAction(ISD::LOAD, MVT::i64, Legal);
392 setOperationAction(ISD::STORE, MVT::i64, Legal);
393 } else {
394 setOperationAction(ISD::LOAD, MVT::i64, Custom);
395 setOperationAction(ISD::STORE, MVT::i64, Custom);
396 }
397 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
398 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
399 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
400 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
401 }
402
403 if (!Subtarget.isGP64bit()) {
404 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
405 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
406 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
407 }
408
409 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
410 if (Subtarget.isGP64bit())
411 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom);
412
413 setOperationAction(ISD::SDIV, MVT::i32, Expand);
414 setOperationAction(ISD::SREM, MVT::i32, Expand);
415 setOperationAction(ISD::UDIV, MVT::i32, Expand);
416 setOperationAction(ISD::UREM, MVT::i32, Expand);
417 setOperationAction(ISD::SDIV, MVT::i64, Expand);
418 setOperationAction(ISD::SREM, MVT::i64, Expand);
419 setOperationAction(ISD::UDIV, MVT::i64, Expand);
420 setOperationAction(ISD::UREM, MVT::i64, Expand);
421
422 // Operations not directly supported by Mips.
423 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
424 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
425 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
426 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
427 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
428 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
429 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
430 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
431 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
432 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
433 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
434 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
435 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
436 if (Subtarget.hasCnMips()) {
437 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
438 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
439 } else {
440 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
441 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
442 }
443 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
444 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
445 setOperationAction(ISD::ROTL, MVT::i32, Expand);
446 setOperationAction(ISD::ROTL, MVT::i64, Expand);
447 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
448 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
449
450 if (!Subtarget.hasMips32r2())
451 setOperationAction(ISD::ROTR, MVT::i32, Expand);
452
453 if (!Subtarget.hasMips64r2())
454 setOperationAction(ISD::ROTR, MVT::i64, Expand);
455
456 setOperationAction(ISD::FSIN, MVT::f32, Expand);
457 setOperationAction(ISD::FSIN, MVT::f64, Expand);
458 setOperationAction(ISD::FCOS, MVT::f32, Expand);
459 setOperationAction(ISD::FCOS, MVT::f64, Expand);
460 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
461 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
462 setOperationAction(ISD::FPOW, MVT::f32, Expand);
463 setOperationAction(ISD::FPOW, MVT::f64, Expand);
464 setOperationAction(ISD::FLOG, MVT::f32, Expand);
465 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
466 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
467 setOperationAction(ISD::FEXP, MVT::f32, Expand);
468 setOperationAction(ISD::FMA, MVT::f32, Expand);
469 setOperationAction(ISD::FMA, MVT::f64, Expand);
470 setOperationAction(ISD::FREM, MVT::f32, Expand);
471 setOperationAction(ISD::FREM, MVT::f64, Expand);
472
473 // Lower f16 conversion operations into library calls
474 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
475 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
476 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
477 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
478
479 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
480
481 setOperationAction(ISD::VASTART, MVT::Other, Custom);
482 setOperationAction(ISD::VAARG, MVT::Other, Custom);
483 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
484 setOperationAction(ISD::VAEND, MVT::Other, Expand);
485
486 // Use the default for now
487 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
488 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
489
490 if (!Subtarget.isGP64bit()) {
491 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
492 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
493 }
494
495 if (!Subtarget.hasMips32r2()) {
496 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
497 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
498 }
499
500 // MIPS16 lacks MIPS32's clz and clo instructions.
501 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode())
502 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
503 if (!Subtarget.hasMips64())
504 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
505
506 if (!Subtarget.hasMips32r2())
507 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
508 if (!Subtarget.hasMips64r2())
509 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
510
511 if (Subtarget.isGP64bit() && Subtarget.hasMips64r6()) {
512 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Legal);
513 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Legal);
514 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Legal);
515 setTruncStoreAction(MVT::i64, MVT::i32, Legal);
516 } else if (Subtarget.isGP64bit()) {
517 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom);
518 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom);
519 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom);
520 setTruncStoreAction(MVT::i64, MVT::i32, Custom);
521 }
522
523 setOperationAction(ISD::TRAP, MVT::Other, Legal);
524
525 setTargetDAGCombine({ISD::SDIVREM, ISD::UDIVREM, ISD::SELECT, ISD::AND,
526 ISD::OR, ISD::ADD, ISD::SUB, ISD::AssertZext, ISD::SHL,
527 ISD::SIGN_EXTEND});
528
529 if (Subtarget.isGP64bit())
530 setMaxAtomicSizeInBitsSupported(64);
531 else
532 setMaxAtomicSizeInBitsSupported(32);
533
534 setMinFunctionAlignment(Subtarget.isGP64bit() ? Align(8) : Align(4));
535
536 // The arguments on the stack are defined in terms of 4-byte slots on O32
537 // and 8-byte slots on N32/N64.
538 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? Align(8)
539 : Align(4));
540
541 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP);
542
543 MaxStoresPerMemcpy = 16;
544
545 isMicroMips = Subtarget.inMicroMipsMode();
546 }
547
548 const MipsTargetLowering *
create(const MipsTargetMachine & TM,const MipsSubtarget & STI)549 MipsTargetLowering::create(const MipsTargetMachine &TM,
550 const MipsSubtarget &STI) {
551 if (STI.inMips16Mode())
552 return createMips16TargetLowering(TM, STI);
553
554 return createMipsSETargetLowering(TM, STI);
555 }
556
557 // Create a fast isel object.
558 FastISel *
createFastISel(FunctionLoweringInfo & funcInfo,const TargetLibraryInfo * libInfo) const559 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
560 const TargetLibraryInfo *libInfo) const {
561 const MipsTargetMachine &TM =
562 static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget());
563
564 // We support only the standard encoding [MIPS32,MIPS32R5] ISAs.
565 bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() &&
566 !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() &&
567 !Subtarget.inMicroMipsMode();
568
569 // Disable if either of the following is true:
570 // We do not generate PIC, the ABI is not O32, XGOT is being used.
571 if (!TM.isPositionIndependent() || !TM.getABI().IsO32() ||
572 Subtarget.useXGOT())
573 UseFastISel = false;
574
575 return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr;
576 }
577
getSetCCResultType(const DataLayout &,LLVMContext &,EVT VT) const578 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
579 EVT VT) const {
580 if (!VT.isVector())
581 return MVT::i32;
582 return VT.changeVectorElementTypeToInteger();
583 }
584
performDivRemCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)585 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
586 TargetLowering::DAGCombinerInfo &DCI,
587 const MipsSubtarget &Subtarget) {
588 if (DCI.isBeforeLegalizeOps())
589 return SDValue();
590
591 EVT Ty = N->getValueType(0);
592 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
593 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
594 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
595 MipsISD::DivRemU16;
596 SDLoc DL(N);
597
598 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
599 N->getOperand(0), N->getOperand(1));
600 SDValue InChain = DAG.getEntryNode();
601 SDValue InGlue = DivRem;
602
603 // insert MFLO
604 if (N->hasAnyUseOfValue(0)) {
605 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
606 InGlue);
607 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
608 InChain = CopyFromLo.getValue(1);
609 InGlue = CopyFromLo.getValue(2);
610 }
611
612 // insert MFHI
613 if (N->hasAnyUseOfValue(1)) {
614 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
615 HI, Ty, InGlue);
616 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
617 }
618
619 return SDValue();
620 }
621
condCodeToFCC(ISD::CondCode CC)622 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
623 switch (CC) {
624 default: llvm_unreachable("Unknown fp condition code!");
625 case ISD::SETEQ:
626 case ISD::SETOEQ: return Mips::FCOND_OEQ;
627 case ISD::SETUNE: return Mips::FCOND_UNE;
628 case ISD::SETLT:
629 case ISD::SETOLT: return Mips::FCOND_OLT;
630 case ISD::SETGT:
631 case ISD::SETOGT: return Mips::FCOND_OGT;
632 case ISD::SETLE:
633 case ISD::SETOLE: return Mips::FCOND_OLE;
634 case ISD::SETGE:
635 case ISD::SETOGE: return Mips::FCOND_OGE;
636 case ISD::SETULT: return Mips::FCOND_ULT;
637 case ISD::SETULE: return Mips::FCOND_ULE;
638 case ISD::SETUGT: return Mips::FCOND_UGT;
639 case ISD::SETUGE: return Mips::FCOND_UGE;
640 case ISD::SETUO: return Mips::FCOND_UN;
641 case ISD::SETO: return Mips::FCOND_OR;
642 case ISD::SETNE:
643 case ISD::SETONE: return Mips::FCOND_ONE;
644 case ISD::SETUEQ: return Mips::FCOND_UEQ;
645 }
646 }
647
648 /// This function returns true if the floating point conditional branches and
649 /// conditional moves which use condition code CC should be inverted.
invertFPCondCodeUser(Mips::CondCode CC)650 static bool invertFPCondCodeUser(Mips::CondCode CC) {
651 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
652 return false;
653
654 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
655 "Illegal Condition Code");
656
657 return true;
658 }
659
660 // Creates and returns an FPCmp node from a setcc node.
661 // Returns Op if setcc is not a floating point comparison.
createFPCmp(SelectionDAG & DAG,const SDValue & Op)662 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
663 // must be a SETCC node
664 if (Op.getOpcode() != ISD::SETCC)
665 return Op;
666
667 SDValue LHS = Op.getOperand(0);
668
669 if (!LHS.getValueType().isFloatingPoint())
670 return Op;
671
672 SDValue RHS = Op.getOperand(1);
673 SDLoc DL(Op);
674
675 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
676 // node if necessary.
677 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
678
679 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
680 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32));
681 }
682
683 // Creates and returns a CMovFPT/F node.
createCMovFP(SelectionDAG & DAG,SDValue Cond,SDValue True,SDValue False,const SDLoc & DL)684 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
685 SDValue False, const SDLoc &DL) {
686 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
687 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
688 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
689
690 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
691 True.getValueType(), True, FCC0, False, Cond);
692 }
693
performSELECTCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)694 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
695 TargetLowering::DAGCombinerInfo &DCI,
696 const MipsSubtarget &Subtarget) {
697 if (DCI.isBeforeLegalizeOps())
698 return SDValue();
699
700 SDValue SetCC = N->getOperand(0);
701
702 if ((SetCC.getOpcode() != ISD::SETCC) ||
703 !SetCC.getOperand(0).getValueType().isInteger())
704 return SDValue();
705
706 SDValue False = N->getOperand(2);
707 EVT FalseTy = False.getValueType();
708
709 if (!FalseTy.isInteger())
710 return SDValue();
711
712 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
713
714 // If the RHS (False) is 0, we swap the order of the operands
715 // of ISD::SELECT (obviously also inverting the condition) so that we can
716 // take advantage of conditional moves using the $0 register.
717 // Example:
718 // return (a != 0) ? x : 0;
719 // load $reg, x
720 // movz $reg, $0, a
721 if (!FalseC)
722 return SDValue();
723
724 const SDLoc DL(N);
725
726 if (!FalseC->getZExtValue()) {
727 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
728 SDValue True = N->getOperand(1);
729
730 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
731 SetCC.getOperand(1),
732 ISD::getSetCCInverse(CC, SetCC.getValueType()));
733
734 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
735 }
736
737 // If both operands are integer constants there's a possibility that we
738 // can do some interesting optimizations.
739 SDValue True = N->getOperand(1);
740 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
741
742 if (!TrueC || !True.getValueType().isInteger())
743 return SDValue();
744
745 // We'll also ignore MVT::i64 operands as this optimizations proves
746 // to be ineffective because of the required sign extensions as the result
747 // of a SETCC operator is always MVT::i32 for non-vector types.
748 if (True.getValueType() == MVT::i64)
749 return SDValue();
750
751 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
752
753 // 1) (a < x) ? y : y-1
754 // slti $reg1, a, x
755 // addiu $reg2, $reg1, y-1
756 if (Diff == 1)
757 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
758
759 // 2) (a < x) ? y-1 : y
760 // slti $reg1, a, x
761 // xor $reg1, $reg1, 1
762 // addiu $reg2, $reg1, y-1
763 if (Diff == -1) {
764 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
765 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
766 SetCC.getOperand(1),
767 ISD::getSetCCInverse(CC, SetCC.getValueType()));
768 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
769 }
770
771 // Could not optimize.
772 return SDValue();
773 }
774
performCMovFPCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)775 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG,
776 TargetLowering::DAGCombinerInfo &DCI,
777 const MipsSubtarget &Subtarget) {
778 if (DCI.isBeforeLegalizeOps())
779 return SDValue();
780
781 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2);
782
783 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse);
784 if (!FalseC || FalseC->getZExtValue())
785 return SDValue();
786
787 // Since RHS (False) is 0, we swap the order of the True/False operands
788 // (obviously also inverting the condition) so that we can
789 // take advantage of conditional moves using the $0 register.
790 // Example:
791 // return (a != 0) ? x : 0;
792 // load $reg, x
793 // movz $reg, $0, a
794 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F :
795 MipsISD::CMovFP_T;
796
797 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3);
798 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(),
799 ValueIfFalse, FCC, ValueIfTrue, Glue);
800 }
801
performANDCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)802 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
803 TargetLowering::DAGCombinerInfo &DCI,
804 const MipsSubtarget &Subtarget) {
805 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
806 return SDValue();
807
808 SDValue FirstOperand = N->getOperand(0);
809 unsigned FirstOperandOpc = FirstOperand.getOpcode();
810 SDValue Mask = N->getOperand(1);
811 EVT ValTy = N->getValueType(0);
812 SDLoc DL(N);
813
814 uint64_t Pos = 0;
815 unsigned SMPos, SMSize;
816 ConstantSDNode *CN;
817 SDValue NewOperand;
818 unsigned Opc;
819
820 // Op's second operand must be a shifted mask.
821 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
822 !isShiftedMask_64(CN->getZExtValue(), SMPos, SMSize))
823 return SDValue();
824
825 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) {
826 // Pattern match EXT.
827 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
828 // => ext $dst, $src, pos, size
829
830 // The second operand of the shift must be an immediate.
831 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
832 return SDValue();
833
834 Pos = CN->getZExtValue();
835
836 // Return if the shifted mask does not start at bit 0 or the sum of its size
837 // and Pos exceeds the word's size.
838 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
839 return SDValue();
840
841 Opc = MipsISD::Ext;
842 NewOperand = FirstOperand.getOperand(0);
843 } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) {
844 // Pattern match CINS.
845 // $dst = and (shl $src , pos), mask
846 // => cins $dst, $src, pos, size
847 // mask is a shifted mask with consecutive 1's, pos = shift amount,
848 // size = population count.
849
850 // The second operand of the shift must be an immediate.
851 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
852 return SDValue();
853
854 Pos = CN->getZExtValue();
855
856 if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 ||
857 Pos + SMSize > ValTy.getSizeInBits())
858 return SDValue();
859
860 NewOperand = FirstOperand.getOperand(0);
861 // SMSize is 'location' (position) in this case, not size.
862 SMSize--;
863 Opc = MipsISD::CIns;
864 } else {
865 // Pattern match EXT.
866 // $dst = and $src, (2**size - 1) , if size > 16
867 // => ext $dst, $src, pos, size , pos = 0
868
869 // If the mask is <= 0xffff, andi can be used instead.
870 if (CN->getZExtValue() <= 0xffff)
871 return SDValue();
872
873 // Return if the mask doesn't start at position 0.
874 if (SMPos)
875 return SDValue();
876
877 Opc = MipsISD::Ext;
878 NewOperand = FirstOperand;
879 }
880 return DAG.getNode(Opc, DL, ValTy, NewOperand,
881 DAG.getConstant(Pos, DL, MVT::i32),
882 DAG.getConstant(SMSize, DL, MVT::i32));
883 }
884
performORCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)885 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
886 TargetLowering::DAGCombinerInfo &DCI,
887 const MipsSubtarget &Subtarget) {
888 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
889 return SDValue();
890
891 SDValue FirstOperand = N->getOperand(0), SecondOperand = N->getOperand(1);
892 unsigned SMPos0, SMSize0, SMPos1, SMSize1;
893 ConstantSDNode *CN, *CN1;
894
895 if ((FirstOperand.getOpcode() == ISD::AND &&
896 SecondOperand.getOpcode() == ISD::SHL) ||
897 (FirstOperand.getOpcode() == ISD::SHL &&
898 SecondOperand.getOpcode() == ISD::AND)) {
899 // Pattern match INS.
900 // $dst = or (and $src1, (2**size0 - 1)), (shl $src2, size0)
901 // ==> ins $src1, $src2, pos, size, pos = size0, size = 32 - pos;
902 // Or:
903 // $dst = or (shl $src2, size0), (and $src1, (2**size0 - 1))
904 // ==> ins $src1, $src2, pos, size, pos = size0, size = 32 - pos;
905 SDValue AndOperand0 = FirstOperand.getOpcode() == ISD::AND
906 ? FirstOperand.getOperand(0)
907 : SecondOperand.getOperand(0);
908 SDValue ShlOperand0 = FirstOperand.getOpcode() == ISD::AND
909 ? SecondOperand.getOperand(0)
910 : FirstOperand.getOperand(0);
911 SDValue AndMask = FirstOperand.getOpcode() == ISD::AND
912 ? FirstOperand.getOperand(1)
913 : SecondOperand.getOperand(1);
914 if (!(CN = dyn_cast<ConstantSDNode>(AndMask)) ||
915 !isShiftedMask_64(CN->getZExtValue(), SMPos0, SMSize0))
916 return SDValue();
917
918 SDValue ShlShift = FirstOperand.getOpcode() == ISD::AND
919 ? SecondOperand.getOperand(1)
920 : FirstOperand.getOperand(1);
921 if (!(CN = dyn_cast<ConstantSDNode>(ShlShift)))
922 return SDValue();
923 uint64_t ShlShiftValue = CN->getZExtValue();
924
925 if (SMPos0 != 0 || SMSize0 != ShlShiftValue)
926 return SDValue();
927
928 SDLoc DL(N);
929 EVT ValTy = N->getValueType(0);
930 SMPos1 = ShlShiftValue;
931 assert(SMPos1 < ValTy.getSizeInBits());
932 SMSize1 = (ValTy == MVT::i64 ? 64 : 32) - SMPos1;
933 return DAG.getNode(MipsISD::Ins, DL, ValTy, ShlOperand0,
934 DAG.getConstant(SMPos1, DL, MVT::i32),
935 DAG.getConstant(SMSize1, DL, MVT::i32), AndOperand0);
936 }
937
938 // See if Op's first operand matches (and $src1 , mask0).
939 if (FirstOperand.getOpcode() != ISD::AND)
940 return SDValue();
941
942 // Pattern match INS.
943 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
944 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
945 // => ins $dst, $src, size, pos, $src1
946 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) ||
947 !isShiftedMask_64(~CN->getSExtValue(), SMPos0, SMSize0))
948 return SDValue();
949
950 // See if Op's second operand matches (and (shl $src, pos), mask1).
951 if (SecondOperand.getOpcode() == ISD::AND &&
952 SecondOperand.getOperand(0).getOpcode() == ISD::SHL) {
953
954 if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand.getOperand(1))) ||
955 !isShiftedMask_64(CN->getZExtValue(), SMPos1, SMSize1))
956 return SDValue();
957
958 // The shift masks must have the same position and size.
959 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
960 return SDValue();
961
962 SDValue Shl = SecondOperand.getOperand(0);
963
964 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
965 return SDValue();
966
967 unsigned Shamt = CN->getZExtValue();
968
969 // Return if the shift amount and the first bit position of mask are not the
970 // same.
971 EVT ValTy = N->getValueType(0);
972 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
973 return SDValue();
974
975 SDLoc DL(N);
976 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0),
977 DAG.getConstant(SMPos0, DL, MVT::i32),
978 DAG.getConstant(SMSize0, DL, MVT::i32),
979 FirstOperand.getOperand(0));
980 } else {
981 // Pattern match DINS.
982 // $dst = or (and $src, mask0), mask1
983 // where mask0 = ((1 << SMSize0) -1) << SMPos0
984 // => dins $dst, $src, pos, size
985 if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) &&
986 ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) ||
987 (SMSize0 + SMPos0 <= 32))) {
988 // Check if AND instruction has constant as argument
989 bool isConstCase = SecondOperand.getOpcode() != ISD::AND;
990 if (SecondOperand.getOpcode() == ISD::AND) {
991 if (!(CN1 = dyn_cast<ConstantSDNode>(SecondOperand->getOperand(1))))
992 return SDValue();
993 } else {
994 if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1))))
995 return SDValue();
996 }
997 // Don't generate INS if constant OR operand doesn't fit into bits
998 // cleared by constant AND operand.
999 if (CN->getSExtValue() & CN1->getSExtValue())
1000 return SDValue();
1001
1002 SDLoc DL(N);
1003 EVT ValTy = N->getOperand(0)->getValueType(0);
1004 SDValue Const1;
1005 SDValue SrlX;
1006 if (!isConstCase) {
1007 Const1 = DAG.getConstant(SMPos0, DL, MVT::i32);
1008 SrlX = DAG.getNode(ISD::SRL, DL, SecondOperand->getValueType(0),
1009 SecondOperand, Const1);
1010 }
1011 return DAG.getNode(
1012 MipsISD::Ins, DL, N->getValueType(0),
1013 isConstCase
1014 ? DAG.getSignedConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy)
1015 : SrlX,
1016 DAG.getConstant(SMPos0, DL, MVT::i32),
1017 DAG.getConstant(ValTy.getSizeInBits() / 8 < 8 ? SMSize0 & 31
1018 : SMSize0,
1019 DL, MVT::i32),
1020 FirstOperand->getOperand(0));
1021 }
1022 return SDValue();
1023 }
1024 }
1025
performMADD_MSUBCombine(SDNode * ROOTNode,SelectionDAG & CurDAG,const MipsSubtarget & Subtarget)1026 static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG,
1027 const MipsSubtarget &Subtarget) {
1028 // ROOTNode must have a multiplication as an operand for the match to be
1029 // successful.
1030 if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL &&
1031 ROOTNode->getOperand(1).getOpcode() != ISD::MUL)
1032 return SDValue();
1033
1034 // In the case where we have a multiplication as the left operand of
1035 // of a subtraction, we can't combine into a MipsISD::MSub node as the
1036 // the instruction definition of msub(u) places the multiplication on
1037 // on the right.
1038 if (ROOTNode->getOpcode() == ISD::SUB &&
1039 ROOTNode->getOperand(0).getOpcode() == ISD::MUL)
1040 return SDValue();
1041
1042 // We don't handle vector types here.
1043 if (ROOTNode->getValueType(0).isVector())
1044 return SDValue();
1045
1046 // For MIPS64, madd / msub instructions are inefficent to use with 64 bit
1047 // arithmetic. E.g.
1048 // (add (mul a b) c) =>
1049 // let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in
1050 // MIPS64: (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32)
1051 // or
1052 // MIPS64R2: (dins (mflo res) (mfhi res) 32 32)
1053 //
1054 // The overhead of setting up the Hi/Lo registers and reassembling the
1055 // result makes this a dubious optimzation for MIPS64. The core of the
1056 // problem is that Hi/Lo contain the upper and lower 32 bits of the
1057 // operand and result.
1058 //
1059 // It requires a chain of 4 add/mul for MIPS64R2 to get better code
1060 // density than doing it naively, 5 for MIPS64. Additionally, using
1061 // madd/msub on MIPS64 requires the operands actually be 32 bit sign
1062 // extended operands, not true 64 bit values.
1063 //
1064 // FIXME: For the moment, disable this completely for MIPS64.
1065 if (Subtarget.hasMips64())
1066 return SDValue();
1067
1068 SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
1069 ? ROOTNode->getOperand(0)
1070 : ROOTNode->getOperand(1);
1071
1072 SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
1073 ? ROOTNode->getOperand(1)
1074 : ROOTNode->getOperand(0);
1075
1076 // Transform this to a MADD only if the user of this node is the add.
1077 // If there are other users of the mul, this function returns here.
1078 if (!Mult.hasOneUse())
1079 return SDValue();
1080
1081 // maddu and madd are unusual instructions in that on MIPS64 bits 63..31
1082 // must be in canonical form, i.e. sign extended. For MIPS32, the operands
1083 // of the multiply must have 32 or more sign bits, otherwise we cannot
1084 // perform this optimization. We have to check this here as we're performing
1085 // this optimization pre-legalization.
1086 SDValue MultLHS = Mult->getOperand(0);
1087 SDValue MultRHS = Mult->getOperand(1);
1088
1089 bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND &&
1090 MultRHS->getOpcode() == ISD::SIGN_EXTEND;
1091 bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND &&
1092 MultRHS->getOpcode() == ISD::ZERO_EXTEND;
1093
1094 if (!IsSigned && !IsUnsigned)
1095 return SDValue();
1096
1097 // Initialize accumulator.
1098 SDLoc DL(ROOTNode);
1099 SDValue BottomHalf, TopHalf;
1100 std::tie(BottomHalf, TopHalf) =
1101 CurDAG.SplitScalar(AddOperand, DL, MVT::i32, MVT::i32);
1102 SDValue ACCIn =
1103 CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, BottomHalf, TopHalf);
1104
1105 // Create MipsMAdd(u) / MipsMSub(u) node.
1106 bool IsAdd = ROOTNode->getOpcode() == ISD::ADD;
1107 unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd)
1108 : (IsUnsigned ? MipsISD::MSubu : MipsISD::MSub);
1109 SDValue MAddOps[3] = {
1110 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)),
1111 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn};
1112 SDValue MAdd = CurDAG.getNode(Opcode, DL, MVT::Untyped, MAddOps);
1113
1114 SDValue ResLo = CurDAG.getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
1115 SDValue ResHi = CurDAG.getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
1116 SDValue Combined =
1117 CurDAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResLo, ResHi);
1118 return Combined;
1119 }
1120
performSUBCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)1121 static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG,
1122 TargetLowering::DAGCombinerInfo &DCI,
1123 const MipsSubtarget &Subtarget) {
1124 // (sub v0 (mul v1, v2)) => (msub v1, v2, v0)
1125 if (DCI.isBeforeLegalizeOps()) {
1126 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
1127 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64)
1128 return performMADD_MSUBCombine(N, DAG, Subtarget);
1129
1130 return SDValue();
1131 }
1132
1133 return SDValue();
1134 }
1135
performADDCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)1136 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
1137 TargetLowering::DAGCombinerInfo &DCI,
1138 const MipsSubtarget &Subtarget) {
1139 // (add v0 (mul v1, v2)) => (madd v1, v2, v0)
1140 if (DCI.isBeforeLegalizeOps()) {
1141 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
1142 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64)
1143 return performMADD_MSUBCombine(N, DAG, Subtarget);
1144
1145 return SDValue();
1146 }
1147
1148 // When loading from a jump table, push the Lo node to the position that
1149 // allows folding it into a load immediate.
1150 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
1151 // (add (add abs_lo(tjt), v1), v0) => (add (add v0, v1), abs_lo(tjt))
1152 SDValue InnerAdd = N->getOperand(1);
1153 SDValue Index = N->getOperand(0);
1154 if (InnerAdd.getOpcode() != ISD::ADD)
1155 std::swap(InnerAdd, Index);
1156 if (InnerAdd.getOpcode() != ISD::ADD)
1157 return SDValue();
1158
1159 SDValue Lo = InnerAdd.getOperand(0);
1160 SDValue Other = InnerAdd.getOperand(1);
1161 if (Lo.getOpcode() != MipsISD::Lo)
1162 std::swap(Lo, Other);
1163
1164 if ((Lo.getOpcode() != MipsISD::Lo) ||
1165 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
1166 return SDValue();
1167
1168 EVT ValTy = N->getValueType(0);
1169 SDLoc DL(N);
1170
1171 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, Index, Other);
1172 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
1173 }
1174
performSHLCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)1175 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
1176 TargetLowering::DAGCombinerInfo &DCI,
1177 const MipsSubtarget &Subtarget) {
1178 // Pattern match CINS.
1179 // $dst = shl (and $src , imm), pos
1180 // => cins $dst, $src, pos, size
1181
1182 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips())
1183 return SDValue();
1184
1185 SDValue FirstOperand = N->getOperand(0);
1186 unsigned FirstOperandOpc = FirstOperand.getOpcode();
1187 SDValue SecondOperand = N->getOperand(1);
1188 EVT ValTy = N->getValueType(0);
1189 SDLoc DL(N);
1190
1191 uint64_t Pos = 0;
1192 unsigned SMPos, SMSize;
1193 ConstantSDNode *CN;
1194 SDValue NewOperand;
1195
1196 // The second operand of the shift must be an immediate.
1197 if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand)))
1198 return SDValue();
1199
1200 Pos = CN->getZExtValue();
1201
1202 if (Pos >= ValTy.getSizeInBits())
1203 return SDValue();
1204
1205 if (FirstOperandOpc != ISD::AND)
1206 return SDValue();
1207
1208 // AND's second operand must be a shifted mask.
1209 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) ||
1210 !isShiftedMask_64(CN->getZExtValue(), SMPos, SMSize))
1211 return SDValue();
1212
1213 // Return if the shifted mask does not start at bit 0 or the sum of its size
1214 // and Pos exceeds the word's size.
1215 if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits())
1216 return SDValue();
1217
1218 NewOperand = FirstOperand.getOperand(0);
1219 // SMSize is 'location' (position) in this case, not size.
1220 SMSize--;
1221
1222 return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand,
1223 DAG.getConstant(Pos, DL, MVT::i32),
1224 DAG.getConstant(SMSize, DL, MVT::i32));
1225 }
1226
performSignExtendCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)1227 static SDValue performSignExtendCombine(SDNode *N, SelectionDAG &DAG,
1228 TargetLowering::DAGCombinerInfo &DCI,
1229 const MipsSubtarget &Subtarget) {
1230 if (DCI.Level != AfterLegalizeDAG || !Subtarget.isGP64bit()) {
1231 return SDValue();
1232 }
1233
1234 SDValue N0 = N->getOperand(0);
1235 EVT VT = N->getValueType(0);
1236
1237 // Pattern match XOR.
1238 // $dst = sign_extend (xor (trunc $src, i32), imm)
1239 // => $dst = xor (signext_inreg $src, i32), imm
1240 if (N0.getOpcode() == ISD::XOR &&
1241 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
1242 N0.getOperand(1).getOpcode() == ISD::Constant) {
1243 SDValue TruncateSource = N0.getOperand(0).getOperand(0);
1244 auto *ConstantOperand = dyn_cast<ConstantSDNode>(N0->getOperand(1));
1245
1246 SDValue FirstOperand =
1247 DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N0), VT, TruncateSource,
1248 DAG.getValueType(N0.getOperand(0).getValueType()));
1249
1250 int64_t ConstImm = ConstantOperand->getSExtValue();
1251 return DAG.getNode(ISD::XOR, SDLoc(N0), VT, FirstOperand,
1252 DAG.getConstant(ConstImm, SDLoc(N0), VT));
1253 }
1254
1255 return SDValue();
1256 }
1257
PerformDAGCombine(SDNode * N,DAGCombinerInfo & DCI) const1258 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
1259 const {
1260 SelectionDAG &DAG = DCI.DAG;
1261 unsigned Opc = N->getOpcode();
1262
1263 switch (Opc) {
1264 default: break;
1265 case ISD::SDIVREM:
1266 case ISD::UDIVREM:
1267 return performDivRemCombine(N, DAG, DCI, Subtarget);
1268 case ISD::SELECT:
1269 return performSELECTCombine(N, DAG, DCI, Subtarget);
1270 case MipsISD::CMovFP_F:
1271 case MipsISD::CMovFP_T:
1272 return performCMovFPCombine(N, DAG, DCI, Subtarget);
1273 case ISD::AND:
1274 return performANDCombine(N, DAG, DCI, Subtarget);
1275 case ISD::OR:
1276 return performORCombine(N, DAG, DCI, Subtarget);
1277 case ISD::ADD:
1278 return performADDCombine(N, DAG, DCI, Subtarget);
1279 case ISD::SHL:
1280 return performSHLCombine(N, DAG, DCI, Subtarget);
1281 case ISD::SUB:
1282 return performSUBCombine(N, DAG, DCI, Subtarget);
1283 case ISD::SIGN_EXTEND:
1284 return performSignExtendCombine(N, DAG, DCI, Subtarget);
1285 }
1286
1287 return SDValue();
1288 }
1289
isCheapToSpeculateCttz(Type * Ty) const1290 bool MipsTargetLowering::isCheapToSpeculateCttz(Type *Ty) const {
1291 return Subtarget.hasMips32();
1292 }
1293
isCheapToSpeculateCtlz(Type * Ty) const1294 bool MipsTargetLowering::isCheapToSpeculateCtlz(Type *Ty) const {
1295 return Subtarget.hasMips32();
1296 }
1297
hasBitTest(SDValue X,SDValue Y) const1298 bool MipsTargetLowering::hasBitTest(SDValue X, SDValue Y) const {
1299 // We can use ANDI+SLTIU as a bit test. Y contains the bit position.
1300 // For MIPSR2 or later, we may be able to use the `ext` instruction or its'
1301 // double-word variants.
1302 if (auto *C = dyn_cast<ConstantSDNode>(Y))
1303 return C->getAPIntValue().ule(15);
1304
1305 return false;
1306 }
1307
shouldFoldConstantShiftPairToMask(const SDNode * N,CombineLevel Level) const1308 bool MipsTargetLowering::shouldFoldConstantShiftPairToMask(
1309 const SDNode *N, CombineLevel Level) const {
1310 assert(((N->getOpcode() == ISD::SHL &&
1311 N->getOperand(0).getOpcode() == ISD::SRL) ||
1312 (N->getOpcode() == ISD::SRL &&
1313 N->getOperand(0).getOpcode() == ISD::SHL)) &&
1314 "Expected shift-shift mask");
1315
1316 if (N->getOperand(0).getValueType().isVector())
1317 return false;
1318 return true;
1319 }
1320
1321 void
ReplaceNodeResults(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG) const1322 MipsTargetLowering::ReplaceNodeResults(SDNode *N,
1323 SmallVectorImpl<SDValue> &Results,
1324 SelectionDAG &DAG) const {
1325 return LowerOperationWrapper(N, Results, DAG);
1326 }
1327
1328 SDValue MipsTargetLowering::
LowerOperation(SDValue Op,SelectionDAG & DAG) const1329 LowerOperation(SDValue Op, SelectionDAG &DAG) const
1330 {
1331 switch (Op.getOpcode())
1332 {
1333 case ISD::BRCOND: return lowerBRCOND(Op, DAG);
1334 case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
1335 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
1336 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
1337 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
1338 case ISD::JumpTable: return lowerJumpTable(Op, DAG);
1339 case ISD::SELECT: return lowerSELECT(Op, DAG);
1340 case ISD::SETCC: return lowerSETCC(Op, DAG);
1341 case ISD::VASTART: return lowerVASTART(Op, DAG);
1342 case ISD::VAARG: return lowerVAARG(Op, DAG);
1343 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
1344 case ISD::FABS: return lowerFABS(Op, DAG);
1345 case ISD::FCANONICALIZE:
1346 return lowerFCANONICALIZE(Op, DAG);
1347 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
1348 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
1349 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
1350 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
1351 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
1352 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
1353 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
1354 case ISD::LOAD: return lowerLOAD(Op, DAG);
1355 case ISD::STORE: return lowerSTORE(Op, DAG);
1356 case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG);
1357 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
1358 case ISD::READCYCLECOUNTER:
1359 return lowerREADCYCLECOUNTER(Op, DAG);
1360 }
1361 return SDValue();
1362 }
1363
1364 //===----------------------------------------------------------------------===//
1365 // Lower helper functions
1366 //===----------------------------------------------------------------------===//
1367
1368 // addLiveIn - This helper function adds the specified physical register to the
1369 // MachineFunction as a live in value. It also creates a corresponding
1370 // virtual register for it.
1371 static unsigned
addLiveIn(MachineFunction & MF,unsigned PReg,const TargetRegisterClass * RC)1372 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
1373 {
1374 Register VReg = MF.getRegInfo().createVirtualRegister(RC);
1375 MF.getRegInfo().addLiveIn(PReg, VReg);
1376 return VReg;
1377 }
1378
insertDivByZeroTrap(MachineInstr & MI,MachineBasicBlock & MBB,const TargetInstrInfo & TII,bool Is64Bit,bool IsMicroMips)1379 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI,
1380 MachineBasicBlock &MBB,
1381 const TargetInstrInfo &TII,
1382 bool Is64Bit, bool IsMicroMips) {
1383 if (NoZeroDivCheck)
1384 return &MBB;
1385
1386 // Insert instruction "teq $divisor_reg, $zero, 7".
1387 MachineBasicBlock::iterator I(MI);
1388 MachineInstrBuilder MIB;
1389 MachineOperand &Divisor = MI.getOperand(2);
1390 MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(),
1391 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
1392 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
1393 .addReg(Mips::ZERO)
1394 .addImm(7);
1395
1396 // Use the 32-bit sub-register if this is a 64-bit division.
1397 if (Is64Bit)
1398 MIB->getOperand(0).setSubReg(Mips::sub_32);
1399
1400 // Clear Divisor's kill flag.
1401 Divisor.setIsKill(false);
1402
1403 // We would normally delete the original instruction here but in this case
1404 // we only needed to inject an additional instruction rather than replace it.
1405
1406 return &MBB;
1407 }
1408
1409 MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr & MI,MachineBasicBlock * BB) const1410 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1411 MachineBasicBlock *BB) const {
1412 switch (MI.getOpcode()) {
1413 default:
1414 llvm_unreachable("Unexpected instr type to insert");
1415 case Mips::ATOMIC_LOAD_ADD_I8:
1416 return emitAtomicBinaryPartword(MI, BB, 1);
1417 case Mips::ATOMIC_LOAD_ADD_I16:
1418 return emitAtomicBinaryPartword(MI, BB, 2);
1419 case Mips::ATOMIC_LOAD_ADD_I32:
1420 return emitAtomicBinary(MI, BB);
1421 case Mips::ATOMIC_LOAD_ADD_I64:
1422 return emitAtomicBinary(MI, BB);
1423
1424 case Mips::ATOMIC_LOAD_AND_I8:
1425 return emitAtomicBinaryPartword(MI, BB, 1);
1426 case Mips::ATOMIC_LOAD_AND_I16:
1427 return emitAtomicBinaryPartword(MI, BB, 2);
1428 case Mips::ATOMIC_LOAD_AND_I32:
1429 return emitAtomicBinary(MI, BB);
1430 case Mips::ATOMIC_LOAD_AND_I64:
1431 return emitAtomicBinary(MI, BB);
1432
1433 case Mips::ATOMIC_LOAD_OR_I8:
1434 return emitAtomicBinaryPartword(MI, BB, 1);
1435 case Mips::ATOMIC_LOAD_OR_I16:
1436 return emitAtomicBinaryPartword(MI, BB, 2);
1437 case Mips::ATOMIC_LOAD_OR_I32:
1438 return emitAtomicBinary(MI, BB);
1439 case Mips::ATOMIC_LOAD_OR_I64:
1440 return emitAtomicBinary(MI, BB);
1441
1442 case Mips::ATOMIC_LOAD_XOR_I8:
1443 return emitAtomicBinaryPartword(MI, BB, 1);
1444 case Mips::ATOMIC_LOAD_XOR_I16:
1445 return emitAtomicBinaryPartword(MI, BB, 2);
1446 case Mips::ATOMIC_LOAD_XOR_I32:
1447 return emitAtomicBinary(MI, BB);
1448 case Mips::ATOMIC_LOAD_XOR_I64:
1449 return emitAtomicBinary(MI, BB);
1450
1451 case Mips::ATOMIC_LOAD_NAND_I8:
1452 return emitAtomicBinaryPartword(MI, BB, 1);
1453 case Mips::ATOMIC_LOAD_NAND_I16:
1454 return emitAtomicBinaryPartword(MI, BB, 2);
1455 case Mips::ATOMIC_LOAD_NAND_I32:
1456 return emitAtomicBinary(MI, BB);
1457 case Mips::ATOMIC_LOAD_NAND_I64:
1458 return emitAtomicBinary(MI, BB);
1459
1460 case Mips::ATOMIC_LOAD_SUB_I8:
1461 return emitAtomicBinaryPartword(MI, BB, 1);
1462 case Mips::ATOMIC_LOAD_SUB_I16:
1463 return emitAtomicBinaryPartword(MI, BB, 2);
1464 case Mips::ATOMIC_LOAD_SUB_I32:
1465 return emitAtomicBinary(MI, BB);
1466 case Mips::ATOMIC_LOAD_SUB_I64:
1467 return emitAtomicBinary(MI, BB);
1468
1469 case Mips::ATOMIC_SWAP_I8:
1470 return emitAtomicBinaryPartword(MI, BB, 1);
1471 case Mips::ATOMIC_SWAP_I16:
1472 return emitAtomicBinaryPartword(MI, BB, 2);
1473 case Mips::ATOMIC_SWAP_I32:
1474 return emitAtomicBinary(MI, BB);
1475 case Mips::ATOMIC_SWAP_I64:
1476 return emitAtomicBinary(MI, BB);
1477
1478 case Mips::ATOMIC_CMP_SWAP_I8:
1479 return emitAtomicCmpSwapPartword(MI, BB, 1);
1480 case Mips::ATOMIC_CMP_SWAP_I16:
1481 return emitAtomicCmpSwapPartword(MI, BB, 2);
1482 case Mips::ATOMIC_CMP_SWAP_I32:
1483 return emitAtomicCmpSwap(MI, BB);
1484 case Mips::ATOMIC_CMP_SWAP_I64:
1485 return emitAtomicCmpSwap(MI, BB);
1486
1487 case Mips::ATOMIC_LOAD_MIN_I8:
1488 return emitAtomicBinaryPartword(MI, BB, 1);
1489 case Mips::ATOMIC_LOAD_MIN_I16:
1490 return emitAtomicBinaryPartword(MI, BB, 2);
1491 case Mips::ATOMIC_LOAD_MIN_I32:
1492 return emitAtomicBinary(MI, BB);
1493 case Mips::ATOMIC_LOAD_MIN_I64:
1494 return emitAtomicBinary(MI, BB);
1495
1496 case Mips::ATOMIC_LOAD_MAX_I8:
1497 return emitAtomicBinaryPartword(MI, BB, 1);
1498 case Mips::ATOMIC_LOAD_MAX_I16:
1499 return emitAtomicBinaryPartword(MI, BB, 2);
1500 case Mips::ATOMIC_LOAD_MAX_I32:
1501 return emitAtomicBinary(MI, BB);
1502 case Mips::ATOMIC_LOAD_MAX_I64:
1503 return emitAtomicBinary(MI, BB);
1504
1505 case Mips::ATOMIC_LOAD_UMIN_I8:
1506 return emitAtomicBinaryPartword(MI, BB, 1);
1507 case Mips::ATOMIC_LOAD_UMIN_I16:
1508 return emitAtomicBinaryPartword(MI, BB, 2);
1509 case Mips::ATOMIC_LOAD_UMIN_I32:
1510 return emitAtomicBinary(MI, BB);
1511 case Mips::ATOMIC_LOAD_UMIN_I64:
1512 return emitAtomicBinary(MI, BB);
1513
1514 case Mips::ATOMIC_LOAD_UMAX_I8:
1515 return emitAtomicBinaryPartword(MI, BB, 1);
1516 case Mips::ATOMIC_LOAD_UMAX_I16:
1517 return emitAtomicBinaryPartword(MI, BB, 2);
1518 case Mips::ATOMIC_LOAD_UMAX_I32:
1519 return emitAtomicBinary(MI, BB);
1520 case Mips::ATOMIC_LOAD_UMAX_I64:
1521 return emitAtomicBinary(MI, BB);
1522
1523 case Mips::PseudoSDIV:
1524 case Mips::PseudoUDIV:
1525 case Mips::DIV:
1526 case Mips::DIVU:
1527 case Mips::MOD:
1528 case Mips::MODU:
1529 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false,
1530 false);
1531 case Mips::SDIV_MM_Pseudo:
1532 case Mips::UDIV_MM_Pseudo:
1533 case Mips::SDIV_MM:
1534 case Mips::UDIV_MM:
1535 case Mips::DIV_MMR6:
1536 case Mips::DIVU_MMR6:
1537 case Mips::MOD_MMR6:
1538 case Mips::MODU_MMR6:
1539 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true);
1540 case Mips::PseudoDSDIV:
1541 case Mips::PseudoDUDIV:
1542 case Mips::DDIV:
1543 case Mips::DDIVU:
1544 case Mips::DMOD:
1545 case Mips::DMODU:
1546 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false);
1547
1548 case Mips::PseudoSELECT_I:
1549 case Mips::PseudoSELECT_I64:
1550 case Mips::PseudoSELECT_S:
1551 case Mips::PseudoSELECT_D32:
1552 case Mips::PseudoSELECT_D64:
1553 return emitPseudoSELECT(MI, BB, false, Mips::BNE);
1554 case Mips::PseudoSELECTFP_F_I:
1555 case Mips::PseudoSELECTFP_F_I64:
1556 case Mips::PseudoSELECTFP_F_S:
1557 case Mips::PseudoSELECTFP_F_D32:
1558 case Mips::PseudoSELECTFP_F_D64:
1559 return emitPseudoSELECT(MI, BB, true, Mips::BC1F);
1560 case Mips::PseudoSELECTFP_T_I:
1561 case Mips::PseudoSELECTFP_T_I64:
1562 case Mips::PseudoSELECTFP_T_S:
1563 case Mips::PseudoSELECTFP_T_D32:
1564 case Mips::PseudoSELECTFP_T_D64:
1565 return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
1566 case Mips::PseudoD_SELECT_I:
1567 case Mips::PseudoD_SELECT_I64:
1568 return emitPseudoD_SELECT(MI, BB);
1569 case Mips::LDR_W:
1570 return emitLDR_W(MI, BB);
1571 case Mips::LDR_D:
1572 return emitLDR_D(MI, BB);
1573 case Mips::STR_W:
1574 return emitSTR_W(MI, BB);
1575 case Mips::STR_D:
1576 return emitSTR_D(MI, BB);
1577 }
1578 }
1579
1580 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1581 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1582 MachineBasicBlock *
emitAtomicBinary(MachineInstr & MI,MachineBasicBlock * BB) const1583 MipsTargetLowering::emitAtomicBinary(MachineInstr &MI,
1584 MachineBasicBlock *BB) const {
1585
1586 MachineFunction *MF = BB->getParent();
1587 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1588 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1589 DebugLoc DL = MI.getDebugLoc();
1590
1591 unsigned AtomicOp;
1592 bool NeedsAdditionalReg = false;
1593 switch (MI.getOpcode()) {
1594 case Mips::ATOMIC_LOAD_ADD_I32:
1595 AtomicOp = Mips::ATOMIC_LOAD_ADD_I32_POSTRA;
1596 break;
1597 case Mips::ATOMIC_LOAD_SUB_I32:
1598 AtomicOp = Mips::ATOMIC_LOAD_SUB_I32_POSTRA;
1599 break;
1600 case Mips::ATOMIC_LOAD_AND_I32:
1601 AtomicOp = Mips::ATOMIC_LOAD_AND_I32_POSTRA;
1602 break;
1603 case Mips::ATOMIC_LOAD_OR_I32:
1604 AtomicOp = Mips::ATOMIC_LOAD_OR_I32_POSTRA;
1605 break;
1606 case Mips::ATOMIC_LOAD_XOR_I32:
1607 AtomicOp = Mips::ATOMIC_LOAD_XOR_I32_POSTRA;
1608 break;
1609 case Mips::ATOMIC_LOAD_NAND_I32:
1610 AtomicOp = Mips::ATOMIC_LOAD_NAND_I32_POSTRA;
1611 break;
1612 case Mips::ATOMIC_SWAP_I32:
1613 AtomicOp = Mips::ATOMIC_SWAP_I32_POSTRA;
1614 break;
1615 case Mips::ATOMIC_LOAD_ADD_I64:
1616 AtomicOp = Mips::ATOMIC_LOAD_ADD_I64_POSTRA;
1617 break;
1618 case Mips::ATOMIC_LOAD_SUB_I64:
1619 AtomicOp = Mips::ATOMIC_LOAD_SUB_I64_POSTRA;
1620 break;
1621 case Mips::ATOMIC_LOAD_AND_I64:
1622 AtomicOp = Mips::ATOMIC_LOAD_AND_I64_POSTRA;
1623 break;
1624 case Mips::ATOMIC_LOAD_OR_I64:
1625 AtomicOp = Mips::ATOMIC_LOAD_OR_I64_POSTRA;
1626 break;
1627 case Mips::ATOMIC_LOAD_XOR_I64:
1628 AtomicOp = Mips::ATOMIC_LOAD_XOR_I64_POSTRA;
1629 break;
1630 case Mips::ATOMIC_LOAD_NAND_I64:
1631 AtomicOp = Mips::ATOMIC_LOAD_NAND_I64_POSTRA;
1632 break;
1633 case Mips::ATOMIC_SWAP_I64:
1634 AtomicOp = Mips::ATOMIC_SWAP_I64_POSTRA;
1635 break;
1636 case Mips::ATOMIC_LOAD_MIN_I32:
1637 AtomicOp = Mips::ATOMIC_LOAD_MIN_I32_POSTRA;
1638 NeedsAdditionalReg = true;
1639 break;
1640 case Mips::ATOMIC_LOAD_MAX_I32:
1641 AtomicOp = Mips::ATOMIC_LOAD_MAX_I32_POSTRA;
1642 NeedsAdditionalReg = true;
1643 break;
1644 case Mips::ATOMIC_LOAD_UMIN_I32:
1645 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I32_POSTRA;
1646 NeedsAdditionalReg = true;
1647 break;
1648 case Mips::ATOMIC_LOAD_UMAX_I32:
1649 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I32_POSTRA;
1650 NeedsAdditionalReg = true;
1651 break;
1652 case Mips::ATOMIC_LOAD_MIN_I64:
1653 AtomicOp = Mips::ATOMIC_LOAD_MIN_I64_POSTRA;
1654 NeedsAdditionalReg = true;
1655 break;
1656 case Mips::ATOMIC_LOAD_MAX_I64:
1657 AtomicOp = Mips::ATOMIC_LOAD_MAX_I64_POSTRA;
1658 NeedsAdditionalReg = true;
1659 break;
1660 case Mips::ATOMIC_LOAD_UMIN_I64:
1661 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I64_POSTRA;
1662 NeedsAdditionalReg = true;
1663 break;
1664 case Mips::ATOMIC_LOAD_UMAX_I64:
1665 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I64_POSTRA;
1666 NeedsAdditionalReg = true;
1667 break;
1668 default:
1669 llvm_unreachable("Unknown pseudo atomic for replacement!");
1670 }
1671
1672 Register OldVal = MI.getOperand(0).getReg();
1673 Register Ptr = MI.getOperand(1).getReg();
1674 Register Incr = MI.getOperand(2).getReg();
1675 Register Scratch = RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal));
1676
1677 MachineBasicBlock::iterator II(MI);
1678
1679 // The scratch registers here with the EarlyClobber | Define | Implicit
1680 // flags is used to persuade the register allocator and the machine
1681 // verifier to accept the usage of this register. This has to be a real
1682 // register which has an UNDEF value but is dead after the instruction which
1683 // is unique among the registers chosen for the instruction.
1684
1685 // The EarlyClobber flag has the semantic properties that the operand it is
1686 // attached to is clobbered before the rest of the inputs are read. Hence it
1687 // must be unique among the operands to the instruction.
1688 // The Define flag is needed to coerce the machine verifier that an Undef
1689 // value isn't a problem.
1690 // The Dead flag is needed as the value in scratch isn't used by any other
1691 // instruction. Kill isn't used as Dead is more precise.
1692 // The implicit flag is here due to the interaction between the other flags
1693 // and the machine verifier.
1694
1695 // For correctness purpose, a new pseudo is introduced here. We need this
1696 // new pseudo, so that FastRegisterAllocator does not see an ll/sc sequence
1697 // that is spread over >1 basic blocks. A register allocator which
1698 // introduces (or any codegen infact) a store, can violate the expectations
1699 // of the hardware.
1700 //
1701 // An atomic read-modify-write sequence starts with a linked load
1702 // instruction and ends with a store conditional instruction. The atomic
1703 // read-modify-write sequence fails if any of the following conditions
1704 // occur between the execution of ll and sc:
1705 // * A coherent store is completed by another process or coherent I/O
1706 // module into the block of synchronizable physical memory containing
1707 // the word. The size and alignment of the block is
1708 // implementation-dependent.
1709 // * A coherent store is executed between an LL and SC sequence on the
1710 // same processor to the block of synchornizable physical memory
1711 // containing the word.
1712 //
1713
1714 Register PtrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Ptr));
1715 Register IncrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Incr));
1716
1717 BuildMI(*BB, II, DL, TII->get(Mips::COPY), IncrCopy).addReg(Incr);
1718 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
1719
1720 MachineInstrBuilder MIB =
1721 BuildMI(*BB, II, DL, TII->get(AtomicOp))
1722 .addReg(OldVal, RegState::Define | RegState::EarlyClobber)
1723 .addReg(PtrCopy)
1724 .addReg(IncrCopy)
1725 .addReg(Scratch, RegState::Define | RegState::EarlyClobber |
1726 RegState::Implicit | RegState::Dead);
1727 if (NeedsAdditionalReg) {
1728 Register Scratch2 =
1729 RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal));
1730 MIB.addReg(Scratch2, RegState::Define | RegState::EarlyClobber |
1731 RegState::Implicit | RegState::Dead);
1732 }
1733
1734 MI.eraseFromParent();
1735
1736 return BB;
1737 }
1738
emitSignExtendToI32InReg(MachineInstr & MI,MachineBasicBlock * BB,unsigned Size,unsigned DstReg,unsigned SrcReg) const1739 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
1740 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg,
1741 unsigned SrcReg) const {
1742 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1743 const DebugLoc &DL = MI.getDebugLoc();
1744
1745 if (Subtarget.hasMips32r2() && Size == 1) {
1746 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1747 return BB;
1748 }
1749
1750 if (Subtarget.hasMips32r2() && Size == 2) {
1751 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1752 return BB;
1753 }
1754
1755 MachineFunction *MF = BB->getParent();
1756 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1757 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1758 Register ScrReg = RegInfo.createVirtualRegister(RC);
1759
1760 assert(Size < 32);
1761 int64_t ShiftImm = 32 - (Size * 8);
1762
1763 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1764 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1765
1766 return BB;
1767 }
1768
emitAtomicBinaryPartword(MachineInstr & MI,MachineBasicBlock * BB,unsigned Size) const1769 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
1770 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const {
1771 assert((Size == 1 || Size == 2) &&
1772 "Unsupported size for EmitAtomicBinaryPartial.");
1773
1774 MachineFunction *MF = BB->getParent();
1775 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1776 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1777 const bool ArePtrs64bit = ABI.ArePtrs64bit();
1778 const TargetRegisterClass *RCp =
1779 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1780 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1781 DebugLoc DL = MI.getDebugLoc();
1782
1783 Register Dest = MI.getOperand(0).getReg();
1784 Register Ptr = MI.getOperand(1).getReg();
1785 Register Incr = MI.getOperand(2).getReg();
1786
1787 Register AlignedAddr = RegInfo.createVirtualRegister(RCp);
1788 Register ShiftAmt = RegInfo.createVirtualRegister(RC);
1789 Register Mask = RegInfo.createVirtualRegister(RC);
1790 Register Mask2 = RegInfo.createVirtualRegister(RC);
1791 Register Incr2 = RegInfo.createVirtualRegister(RC);
1792 Register MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1793 Register PtrLSB2 = RegInfo.createVirtualRegister(RC);
1794 Register MaskUpper = RegInfo.createVirtualRegister(RC);
1795 Register Scratch = RegInfo.createVirtualRegister(RC);
1796 Register Scratch2 = RegInfo.createVirtualRegister(RC);
1797 Register Scratch3 = RegInfo.createVirtualRegister(RC);
1798
1799 unsigned AtomicOp = 0;
1800 bool NeedsAdditionalReg = false;
1801 switch (MI.getOpcode()) {
1802 case Mips::ATOMIC_LOAD_NAND_I8:
1803 AtomicOp = Mips::ATOMIC_LOAD_NAND_I8_POSTRA;
1804 break;
1805 case Mips::ATOMIC_LOAD_NAND_I16:
1806 AtomicOp = Mips::ATOMIC_LOAD_NAND_I16_POSTRA;
1807 break;
1808 case Mips::ATOMIC_SWAP_I8:
1809 AtomicOp = Mips::ATOMIC_SWAP_I8_POSTRA;
1810 break;
1811 case Mips::ATOMIC_SWAP_I16:
1812 AtomicOp = Mips::ATOMIC_SWAP_I16_POSTRA;
1813 break;
1814 case Mips::ATOMIC_LOAD_ADD_I8:
1815 AtomicOp = Mips::ATOMIC_LOAD_ADD_I8_POSTRA;
1816 break;
1817 case Mips::ATOMIC_LOAD_ADD_I16:
1818 AtomicOp = Mips::ATOMIC_LOAD_ADD_I16_POSTRA;
1819 break;
1820 case Mips::ATOMIC_LOAD_SUB_I8:
1821 AtomicOp = Mips::ATOMIC_LOAD_SUB_I8_POSTRA;
1822 break;
1823 case Mips::ATOMIC_LOAD_SUB_I16:
1824 AtomicOp = Mips::ATOMIC_LOAD_SUB_I16_POSTRA;
1825 break;
1826 case Mips::ATOMIC_LOAD_AND_I8:
1827 AtomicOp = Mips::ATOMIC_LOAD_AND_I8_POSTRA;
1828 break;
1829 case Mips::ATOMIC_LOAD_AND_I16:
1830 AtomicOp = Mips::ATOMIC_LOAD_AND_I16_POSTRA;
1831 break;
1832 case Mips::ATOMIC_LOAD_OR_I8:
1833 AtomicOp = Mips::ATOMIC_LOAD_OR_I8_POSTRA;
1834 break;
1835 case Mips::ATOMIC_LOAD_OR_I16:
1836 AtomicOp = Mips::ATOMIC_LOAD_OR_I16_POSTRA;
1837 break;
1838 case Mips::ATOMIC_LOAD_XOR_I8:
1839 AtomicOp = Mips::ATOMIC_LOAD_XOR_I8_POSTRA;
1840 break;
1841 case Mips::ATOMIC_LOAD_XOR_I16:
1842 AtomicOp = Mips::ATOMIC_LOAD_XOR_I16_POSTRA;
1843 break;
1844 case Mips::ATOMIC_LOAD_MIN_I8:
1845 AtomicOp = Mips::ATOMIC_LOAD_MIN_I8_POSTRA;
1846 NeedsAdditionalReg = true;
1847 break;
1848 case Mips::ATOMIC_LOAD_MIN_I16:
1849 AtomicOp = Mips::ATOMIC_LOAD_MIN_I16_POSTRA;
1850 NeedsAdditionalReg = true;
1851 break;
1852 case Mips::ATOMIC_LOAD_MAX_I8:
1853 AtomicOp = Mips::ATOMIC_LOAD_MAX_I8_POSTRA;
1854 NeedsAdditionalReg = true;
1855 break;
1856 case Mips::ATOMIC_LOAD_MAX_I16:
1857 AtomicOp = Mips::ATOMIC_LOAD_MAX_I16_POSTRA;
1858 NeedsAdditionalReg = true;
1859 break;
1860 case Mips::ATOMIC_LOAD_UMIN_I8:
1861 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I8_POSTRA;
1862 NeedsAdditionalReg = true;
1863 break;
1864 case Mips::ATOMIC_LOAD_UMIN_I16:
1865 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I16_POSTRA;
1866 NeedsAdditionalReg = true;
1867 break;
1868 case Mips::ATOMIC_LOAD_UMAX_I8:
1869 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I8_POSTRA;
1870 NeedsAdditionalReg = true;
1871 break;
1872 case Mips::ATOMIC_LOAD_UMAX_I16:
1873 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I16_POSTRA;
1874 NeedsAdditionalReg = true;
1875 break;
1876 default:
1877 llvm_unreachable("Unknown subword atomic pseudo for expansion!");
1878 }
1879
1880 // insert new blocks after the current block
1881 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1882 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1883 MachineFunction::iterator It = ++BB->getIterator();
1884 MF->insert(It, exitMBB);
1885
1886 // Transfer the remainder of BB and its successor edges to exitMBB.
1887 exitMBB->splice(exitMBB->begin(), BB,
1888 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1889 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1890
1891 BB->addSuccessor(exitMBB, BranchProbability::getOne());
1892
1893 // thisMBB:
1894 // addiu masklsb2,$0,-4 # 0xfffffffc
1895 // and alignedaddr,ptr,masklsb2
1896 // andi ptrlsb2,ptr,3
1897 // sll shiftamt,ptrlsb2,3
1898 // ori maskupper,$0,255 # 0xff
1899 // sll mask,maskupper,shiftamt
1900 // nor mask2,$0,mask
1901 // sll incr2,incr,shiftamt
1902
1903 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1904 BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2)
1905 .addReg(ABI.GetNullPtr()).addImm(-4);
1906 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr)
1907 .addReg(Ptr).addReg(MaskLSB2);
1908 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1909 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1910 if (Subtarget.isLittle()) {
1911 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1912 } else {
1913 Register Off = RegInfo.createVirtualRegister(RC);
1914 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1915 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1916 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1917 }
1918 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1919 .addReg(Mips::ZERO).addImm(MaskImm);
1920 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1921 .addReg(MaskUpper).addReg(ShiftAmt);
1922 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1923 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1924
1925
1926 // The purposes of the flags on the scratch registers is explained in
1927 // emitAtomicBinary. In summary, we need a scratch register which is going to
1928 // be undef, that is unique among registers chosen for the instruction.
1929
1930 MachineInstrBuilder MIB =
1931 BuildMI(BB, DL, TII->get(AtomicOp))
1932 .addReg(Dest, RegState::Define | RegState::EarlyClobber)
1933 .addReg(AlignedAddr)
1934 .addReg(Incr2)
1935 .addReg(Mask)
1936 .addReg(Mask2)
1937 .addReg(ShiftAmt)
1938 .addReg(Scratch, RegState::EarlyClobber | RegState::Define |
1939 RegState::Dead | RegState::Implicit)
1940 .addReg(Scratch2, RegState::EarlyClobber | RegState::Define |
1941 RegState::Dead | RegState::Implicit)
1942 .addReg(Scratch3, RegState::EarlyClobber | RegState::Define |
1943 RegState::Dead | RegState::Implicit);
1944 if (NeedsAdditionalReg) {
1945 Register Scratch4 = RegInfo.createVirtualRegister(RC);
1946 MIB.addReg(Scratch4, RegState::EarlyClobber | RegState::Define |
1947 RegState::Dead | RegState::Implicit);
1948 }
1949
1950 MI.eraseFromParent(); // The instruction is gone now.
1951
1952 return exitMBB;
1953 }
1954
1955 // Lower atomic compare and swap to a pseudo instruction, taking care to
1956 // define a scratch register for the pseudo instruction's expansion. The
1957 // instruction is expanded after the register allocator as to prevent
1958 // the insertion of stores between the linked load and the store conditional.
1959
1960 MachineBasicBlock *
emitAtomicCmpSwap(MachineInstr & MI,MachineBasicBlock * BB) const1961 MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI,
1962 MachineBasicBlock *BB) const {
1963
1964 assert((MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ||
1965 MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I64) &&
1966 "Unsupported atomic pseudo for EmitAtomicCmpSwap.");
1967
1968 const unsigned Size = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ? 4 : 8;
1969
1970 MachineFunction *MF = BB->getParent();
1971 MachineRegisterInfo &MRI = MF->getRegInfo();
1972 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1973 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1974 DebugLoc DL = MI.getDebugLoc();
1975
1976 unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32
1977 ? Mips::ATOMIC_CMP_SWAP_I32_POSTRA
1978 : Mips::ATOMIC_CMP_SWAP_I64_POSTRA;
1979 Register Dest = MI.getOperand(0).getReg();
1980 Register Ptr = MI.getOperand(1).getReg();
1981 Register OldVal = MI.getOperand(2).getReg();
1982 Register NewVal = MI.getOperand(3).getReg();
1983
1984 Register Scratch = MRI.createVirtualRegister(RC);
1985 MachineBasicBlock::iterator II(MI);
1986
1987 // We need to create copies of the various registers and kill them at the
1988 // atomic pseudo. If the copies are not made, when the atomic is expanded
1989 // after fast register allocation, the spills will end up outside of the
1990 // blocks that their values are defined in, causing livein errors.
1991
1992 Register PtrCopy = MRI.createVirtualRegister(MRI.getRegClass(Ptr));
1993 Register OldValCopy = MRI.createVirtualRegister(MRI.getRegClass(OldVal));
1994 Register NewValCopy = MRI.createVirtualRegister(MRI.getRegClass(NewVal));
1995
1996 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
1997 BuildMI(*BB, II, DL, TII->get(Mips::COPY), OldValCopy).addReg(OldVal);
1998 BuildMI(*BB, II, DL, TII->get(Mips::COPY), NewValCopy).addReg(NewVal);
1999
2000 // The purposes of the flags on the scratch registers is explained in
2001 // emitAtomicBinary. In summary, we need a scratch register which is going to
2002 // be undef, that is unique among registers chosen for the instruction.
2003
2004 BuildMI(*BB, II, DL, TII->get(AtomicOp))
2005 .addReg(Dest, RegState::Define | RegState::EarlyClobber)
2006 .addReg(PtrCopy, RegState::Kill)
2007 .addReg(OldValCopy, RegState::Kill)
2008 .addReg(NewValCopy, RegState::Kill)
2009 .addReg(Scratch, RegState::EarlyClobber | RegState::Define |
2010 RegState::Dead | RegState::Implicit);
2011
2012 MI.eraseFromParent(); // The instruction is gone now.
2013
2014 return BB;
2015 }
2016
emitAtomicCmpSwapPartword(MachineInstr & MI,MachineBasicBlock * BB,unsigned Size) const2017 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
2018 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const {
2019 assert((Size == 1 || Size == 2) &&
2020 "Unsupported size for EmitAtomicCmpSwapPartial.");
2021
2022 MachineFunction *MF = BB->getParent();
2023 MachineRegisterInfo &RegInfo = MF->getRegInfo();
2024 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
2025 const bool ArePtrs64bit = ABI.ArePtrs64bit();
2026 const TargetRegisterClass *RCp =
2027 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
2028 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
2029 DebugLoc DL = MI.getDebugLoc();
2030
2031 Register Dest = MI.getOperand(0).getReg();
2032 Register Ptr = MI.getOperand(1).getReg();
2033 Register CmpVal = MI.getOperand(2).getReg();
2034 Register NewVal = MI.getOperand(3).getReg();
2035
2036 Register AlignedAddr = RegInfo.createVirtualRegister(RCp);
2037 Register ShiftAmt = RegInfo.createVirtualRegister(RC);
2038 Register Mask = RegInfo.createVirtualRegister(RC);
2039 Register Mask2 = RegInfo.createVirtualRegister(RC);
2040 Register ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
2041 Register ShiftedNewVal = RegInfo.createVirtualRegister(RC);
2042 Register MaskLSB2 = RegInfo.createVirtualRegister(RCp);
2043 Register PtrLSB2 = RegInfo.createVirtualRegister(RC);
2044 Register MaskUpper = RegInfo.createVirtualRegister(RC);
2045 Register MaskedCmpVal = RegInfo.createVirtualRegister(RC);
2046 Register MaskedNewVal = RegInfo.createVirtualRegister(RC);
2047 unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I8
2048 ? Mips::ATOMIC_CMP_SWAP_I8_POSTRA
2049 : Mips::ATOMIC_CMP_SWAP_I16_POSTRA;
2050
2051 // The scratch registers here with the EarlyClobber | Define | Dead | Implicit
2052 // flags are used to coerce the register allocator and the machine verifier to
2053 // accept the usage of these registers.
2054 // The EarlyClobber flag has the semantic properties that the operand it is
2055 // attached to is clobbered before the rest of the inputs are read. Hence it
2056 // must be unique among the operands to the instruction.
2057 // The Define flag is needed to coerce the machine verifier that an Undef
2058 // value isn't a problem.
2059 // The Dead flag is needed as the value in scratch isn't used by any other
2060 // instruction. Kill isn't used as Dead is more precise.
2061 Register Scratch = RegInfo.createVirtualRegister(RC);
2062 Register Scratch2 = RegInfo.createVirtualRegister(RC);
2063
2064 // insert new blocks after the current block
2065 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2066 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
2067 MachineFunction::iterator It = ++BB->getIterator();
2068 MF->insert(It, exitMBB);
2069
2070 // Transfer the remainder of BB and its successor edges to exitMBB.
2071 exitMBB->splice(exitMBB->begin(), BB,
2072 std::next(MachineBasicBlock::iterator(MI)), BB->end());
2073 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
2074
2075 BB->addSuccessor(exitMBB, BranchProbability::getOne());
2076
2077 // thisMBB:
2078 // addiu masklsb2,$0,-4 # 0xfffffffc
2079 // and alignedaddr,ptr,masklsb2
2080 // andi ptrlsb2,ptr,3
2081 // xori ptrlsb2,ptrlsb2,3 # Only for BE
2082 // sll shiftamt,ptrlsb2,3
2083 // ori maskupper,$0,255 # 0xff
2084 // sll mask,maskupper,shiftamt
2085 // nor mask2,$0,mask
2086 // andi maskedcmpval,cmpval,255
2087 // sll shiftedcmpval,maskedcmpval,shiftamt
2088 // andi maskednewval,newval,255
2089 // sll shiftednewval,maskednewval,shiftamt
2090 int64_t MaskImm = (Size == 1) ? 255 : 65535;
2091 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
2092 .addReg(ABI.GetNullPtr()).addImm(-4);
2093 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
2094 .addReg(Ptr).addReg(MaskLSB2);
2095 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
2096 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
2097 if (Subtarget.isLittle()) {
2098 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
2099 } else {
2100 Register Off = RegInfo.createVirtualRegister(RC);
2101 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
2102 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
2103 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
2104 }
2105 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
2106 .addReg(Mips::ZERO).addImm(MaskImm);
2107 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
2108 .addReg(MaskUpper).addReg(ShiftAmt);
2109 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
2110 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
2111 .addReg(CmpVal).addImm(MaskImm);
2112 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
2113 .addReg(MaskedCmpVal).addReg(ShiftAmt);
2114 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
2115 .addReg(NewVal).addImm(MaskImm);
2116 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
2117 .addReg(MaskedNewVal).addReg(ShiftAmt);
2118
2119 // The purposes of the flags on the scratch registers are explained in
2120 // emitAtomicBinary. In summary, we need a scratch register which is going to
2121 // be undef, that is unique among the register chosen for the instruction.
2122
2123 BuildMI(BB, DL, TII->get(AtomicOp))
2124 .addReg(Dest, RegState::Define | RegState::EarlyClobber)
2125 .addReg(AlignedAddr)
2126 .addReg(Mask)
2127 .addReg(ShiftedCmpVal)
2128 .addReg(Mask2)
2129 .addReg(ShiftedNewVal)
2130 .addReg(ShiftAmt)
2131 .addReg(Scratch, RegState::EarlyClobber | RegState::Define |
2132 RegState::Dead | RegState::Implicit)
2133 .addReg(Scratch2, RegState::EarlyClobber | RegState::Define |
2134 RegState::Dead | RegState::Implicit);
2135
2136 MI.eraseFromParent(); // The instruction is gone now.
2137
2138 return exitMBB;
2139 }
2140
lowerREADCYCLECOUNTER(SDValue Op,SelectionDAG & DAG) const2141 SDValue MipsTargetLowering::lowerREADCYCLECOUNTER(SDValue Op,
2142 SelectionDAG &DAG) const {
2143 SmallVector<SDValue, 3> Results;
2144 SDLoc DL(Op);
2145 MachineFunction &MF = DAG.getMachineFunction();
2146 unsigned RdhwrOpc, DestReg;
2147 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2148
2149 if (PtrVT == MVT::i64) {
2150 RdhwrOpc = Mips::RDHWR64;
2151 DestReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
2152 SDNode *Rdhwr = DAG.getMachineNode(RdhwrOpc, DL, MVT::i64, MVT::Glue,
2153 DAG.getRegister(Mips::HWR2, MVT::i32),
2154 DAG.getTargetConstant(0, DL, MVT::i32));
2155 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, DestReg,
2156 SDValue(Rdhwr, 0), SDValue(Rdhwr, 1));
2157 SDValue ResNode =
2158 DAG.getCopyFromReg(Chain, DL, DestReg, MVT::i64, Chain.getValue(1));
2159 Results.push_back(ResNode);
2160 Results.push_back(ResNode.getValue(1));
2161 } else {
2162 RdhwrOpc = Mips::RDHWR;
2163 DestReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
2164 SDNode *Rdhwr = DAG.getMachineNode(RdhwrOpc, DL, MVT::i32, MVT::Glue,
2165 DAG.getRegister(Mips::HWR2, MVT::i32),
2166 DAG.getTargetConstant(0, DL, MVT::i32));
2167 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, DestReg,
2168 SDValue(Rdhwr, 0), SDValue(Rdhwr, 1));
2169 SDValue ResNode =
2170 DAG.getCopyFromReg(Chain, DL, DestReg, MVT::i32, Chain.getValue(1));
2171 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResNode,
2172 DAG.getConstant(0, DL, MVT::i32)));
2173 Results.push_back(ResNode.getValue(1));
2174 }
2175
2176 return DAG.getMergeValues(Results, DL);
2177 }
2178
lowerBRCOND(SDValue Op,SelectionDAG & DAG) const2179 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
2180 // The first operand is the chain, the second is the condition, the third is
2181 // the block to branch to if the condition is true.
2182 SDValue Chain = Op.getOperand(0);
2183 SDValue Dest = Op.getOperand(2);
2184 SDLoc DL(Op);
2185
2186 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
2187 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
2188
2189 // Return if flag is not set by a floating point comparison.
2190 if (CondRes.getOpcode() != MipsISD::FPCmp)
2191 return Op;
2192
2193 SDValue CCNode = CondRes.getOperand(2);
2194 Mips::CondCode CC = (Mips::CondCode)CCNode->getAsZExtVal();
2195 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
2196 SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32);
2197 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
2198 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
2199 FCC0, Dest, CondRes);
2200 }
2201
2202 SDValue MipsTargetLowering::
lowerSELECT(SDValue Op,SelectionDAG & DAG) const2203 lowerSELECT(SDValue Op, SelectionDAG &DAG) const
2204 {
2205 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
2206 SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
2207
2208 // Return if flag is not set by a floating point comparison.
2209 if (Cond.getOpcode() != MipsISD::FPCmp)
2210 return Op;
2211
2212 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
2213 SDLoc(Op));
2214 }
2215
lowerSETCC(SDValue Op,SelectionDAG & DAG) const2216 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2217 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
2218 SDValue Cond = createFPCmp(DAG, Op);
2219
2220 assert(Cond.getOpcode() == MipsISD::FPCmp &&
2221 "Floating point operand expected.");
2222
2223 SDLoc DL(Op);
2224 SDValue True = DAG.getConstant(1, DL, MVT::i32);
2225 SDValue False = DAG.getConstant(0, DL, MVT::i32);
2226
2227 return createCMovFP(DAG, Cond, True, False, DL);
2228 }
2229
lowerGlobalAddress(SDValue Op,SelectionDAG & DAG) const2230 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
2231 SelectionDAG &DAG) const {
2232 EVT Ty = Op.getValueType();
2233 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
2234 const GlobalValue *GV = N->getGlobal();
2235
2236 if (GV->hasDLLImportStorageClass()) {
2237 assert(Subtarget.isTargetWindows() &&
2238 "Windows is the only supported COFF target");
2239 return getDllimportVariable(
2240 N, SDLoc(N), Ty, DAG, DAG.getEntryNode(),
2241 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2242 }
2243
2244 if (!isPositionIndependent()) {
2245 const MipsTargetObjectFile *TLOF =
2246 static_cast<const MipsTargetObjectFile *>(
2247 getTargetMachine().getObjFileLowering());
2248 const GlobalObject *GO = GV->getAliaseeObject();
2249 if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine()))
2250 // %gp_rel relocation
2251 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
2252
2253 // %hi/%lo relocation
2254 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2255 // %highest/%higher/%hi/%lo relocation
2256 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2257 }
2258
2259 // Every other architecture would use shouldAssumeDSOLocal in here, but
2260 // mips is special.
2261 // * In PIC code mips requires got loads even for local statics!
2262 // * To save on got entries, for local statics the got entry contains the
2263 // page and an additional add instruction takes care of the low bits.
2264 // * It is legal to access a hidden symbol with a non hidden undefined,
2265 // so one cannot guarantee that all access to a hidden symbol will know
2266 // it is hidden.
2267 // * Mips linkers don't support creating a page and a full got entry for
2268 // the same symbol.
2269 // * Given all that, we have to use a full got entry for hidden symbols :-(
2270 if (GV->hasLocalLinkage())
2271 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2272
2273 if (Subtarget.useXGOT())
2274 return getAddrGlobalLargeGOT(
2275 N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16,
2276 DAG.getEntryNode(),
2277 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2278
2279 return getAddrGlobal(
2280 N, SDLoc(N), Ty, DAG,
2281 (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT,
2282 DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2283 }
2284
lowerBlockAddress(SDValue Op,SelectionDAG & DAG) const2285 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
2286 SelectionDAG &DAG) const {
2287 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
2288 EVT Ty = Op.getValueType();
2289
2290 if (!isPositionIndependent())
2291 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2292 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2293
2294 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2295 }
2296
2297 SDValue MipsTargetLowering::
lowerGlobalTLSAddress(SDValue Op,SelectionDAG & DAG) const2298 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
2299 {
2300 // If the relocation model is PIC, use the General Dynamic TLS Model or
2301 // Local Dynamic TLS model, otherwise use the Initial Exec or
2302 // Local Exec TLS Model.
2303
2304 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2305 if (DAG.getTarget().useEmulatedTLS())
2306 return LowerToTLSEmulatedModel(GA, DAG);
2307
2308 SDLoc DL(GA);
2309 const GlobalValue *GV = GA->getGlobal();
2310 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2311
2312 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
2313
2314 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
2315 // General Dynamic and Local Dynamic TLS Model.
2316 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
2317 : MipsII::MO_TLSGD;
2318
2319 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
2320 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
2321 getGlobalReg(DAG, PtrVT), TGA);
2322 unsigned PtrSize = PtrVT.getSizeInBits();
2323 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
2324
2325 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
2326
2327 ArgListTy Args;
2328 ArgListEntry Entry;
2329 Entry.Node = Argument;
2330 Entry.Ty = PtrTy;
2331 Args.push_back(Entry);
2332
2333 TargetLowering::CallLoweringInfo CLI(DAG);
2334 CLI.setDebugLoc(DL)
2335 .setChain(DAG.getEntryNode())
2336 .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args));
2337 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2338
2339 SDValue Ret = CallResult.first;
2340
2341 if (model != TLSModel::LocalDynamic)
2342 return Ret;
2343
2344 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2345 MipsII::MO_DTPREL_HI);
2346 SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi);
2347 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2348 MipsII::MO_DTPREL_LO);
2349 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
2350 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
2351 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
2352 }
2353
2354 SDValue Offset;
2355 if (model == TLSModel::InitialExec) {
2356 // Initial Exec TLS Model
2357 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2358 MipsII::MO_GOTTPREL);
2359 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
2360 TGA);
2361 Offset =
2362 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo());
2363 } else {
2364 // Local Exec TLS Model
2365 assert(model == TLSModel::LocalExec);
2366 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2367 MipsII::MO_TPREL_HI);
2368 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2369 MipsII::MO_TPREL_LO);
2370 SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi);
2371 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
2372 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
2373 }
2374
2375 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
2376 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
2377 }
2378
2379 SDValue MipsTargetLowering::
lowerJumpTable(SDValue Op,SelectionDAG & DAG) const2380 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
2381 {
2382 JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
2383 EVT Ty = Op.getValueType();
2384
2385 if (!isPositionIndependent())
2386 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2387 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2388
2389 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2390 }
2391
2392 SDValue MipsTargetLowering::
lowerConstantPool(SDValue Op,SelectionDAG & DAG) const2393 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
2394 {
2395 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
2396 EVT Ty = Op.getValueType();
2397
2398 if (!isPositionIndependent()) {
2399 const MipsTargetObjectFile *TLOF =
2400 static_cast<const MipsTargetObjectFile *>(
2401 getTargetMachine().getObjFileLowering());
2402
2403 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(),
2404 getTargetMachine()))
2405 // %gp_rel relocation
2406 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
2407
2408 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2409 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2410 }
2411
2412 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2413 }
2414
lowerVASTART(SDValue Op,SelectionDAG & DAG) const2415 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2416 MachineFunction &MF = DAG.getMachineFunction();
2417 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2418
2419 SDLoc DL(Op);
2420 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2421 getPointerTy(MF.getDataLayout()));
2422
2423 // vastart just stores the address of the VarArgsFrameIndex slot into the
2424 // memory location argument.
2425 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2426 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
2427 MachinePointerInfo(SV));
2428 }
2429
lowerVAARG(SDValue Op,SelectionDAG & DAG) const2430 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
2431 SDNode *Node = Op.getNode();
2432 EVT VT = Node->getValueType(0);
2433 SDValue Chain = Node->getOperand(0);
2434 SDValue VAListPtr = Node->getOperand(1);
2435 const Align Align =
2436 llvm::MaybeAlign(Node->getConstantOperandVal(3)).valueOrOne();
2437 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2438 SDLoc DL(Node);
2439 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4;
2440
2441 SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain,
2442 VAListPtr, MachinePointerInfo(SV));
2443 SDValue VAList = VAListLoad;
2444
2445 // Re-align the pointer if necessary.
2446 // It should only ever be necessary for 64-bit types on O32 since the minimum
2447 // argument alignment is the same as the maximum type alignment for N32/N64.
2448 //
2449 // FIXME: We currently align too often. The code generator doesn't notice
2450 // when the pointer is still aligned from the last va_arg (or pair of
2451 // va_args for the i64 on O32 case).
2452 if (Align > getMinStackArgumentAlignment()) {
2453 VAList = DAG.getNode(
2454 ISD::ADD, DL, VAList.getValueType(), VAList,
2455 DAG.getConstant(Align.value() - 1, DL, VAList.getValueType()));
2456
2457 VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList,
2458 DAG.getSignedConstant(-(int64_t)Align.value(), DL,
2459 VAList.getValueType()));
2460 }
2461
2462 // Increment the pointer, VAList, to the next vaarg.
2463 auto &TD = DAG.getDataLayout();
2464 unsigned ArgSizeInBytes =
2465 TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
2466 SDValue Tmp3 =
2467 DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
2468 DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes),
2469 DL, VAList.getValueType()));
2470 // Store the incremented VAList to the legalized pointer
2471 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
2472 MachinePointerInfo(SV));
2473
2474 // In big-endian mode we must adjust the pointer when the load size is smaller
2475 // than the argument slot size. We must also reduce the known alignment to
2476 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get
2477 // the correct half of the slot, and reduce the alignment from 8 (slot
2478 // alignment) down to 4 (type alignment).
2479 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
2480 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
2481 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
2482 DAG.getIntPtrConstant(Adjustment, DL));
2483 }
2484 // Load the actual argument out of the pointer VAList
2485 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo());
2486 }
2487
lowerFCOPYSIGN32(SDValue Op,SelectionDAG & DAG,bool HasExtractInsert)2488 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
2489 bool HasExtractInsert) {
2490 EVT TyX = Op.getOperand(0).getValueType();
2491 EVT TyY = Op.getOperand(1).getValueType();
2492 SDLoc DL(Op);
2493 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2494 SDValue Const31 = DAG.getConstant(31, DL, MVT::i32);
2495 SDValue Res;
2496
2497 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2498 // to i32.
2499 SDValue X = (TyX == MVT::f32) ?
2500 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2501 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2502 Const1);
2503 SDValue Y = (TyY == MVT::f32) ?
2504 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
2505 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
2506 Const1);
2507
2508 if (HasExtractInsert) {
2509 // ext E, Y, 31, 1 ; extract bit31 of Y
2510 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
2511 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
2512 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
2513 } else {
2514 // sll SllX, X, 1
2515 // srl SrlX, SllX, 1
2516 // srl SrlY, Y, 31
2517 // sll SllY, SrlX, 31
2518 // or Or, SrlX, SllY
2519 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2520 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2521 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
2522 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
2523 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
2524 }
2525
2526 if (TyX == MVT::f32)
2527 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
2528
2529 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2530 Op.getOperand(0),
2531 DAG.getConstant(0, DL, MVT::i32));
2532 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2533 }
2534
lowerFCOPYSIGN64(SDValue Op,SelectionDAG & DAG,bool HasExtractInsert)2535 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
2536 bool HasExtractInsert) {
2537 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
2538 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
2539 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
2540 SDLoc DL(Op);
2541 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2542
2543 // Bitcast to integer nodes.
2544 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
2545 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
2546
2547 if (HasExtractInsert) {
2548 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
2549 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
2550 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
2551 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1);
2552
2553 if (WidthX > WidthY)
2554 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
2555 else if (WidthY > WidthX)
2556 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
2557
2558 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
2559 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1,
2560 X);
2561 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
2562 }
2563
2564 // (d)sll SllX, X, 1
2565 // (d)srl SrlX, SllX, 1
2566 // (d)srl SrlY, Y, width(Y)-1
2567 // (d)sll SllY, SrlX, width(Y)-1
2568 // or Or, SrlX, SllY
2569 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
2570 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
2571 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2572 DAG.getConstant(WidthY - 1, DL, MVT::i32));
2573
2574 if (WidthX > WidthY)
2575 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
2576 else if (WidthY > WidthX)
2577 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
2578
2579 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2580 DAG.getConstant(WidthX - 1, DL, MVT::i32));
2581 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2582 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2583 }
2584
2585 SDValue
lowerFCOPYSIGN(SDValue Op,SelectionDAG & DAG) const2586 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2587 if (Subtarget.isGP64bit())
2588 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert());
2589
2590 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert());
2591 }
2592
lowerFABS32(SDValue Op,SelectionDAG & DAG,bool HasExtractInsert) const2593 SDValue MipsTargetLowering::lowerFABS32(SDValue Op, SelectionDAG &DAG,
2594 bool HasExtractInsert) const {
2595 SDLoc DL(Op);
2596 SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32);
2597
2598 if (DAG.getTarget().Options.NoNaNsFPMath || Subtarget.inAbs2008Mode())
2599 return DAG.getNode(MipsISD::FAbs, DL, Op.getValueType(), Op.getOperand(0));
2600
2601 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2602 // to i32.
2603 SDValue X = (Op.getValueType() == MVT::f32)
2604 ? DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0))
2605 : DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2606 Op.getOperand(0), Const1);
2607
2608 // Clear MSB.
2609 if (HasExtractInsert)
2610 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
2611 DAG.getRegister(Mips::ZERO, MVT::i32),
2612 DAG.getConstant(31, DL, MVT::i32), Const1, X);
2613 else {
2614 // TODO: Provide DAG patterns which transform (and x, cst)
2615 // back to a (shl (srl x (clz cst)) (clz cst)) sequence.
2616 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2617 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2618 }
2619
2620 if (Op.getValueType() == MVT::f32)
2621 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
2622
2623 // FIXME: For mips32r2, the sequence of (BuildPairF64 (ins (ExtractElementF64
2624 // Op 1), $zero, 31 1) (ExtractElementF64 Op 0)) and the Op has one use, we
2625 // should be able to drop the usage of mfc1/mtc1 and rewrite the register in
2626 // place.
2627 SDValue LowX =
2628 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2629 DAG.getConstant(0, DL, MVT::i32));
2630 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2631 }
2632
lowerFABS64(SDValue Op,SelectionDAG & DAG,bool HasExtractInsert) const2633 SDValue MipsTargetLowering::lowerFABS64(SDValue Op, SelectionDAG &DAG,
2634 bool HasExtractInsert) const {
2635 SDLoc DL(Op);
2636 SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32);
2637
2638 if (DAG.getTarget().Options.NoNaNsFPMath || Subtarget.inAbs2008Mode())
2639 return DAG.getNode(MipsISD::FAbs, DL, Op.getValueType(), Op.getOperand(0));
2640
2641 // Bitcast to integer node.
2642 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
2643
2644 // Clear MSB.
2645 if (HasExtractInsert)
2646 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
2647 DAG.getRegister(Mips::ZERO_64, MVT::i64),
2648 DAG.getConstant(63, DL, MVT::i32), Const1, X);
2649 else {
2650 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
2651 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
2652 }
2653
2654 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
2655 }
2656
lowerFABS(SDValue Op,SelectionDAG & DAG) const2657 SDValue MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const {
2658 if ((ABI.IsN32() || ABI.IsN64()) && (Op.getValueType() == MVT::f64))
2659 return lowerFABS64(Op, DAG, Subtarget.hasExtractInsert());
2660
2661 return lowerFABS32(Op, DAG, Subtarget.hasExtractInsert());
2662 }
2663
lowerFCANONICALIZE(SDValue Op,SelectionDAG & DAG) const2664 SDValue MipsTargetLowering::lowerFCANONICALIZE(SDValue Op,
2665 SelectionDAG &DAG) const {
2666 SDLoc DL(Op);
2667 EVT VT = Op.getValueType();
2668 SDValue Operand = Op.getOperand(0);
2669 SDNodeFlags Flags = Op->getFlags();
2670
2671 if (Flags.hasNoNaNs() || DAG.isKnownNeverNaN(Operand))
2672 return Operand;
2673
2674 SDValue Quiet = DAG.getNode(ISD::FADD, DL, VT, Operand, Operand);
2675 return DAG.getSelectCC(DL, Operand, Operand, Quiet, Operand, ISD::SETUO);
2676 }
2677
2678 SDValue MipsTargetLowering::
lowerFRAMEADDR(SDValue Op,SelectionDAG & DAG) const2679 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2680 // check the depth
2681 if (Op.getConstantOperandVal(0) != 0) {
2682 DAG.getContext()->emitError(
2683 "return address can be determined only for current frame");
2684 return SDValue();
2685 }
2686
2687 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2688 MFI.setFrameAddressIsTaken(true);
2689 EVT VT = Op.getValueType();
2690 SDLoc DL(Op);
2691 SDValue FrameAddr = DAG.getCopyFromReg(
2692 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT);
2693 return FrameAddr;
2694 }
2695
lowerRETURNADDR(SDValue Op,SelectionDAG & DAG) const2696 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
2697 SelectionDAG &DAG) const {
2698 // check the depth
2699 if (Op.getConstantOperandVal(0) != 0) {
2700 DAG.getContext()->emitError(
2701 "return address can be determined only for current frame");
2702 return SDValue();
2703 }
2704
2705 MachineFunction &MF = DAG.getMachineFunction();
2706 MachineFrameInfo &MFI = MF.getFrameInfo();
2707 MVT VT = Op.getSimpleValueType();
2708 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
2709 MFI.setReturnAddressIsTaken(true);
2710
2711 // Return RA, which contains the return address. Mark it an implicit live-in.
2712 Register Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2713 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
2714 }
2715
2716 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is
2717 // generated from __builtin_eh_return (offset, handler)
2718 // The effect of this is to adjust the stack pointer by "offset"
2719 // and then branch to "handler".
lowerEH_RETURN(SDValue Op,SelectionDAG & DAG) const2720 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2721 const {
2722 MachineFunction &MF = DAG.getMachineFunction();
2723 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2724
2725 MipsFI->setCallsEhReturn();
2726 SDValue Chain = Op.getOperand(0);
2727 SDValue Offset = Op.getOperand(1);
2728 SDValue Handler = Op.getOperand(2);
2729 SDLoc DL(Op);
2730 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2731
2732 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2733 // EH_RETURN nodes, so that instructions are emitted back-to-back.
2734 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1;
2735 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
2736 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2737 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2738 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
2739 DAG.getRegister(OffsetReg, Ty),
2740 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())),
2741 Chain.getValue(1));
2742 }
2743
lowerATOMIC_FENCE(SDValue Op,SelectionDAG & DAG) const2744 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
2745 SelectionDAG &DAG) const {
2746 // FIXME: Need pseudo-fence for 'singlethread' fences
2747 // FIXME: Set SType for weaker fences where supported/appropriate.
2748 unsigned SType = 0;
2749 SDLoc DL(Op);
2750 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
2751 DAG.getConstant(SType, DL, MVT::i32));
2752 }
2753
lowerShiftLeftParts(SDValue Op,SelectionDAG & DAG) const2754 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
2755 SelectionDAG &DAG) const {
2756 SDLoc DL(Op);
2757 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2758
2759 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2760 SDValue Shamt = Op.getOperand(2);
2761 // if shamt < (VT.bits):
2762 // lo = (shl lo, shamt)
2763 // hi = (or (shl hi, shamt) (srl (srl lo, 1), (xor shamt, (VT.bits-1))))
2764 // else:
2765 // lo = 0
2766 // hi = (shl lo, shamt[4:0])
2767 SDValue Not =
2768 DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2769 DAG.getConstant(VT.getSizeInBits() - 1, DL, MVT::i32));
2770 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2771 DAG.getConstant(1, DL, VT));
2772 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
2773 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2774 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2775 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
2776 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2777 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2778 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2779 DAG.getConstant(0, DL, VT), ShiftLeftLo);
2780 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
2781
2782 SDValue Ops[2] = {Lo, Hi};
2783 return DAG.getMergeValues(Ops, DL);
2784 }
2785
lowerShiftRightParts(SDValue Op,SelectionDAG & DAG,bool IsSRA) const2786 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2787 bool IsSRA) const {
2788 SDLoc DL(Op);
2789 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2790 SDValue Shamt = Op.getOperand(2);
2791 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2792
2793 // if shamt < (VT.bits):
2794 // lo = (or (shl (shl hi, 1), (xor shamt, (VT.bits-1))) (srl lo, shamt))
2795 // if isSRA:
2796 // hi = (sra hi, shamt)
2797 // else:
2798 // hi = (srl hi, shamt)
2799 // else:
2800 // if isSRA:
2801 // lo = (sra hi, shamt[4:0])
2802 // hi = (sra hi, 31)
2803 // else:
2804 // lo = (srl hi, shamt[4:0])
2805 // hi = 0
2806 SDValue Not =
2807 DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2808 DAG.getConstant(VT.getSizeInBits() - 1, DL, MVT::i32));
2809 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
2810 DAG.getConstant(1, DL, VT));
2811 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
2812 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2813 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2814 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
2815 DL, VT, Hi, Shamt);
2816 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2817 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2818 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
2819 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT));
2820
2821 if (!(Subtarget.hasMips4() || Subtarget.hasMips32())) {
2822 SDVTList VTList = DAG.getVTList(VT, VT);
2823 return DAG.getNode(Subtarget.isGP64bit() ? MipsISD::DOUBLE_SELECT_I64
2824 : MipsISD::DOUBLE_SELECT_I,
2825 DL, VTList, Cond, ShiftRightHi,
2826 IsSRA ? Ext : DAG.getConstant(0, DL, VT), Or,
2827 ShiftRightHi);
2828 }
2829
2830 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
2831 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2832 IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi);
2833
2834 SDValue Ops[2] = {Lo, Hi};
2835 return DAG.getMergeValues(Ops, DL);
2836 }
2837
createLoadLR(unsigned Opc,SelectionDAG & DAG,LoadSDNode * LD,SDValue Chain,SDValue Src,unsigned Offset)2838 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2839 SDValue Chain, SDValue Src, unsigned Offset) {
2840 SDValue Ptr = LD->getBasePtr();
2841 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2842 EVT BasePtrVT = Ptr.getValueType();
2843 SDLoc DL(LD);
2844 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2845
2846 if (Offset)
2847 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2848 DAG.getConstant(Offset, DL, BasePtrVT));
2849
2850 SDValue Ops[] = { Chain, Ptr, Src };
2851 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2852 LD->getMemOperand());
2853 }
2854
2855 // Expand an unaligned 32 or 64-bit integer load node.
lowerLOAD(SDValue Op,SelectionDAG & DAG) const2856 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2857 LoadSDNode *LD = cast<LoadSDNode>(Op);
2858 EVT MemVT = LD->getMemoryVT();
2859
2860 if (Subtarget.systemSupportsUnalignedAccess())
2861 return Op;
2862
2863 // Return if load is aligned or if MemVT is neither i32 nor i64.
2864 if ((LD->getAlign().value() >= (MemVT.getSizeInBits() / 8)) ||
2865 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2866 return SDValue();
2867
2868 bool IsLittle = Subtarget.isLittle();
2869 EVT VT = Op.getValueType();
2870 ISD::LoadExtType ExtType = LD->getExtensionType();
2871 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2872
2873 assert((VT == MVT::i32) || (VT == MVT::i64));
2874
2875 // Expand
2876 // (set dst, (i64 (load baseptr)))
2877 // to
2878 // (set tmp, (ldl (add baseptr, 7), undef))
2879 // (set dst, (ldr baseptr, tmp))
2880 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2881 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2882 IsLittle ? 7 : 0);
2883 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2884 IsLittle ? 0 : 7);
2885 }
2886
2887 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2888 IsLittle ? 3 : 0);
2889 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2890 IsLittle ? 0 : 3);
2891
2892 // Expand
2893 // (set dst, (i32 (load baseptr))) or
2894 // (set dst, (i64 (sextload baseptr))) or
2895 // (set dst, (i64 (extload baseptr)))
2896 // to
2897 // (set tmp, (lwl (add baseptr, 3), undef))
2898 // (set dst, (lwr baseptr, tmp))
2899 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2900 (ExtType == ISD::EXTLOAD))
2901 return LWR;
2902
2903 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2904
2905 // Expand
2906 // (set dst, (i64 (zextload baseptr)))
2907 // to
2908 // (set tmp0, (lwl (add baseptr, 3), undef))
2909 // (set tmp1, (lwr baseptr, tmp0))
2910 // (set tmp2, (shl tmp1, 32))
2911 // (set dst, (srl tmp2, 32))
2912 SDLoc DL(LD);
2913 SDValue Const32 = DAG.getConstant(32, DL, MVT::i32);
2914 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2915 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2916 SDValue Ops[] = { SRL, LWR.getValue(1) };
2917 return DAG.getMergeValues(Ops, DL);
2918 }
2919
createStoreLR(unsigned Opc,SelectionDAG & DAG,StoreSDNode * SD,SDValue Chain,unsigned Offset)2920 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2921 SDValue Chain, unsigned Offset) {
2922 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2923 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2924 SDLoc DL(SD);
2925 SDVTList VTList = DAG.getVTList(MVT::Other);
2926
2927 if (Offset)
2928 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2929 DAG.getConstant(Offset, DL, BasePtrVT));
2930
2931 SDValue Ops[] = { Chain, Value, Ptr };
2932 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2933 SD->getMemOperand());
2934 }
2935
2936 // Expand an unaligned 32 or 64-bit integer store node.
lowerUnalignedIntStore(StoreSDNode * SD,SelectionDAG & DAG,bool IsLittle)2937 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
2938 bool IsLittle) {
2939 SDValue Value = SD->getValue(), Chain = SD->getChain();
2940 EVT VT = Value.getValueType();
2941
2942 // Expand
2943 // (store val, baseptr) or
2944 // (truncstore val, baseptr)
2945 // to
2946 // (swl val, (add baseptr, 3))
2947 // (swr val, baseptr)
2948 if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2949 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2950 IsLittle ? 3 : 0);
2951 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2952 }
2953
2954 assert(VT == MVT::i64);
2955
2956 // Expand
2957 // (store val, baseptr)
2958 // to
2959 // (sdl val, (add baseptr, 7))
2960 // (sdr val, baseptr)
2961 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2962 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2963 }
2964
2965 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
lowerFP_TO_SINT_STORE(StoreSDNode * SD,SelectionDAG & DAG,bool SingleFloat)2966 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG,
2967 bool SingleFloat) {
2968 SDValue Val = SD->getValue();
2969
2970 if (Val.getOpcode() != ISD::FP_TO_SINT ||
2971 (Val.getValueSizeInBits() > 32 && SingleFloat))
2972 return SDValue();
2973
2974 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
2975 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2976 Val.getOperand(0));
2977 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2978 SD->getPointerInfo(), SD->getAlign(),
2979 SD->getMemOperand()->getFlags());
2980 }
2981
lowerSTORE(SDValue Op,SelectionDAG & DAG) const2982 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2983 StoreSDNode *SD = cast<StoreSDNode>(Op);
2984 EVT MemVT = SD->getMemoryVT();
2985
2986 // Lower unaligned integer stores.
2987 if (!Subtarget.systemSupportsUnalignedAccess() &&
2988 (SD->getAlign().value() < (MemVT.getSizeInBits() / 8)) &&
2989 ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2990 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle());
2991
2992 return lowerFP_TO_SINT_STORE(SD, DAG, Subtarget.isSingleFloat());
2993 }
2994
lowerEH_DWARF_CFA(SDValue Op,SelectionDAG & DAG) const2995 SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op,
2996 SelectionDAG &DAG) const {
2997
2998 // Return a fixed StackObject with offset 0 which points to the old stack
2999 // pointer.
3000 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
3001 EVT ValTy = Op->getValueType(0);
3002 int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
3003 return DAG.getFrameIndex(FI, ValTy);
3004 }
3005
lowerFP_TO_SINT(SDValue Op,SelectionDAG & DAG) const3006 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
3007 SelectionDAG &DAG) const {
3008 if (Op.getValueSizeInBits() > 32 && Subtarget.isSingleFloat())
3009 return SDValue();
3010
3011 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
3012 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
3013 Op.getOperand(0));
3014 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
3015 }
3016
3017 //===----------------------------------------------------------------------===//
3018 // Calling Convention Implementation
3019 //===----------------------------------------------------------------------===//
3020
3021 //===----------------------------------------------------------------------===//
3022 // TODO: Implement a generic logic using tblgen that can support this.
3023 // Mips O32 ABI rules:
3024 // ---
3025 // i32 - Passed in A0, A1, A2, A3 and stack
3026 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
3027 // an argument. Otherwise, passed in A1, A2, A3 and stack.
3028 // f64 - Only passed in two aliased f32 registers if no int reg has been used
3029 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
3030 // not used, it must be shadowed. If only A3 is available, shadow it and
3031 // go to stack.
3032 // vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack.
3033 // vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3}
3034 // with the remainder spilled to the stack.
3035 // vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases
3036 // spilling the remainder to the stack.
3037 //
3038 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
3039 //===----------------------------------------------------------------------===//
3040
CC_MipsO32(unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State,ArrayRef<MCPhysReg> F64Regs)3041 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
3042 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
3043 CCState &State, ArrayRef<MCPhysReg> F64Regs) {
3044 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>(
3045 State.getMachineFunction().getSubtarget());
3046
3047 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
3048
3049 const MipsCCState * MipsState = static_cast<MipsCCState *>(&State);
3050
3051 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
3052
3053 static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 };
3054
3055 // Do not process byval args here.
3056 if (ArgFlags.isByVal())
3057 return true;
3058
3059 // Promote i8 and i16
3060 if (ArgFlags.isInReg() && !Subtarget.isLittle()) {
3061 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
3062 LocVT = MVT::i32;
3063 if (ArgFlags.isSExt())
3064 LocInfo = CCValAssign::SExtUpper;
3065 else if (ArgFlags.isZExt())
3066 LocInfo = CCValAssign::ZExtUpper;
3067 else
3068 LocInfo = CCValAssign::AExtUpper;
3069 }
3070 }
3071
3072 // Promote i8 and i16
3073 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
3074 LocVT = MVT::i32;
3075 if (ArgFlags.isSExt())
3076 LocInfo = CCValAssign::SExt;
3077 else if (ArgFlags.isZExt())
3078 LocInfo = CCValAssign::ZExt;
3079 else
3080 LocInfo = CCValAssign::AExt;
3081 }
3082
3083 unsigned Reg;
3084
3085 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
3086 // is true: function is vararg, argument is 3rd or higher, there is previous
3087 // argument which is not f32 or f64.
3088 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 ||
3089 State.getFirstUnallocated(F32Regs) != ValNo;
3090 Align OrigAlign = ArgFlags.getNonZeroOrigAlign();
3091 bool isI64 = (ValVT == MVT::i32 && OrigAlign == Align(8));
3092 bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo);
3093
3094 // The MIPS vector ABI for floats passes them in a pair of registers
3095 if (ValVT == MVT::i32 && isVectorFloat) {
3096 // This is the start of an vector that was scalarized into an unknown number
3097 // of components. It doesn't matter how many there are. Allocate one of the
3098 // notional 8 byte aligned registers which map onto the argument stack, and
3099 // shadow the register lost to alignment requirements.
3100 if (ArgFlags.isSplit()) {
3101 Reg = State.AllocateReg(FloatVectorIntRegs);
3102 if (Reg == Mips::A2)
3103 State.AllocateReg(Mips::A1);
3104 else if (Reg == 0)
3105 State.AllocateReg(Mips::A3);
3106 } else {
3107 // If we're an intermediate component of the split, we can just attempt to
3108 // allocate a register directly.
3109 Reg = State.AllocateReg(IntRegs);
3110 }
3111 } else if (ValVT == MVT::i32 ||
3112 (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
3113 Reg = State.AllocateReg(IntRegs);
3114 // If this is the first part of an i64 arg,
3115 // the allocated register must be either A0 or A2.
3116 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
3117 Reg = State.AllocateReg(IntRegs);
3118 LocVT = MVT::i32;
3119 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
3120 // Allocate int register and shadow next int register. If first
3121 // available register is Mips::A1 or Mips::A3, shadow it too.
3122 Reg = State.AllocateReg(IntRegs);
3123 if (Reg == Mips::A1 || Reg == Mips::A3)
3124 Reg = State.AllocateReg(IntRegs);
3125
3126 if (Reg) {
3127 LocVT = MVT::i32;
3128
3129 State.addLoc(
3130 CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3131 MCRegister HiReg = State.AllocateReg(IntRegs);
3132 assert(HiReg);
3133 State.addLoc(
3134 CCValAssign::getCustomReg(ValNo, ValVT, HiReg, LocVT, LocInfo));
3135 return false;
3136 }
3137 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
3138 // we are guaranteed to find an available float register
3139 if (ValVT == MVT::f32) {
3140 Reg = State.AllocateReg(F32Regs);
3141 // Shadow int register
3142 State.AllocateReg(IntRegs);
3143 } else {
3144 Reg = State.AllocateReg(F64Regs);
3145 // Shadow int registers
3146 MCRegister Reg2 = State.AllocateReg(IntRegs);
3147 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
3148 State.AllocateReg(IntRegs);
3149 State.AllocateReg(IntRegs);
3150 }
3151 } else
3152 llvm_unreachable("Cannot handle this ValVT.");
3153
3154 if (!Reg) {
3155 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(), OrigAlign);
3156 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
3157 } else
3158 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3159
3160 return false;
3161 }
3162
CC_MipsO32_FP32(unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State)3163 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
3164 MVT LocVT, CCValAssign::LocInfo LocInfo,
3165 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3166 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
3167
3168 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
3169 }
3170
CC_MipsO32_FP64(unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State)3171 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
3172 MVT LocVT, CCValAssign::LocInfo LocInfo,
3173 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3174 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
3175
3176 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
3177 }
3178
3179 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
3180 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
3181 CCState &State) LLVM_ATTRIBUTE_UNUSED;
3182
3183 #include "MipsGenCallingConv.inc"
3184
CCAssignFnForCall() const3185 CCAssignFn *MipsTargetLowering::CCAssignFnForCall() const{
3186 return CC_Mips_FixedArg;
3187 }
3188
CCAssignFnForReturn() const3189 CCAssignFn *MipsTargetLowering::CCAssignFnForReturn() const{
3190 return RetCC_Mips;
3191 }
3192 //===----------------------------------------------------------------------===//
3193 // Call Calling Convention Implementation
3194 //===----------------------------------------------------------------------===//
3195
passArgOnStack(SDValue StackPtr,unsigned Offset,SDValue Chain,SDValue Arg,const SDLoc & DL,bool IsTailCall,SelectionDAG & DAG) const3196 SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
3197 SDValue Chain, SDValue Arg,
3198 const SDLoc &DL, bool IsTailCall,
3199 SelectionDAG &DAG) const {
3200 if (!IsTailCall) {
3201 SDValue PtrOff =
3202 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
3203 DAG.getIntPtrConstant(Offset, DL));
3204 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo());
3205 }
3206
3207 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
3208 int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
3209 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3210 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), MaybeAlign(),
3211 MachineMemOperand::MOVolatile);
3212 }
3213
3214 void MipsTargetLowering::
getOpndList(SmallVectorImpl<SDValue> & Ops,std::deque<std::pair<unsigned,SDValue>> & RegsToPass,bool IsPICCall,bool GlobalOrExternal,bool InternalLinkage,bool IsCallReloc,CallLoweringInfo & CLI,SDValue Callee,SDValue Chain) const3215 getOpndList(SmallVectorImpl<SDValue> &Ops,
3216 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
3217 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
3218 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
3219 SDValue Chain) const {
3220 // Insert node "GP copy globalreg" before call to function.
3221 //
3222 // R_MIPS_CALL* operators (emitted when non-internal functions are called
3223 // in PIC mode) allow symbols to be resolved via lazy binding.
3224 // The lazy binding stub requires GP to point to the GOT.
3225 // Note that we don't need GP to point to the GOT for indirect calls
3226 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates
3227 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs
3228 // used for the function (that is, Mips linker doesn't generate lazy binding
3229 // stub for a function whose address is taken in the program).
3230 if (IsPICCall && !InternalLinkage && IsCallReloc) {
3231 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP;
3232 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
3233 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
3234 }
3235
3236 // Build a sequence of copy-to-reg nodes chained together with token
3237 // chain and flag operands which copy the outgoing args into registers.
3238 // The InGlue in necessary since all emitted instructions must be
3239 // stuck together.
3240 SDValue InGlue;
3241
3242 for (auto &R : RegsToPass) {
3243 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, R.first, R.second, InGlue);
3244 InGlue = Chain.getValue(1);
3245 }
3246
3247 // Add argument registers to the end of the list so that they are
3248 // known live into the call.
3249 for (auto &R : RegsToPass)
3250 Ops.push_back(CLI.DAG.getRegister(R.first, R.second.getValueType()));
3251
3252 // Add a register mask operand representing the call-preserved registers.
3253 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
3254 const uint32_t *Mask =
3255 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv);
3256 assert(Mask && "Missing call preserved mask for calling convention");
3257 if (Subtarget.inMips16HardFloat()) {
3258 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
3259 StringRef Sym = G->getGlobal()->getName();
3260 Function *F = G->getGlobal()->getParent()->getFunction(Sym);
3261 if (F && F->hasFnAttribute("__Mips16RetHelper")) {
3262 Mask = MipsRegisterInfo::getMips16RetHelperMask();
3263 }
3264 }
3265 }
3266 Ops.push_back(CLI.DAG.getRegisterMask(Mask));
3267
3268 if (InGlue.getNode())
3269 Ops.push_back(InGlue);
3270 }
3271
AdjustInstrPostInstrSelection(MachineInstr & MI,SDNode * Node) const3272 void MipsTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
3273 SDNode *Node) const {
3274 switch (MI.getOpcode()) {
3275 default:
3276 return;
3277 case Mips::JALR:
3278 case Mips::JALRPseudo:
3279 case Mips::JALR64:
3280 case Mips::JALR64Pseudo:
3281 case Mips::JALR16_MM:
3282 case Mips::JALRC16_MMR6:
3283 case Mips::TAILCALLREG:
3284 case Mips::TAILCALLREG64:
3285 case Mips::TAILCALLR6REG:
3286 case Mips::TAILCALL64R6REG:
3287 case Mips::TAILCALLREG_MM:
3288 case Mips::TAILCALLREG_MMR6: {
3289 if (!EmitJalrReloc ||
3290 Subtarget.inMips16Mode() ||
3291 !isPositionIndependent() ||
3292 Node->getNumOperands() < 1 ||
3293 Node->getOperand(0).getNumOperands() < 2) {
3294 return;
3295 }
3296 // We are after the callee address, set by LowerCall().
3297 // If added to MI, asm printer will emit .reloc R_MIPS_JALR for the
3298 // symbol.
3299 const SDValue TargetAddr = Node->getOperand(0).getOperand(1);
3300 StringRef Sym;
3301 if (const GlobalAddressSDNode *G =
3302 dyn_cast_or_null<const GlobalAddressSDNode>(TargetAddr)) {
3303 // We must not emit the R_MIPS_JALR relocation against data symbols
3304 // since this will cause run-time crashes if the linker replaces the
3305 // call instruction with a relative branch to the data symbol.
3306 if (!isa<Function>(G->getGlobal())) {
3307 LLVM_DEBUG(dbgs() << "Not adding R_MIPS_JALR against data symbol "
3308 << G->getGlobal()->getName() << "\n");
3309 return;
3310 }
3311 Sym = G->getGlobal()->getName();
3312 }
3313 else if (const ExternalSymbolSDNode *ES =
3314 dyn_cast_or_null<const ExternalSymbolSDNode>(TargetAddr)) {
3315 Sym = ES->getSymbol();
3316 }
3317
3318 if (Sym.empty())
3319 return;
3320
3321 MachineFunction *MF = MI.getParent()->getParent();
3322 MCSymbol *S = MF->getContext().getOrCreateSymbol(Sym);
3323 LLVM_DEBUG(dbgs() << "Adding R_MIPS_JALR against " << Sym << "\n");
3324 MI.addOperand(MachineOperand::CreateMCSymbol(S, MipsII::MO_JALR));
3325 }
3326 }
3327 }
3328
3329 /// LowerCall - functions arguments are copied from virtual regs to
3330 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
3331 SDValue
LowerCall(TargetLowering::CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const3332 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3333 SmallVectorImpl<SDValue> &InVals) const {
3334 SelectionDAG &DAG = CLI.DAG;
3335 SDLoc DL = CLI.DL;
3336 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3337 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3338 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3339 SDValue Chain = CLI.Chain;
3340 SDValue Callee = CLI.Callee;
3341 bool &IsTailCall = CLI.IsTailCall;
3342 CallingConv::ID CallConv = CLI.CallConv;
3343 bool IsVarArg = CLI.IsVarArg;
3344
3345 MachineFunction &MF = DAG.getMachineFunction();
3346 MachineFrameInfo &MFI = MF.getFrameInfo();
3347 const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
3348 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
3349 bool IsPIC = isPositionIndependent();
3350
3351 // Analyze operands of the call, assigning locations to each operand.
3352 SmallVector<CCValAssign, 16> ArgLocs;
3353 MipsCCState CCInfo(
3354 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
3355 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget));
3356
3357 const ExternalSymbolSDNode *ES =
3358 dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode());
3359
3360 // There is one case where CALLSEQ_START..CALLSEQ_END can be nested, which
3361 // is during the lowering of a call with a byval argument which produces
3362 // a call to memcpy. For the O32 case, this causes the caller to allocate
3363 // stack space for the reserved argument area for the callee, then recursively
3364 // again for the memcpy call. In the NEWABI case, this doesn't occur as those
3365 // ABIs mandate that the callee allocates the reserved argument area. We do
3366 // still produce nested CALLSEQ_START..CALLSEQ_END with zero space though.
3367 //
3368 // If the callee has a byval argument and memcpy is used, we are mandated
3369 // to already have produced a reserved argument area for the callee for O32.
3370 // Therefore, the reserved argument area can be reused for both calls.
3371 //
3372 // Other cases of calling memcpy cannot have a chain with a CALLSEQ_START
3373 // present, as we have yet to hook that node onto the chain.
3374 //
3375 // Hence, the CALLSEQ_START and CALLSEQ_END nodes can be eliminated in this
3376 // case. GCC does a similar trick, in that wherever possible, it calculates
3377 // the maximum out going argument area (including the reserved area), and
3378 // preallocates the stack space on entrance to the caller.
3379 //
3380 // FIXME: We should do the same for efficiency and space.
3381
3382 // Note: The check on the calling convention below must match
3383 // MipsABIInfo::GetCalleeAllocdArgSizeInBytes().
3384 bool MemcpyInByVal = ES && StringRef(ES->getSymbol()) == "memcpy" &&
3385 CallConv != CallingConv::Fast &&
3386 Chain.getOpcode() == ISD::CALLSEQ_START;
3387
3388 // Allocate the reserved argument area. It seems strange to do this from the
3389 // caller side but removing it breaks the frame size calculation.
3390 unsigned ReservedArgArea =
3391 MemcpyInByVal ? 0 : ABI.GetCalleeAllocdArgSizeInBytes(CallConv);
3392 CCInfo.AllocateStack(ReservedArgArea, Align(1));
3393
3394 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(),
3395 ES ? ES->getSymbol() : nullptr);
3396
3397 // Get a count of how many bytes are to be pushed on the stack.
3398 unsigned StackSize = CCInfo.getStackSize();
3399
3400 // Call site info for function parameters tracking.
3401 MachineFunction::CallSiteInfo CSInfo;
3402
3403 // Check if it's really possible to do a tail call. Restrict it to functions
3404 // that are part of this compilation unit.
3405 bool InternalLinkage = false;
3406 if (IsTailCall) {
3407 IsTailCall = isEligibleForTailCallOptimization(
3408 CCInfo, StackSize, *MF.getInfo<MipsFunctionInfo>());
3409 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3410 InternalLinkage = G->getGlobal()->hasInternalLinkage();
3411 IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() ||
3412 G->getGlobal()->hasPrivateLinkage() ||
3413 G->getGlobal()->hasHiddenVisibility() ||
3414 G->getGlobal()->hasProtectedVisibility());
3415 }
3416 }
3417 if (!IsTailCall && CLI.CB && CLI.CB->isMustTailCall())
3418 report_fatal_error("failed to perform tail call elimination on a call "
3419 "site marked musttail");
3420
3421 if (IsTailCall)
3422 ++NumTailCalls;
3423
3424 // Chain is the output chain of the last Load/Store or CopyToReg node.
3425 // ByValChain is the output chain of the last Memcpy node created for copying
3426 // byval arguments to the stack.
3427 unsigned StackAlignment = TFL->getStackAlignment();
3428 StackSize = alignTo(StackSize, StackAlignment);
3429
3430 if (!(IsTailCall || MemcpyInByVal))
3431 Chain = DAG.getCALLSEQ_START(Chain, StackSize, 0, DL);
3432
3433 SDValue StackPtr =
3434 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
3435 getPointerTy(DAG.getDataLayout()));
3436 std::deque<std::pair<unsigned, SDValue>> RegsToPass;
3437 SmallVector<SDValue, 8> MemOpChains;
3438
3439 CCInfo.rewindByValRegsInfo();
3440
3441 // Walk the register/memloc assignments, inserting copies/loads.
3442 for (unsigned i = 0, e = ArgLocs.size(), OutIdx = 0; i != e; ++i, ++OutIdx) {
3443 SDValue Arg = OutVals[OutIdx];
3444 CCValAssign &VA = ArgLocs[i];
3445 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
3446 ISD::ArgFlagsTy Flags = Outs[OutIdx].Flags;
3447 bool UseUpperBits = false;
3448
3449 // ByVal Arg.
3450 if (Flags.isByVal()) {
3451 unsigned FirstByValReg, LastByValReg;
3452 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3453 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3454
3455 assert(Flags.getByValSize() &&
3456 "ByVal args of size 0 should have been ignored by front-end.");
3457 assert(ByValIdx < CCInfo.getInRegsParamsCount());
3458 assert(!IsTailCall &&
3459 "Do not tail-call optimize if there is a byval argument.");
3460 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
3461 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(),
3462 VA);
3463 CCInfo.nextInRegsParam();
3464 continue;
3465 }
3466
3467 // Promote the value if needed.
3468 switch (VA.getLocInfo()) {
3469 default:
3470 llvm_unreachable("Unknown loc info!");
3471 case CCValAssign::Full:
3472 if (VA.isRegLoc()) {
3473 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
3474 (ValVT == MVT::f64 && LocVT == MVT::i64) ||
3475 (ValVT == MVT::i64 && LocVT == MVT::f64))
3476 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
3477 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
3478 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
3479 Arg, DAG.getConstant(0, DL, MVT::i32));
3480 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
3481 Arg, DAG.getConstant(1, DL, MVT::i32));
3482 if (!Subtarget.isLittle())
3483 std::swap(Lo, Hi);
3484
3485 assert(VA.needsCustom());
3486
3487 Register LocRegLo = VA.getLocReg();
3488 Register LocRegHigh = ArgLocs[++i].getLocReg();
3489 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
3490 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
3491 continue;
3492 }
3493 }
3494 break;
3495 case CCValAssign::BCvt:
3496 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
3497 break;
3498 case CCValAssign::SExtUpper:
3499 UseUpperBits = true;
3500 [[fallthrough]];
3501 case CCValAssign::SExt:
3502 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
3503 break;
3504 case CCValAssign::ZExtUpper:
3505 UseUpperBits = true;
3506 [[fallthrough]];
3507 case CCValAssign::ZExt:
3508 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
3509 break;
3510 case CCValAssign::AExtUpper:
3511 UseUpperBits = true;
3512 [[fallthrough]];
3513 case CCValAssign::AExt:
3514 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
3515 break;
3516 }
3517
3518 if (UseUpperBits) {
3519 unsigned ValSizeInBits = Outs[OutIdx].ArgVT.getSizeInBits();
3520 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3521 Arg = DAG.getNode(
3522 ISD::SHL, DL, VA.getLocVT(), Arg,
3523 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3524 }
3525
3526 // Arguments that can be passed on register must be kept at
3527 // RegsToPass vector
3528 if (VA.isRegLoc()) {
3529 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3530
3531 // If the parameter is passed through reg $D, which splits into
3532 // two physical registers, avoid creating call site info.
3533 if (Mips::AFGR64RegClass.contains(VA.getLocReg()))
3534 continue;
3535
3536 // Collect CSInfo about which register passes which parameter.
3537 const TargetOptions &Options = DAG.getTarget().Options;
3538 if (Options.EmitCallSiteInfo)
3539 CSInfo.ArgRegPairs.emplace_back(VA.getLocReg(), i);
3540
3541 continue;
3542 }
3543
3544 // Register can't get to this point...
3545 assert(VA.isMemLoc());
3546
3547 // emit ISD::STORE whichs stores the
3548 // parameter value to a stack Location
3549 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
3550 Chain, Arg, DL, IsTailCall, DAG));
3551 }
3552
3553 // Transform all store nodes into one single node because all store
3554 // nodes are independent of each other.
3555 if (!MemOpChains.empty())
3556 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
3557
3558 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
3559 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3560 // node so that legalize doesn't hack it.
3561
3562 EVT Ty = Callee.getValueType();
3563 bool GlobalOrExternal = false, IsCallReloc = false;
3564
3565 // The long-calls feature is ignored in case of PIC.
3566 // While we do not support -mshared / -mno-shared properly,
3567 // ignore long-calls in case of -mabicalls too.
3568 if (!Subtarget.isABICalls() && !IsPIC) {
3569 // If the function should be called using "long call",
3570 // get its address into a register to prevent using
3571 // of the `jal` instruction for the direct call.
3572 if (auto *N = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3573 if (Subtarget.useLongCalls())
3574 Callee = Subtarget.hasSym32()
3575 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
3576 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
3577 } else if (auto *N = dyn_cast<GlobalAddressSDNode>(Callee)) {
3578 bool UseLongCalls = Subtarget.useLongCalls();
3579 // If the function has long-call/far/near attribute
3580 // it overrides command line switch pased to the backend.
3581 if (auto *F = dyn_cast<Function>(N->getGlobal())) {
3582 if (F->hasFnAttribute("long-call"))
3583 UseLongCalls = true;
3584 else if (F->hasFnAttribute("short-call"))
3585 UseLongCalls = false;
3586 }
3587 if (UseLongCalls)
3588 Callee = Subtarget.hasSym32()
3589 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
3590 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
3591 }
3592 }
3593
3594 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3595 if (Subtarget.isTargetCOFF() &&
3596 G->getGlobal()->hasDLLImportStorageClass()) {
3597 assert(Subtarget.isTargetWindows() &&
3598 "Windows is the only supported COFF target");
3599 auto PtrInfo = MachinePointerInfo();
3600 Callee = DAG.getLoad(Ty, DL, Chain,
3601 getDllimportSymbol(G, SDLoc(G), Ty, DAG), PtrInfo);
3602 } else if (IsPIC) {
3603 const GlobalValue *Val = G->getGlobal();
3604 InternalLinkage = Val->hasInternalLinkage();
3605
3606 if (InternalLinkage)
3607 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64());
3608 else if (Subtarget.useXGOT()) {
3609 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16,
3610 MipsII::MO_CALL_LO16, Chain,
3611 FuncInfo->callPtrInfo(MF, Val));
3612 IsCallReloc = true;
3613 } else {
3614 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
3615 FuncInfo->callPtrInfo(MF, Val));
3616 IsCallReloc = true;
3617 }
3618 } else
3619 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL,
3620 getPointerTy(DAG.getDataLayout()), 0,
3621 MipsII::MO_NO_FLAG);
3622 GlobalOrExternal = true;
3623 }
3624 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3625 const char *Sym = S->getSymbol();
3626
3627 if (!IsPIC) // static
3628 Callee = DAG.getTargetExternalSymbol(
3629 Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG);
3630 else if (Subtarget.useXGOT()) {
3631 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16,
3632 MipsII::MO_CALL_LO16, Chain,
3633 FuncInfo->callPtrInfo(MF, Sym));
3634 IsCallReloc = true;
3635 } else { // PIC
3636 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
3637 FuncInfo->callPtrInfo(MF, Sym));
3638 IsCallReloc = true;
3639 }
3640
3641 GlobalOrExternal = true;
3642 }
3643
3644 SmallVector<SDValue, 8> Ops(1, Chain);
3645 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3646
3647 getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage,
3648 IsCallReloc, CLI, Callee, Chain);
3649
3650 if (IsTailCall) {
3651 MF.getFrameInfo().setHasTailCall();
3652 SDValue Ret = DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
3653 DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
3654 return Ret;
3655 }
3656
3657 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
3658 SDValue InGlue = Chain.getValue(1);
3659
3660 DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
3661
3662 // Create the CALLSEQ_END node in the case of where it is not a call to
3663 // memcpy.
3664 if (!(MemcpyInByVal)) {
3665 Chain = DAG.getCALLSEQ_END(Chain, StackSize, 0, InGlue, DL);
3666 InGlue = Chain.getValue(1);
3667 }
3668
3669 // Handle result values, copying them out of physregs into vregs that we
3670 // return.
3671 return LowerCallResult(Chain, InGlue, CallConv, IsVarArg, Ins, DL, DAG,
3672 InVals, CLI);
3673 }
3674
3675 /// LowerCallResult - Lower the result values of a call into the
3676 /// appropriate copies out of appropriate physical registers.
LowerCallResult(SDValue Chain,SDValue InGlue,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals,TargetLowering::CallLoweringInfo & CLI) const3677 SDValue MipsTargetLowering::LowerCallResult(
3678 SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool IsVarArg,
3679 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3680 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
3681 TargetLowering::CallLoweringInfo &CLI) const {
3682 // Assign locations to each value returned by this call.
3683 SmallVector<CCValAssign, 16> RVLocs;
3684 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
3685 *DAG.getContext());
3686
3687 const ExternalSymbolSDNode *ES =
3688 dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.Callee.getNode());
3689 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.RetTy,
3690 ES ? ES->getSymbol() : nullptr);
3691
3692 // Copy all of the result registers out of their specified physreg.
3693 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3694 CCValAssign &VA = RVLocs[i];
3695 assert(VA.isRegLoc() && "Can only return in registers!");
3696
3697 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
3698 RVLocs[i].getLocVT(), InGlue);
3699 Chain = Val.getValue(1);
3700 InGlue = Val.getValue(2);
3701
3702 if (VA.isUpperBitsInLoc()) {
3703 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits();
3704 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3705 unsigned Shift =
3706 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
3707 Val = DAG.getNode(
3708 Shift, DL, VA.getLocVT(), Val,
3709 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3710 }
3711
3712 switch (VA.getLocInfo()) {
3713 default:
3714 llvm_unreachable("Unknown loc info!");
3715 case CCValAssign::Full:
3716 break;
3717 case CCValAssign::BCvt:
3718 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
3719 break;
3720 case CCValAssign::AExt:
3721 case CCValAssign::AExtUpper:
3722 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3723 break;
3724 case CCValAssign::ZExt:
3725 case CCValAssign::ZExtUpper:
3726 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
3727 DAG.getValueType(VA.getValVT()));
3728 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3729 break;
3730 case CCValAssign::SExt:
3731 case CCValAssign::SExtUpper:
3732 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
3733 DAG.getValueType(VA.getValVT()));
3734 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3735 break;
3736 }
3737
3738 InVals.push_back(Val);
3739 }
3740
3741 return Chain;
3742 }
3743
UnpackFromArgumentSlot(SDValue Val,const CCValAssign & VA,EVT ArgVT,const SDLoc & DL,SelectionDAG & DAG)3744 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA,
3745 EVT ArgVT, const SDLoc &DL,
3746 SelectionDAG &DAG) {
3747 MVT LocVT = VA.getLocVT();
3748 EVT ValVT = VA.getValVT();
3749
3750 // Shift into the upper bits if necessary.
3751 switch (VA.getLocInfo()) {
3752 default:
3753 break;
3754 case CCValAssign::AExtUpper:
3755 case CCValAssign::SExtUpper:
3756 case CCValAssign::ZExtUpper: {
3757 unsigned ValSizeInBits = ArgVT.getSizeInBits();
3758 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3759 unsigned Opcode =
3760 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
3761 Val = DAG.getNode(
3762 Opcode, DL, VA.getLocVT(), Val,
3763 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3764 break;
3765 }
3766 }
3767
3768 // If this is an value smaller than the argument slot size (32-bit for O32,
3769 // 64-bit for N32/N64), it has been promoted in some way to the argument slot
3770 // size. Extract the value and insert any appropriate assertions regarding
3771 // sign/zero extension.
3772 switch (VA.getLocInfo()) {
3773 default:
3774 llvm_unreachable("Unknown loc info!");
3775 case CCValAssign::Full:
3776 break;
3777 case CCValAssign::AExtUpper:
3778 case CCValAssign::AExt:
3779 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3780 break;
3781 case CCValAssign::SExtUpper:
3782 case CCValAssign::SExt:
3783 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT));
3784 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3785 break;
3786 case CCValAssign::ZExtUpper:
3787 case CCValAssign::ZExt:
3788 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT));
3789 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3790 break;
3791 case CCValAssign::BCvt:
3792 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
3793 break;
3794 }
3795
3796 return Val;
3797 }
3798
3799 //===----------------------------------------------------------------------===//
3800 // Formal Arguments Calling Convention Implementation
3801 //===----------------------------------------------------------------------===//
3802 /// LowerFormalArguments - transform physical registers into virtual registers
3803 /// and generate load operations for arguments places on the stack.
LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const3804 SDValue MipsTargetLowering::LowerFormalArguments(
3805 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
3806 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3807 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3808 MachineFunction &MF = DAG.getMachineFunction();
3809 MachineFrameInfo &MFI = MF.getFrameInfo();
3810 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3811
3812 MipsFI->setVarArgsFrameIndex(0);
3813
3814 // Used with vargs to acumulate store chains.
3815 std::vector<SDValue> OutChains;
3816
3817 // Assign locations to all of the incoming arguments.
3818 SmallVector<CCValAssign, 16> ArgLocs;
3819 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
3820 *DAG.getContext());
3821 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), Align(1));
3822 const Function &Func = DAG.getMachineFunction().getFunction();
3823 Function::const_arg_iterator FuncArg = Func.arg_begin();
3824
3825 if (Func.hasFnAttribute("interrupt") && !Func.arg_empty())
3826 report_fatal_error(
3827 "Functions with the interrupt attribute cannot have arguments!");
3828
3829 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
3830 MipsFI->setFormalArgInfo(CCInfo.getStackSize(),
3831 CCInfo.getInRegsParamsCount() > 0);
3832
3833 unsigned CurArgIdx = 0;
3834 CCInfo.rewindByValRegsInfo();
3835
3836 for (unsigned i = 0, e = ArgLocs.size(), InsIdx = 0; i != e; ++i, ++InsIdx) {
3837 CCValAssign &VA = ArgLocs[i];
3838 if (Ins[InsIdx].isOrigArg()) {
3839 std::advance(FuncArg, Ins[InsIdx].getOrigArgIndex() - CurArgIdx);
3840 CurArgIdx = Ins[InsIdx].getOrigArgIndex();
3841 }
3842 EVT ValVT = VA.getValVT();
3843 ISD::ArgFlagsTy Flags = Ins[InsIdx].Flags;
3844 bool IsRegLoc = VA.isRegLoc();
3845
3846 if (Flags.isByVal()) {
3847 assert(Ins[InsIdx].isOrigArg() && "Byval arguments cannot be implicit");
3848 unsigned FirstByValReg, LastByValReg;
3849 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3850 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3851
3852 assert(Flags.getByValSize() &&
3853 "ByVal args of size 0 should have been ignored by front-end.");
3854 assert(ByValIdx < CCInfo.getInRegsParamsCount());
3855 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
3856 FirstByValReg, LastByValReg, VA, CCInfo);
3857 CCInfo.nextInRegsParam();
3858 continue;
3859 }
3860
3861 // Arguments stored on registers
3862 if (IsRegLoc) {
3863 MVT RegVT = VA.getLocVT();
3864 Register ArgReg = VA.getLocReg();
3865 const TargetRegisterClass *RC = getRegClassFor(RegVT);
3866
3867 // Transform the arguments stored on
3868 // physical registers into virtual ones
3869 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
3870 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
3871
3872 ArgValue =
3873 UnpackFromArgumentSlot(ArgValue, VA, Ins[InsIdx].ArgVT, DL, DAG);
3874
3875 // Handle floating point arguments passed in integer registers and
3876 // long double arguments passed in floating point registers.
3877 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3878 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3879 (RegVT == MVT::f64 && ValVT == MVT::i64))
3880 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
3881 else if (ABI.IsO32() && RegVT == MVT::i32 &&
3882 ValVT == MVT::f64) {
3883 assert(VA.needsCustom() && "Expected custom argument for f64 split");
3884 CCValAssign &NextVA = ArgLocs[++i];
3885 unsigned Reg2 =
3886 addLiveIn(DAG.getMachineFunction(), NextVA.getLocReg(), RC);
3887 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
3888 if (!Subtarget.isLittle())
3889 std::swap(ArgValue, ArgValue2);
3890 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
3891 ArgValue, ArgValue2);
3892 }
3893
3894 InVals.push_back(ArgValue);
3895 } else { // VA.isRegLoc()
3896 MVT LocVT = VA.getLocVT();
3897
3898 assert(!VA.needsCustom() && "unexpected custom memory argument");
3899
3900 // Only arguments pased on the stack should make it here.
3901 assert(VA.isMemLoc());
3902
3903 // The stack pointer offset is relative to the caller stack frame.
3904 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
3905 VA.getLocMemOffset(), true);
3906
3907 // Create load nodes to retrieve arguments from the stack
3908 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3909 SDValue ArgValue = DAG.getLoad(
3910 LocVT, DL, Chain, FIN,
3911 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3912 OutChains.push_back(ArgValue.getValue(1));
3913
3914 ArgValue =
3915 UnpackFromArgumentSlot(ArgValue, VA, Ins[InsIdx].ArgVT, DL, DAG);
3916
3917 InVals.push_back(ArgValue);
3918 }
3919 }
3920
3921 for (unsigned i = 0, e = ArgLocs.size(), InsIdx = 0; i != e; ++i, ++InsIdx) {
3922
3923 if (ArgLocs[i].needsCustom()) {
3924 ++i;
3925 continue;
3926 }
3927
3928 // The mips ABIs for returning structs by value requires that we copy
3929 // the sret argument into $v0 for the return. Save the argument into
3930 // a virtual register so that we can access it from the return points.
3931 if (Ins[InsIdx].Flags.isSRet()) {
3932 unsigned Reg = MipsFI->getSRetReturnReg();
3933 if (!Reg) {
3934 Reg = MF.getRegInfo().createVirtualRegister(
3935 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32));
3936 MipsFI->setSRetReturnReg(Reg);
3937 }
3938 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
3939 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
3940 break;
3941 }
3942 }
3943
3944 if (IsVarArg)
3945 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo);
3946
3947 // All stores are grouped in one node to allow the matching between
3948 // the size of Ins and InVals. This only happens when on varg functions
3949 if (!OutChains.empty()) {
3950 OutChains.push_back(Chain);
3951 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
3952 }
3953
3954 return Chain;
3955 }
3956
3957 //===----------------------------------------------------------------------===//
3958 // Return Value Calling Convention Implementation
3959 //===----------------------------------------------------------------------===//
3960
3961 bool
CanLowerReturn(CallingConv::ID CallConv,MachineFunction & MF,bool IsVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,LLVMContext & Context,const Type * RetTy) const3962 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3963 MachineFunction &MF, bool IsVarArg,
3964 const SmallVectorImpl<ISD::OutputArg> &Outs,
3965 LLVMContext &Context, const Type *RetTy) const {
3966 SmallVector<CCValAssign, 16> RVLocs;
3967 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3968 return CCInfo.CheckCallReturn(Outs, RetCC_Mips, RetTy);
3969 }
3970
shouldSignExtendTypeInLibCall(Type * Ty,bool IsSigned) const3971 bool MipsTargetLowering::shouldSignExtendTypeInLibCall(Type *Ty,
3972 bool IsSigned) const {
3973 if ((ABI.IsN32() || ABI.IsN64()) && Ty->isIntegerTy(32))
3974 return true;
3975
3976 return IsSigned;
3977 }
3978
3979 SDValue
LowerInterruptReturn(SmallVectorImpl<SDValue> & RetOps,const SDLoc & DL,SelectionDAG & DAG) const3980 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
3981 const SDLoc &DL,
3982 SelectionDAG &DAG) const {
3983 MachineFunction &MF = DAG.getMachineFunction();
3984 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3985
3986 MipsFI->setISR();
3987
3988 return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps);
3989 }
3990
3991 SDValue
LowerReturn(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,const SDLoc & DL,SelectionDAG & DAG) const3992 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3993 bool IsVarArg,
3994 const SmallVectorImpl<ISD::OutputArg> &Outs,
3995 const SmallVectorImpl<SDValue> &OutVals,
3996 const SDLoc &DL, SelectionDAG &DAG) const {
3997 // CCValAssign - represent the assignment of
3998 // the return value to a location
3999 SmallVector<CCValAssign, 16> RVLocs;
4000 MachineFunction &MF = DAG.getMachineFunction();
4001
4002 // CCState - Info about the registers and stack slot.
4003 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
4004
4005 // Analyze return values.
4006 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
4007
4008 SDValue Glue;
4009 SmallVector<SDValue, 4> RetOps(1, Chain);
4010
4011 // Copy the result values into the output registers.
4012 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4013 SDValue Val = OutVals[i];
4014 CCValAssign &VA = RVLocs[i];
4015 assert(VA.isRegLoc() && "Can only return in registers!");
4016 bool UseUpperBits = false;
4017
4018 switch (VA.getLocInfo()) {
4019 default:
4020 llvm_unreachable("Unknown loc info!");
4021 case CCValAssign::Full:
4022 break;
4023 case CCValAssign::BCvt:
4024 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val);
4025 break;
4026 case CCValAssign::AExtUpper:
4027 UseUpperBits = true;
4028 [[fallthrough]];
4029 case CCValAssign::AExt:
4030 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);
4031 break;
4032 case CCValAssign::ZExtUpper:
4033 UseUpperBits = true;
4034 [[fallthrough]];
4035 case CCValAssign::ZExt:
4036 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
4037 break;
4038 case CCValAssign::SExtUpper:
4039 UseUpperBits = true;
4040 [[fallthrough]];
4041 case CCValAssign::SExt:
4042 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
4043 break;
4044 }
4045
4046 if (UseUpperBits) {
4047 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
4048 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
4049 Val = DAG.getNode(
4050 ISD::SHL, DL, VA.getLocVT(), Val,
4051 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
4052 }
4053
4054 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue);
4055
4056 // Guarantee that all emitted copies are stuck together with flags.
4057 Glue = Chain.getValue(1);
4058 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4059 }
4060
4061 // The mips ABIs for returning structs by value requires that we copy
4062 // the sret argument into $v0 for the return. We saved the argument into
4063 // a virtual register in the entry block, so now we copy the value out
4064 // and into $v0.
4065 if (MF.getFunction().hasStructRetAttr()) {
4066 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
4067 unsigned Reg = MipsFI->getSRetReturnReg();
4068
4069 if (!Reg)
4070 llvm_unreachable("sret virtual register not created in the entry block");
4071 SDValue Val =
4072 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
4073 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
4074
4075 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Glue);
4076 Glue = Chain.getValue(1);
4077 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout())));
4078 }
4079
4080 RetOps[0] = Chain; // Update chain.
4081
4082 // Add the glue if we have it.
4083 if (Glue.getNode())
4084 RetOps.push_back(Glue);
4085
4086 // ISRs must use "eret".
4087 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt"))
4088 return LowerInterruptReturn(RetOps, DL, DAG);
4089
4090 // Standard return on Mips is a "jr $ra"
4091 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
4092 }
4093
4094 //===----------------------------------------------------------------------===//
4095 // Mips Inline Assembly Support
4096 //===----------------------------------------------------------------------===//
4097
4098 /// getConstraintType - Given a constraint letter, return the type of
4099 /// constraint it is for this target.
4100 MipsTargetLowering::ConstraintType
getConstraintType(StringRef Constraint) const4101 MipsTargetLowering::getConstraintType(StringRef Constraint) const {
4102 // Mips specific constraints
4103 // GCC config/mips/constraints.md
4104 //
4105 // 'd' : An address register. Equivalent to r
4106 // unless generating MIPS16 code.
4107 // 'y' : Equivalent to r; retained for
4108 // backwards compatibility.
4109 // 'c' : A register suitable for use in an indirect
4110 // jump. This will always be $25 for -mabicalls.
4111 // 'l' : The lo register. 1 word storage.
4112 // 'x' : The hilo register pair. Double word storage.
4113 if (Constraint.size() == 1) {
4114 switch (Constraint[0]) {
4115 default : break;
4116 case 'd':
4117 case 'y':
4118 case 'f':
4119 case 'c':
4120 case 'l':
4121 case 'x':
4122 return C_RegisterClass;
4123 case 'R':
4124 return C_Memory;
4125 }
4126 }
4127
4128 if (Constraint == "ZC")
4129 return C_Memory;
4130
4131 return TargetLowering::getConstraintType(Constraint);
4132 }
4133
4134 /// Examine constraint type and operand type and determine a weight value.
4135 /// This object must already have been set up with the operand type
4136 /// and the current alternative constraint selected.
4137 TargetLowering::ConstraintWeight
getSingleConstraintMatchWeight(AsmOperandInfo & info,const char * constraint) const4138 MipsTargetLowering::getSingleConstraintMatchWeight(
4139 AsmOperandInfo &info, const char *constraint) const {
4140 ConstraintWeight weight = CW_Invalid;
4141 Value *CallOperandVal = info.CallOperandVal;
4142 // If we don't have a value, we can't do a match,
4143 // but allow it at the lowest weight.
4144 if (!CallOperandVal)
4145 return CW_Default;
4146 Type *type = CallOperandVal->getType();
4147 // Look at the constraint type.
4148 switch (*constraint) {
4149 default:
4150 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
4151 break;
4152 case 'd':
4153 case 'y':
4154 if (type->isIntegerTy())
4155 weight = CW_Register;
4156 break;
4157 case 'f': // FPU or MSA register
4158 if (Subtarget.hasMSA() && type->isVectorTy() &&
4159 type->getPrimitiveSizeInBits().getFixedValue() == 128)
4160 weight = CW_Register;
4161 else if (type->isFloatTy())
4162 weight = CW_Register;
4163 break;
4164 case 'c': // $25 for indirect jumps
4165 case 'l': // lo register
4166 case 'x': // hilo register pair
4167 if (type->isIntegerTy())
4168 weight = CW_SpecificReg;
4169 break;
4170 case 'I': // signed 16 bit immediate
4171 case 'J': // integer zero
4172 case 'K': // unsigned 16 bit immediate
4173 case 'L': // signed 32 bit immediate where lower 16 bits are 0
4174 case 'N': // immediate in the range of -65535 to -1 (inclusive)
4175 case 'O': // signed 15 bit immediate (+- 16383)
4176 case 'P': // immediate in the range of 65535 to 1 (inclusive)
4177 if (isa<ConstantInt>(CallOperandVal))
4178 weight = CW_Constant;
4179 break;
4180 case 'R':
4181 weight = CW_Memory;
4182 break;
4183 }
4184 return weight;
4185 }
4186
4187 /// This is a helper function to parse a physical register string and split it
4188 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
4189 /// that is returned indicates whether parsing was successful. The second flag
4190 /// is true if the numeric part exists.
parsePhysicalReg(StringRef C,StringRef & Prefix,unsigned long long & Reg)4191 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,
4192 unsigned long long &Reg) {
4193 if (C.front() != '{' || C.back() != '}')
4194 return std::make_pair(false, false);
4195
4196 // Search for the first numeric character.
4197 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
4198 I = std::find_if(B, E, isdigit);
4199
4200 Prefix = StringRef(B, I - B);
4201
4202 // The second flag is set to false if no numeric characters were found.
4203 if (I == E)
4204 return std::make_pair(true, false);
4205
4206 // Parse the numeric characters.
4207 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
4208 true);
4209 }
4210
getTypeForExtReturn(LLVMContext & Context,EVT VT,ISD::NodeType) const4211 EVT MipsTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
4212 ISD::NodeType) const {
4213 bool Cond = !Subtarget.isABI_O32() && VT.getSizeInBits() == 32;
4214 EVT MinVT = getRegisterType(Cond ? MVT::i64 : MVT::i32);
4215 return VT.bitsLT(MinVT) ? MinVT : VT;
4216 }
4217
4218 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
parseRegForInlineAsmConstraint(StringRef C,MVT VT) const4219 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
4220 const TargetRegisterInfo *TRI =
4221 Subtarget.getRegisterInfo();
4222 const TargetRegisterClass *RC;
4223 StringRef Prefix;
4224 unsigned long long Reg;
4225
4226 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
4227
4228 if (!R.first)
4229 return std::make_pair(0U, nullptr);
4230
4231 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo.
4232 // No numeric characters follow "hi" or "lo".
4233 if (R.second)
4234 return std::make_pair(0U, nullptr);
4235
4236 RC = TRI->getRegClass(Prefix == "hi" ?
4237 Mips::HI32RegClassID : Mips::LO32RegClassID);
4238 return std::make_pair(*(RC->begin()), RC);
4239 } else if (Prefix.starts_with("$msa")) {
4240 // Parse $msa(ir|csr|access|save|modify|request|map|unmap)
4241
4242 // No numeric characters follow the name.
4243 if (R.second)
4244 return std::make_pair(0U, nullptr);
4245
4246 Reg = StringSwitch<unsigned long long>(Prefix)
4247 .Case("$msair", Mips::MSAIR)
4248 .Case("$msacsr", Mips::MSACSR)
4249 .Case("$msaaccess", Mips::MSAAccess)
4250 .Case("$msasave", Mips::MSASave)
4251 .Case("$msamodify", Mips::MSAModify)
4252 .Case("$msarequest", Mips::MSARequest)
4253 .Case("$msamap", Mips::MSAMap)
4254 .Case("$msaunmap", Mips::MSAUnmap)
4255 .Default(0);
4256
4257 if (!Reg)
4258 return std::make_pair(0U, nullptr);
4259
4260 RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
4261 return std::make_pair(Reg, RC);
4262 }
4263
4264 if (!R.second)
4265 return std::make_pair(0U, nullptr);
4266
4267 if (Prefix == "$f") { // Parse $f0-$f31.
4268 // If the size of FP registers is 64-bit or Reg is an even number, select
4269 // the 64-bit register class. Otherwise, select the 32-bit register class.
4270 if (VT == MVT::Other)
4271 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
4272
4273 RC = getRegClassFor(VT);
4274
4275 if (RC == &Mips::AFGR64RegClass) {
4276 assert(Reg % 2 == 0);
4277 Reg >>= 1;
4278 }
4279 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7.
4280 RC = TRI->getRegClass(Mips::FCCRegClassID);
4281 else if (Prefix == "$w") { // Parse $w0-$w31.
4282 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
4283 } else { // Parse $0-$31.
4284 assert(Prefix == "$");
4285 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
4286 }
4287
4288 assert(Reg < RC->getNumRegs());
4289 return std::make_pair(*(RC->begin() + Reg), RC);
4290 }
4291
4292 /// Given a register class constraint, like 'r', if this corresponds directly
4293 /// to an LLVM register class, return a register of 0 and the register class
4294 /// pointer.
4295 std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo * TRI,StringRef Constraint,MVT VT) const4296 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
4297 StringRef Constraint,
4298 MVT VT) const {
4299 if (Constraint.size() == 1) {
4300 switch (Constraint[0]) {
4301 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
4302 case 'y': // Same as 'r'. Exists for compatibility.
4303 case 'r':
4304 if ((VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 ||
4305 VT == MVT::i1) ||
4306 (VT == MVT::f32 && Subtarget.useSoftFloat())) {
4307 if (Subtarget.inMips16Mode())
4308 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
4309 return std::make_pair(0U, &Mips::GPR32RegClass);
4310 }
4311 if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
4312 !Subtarget.isGP64bit())
4313 return std::make_pair(0U, &Mips::GPR32RegClass);
4314 if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
4315 Subtarget.isGP64bit())
4316 return std::make_pair(0U, &Mips::GPR64RegClass);
4317 // This will generate an error message
4318 return std::make_pair(0U, nullptr);
4319 case 'f': // FPU or MSA register
4320 if (VT == MVT::v16i8)
4321 return std::make_pair(0U, &Mips::MSA128BRegClass);
4322 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
4323 return std::make_pair(0U, &Mips::MSA128HRegClass);
4324 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
4325 return std::make_pair(0U, &Mips::MSA128WRegClass);
4326 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
4327 return std::make_pair(0U, &Mips::MSA128DRegClass);
4328 else if (VT == MVT::f32)
4329 return std::make_pair(0U, &Mips::FGR32RegClass);
4330 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) {
4331 if (Subtarget.isFP64bit())
4332 return std::make_pair(0U, &Mips::FGR64RegClass);
4333 return std::make_pair(0U, &Mips::AFGR64RegClass);
4334 }
4335 break;
4336 case 'c': // register suitable for indirect jump
4337 if (VT == MVT::i32)
4338 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
4339 if (VT == MVT::i64)
4340 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
4341 // This will generate an error message
4342 return std::make_pair(0U, nullptr);
4343 case 'l': // use the `lo` register to store values
4344 // that are no bigger than a word
4345 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
4346 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
4347 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
4348 case 'x': // use the concatenated `hi` and `lo` registers
4349 // to store doubleword values
4350 // Fixme: Not triggering the use of both hi and low
4351 // This will generate an error message
4352 return std::make_pair(0U, nullptr);
4353 }
4354 }
4355
4356 if (!Constraint.empty()) {
4357 std::pair<unsigned, const TargetRegisterClass *> R;
4358 R = parseRegForInlineAsmConstraint(Constraint, VT);
4359
4360 if (R.second)
4361 return R;
4362 }
4363
4364 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
4365 }
4366
4367 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4368 /// vector. If it is invalid, don't add anything to Ops.
LowerAsmOperandForConstraint(SDValue Op,StringRef Constraint,std::vector<SDValue> & Ops,SelectionDAG & DAG) const4369 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
4370 StringRef Constraint,
4371 std::vector<SDValue> &Ops,
4372 SelectionDAG &DAG) const {
4373 SDLoc DL(Op);
4374 SDValue Result;
4375
4376 // Only support length 1 constraints for now.
4377 if (Constraint.size() > 1)
4378 return;
4379
4380 char ConstraintLetter = Constraint[0];
4381 switch (ConstraintLetter) {
4382 default: break; // This will fall through to the generic implementation
4383 case 'I': // Signed 16 bit constant
4384 // If this fails, the parent routine will give an error
4385 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4386 EVT Type = Op.getValueType();
4387 int64_t Val = C->getSExtValue();
4388 if (isInt<16>(Val)) {
4389 Result = DAG.getSignedTargetConstant(Val, DL, Type);
4390 break;
4391 }
4392 }
4393 return;
4394 case 'J': // integer zero
4395 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4396 EVT Type = Op.getValueType();
4397 int64_t Val = C->getZExtValue();
4398 if (Val == 0) {
4399 Result = DAG.getTargetConstant(0, DL, Type);
4400 break;
4401 }
4402 }
4403 return;
4404 case 'K': // unsigned 16 bit immediate
4405 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4406 EVT Type = Op.getValueType();
4407 uint64_t Val = (uint64_t)C->getZExtValue();
4408 if (isUInt<16>(Val)) {
4409 Result = DAG.getTargetConstant(Val, DL, Type);
4410 break;
4411 }
4412 }
4413 return;
4414 case 'L': // signed 32 bit immediate where lower 16 bits are 0
4415 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4416 EVT Type = Op.getValueType();
4417 int64_t Val = C->getSExtValue();
4418 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
4419 Result = DAG.getSignedTargetConstant(Val, DL, Type);
4420 break;
4421 }
4422 }
4423 return;
4424 case 'N': // immediate in the range of -65535 to -1 (inclusive)
4425 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4426 EVT Type = Op.getValueType();
4427 int64_t Val = C->getSExtValue();
4428 if ((Val >= -65535) && (Val <= -1)) {
4429 Result = DAG.getSignedTargetConstant(Val, DL, Type);
4430 break;
4431 }
4432 }
4433 return;
4434 case 'O': // signed 15 bit immediate
4435 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4436 EVT Type = Op.getValueType();
4437 int64_t Val = C->getSExtValue();
4438 if ((isInt<15>(Val))) {
4439 Result = DAG.getSignedTargetConstant(Val, DL, Type);
4440 break;
4441 }
4442 }
4443 return;
4444 case 'P': // immediate in the range of 1 to 65535 (inclusive)
4445 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4446 EVT Type = Op.getValueType();
4447 int64_t Val = C->getSExtValue();
4448 if ((Val <= 65535) && (Val >= 1)) {
4449 Result = DAG.getTargetConstant(Val, DL, Type);
4450 break;
4451 }
4452 }
4453 return;
4454 }
4455
4456 if (Result.getNode()) {
4457 Ops.push_back(Result);
4458 return;
4459 }
4460
4461 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4462 }
4463
isLegalAddressingMode(const DataLayout & DL,const AddrMode & AM,Type * Ty,unsigned AS,Instruction * I) const4464 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL,
4465 const AddrMode &AM, Type *Ty,
4466 unsigned AS,
4467 Instruction *I) const {
4468 // No global is ever allowed as a base.
4469 if (AM.BaseGV)
4470 return false;
4471
4472 switch (AM.Scale) {
4473 case 0: // "r+i" or just "i", depending on HasBaseReg.
4474 break;
4475 case 1:
4476 if (!AM.HasBaseReg) // allow "r+i".
4477 break;
4478 return false; // disallow "r+r" or "r+r+i".
4479 default:
4480 return false;
4481 }
4482
4483 return true;
4484 }
4485
4486 bool
isOffsetFoldingLegal(const GlobalAddressSDNode * GA) const4487 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4488 // The Mips target isn't yet aware of offsets.
4489 return false;
4490 }
4491
getOptimalMemOpType(LLVMContext & Context,const MemOp & Op,const AttributeList & FuncAttributes) const4492 EVT MipsTargetLowering::getOptimalMemOpType(
4493 LLVMContext &Context, const MemOp &Op,
4494 const AttributeList &FuncAttributes) const {
4495 if (Subtarget.hasMips64())
4496 return MVT::i64;
4497
4498 return MVT::i32;
4499 }
4500
isFPImmLegal(const APFloat & Imm,EVT VT,bool ForCodeSize) const4501 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
4502 bool ForCodeSize) const {
4503 if (VT != MVT::f32 && VT != MVT::f64)
4504 return false;
4505 if (Imm.isNegZero())
4506 return false;
4507 return Imm.isZero();
4508 }
4509
isLegalICmpImmediate(int64_t Imm) const4510 bool MipsTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
4511 return isInt<16>(Imm);
4512 }
4513
isLegalAddImmediate(int64_t Imm) const4514 bool MipsTargetLowering::isLegalAddImmediate(int64_t Imm) const {
4515 return isInt<16>(Imm);
4516 }
4517
getJumpTableEncoding() const4518 unsigned MipsTargetLowering::getJumpTableEncoding() const {
4519 if (!isPositionIndependent())
4520 return MachineJumpTableInfo::EK_BlockAddress;
4521 if (ABI.IsN64())
4522 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
4523 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
4524 }
4525
getPICJumpTableRelocBase(SDValue Table,SelectionDAG & DAG) const4526 SDValue MipsTargetLowering::getPICJumpTableRelocBase(SDValue Table,
4527 SelectionDAG &DAG) const {
4528 if (!isPositionIndependent())
4529 return Table;
4530 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(DAG.getDataLayout()));
4531 }
4532
useSoftFloat() const4533 bool MipsTargetLowering::useSoftFloat() const {
4534 return Subtarget.useSoftFloat();
4535 }
4536
copyByValRegs(SDValue Chain,const SDLoc & DL,std::vector<SDValue> & OutChains,SelectionDAG & DAG,const ISD::ArgFlagsTy & Flags,SmallVectorImpl<SDValue> & InVals,const Argument * FuncArg,unsigned FirstReg,unsigned LastReg,const CCValAssign & VA,MipsCCState & State) const4537 void MipsTargetLowering::copyByValRegs(
4538 SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains,
4539 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
4540 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
4541 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA,
4542 MipsCCState &State) const {
4543 MachineFunction &MF = DAG.getMachineFunction();
4544 MachineFrameInfo &MFI = MF.getFrameInfo();
4545 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes();
4546 unsigned NumRegs = LastReg - FirstReg;
4547 unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
4548 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
4549 int FrameObjOffset;
4550 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs();
4551
4552 if (RegAreaSize)
4553 FrameObjOffset =
4554 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
4555 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes);
4556 else
4557 FrameObjOffset = VA.getLocMemOffset();
4558
4559 // Create frame object.
4560 EVT PtrTy = getPointerTy(DAG.getDataLayout());
4561 // Make the fixed object stored to mutable so that the load instructions
4562 // referencing it have their memory dependencies added.
4563 // Set the frame object as isAliased which clears the underlying objects
4564 // vector in ScheduleDAGInstrs::buildSchedGraph() resulting in addition of all
4565 // stores as dependencies for loads referencing this fixed object.
4566 int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, false, true);
4567 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4568 InVals.push_back(FIN);
4569
4570 if (!NumRegs)
4571 return;
4572
4573 // Copy arg registers.
4574 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8);
4575 const TargetRegisterClass *RC = getRegClassFor(RegTy);
4576
4577 for (unsigned I = 0; I < NumRegs; ++I) {
4578 unsigned ArgReg = ByValArgRegs[FirstReg + I];
4579 unsigned VReg = addLiveIn(MF, ArgReg, RC);
4580 unsigned Offset = I * GPRSizeInBytes;
4581 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
4582 DAG.getConstant(Offset, DL, PtrTy));
4583 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
4584 StorePtr, MachinePointerInfo(FuncArg, Offset));
4585 OutChains.push_back(Store);
4586 }
4587 }
4588
4589 // Copy byVal arg to registers and stack.
passByValArg(SDValue Chain,const SDLoc & DL,std::deque<std::pair<unsigned,SDValue>> & RegsToPass,SmallVectorImpl<SDValue> & MemOpChains,SDValue StackPtr,MachineFrameInfo & MFI,SelectionDAG & DAG,SDValue Arg,unsigned FirstReg,unsigned LastReg,const ISD::ArgFlagsTy & Flags,bool isLittle,const CCValAssign & VA) const4590 void MipsTargetLowering::passByValArg(
4591 SDValue Chain, const SDLoc &DL,
4592 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
4593 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
4594 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
4595 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle,
4596 const CCValAssign &VA) const {
4597 unsigned ByValSizeInBytes = Flags.getByValSize();
4598 unsigned OffsetInBytes = 0; // From beginning of struct
4599 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4600 Align Alignment =
4601 std::min(Flags.getNonZeroByValAlign(), Align(RegSizeInBytes));
4602 EVT PtrTy = getPointerTy(DAG.getDataLayout()),
4603 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
4604 unsigned NumRegs = LastReg - FirstReg;
4605
4606 if (NumRegs) {
4607 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs();
4608 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
4609 unsigned I = 0;
4610
4611 // Copy words to registers.
4612 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) {
4613 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4614 DAG.getConstant(OffsetInBytes, DL, PtrTy));
4615 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
4616 MachinePointerInfo(), Alignment);
4617 MemOpChains.push_back(LoadVal.getValue(1));
4618 unsigned ArgReg = ArgRegs[FirstReg + I];
4619 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
4620 }
4621
4622 // Return if the struct has been fully copied.
4623 if (ByValSizeInBytes == OffsetInBytes)
4624 return;
4625
4626 // Copy the remainder of the byval argument with sub-word loads and shifts.
4627 if (LeftoverBytes) {
4628 SDValue Val;
4629
4630 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
4631 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
4632 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
4633
4634 if (RemainingSizeInBytes < LoadSizeInBytes)
4635 continue;
4636
4637 // Load subword.
4638 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4639 DAG.getConstant(OffsetInBytes, DL,
4640 PtrTy));
4641 SDValue LoadVal = DAG.getExtLoad(
4642 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
4643 MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment);
4644 MemOpChains.push_back(LoadVal.getValue(1));
4645
4646 // Shift the loaded value.
4647 unsigned Shamt;
4648
4649 if (isLittle)
4650 Shamt = TotalBytesLoaded * 8;
4651 else
4652 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
4653
4654 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
4655 DAG.getConstant(Shamt, DL, MVT::i32));
4656
4657 if (Val.getNode())
4658 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
4659 else
4660 Val = Shift;
4661
4662 OffsetInBytes += LoadSizeInBytes;
4663 TotalBytesLoaded += LoadSizeInBytes;
4664 Alignment = std::min(Alignment, Align(LoadSizeInBytes));
4665 }
4666
4667 unsigned ArgReg = ArgRegs[FirstReg + I];
4668 RegsToPass.push_back(std::make_pair(ArgReg, Val));
4669 return;
4670 }
4671 }
4672
4673 // Copy remainder of byval arg to it with memcpy.
4674 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
4675 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4676 DAG.getConstant(OffsetInBytes, DL, PtrTy));
4677 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
4678 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
4679 Chain = DAG.getMemcpy(
4680 Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, DL, PtrTy),
4681 Align(Alignment), /*isVolatile=*/false, /*AlwaysInline=*/false,
4682 /*CI=*/nullptr, std::nullopt, MachinePointerInfo(), MachinePointerInfo());
4683 MemOpChains.push_back(Chain);
4684 }
4685
writeVarArgRegs(std::vector<SDValue> & OutChains,SDValue Chain,const SDLoc & DL,SelectionDAG & DAG,CCState & State) const4686 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
4687 SDValue Chain, const SDLoc &DL,
4688 SelectionDAG &DAG,
4689 CCState &State) const {
4690 ArrayRef<MCPhysReg> ArgRegs = ABI.getVarArgRegs(Subtarget.isGP64bit());
4691 unsigned Idx = State.getFirstUnallocated(ArgRegs);
4692 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4693 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
4694 const TargetRegisterClass *RC = getRegClassFor(RegTy);
4695 MachineFunction &MF = DAG.getMachineFunction();
4696 MachineFrameInfo &MFI = MF.getFrameInfo();
4697 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
4698
4699 // Offset of the first variable argument from stack pointer.
4700 int VaArgOffset;
4701
4702 if (ArgRegs.size() == Idx)
4703 VaArgOffset = alignTo(State.getStackSize(), RegSizeInBytes);
4704 else {
4705 VaArgOffset =
4706 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
4707 (int)(RegSizeInBytes * (ArgRegs.size() - Idx));
4708 }
4709
4710 // Record the frame index of the first variable argument
4711 // which is a value necessary to VASTART.
4712 int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
4713 MipsFI->setVarArgsFrameIndex(FI);
4714
4715 // Copy the integer registers that have not been used for argument passing
4716 // to the argument register save area. For O32, the save area is allocated
4717 // in the caller's stack frame, while for N32/64, it is allocated in the
4718 // callee's stack frame.
4719 for (unsigned I = Idx; I < ArgRegs.size();
4720 ++I, VaArgOffset += RegSizeInBytes) {
4721 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
4722 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
4723 FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
4724 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
4725 SDValue Store =
4726 DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo());
4727 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(
4728 (Value *)nullptr);
4729 OutChains.push_back(Store);
4730 }
4731 }
4732
HandleByVal(CCState * State,unsigned & Size,Align Alignment) const4733 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size,
4734 Align Alignment) const {
4735 const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
4736
4737 assert(Size && "Byval argument's size shouldn't be 0.");
4738
4739 Alignment = std::min(Alignment, TFL->getStackAlign());
4740
4741 unsigned FirstReg = 0;
4742 unsigned NumRegs = 0;
4743
4744 if (State->getCallingConv() != CallingConv::Fast) {
4745 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4746 ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs();
4747 // FIXME: The O32 case actually describes no shadow registers.
4748 const MCPhysReg *ShadowRegs =
4749 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs;
4750
4751 // We used to check the size as well but we can't do that anymore since
4752 // CCState::HandleByVal() rounds up the size after calling this function.
4753 assert(
4754 Alignment >= Align(RegSizeInBytes) &&
4755 "Byval argument's alignment should be a multiple of RegSizeInBytes.");
4756
4757 FirstReg = State->getFirstUnallocated(IntArgRegs);
4758
4759 // If Alignment > RegSizeInBytes, the first arg register must be even.
4760 // FIXME: This condition happens to do the right thing but it's not the
4761 // right way to test it. We want to check that the stack frame offset
4762 // of the register is aligned.
4763 if ((Alignment > RegSizeInBytes) && (FirstReg % 2)) {
4764 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
4765 ++FirstReg;
4766 }
4767
4768 // Mark the registers allocated.
4769 Size = alignTo(Size, RegSizeInBytes);
4770 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size());
4771 Size -= RegSizeInBytes, ++I, ++NumRegs)
4772 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]);
4773 }
4774
4775 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs);
4776 }
4777
emitPseudoSELECT(MachineInstr & MI,MachineBasicBlock * BB,bool isFPCmp,unsigned Opc) const4778 MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI,
4779 MachineBasicBlock *BB,
4780 bool isFPCmp,
4781 unsigned Opc) const {
4782 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
4783 "Subtarget already supports SELECT nodes with the use of"
4784 "conditional-move instructions.");
4785
4786 const TargetInstrInfo *TII =
4787 Subtarget.getInstrInfo();
4788 DebugLoc DL = MI.getDebugLoc();
4789
4790 // To "insert" a SELECT instruction, we actually have to insert the
4791 // diamond control-flow pattern. The incoming instruction knows the
4792 // destination vreg to set, the condition code register to branch on, the
4793 // true/false values to select between, and a branch opcode to use.
4794 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4795 MachineFunction::iterator It = ++BB->getIterator();
4796
4797 // thisMBB:
4798 // ...
4799 // TrueVal = ...
4800 // setcc r1, r2, r3
4801 // bNE r1, r0, copy1MBB
4802 // fallthrough --> copy0MBB
4803 MachineBasicBlock *thisMBB = BB;
4804 MachineFunction *F = BB->getParent();
4805 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4806 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4807 F->insert(It, copy0MBB);
4808 F->insert(It, sinkMBB);
4809
4810 // Transfer the remainder of BB and its successor edges to sinkMBB.
4811 sinkMBB->splice(sinkMBB->begin(), BB,
4812 std::next(MachineBasicBlock::iterator(MI)), BB->end());
4813 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4814
4815 // Next, add the true and fallthrough blocks as its successors.
4816 BB->addSuccessor(copy0MBB);
4817 BB->addSuccessor(sinkMBB);
4818
4819 if (isFPCmp) {
4820 // bc1[tf] cc, sinkMBB
4821 BuildMI(BB, DL, TII->get(Opc))
4822 .addReg(MI.getOperand(1).getReg())
4823 .addMBB(sinkMBB);
4824 } else {
4825 // bne rs, $0, sinkMBB
4826 BuildMI(BB, DL, TII->get(Opc))
4827 .addReg(MI.getOperand(1).getReg())
4828 .addReg(Mips::ZERO)
4829 .addMBB(sinkMBB);
4830 }
4831
4832 // copy0MBB:
4833 // %FalseValue = ...
4834 // # fallthrough to sinkMBB
4835 BB = copy0MBB;
4836
4837 // Update machine-CFG edges
4838 BB->addSuccessor(sinkMBB);
4839
4840 // sinkMBB:
4841 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
4842 // ...
4843 BB = sinkMBB;
4844
4845 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4846 .addReg(MI.getOperand(2).getReg())
4847 .addMBB(thisMBB)
4848 .addReg(MI.getOperand(3).getReg())
4849 .addMBB(copy0MBB);
4850
4851 MI.eraseFromParent(); // The pseudo instruction is gone now.
4852
4853 return BB;
4854 }
4855
4856 MachineBasicBlock *
emitPseudoD_SELECT(MachineInstr & MI,MachineBasicBlock * BB) const4857 MipsTargetLowering::emitPseudoD_SELECT(MachineInstr &MI,
4858 MachineBasicBlock *BB) const {
4859 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
4860 "Subtarget already supports SELECT nodes with the use of"
4861 "conditional-move instructions.");
4862
4863 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
4864 DebugLoc DL = MI.getDebugLoc();
4865
4866 // D_SELECT substitutes two SELECT nodes that goes one after another and
4867 // have the same condition operand. On machines which don't have
4868 // conditional-move instruction, it reduces unnecessary branch instructions
4869 // which are result of using two diamond patterns that are result of two
4870 // SELECT pseudo instructions.
4871 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4872 MachineFunction::iterator It = ++BB->getIterator();
4873
4874 // thisMBB:
4875 // ...
4876 // TrueVal = ...
4877 // setcc r1, r2, r3
4878 // bNE r1, r0, copy1MBB
4879 // fallthrough --> copy0MBB
4880 MachineBasicBlock *thisMBB = BB;
4881 MachineFunction *F = BB->getParent();
4882 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4883 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4884 F->insert(It, copy0MBB);
4885 F->insert(It, sinkMBB);
4886
4887 // Transfer the remainder of BB and its successor edges to sinkMBB.
4888 sinkMBB->splice(sinkMBB->begin(), BB,
4889 std::next(MachineBasicBlock::iterator(MI)), BB->end());
4890 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4891
4892 // Next, add the true and fallthrough blocks as its successors.
4893 BB->addSuccessor(copy0MBB);
4894 BB->addSuccessor(sinkMBB);
4895
4896 // bne rs, $0, sinkMBB
4897 BuildMI(BB, DL, TII->get(Mips::BNE))
4898 .addReg(MI.getOperand(2).getReg())
4899 .addReg(Mips::ZERO)
4900 .addMBB(sinkMBB);
4901
4902 // copy0MBB:
4903 // %FalseValue = ...
4904 // # fallthrough to sinkMBB
4905 BB = copy0MBB;
4906
4907 // Update machine-CFG edges
4908 BB->addSuccessor(sinkMBB);
4909
4910 // sinkMBB:
4911 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
4912 // ...
4913 BB = sinkMBB;
4914
4915 // Use two PHI nodes to select two reults
4916 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4917 .addReg(MI.getOperand(3).getReg())
4918 .addMBB(thisMBB)
4919 .addReg(MI.getOperand(5).getReg())
4920 .addMBB(copy0MBB);
4921 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(1).getReg())
4922 .addReg(MI.getOperand(4).getReg())
4923 .addMBB(thisMBB)
4924 .addReg(MI.getOperand(6).getReg())
4925 .addMBB(copy0MBB);
4926
4927 MI.eraseFromParent(); // The pseudo instruction is gone now.
4928
4929 return BB;
4930 }
4931
4932 // FIXME? Maybe this could be a TableGen attribute on some registers and
4933 // this table could be generated automatically from RegInfo.
4934 Register
getRegisterByName(const char * RegName,LLT VT,const MachineFunction & MF) const4935 MipsTargetLowering::getRegisterByName(const char *RegName, LLT VT,
4936 const MachineFunction &MF) const {
4937 // The Linux kernel uses $28 and sp.
4938 if (Subtarget.isGP64bit()) {
4939 Register Reg = StringSwitch<Register>(RegName)
4940 .Case("$28", Mips::GP_64)
4941 .Case("sp", Mips::SP_64)
4942 .Default(Register());
4943 return Reg;
4944 }
4945
4946 Register Reg = StringSwitch<Register>(RegName)
4947 .Case("$28", Mips::GP)
4948 .Case("sp", Mips::SP)
4949 .Default(Register());
4950 return Reg;
4951 }
4952
emitLDR_W(MachineInstr & MI,MachineBasicBlock * BB) const4953 MachineBasicBlock *MipsTargetLowering::emitLDR_W(MachineInstr &MI,
4954 MachineBasicBlock *BB) const {
4955 MachineFunction *MF = BB->getParent();
4956 MachineRegisterInfo &MRI = MF->getRegInfo();
4957 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
4958 const bool IsLittle = Subtarget.isLittle();
4959 DebugLoc DL = MI.getDebugLoc();
4960
4961 Register Dest = MI.getOperand(0).getReg();
4962 Register Address = MI.getOperand(1).getReg();
4963 unsigned Imm = MI.getOperand(2).getImm();
4964
4965 MachineBasicBlock::iterator I(MI);
4966
4967 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) {
4968 // Mips release 6 can load from adress that is not naturally-aligned.
4969 Register Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
4970 BuildMI(*BB, I, DL, TII->get(Mips::LW))
4971 .addDef(Temp)
4972 .addUse(Address)
4973 .addImm(Imm);
4974 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(Temp);
4975 } else {
4976 // Mips release 5 needs to use instructions that can load from an unaligned
4977 // memory address.
4978 Register LoadHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass);
4979 Register LoadFull = MRI.createVirtualRegister(&Mips::GPR32RegClass);
4980 Register Undef = MRI.createVirtualRegister(&Mips::GPR32RegClass);
4981 BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(Undef);
4982 BuildMI(*BB, I, DL, TII->get(Mips::LWR))
4983 .addDef(LoadHalf)
4984 .addUse(Address)
4985 .addImm(Imm + (IsLittle ? 0 : 3))
4986 .addUse(Undef);
4987 BuildMI(*BB, I, DL, TII->get(Mips::LWL))
4988 .addDef(LoadFull)
4989 .addUse(Address)
4990 .addImm(Imm + (IsLittle ? 3 : 0))
4991 .addUse(LoadHalf);
4992 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(LoadFull);
4993 }
4994
4995 MI.eraseFromParent();
4996 return BB;
4997 }
4998
emitLDR_D(MachineInstr & MI,MachineBasicBlock * BB) const4999 MachineBasicBlock *MipsTargetLowering::emitLDR_D(MachineInstr &MI,
5000 MachineBasicBlock *BB) const {
5001 MachineFunction *MF = BB->getParent();
5002 MachineRegisterInfo &MRI = MF->getRegInfo();
5003 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
5004 const bool IsLittle = Subtarget.isLittle();
5005 DebugLoc DL = MI.getDebugLoc();
5006
5007 Register Dest = MI.getOperand(0).getReg();
5008 Register Address = MI.getOperand(1).getReg();
5009 unsigned Imm = MI.getOperand(2).getImm();
5010
5011 MachineBasicBlock::iterator I(MI);
5012
5013 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) {
5014 // Mips release 6 can load from adress that is not naturally-aligned.
5015 if (Subtarget.isGP64bit()) {
5016 Register Temp = MRI.createVirtualRegister(&Mips::GPR64RegClass);
5017 BuildMI(*BB, I, DL, TII->get(Mips::LD))
5018 .addDef(Temp)
5019 .addUse(Address)
5020 .addImm(Imm);
5021 BuildMI(*BB, I, DL, TII->get(Mips::FILL_D)).addDef(Dest).addUse(Temp);
5022 } else {
5023 Register Wtemp = MRI.createVirtualRegister(&Mips::MSA128WRegClass);
5024 Register Lo = MRI.createVirtualRegister(&Mips::GPR32RegClass);
5025 Register Hi = MRI.createVirtualRegister(&Mips::GPR32RegClass);
5026 BuildMI(*BB, I, DL, TII->get(Mips::LW))
5027 .addDef(Lo)
5028 .addUse(Address)
5029 .addImm(Imm + (IsLittle ? 0 : 4));
5030 BuildMI(*BB, I, DL, TII->get(Mips::LW))
5031 .addDef(Hi)
5032 .addUse(Address)
5033 .addImm(Imm + (IsLittle ? 4 : 0));
5034 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Wtemp).addUse(Lo);
5035 BuildMI(*BB, I, DL, TII->get(Mips::INSERT_W), Dest)
5036 .addUse(Wtemp)
5037 .addUse(Hi)
5038 .addImm(1);
5039 }
5040 } else {
5041 // Mips release 5 needs to use instructions that can load from an unaligned
5042 // memory address.
5043 Register LoHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass);
5044 Register LoFull = MRI.createVirtualRegister(&Mips::GPR32RegClass);
5045 Register LoUndef = MRI.createVirtualRegister(&Mips::GPR32RegClass);
5046 Register HiHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass);
5047 Register HiFull = MRI.createVirtualRegister(&Mips::GPR32RegClass);
5048 Register HiUndef = MRI.createVirtualRegister(&Mips::GPR32RegClass);
5049 Register Wtemp = MRI.createVirtualRegister(&Mips::MSA128WRegClass);
5050 BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(LoUndef);
5051 BuildMI(*BB, I, DL, TII->get(Mips::LWR))
5052 .addDef(LoHalf)
5053 .addUse(Address)
5054 .addImm(Imm + (IsLittle ? 0 : 7))
5055 .addUse(LoUndef);
5056 BuildMI(*BB, I, DL, TII->get(Mips::LWL))
5057 .addDef(LoFull)
5058 .addUse(Address)
5059 .addImm(Imm + (IsLittle ? 3 : 4))
5060 .addUse(LoHalf);
5061 BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(HiUndef);
5062 BuildMI(*BB, I, DL, TII->get(Mips::LWR))
5063 .addDef(HiHalf)
5064 .addUse(Address)
5065 .addImm(Imm + (IsLittle ? 4 : 3))
5066 .addUse(HiUndef);
5067 BuildMI(*BB, I, DL, TII->get(Mips::LWL))
5068 .addDef(HiFull)
5069 .addUse(Address)
5070 .addImm(Imm + (IsLittle ? 7 : 0))
5071 .addUse(HiHalf);
5072 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Wtemp).addUse(LoFull);
5073 BuildMI(*BB, I, DL, TII->get(Mips::INSERT_W), Dest)
5074 .addUse(Wtemp)
5075 .addUse(HiFull)
5076 .addImm(1);
5077 }
5078
5079 MI.eraseFromParent();
5080 return BB;
5081 }
5082
emitSTR_W(MachineInstr & MI,MachineBasicBlock * BB) const5083 MachineBasicBlock *MipsTargetLowering::emitSTR_W(MachineInstr &MI,
5084 MachineBasicBlock *BB) const {
5085 MachineFunction *MF = BB->getParent();
5086 MachineRegisterInfo &MRI = MF->getRegInfo();
5087 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
5088 const bool IsLittle = Subtarget.isLittle();
5089 DebugLoc DL = MI.getDebugLoc();
5090
5091 Register StoreVal = MI.getOperand(0).getReg();
5092 Register Address = MI.getOperand(1).getReg();
5093 unsigned Imm = MI.getOperand(2).getImm();
5094
5095 MachineBasicBlock::iterator I(MI);
5096
5097 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) {
5098 // Mips release 6 can store to adress that is not naturally-aligned.
5099 Register BitcastW = MRI.createVirtualRegister(&Mips::MSA128WRegClass);
5100 Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
5101 BuildMI(*BB, I, DL, TII->get(Mips::COPY)).addDef(BitcastW).addUse(StoreVal);
5102 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W))
5103 .addDef(Tmp)
5104 .addUse(BitcastW)
5105 .addImm(0);
5106 BuildMI(*BB, I, DL, TII->get(Mips::SW))
5107 .addUse(Tmp)
5108 .addUse(Address)
5109 .addImm(Imm);
5110 } else {
5111 // Mips release 5 needs to use instructions that can store to an unaligned
5112 // memory address.
5113 Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
5114 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W))
5115 .addDef(Tmp)
5116 .addUse(StoreVal)
5117 .addImm(0);
5118 BuildMI(*BB, I, DL, TII->get(Mips::SWR))
5119 .addUse(Tmp)
5120 .addUse(Address)
5121 .addImm(Imm + (IsLittle ? 0 : 3));
5122 BuildMI(*BB, I, DL, TII->get(Mips::SWL))
5123 .addUse(Tmp)
5124 .addUse(Address)
5125 .addImm(Imm + (IsLittle ? 3 : 0));
5126 }
5127
5128 MI.eraseFromParent();
5129
5130 return BB;
5131 }
5132
emitSTR_D(MachineInstr & MI,MachineBasicBlock * BB) const5133 MachineBasicBlock *MipsTargetLowering::emitSTR_D(MachineInstr &MI,
5134 MachineBasicBlock *BB) const {
5135 MachineFunction *MF = BB->getParent();
5136 MachineRegisterInfo &MRI = MF->getRegInfo();
5137 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
5138 const bool IsLittle = Subtarget.isLittle();
5139 DebugLoc DL = MI.getDebugLoc();
5140
5141 Register StoreVal = MI.getOperand(0).getReg();
5142 Register Address = MI.getOperand(1).getReg();
5143 unsigned Imm = MI.getOperand(2).getImm();
5144
5145 MachineBasicBlock::iterator I(MI);
5146
5147 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) {
5148 // Mips release 6 can store to adress that is not naturally-aligned.
5149 if (Subtarget.isGP64bit()) {
5150 Register BitcastD = MRI.createVirtualRegister(&Mips::MSA128DRegClass);
5151 Register Lo = MRI.createVirtualRegister(&Mips::GPR64RegClass);
5152 BuildMI(*BB, I, DL, TII->get(Mips::COPY))
5153 .addDef(BitcastD)
5154 .addUse(StoreVal);
5155 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_D))
5156 .addDef(Lo)
5157 .addUse(BitcastD)
5158 .addImm(0);
5159 BuildMI(*BB, I, DL, TII->get(Mips::SD))
5160 .addUse(Lo)
5161 .addUse(Address)
5162 .addImm(Imm);
5163 } else {
5164 Register BitcastW = MRI.createVirtualRegister(&Mips::MSA128WRegClass);
5165 Register Lo = MRI.createVirtualRegister(&Mips::GPR32RegClass);
5166 Register Hi = MRI.createVirtualRegister(&Mips::GPR32RegClass);
5167 BuildMI(*BB, I, DL, TII->get(Mips::COPY))
5168 .addDef(BitcastW)
5169 .addUse(StoreVal);
5170 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W))
5171 .addDef(Lo)
5172 .addUse(BitcastW)
5173 .addImm(0);
5174 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W))
5175 .addDef(Hi)
5176 .addUse(BitcastW)
5177 .addImm(1);
5178 BuildMI(*BB, I, DL, TII->get(Mips::SW))
5179 .addUse(Lo)
5180 .addUse(Address)
5181 .addImm(Imm + (IsLittle ? 0 : 4));
5182 BuildMI(*BB, I, DL, TII->get(Mips::SW))
5183 .addUse(Hi)
5184 .addUse(Address)
5185 .addImm(Imm + (IsLittle ? 4 : 0));
5186 }
5187 } else {
5188 // Mips release 5 needs to use instructions that can store to an unaligned
5189 // memory address.
5190 Register Bitcast = MRI.createVirtualRegister(&Mips::MSA128WRegClass);
5191 Register Lo = MRI.createVirtualRegister(&Mips::GPR32RegClass);
5192 Register Hi = MRI.createVirtualRegister(&Mips::GPR32RegClass);
5193 BuildMI(*BB, I, DL, TII->get(Mips::COPY)).addDef(Bitcast).addUse(StoreVal);
5194 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W))
5195 .addDef(Lo)
5196 .addUse(Bitcast)
5197 .addImm(0);
5198 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W))
5199 .addDef(Hi)
5200 .addUse(Bitcast)
5201 .addImm(1);
5202 BuildMI(*BB, I, DL, TII->get(Mips::SWR))
5203 .addUse(Lo)
5204 .addUse(Address)
5205 .addImm(Imm + (IsLittle ? 0 : 3));
5206 BuildMI(*BB, I, DL, TII->get(Mips::SWL))
5207 .addUse(Lo)
5208 .addUse(Address)
5209 .addImm(Imm + (IsLittle ? 3 : 0));
5210 BuildMI(*BB, I, DL, TII->get(Mips::SWR))
5211 .addUse(Hi)
5212 .addUse(Address)
5213 .addImm(Imm + (IsLittle ? 4 : 7));
5214 BuildMI(*BB, I, DL, TII->get(Mips::SWL))
5215 .addUse(Hi)
5216 .addUse(Address)
5217 .addImm(Imm + (IsLittle ? 7 : 4));
5218 }
5219
5220 MI.eraseFromParent();
5221 return BB;
5222 }
5223