1 //===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that Mips uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsISelLowering.h" 15 #include "MCTargetDesc/MipsBaseInfo.h" 16 #include "MCTargetDesc/MipsInstPrinter.h" 17 #include "MCTargetDesc/MipsMCTargetDesc.h" 18 #include "MipsCCState.h" 19 #include "MipsInstrInfo.h" 20 #include "MipsMachineFunction.h" 21 #include "MipsRegisterInfo.h" 22 #include "MipsSubtarget.h" 23 #include "MipsTargetMachine.h" 24 #include "MipsTargetObjectFile.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/ArrayRef.h" 27 #include "llvm/ADT/SmallVector.h" 28 #include "llvm/ADT/Statistic.h" 29 #include "llvm/ADT/StringRef.h" 30 #include "llvm/ADT/StringSwitch.h" 31 #include "llvm/CodeGen/CallingConvLower.h" 32 #include "llvm/CodeGen/FunctionLoweringInfo.h" 33 #include "llvm/CodeGen/ISDOpcodes.h" 34 #include "llvm/CodeGen/MachineBasicBlock.h" 35 #include "llvm/CodeGen/MachineFrameInfo.h" 36 #include "llvm/CodeGen/MachineFunction.h" 37 #include "llvm/CodeGen/MachineInstr.h" 38 #include "llvm/CodeGen/MachineInstrBuilder.h" 39 #include "llvm/CodeGen/MachineJumpTableInfo.h" 40 #include "llvm/CodeGen/MachineMemOperand.h" 41 #include "llvm/CodeGen/MachineOperand.h" 42 #include "llvm/CodeGen/MachineRegisterInfo.h" 43 #include "llvm/CodeGen/RuntimeLibcalls.h" 44 #include "llvm/CodeGen/SelectionDAG.h" 45 #include "llvm/CodeGen/SelectionDAGNodes.h" 46 #include "llvm/CodeGen/TargetFrameLowering.h" 47 #include "llvm/CodeGen/TargetInstrInfo.h" 48 #include "llvm/CodeGen/TargetRegisterInfo.h" 49 #include "llvm/CodeGen/ValueTypes.h" 50 #include "llvm/IR/CallingConv.h" 51 #include "llvm/IR/Constants.h" 52 #include "llvm/IR/DataLayout.h" 53 #include "llvm/IR/DebugLoc.h" 54 #include "llvm/IR/DerivedTypes.h" 55 #include "llvm/IR/Function.h" 56 #include "llvm/IR/GlobalValue.h" 57 #include "llvm/IR/Type.h" 58 #include "llvm/IR/Value.h" 59 #include "llvm/MC/MCContext.h" 60 #include "llvm/MC/MCRegisterInfo.h" 61 #include "llvm/Support/Casting.h" 62 #include "llvm/Support/CodeGen.h" 63 #include "llvm/Support/CommandLine.h" 64 #include "llvm/Support/Compiler.h" 65 #include "llvm/Support/ErrorHandling.h" 66 #include "llvm/Support/MachineValueType.h" 67 #include "llvm/Support/MathExtras.h" 68 #include "llvm/Target/TargetMachine.h" 69 #include "llvm/Target/TargetOptions.h" 70 #include <algorithm> 71 #include <cassert> 72 #include <cctype> 73 #include <cstdint> 74 #include <deque> 75 #include <iterator> 76 #include <utility> 77 #include <vector> 78 79 using namespace llvm; 80 81 #define DEBUG_TYPE "mips-lower" 82 83 STATISTIC(NumTailCalls, "Number of tail calls"); 84 85 static cl::opt<bool> 86 NoZeroDivCheck("mno-check-zero-division", cl::Hidden, 87 cl::desc("MIPS: Don't trap on integer division by zero."), 88 cl::init(false)); 89 90 extern cl::opt<bool> EmitJalrReloc; 91 92 static const MCPhysReg Mips64DPRegs[8] = { 93 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 94 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 95 }; 96 97 // If I is a shifted mask, set the size (Size) and the first bit of the 98 // mask (Pos), and return true. 99 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 100 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 101 if (!isShiftedMask_64(I)) 102 return false; 103 104 Size = countPopulation(I); 105 Pos = countTrailingZeros(I); 106 return true; 107 } 108 109 // The MIPS MSA ABI passes vector arguments in the integer register set. 110 // The number of integer registers used is dependant on the ABI used. 111 MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context, 112 CallingConv::ID CC, 113 EVT VT) const { 114 if (!VT.isVector()) 115 return getRegisterType(Context, VT); 116 117 return Subtarget.isABI_O32() || VT.getSizeInBits() == 32 ? MVT::i32 118 : MVT::i64; 119 } 120 121 unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context, 122 CallingConv::ID CC, 123 EVT VT) const { 124 if (VT.isVector()) 125 return divideCeil(VT.getSizeInBits(), Subtarget.isABI_O32() ? 32 : 64); 126 return MipsTargetLowering::getNumRegisters(Context, VT); 127 } 128 129 unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv( 130 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, 131 unsigned &NumIntermediates, MVT &RegisterVT) const { 132 // Break down vector types to either 2 i64s or 4 i32s. 133 RegisterVT = getRegisterTypeForCallingConv(Context, CC, VT); 134 IntermediateVT = RegisterVT; 135 NumIntermediates = 136 VT.getFixedSizeInBits() < RegisterVT.getFixedSizeInBits() 137 ? VT.getVectorNumElements() 138 : divideCeil(VT.getSizeInBits(), RegisterVT.getSizeInBits()); 139 return NumIntermediates; 140 } 141 142 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 143 MachineFunction &MF = DAG.getMachineFunction(); 144 MipsFunctionInfo *FI = MF.getInfo<MipsFunctionInfo>(); 145 return DAG.getRegister(FI->getGlobalBaseReg(MF), Ty); 146 } 147 148 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, 149 SelectionDAG &DAG, 150 unsigned Flag) const { 151 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); 152 } 153 154 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty, 155 SelectionDAG &DAG, 156 unsigned Flag) const { 157 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 158 } 159 160 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty, 161 SelectionDAG &DAG, 162 unsigned Flag) const { 163 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 164 } 165 166 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty, 167 SelectionDAG &DAG, 168 unsigned Flag) const { 169 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 170 } 171 172 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, 173 SelectionDAG &DAG, 174 unsigned Flag) const { 175 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlign(), 176 N->getOffset(), Flag); 177 } 178 179 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 180 switch ((MipsISD::NodeType)Opcode) { 181 case MipsISD::FIRST_NUMBER: break; 182 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 183 case MipsISD::TailCall: return "MipsISD::TailCall"; 184 case MipsISD::Highest: return "MipsISD::Highest"; 185 case MipsISD::Higher: return "MipsISD::Higher"; 186 case MipsISD::Hi: return "MipsISD::Hi"; 187 case MipsISD::Lo: return "MipsISD::Lo"; 188 case MipsISD::GotHi: return "MipsISD::GotHi"; 189 case MipsISD::TlsHi: return "MipsISD::TlsHi"; 190 case MipsISD::GPRel: return "MipsISD::GPRel"; 191 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 192 case MipsISD::Ret: return "MipsISD::Ret"; 193 case MipsISD::ERet: return "MipsISD::ERet"; 194 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 195 case MipsISD::FMS: return "MipsISD::FMS"; 196 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 197 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 198 case MipsISD::FSELECT: return "MipsISD::FSELECT"; 199 case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64"; 200 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 201 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 202 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; 203 case MipsISD::MFHI: return "MipsISD::MFHI"; 204 case MipsISD::MFLO: return "MipsISD::MFLO"; 205 case MipsISD::MTLOHI: return "MipsISD::MTLOHI"; 206 case MipsISD::Mult: return "MipsISD::Mult"; 207 case MipsISD::Multu: return "MipsISD::Multu"; 208 case MipsISD::MAdd: return "MipsISD::MAdd"; 209 case MipsISD::MAddu: return "MipsISD::MAddu"; 210 case MipsISD::MSub: return "MipsISD::MSub"; 211 case MipsISD::MSubu: return "MipsISD::MSubu"; 212 case MipsISD::DivRem: return "MipsISD::DivRem"; 213 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 214 case MipsISD::DivRem16: return "MipsISD::DivRem16"; 215 case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; 216 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 217 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 218 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 219 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 220 case MipsISD::Sync: return "MipsISD::Sync"; 221 case MipsISD::Ext: return "MipsISD::Ext"; 222 case MipsISD::Ins: return "MipsISD::Ins"; 223 case MipsISD::CIns: return "MipsISD::CIns"; 224 case MipsISD::LWL: return "MipsISD::LWL"; 225 case MipsISD::LWR: return "MipsISD::LWR"; 226 case MipsISD::SWL: return "MipsISD::SWL"; 227 case MipsISD::SWR: return "MipsISD::SWR"; 228 case MipsISD::LDL: return "MipsISD::LDL"; 229 case MipsISD::LDR: return "MipsISD::LDR"; 230 case MipsISD::SDL: return "MipsISD::SDL"; 231 case MipsISD::SDR: return "MipsISD::SDR"; 232 case MipsISD::EXTP: return "MipsISD::EXTP"; 233 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 234 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 235 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 236 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 237 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 238 case MipsISD::SHILO: return "MipsISD::SHILO"; 239 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 240 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH"; 241 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL"; 242 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR"; 243 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL"; 244 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR"; 245 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL"; 246 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR"; 247 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL"; 248 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR"; 249 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH"; 250 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH"; 251 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W"; 252 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W"; 253 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH"; 254 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH"; 255 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH"; 256 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH"; 257 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH"; 258 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH"; 259 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH"; 260 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH"; 261 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH"; 262 case MipsISD::MULT: return "MipsISD::MULT"; 263 case MipsISD::MULTU: return "MipsISD::MULTU"; 264 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 265 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 266 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 267 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 268 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; 269 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; 270 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; 271 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; 272 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; 273 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; 274 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; 275 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; 276 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; 277 case MipsISD::VCEQ: return "MipsISD::VCEQ"; 278 case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; 279 case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; 280 case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; 281 case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; 282 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; 283 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; 284 case MipsISD::VNOR: return "MipsISD::VNOR"; 285 case MipsISD::VSHF: return "MipsISD::VSHF"; 286 case MipsISD::SHF: return "MipsISD::SHF"; 287 case MipsISD::ILVEV: return "MipsISD::ILVEV"; 288 case MipsISD::ILVOD: return "MipsISD::ILVOD"; 289 case MipsISD::ILVL: return "MipsISD::ILVL"; 290 case MipsISD::ILVR: return "MipsISD::ILVR"; 291 case MipsISD::PCKEV: return "MipsISD::PCKEV"; 292 case MipsISD::PCKOD: return "MipsISD::PCKOD"; 293 case MipsISD::INSVE: return "MipsISD::INSVE"; 294 } 295 return nullptr; 296 } 297 298 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, 299 const MipsSubtarget &STI) 300 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { 301 // Mips does not have i1 type, so use i32 for 302 // setcc operations results (slt, sgt, ...). 303 setBooleanContents(ZeroOrOneBooleanContent); 304 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 305 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA 306 // does. Integer booleans still use 0 and 1. 307 if (Subtarget.hasMips32r6()) 308 setBooleanContents(ZeroOrOneBooleanContent, 309 ZeroOrNegativeOneBooleanContent); 310 311 // Load extented operations for i1 types must be promoted 312 for (MVT VT : MVT::integer_valuetypes()) { 313 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 314 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 315 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 316 } 317 318 // MIPS doesn't have extending float->double load/store. Set LoadExtAction 319 // for f32, f16 320 for (MVT VT : MVT::fp_valuetypes()) { 321 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); 322 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); 323 } 324 325 // Set LoadExtAction for f16 vectors to Expand 326 for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) { 327 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements()); 328 if (F16VT.isValid()) 329 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); 330 } 331 332 setTruncStoreAction(MVT::f32, MVT::f16, Expand); 333 setTruncStoreAction(MVT::f64, MVT::f16, Expand); 334 335 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 336 337 // Used by legalize types to correctly generate the setcc result. 338 // Without this, every float setcc comes with a AND/OR with the result, 339 // we don't want this, since the fpcmp result goes to a flag register, 340 // which is used implicitly by brcond and select operations. 341 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 342 343 // Mips Custom Operations 344 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 345 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 346 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 347 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 348 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 349 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 350 setOperationAction(ISD::SELECT, MVT::f32, Custom); 351 setOperationAction(ISD::SELECT, MVT::f64, Custom); 352 setOperationAction(ISD::SELECT, MVT::i32, Custom); 353 setOperationAction(ISD::SETCC, MVT::f32, Custom); 354 setOperationAction(ISD::SETCC, MVT::f64, Custom); 355 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 356 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 357 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 358 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 359 360 if (!(TM.Options.NoNaNsFPMath || Subtarget.inAbs2008Mode())) { 361 setOperationAction(ISD::FABS, MVT::f32, Custom); 362 setOperationAction(ISD::FABS, MVT::f64, Custom); 363 } 364 365 if (Subtarget.isGP64bit()) { 366 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 367 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 368 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 369 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 370 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 371 setOperationAction(ISD::SELECT, MVT::i64, Custom); 372 setOperationAction(ISD::LOAD, MVT::i64, Custom); 373 setOperationAction(ISD::STORE, MVT::i64, Custom); 374 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 375 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 376 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 377 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 378 } 379 380 if (!Subtarget.isGP64bit()) { 381 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 382 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 383 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 384 } 385 386 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); 387 if (Subtarget.isGP64bit()) 388 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom); 389 390 setOperationAction(ISD::SDIV, MVT::i32, Expand); 391 setOperationAction(ISD::SREM, MVT::i32, Expand); 392 setOperationAction(ISD::UDIV, MVT::i32, Expand); 393 setOperationAction(ISD::UREM, MVT::i32, Expand); 394 setOperationAction(ISD::SDIV, MVT::i64, Expand); 395 setOperationAction(ISD::SREM, MVT::i64, Expand); 396 setOperationAction(ISD::UDIV, MVT::i64, Expand); 397 setOperationAction(ISD::UREM, MVT::i64, Expand); 398 399 // Operations not directly supported by Mips. 400 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 401 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 402 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 403 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 404 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 405 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 406 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 407 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 408 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 409 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 410 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 411 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 412 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 413 if (Subtarget.hasCnMips()) { 414 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 415 setOperationAction(ISD::CTPOP, MVT::i64, Legal); 416 } else { 417 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 418 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 419 } 420 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 421 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 422 setOperationAction(ISD::ROTL, MVT::i32, Expand); 423 setOperationAction(ISD::ROTL, MVT::i64, Expand); 424 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 425 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 426 427 if (!Subtarget.hasMips32r2()) 428 setOperationAction(ISD::ROTR, MVT::i32, Expand); 429 430 if (!Subtarget.hasMips64r2()) 431 setOperationAction(ISD::ROTR, MVT::i64, Expand); 432 433 setOperationAction(ISD::FSIN, MVT::f32, Expand); 434 setOperationAction(ISD::FSIN, MVT::f64, Expand); 435 setOperationAction(ISD::FCOS, MVT::f32, Expand); 436 setOperationAction(ISD::FCOS, MVT::f64, Expand); 437 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 438 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 439 setOperationAction(ISD::FPOW, MVT::f32, Expand); 440 setOperationAction(ISD::FPOW, MVT::f64, Expand); 441 setOperationAction(ISD::FLOG, MVT::f32, Expand); 442 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 443 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 444 setOperationAction(ISD::FEXP, MVT::f32, Expand); 445 setOperationAction(ISD::FMA, MVT::f32, Expand); 446 setOperationAction(ISD::FMA, MVT::f64, Expand); 447 setOperationAction(ISD::FREM, MVT::f32, Expand); 448 setOperationAction(ISD::FREM, MVT::f64, Expand); 449 450 // Lower f16 conversion operations into library calls 451 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); 452 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); 453 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); 454 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); 455 456 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 457 458 setOperationAction(ISD::VASTART, MVT::Other, Custom); 459 setOperationAction(ISD::VAARG, MVT::Other, Custom); 460 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 461 setOperationAction(ISD::VAEND, MVT::Other, Expand); 462 463 // Use the default for now 464 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 465 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 466 467 if (!Subtarget.isGP64bit()) { 468 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 469 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 470 } 471 472 if (!Subtarget.hasMips32r2()) { 473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 474 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 475 } 476 477 // MIPS16 lacks MIPS32's clz and clo instructions. 478 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) 479 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 480 if (!Subtarget.hasMips64()) 481 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 482 483 if (!Subtarget.hasMips32r2()) 484 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 485 if (!Subtarget.hasMips64r2()) 486 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 487 488 if (Subtarget.isGP64bit()) { 489 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom); 490 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom); 491 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); 492 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 493 } 494 495 setOperationAction(ISD::TRAP, MVT::Other, Legal); 496 497 setTargetDAGCombine(ISD::SDIVREM); 498 setTargetDAGCombine(ISD::UDIVREM); 499 setTargetDAGCombine(ISD::SELECT); 500 setTargetDAGCombine(ISD::AND); 501 setTargetDAGCombine(ISD::OR); 502 setTargetDAGCombine(ISD::ADD); 503 setTargetDAGCombine(ISD::SUB); 504 setTargetDAGCombine(ISD::AssertZext); 505 setTargetDAGCombine(ISD::SHL); 506 507 if (ABI.IsO32()) { 508 // These libcalls are not available in 32-bit. 509 setLibcallName(RTLIB::SHL_I128, nullptr); 510 setLibcallName(RTLIB::SRL_I128, nullptr); 511 setLibcallName(RTLIB::SRA_I128, nullptr); 512 setLibcallName(RTLIB::MUL_I128, nullptr); 513 setLibcallName(RTLIB::MULO_I64, nullptr); 514 setLibcallName(RTLIB::MULO_I128, nullptr); 515 } 516 517 setMinFunctionAlignment(Subtarget.isGP64bit() ? Align(8) : Align(4)); 518 519 // The arguments on the stack are defined in terms of 4-byte slots on O32 520 // and 8-byte slots on N32/N64. 521 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? Align(8) 522 : Align(4)); 523 524 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP); 525 526 MaxStoresPerMemcpy = 16; 527 528 isMicroMips = Subtarget.inMicroMipsMode(); 529 } 530 531 const MipsTargetLowering * 532 MipsTargetLowering::create(const MipsTargetMachine &TM, 533 const MipsSubtarget &STI) { 534 if (STI.inMips16Mode()) 535 return createMips16TargetLowering(TM, STI); 536 537 return createMipsSETargetLowering(TM, STI); 538 } 539 540 // Create a fast isel object. 541 FastISel * 542 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, 543 const TargetLibraryInfo *libInfo) const { 544 const MipsTargetMachine &TM = 545 static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget()); 546 547 // We support only the standard encoding [MIPS32,MIPS32R5] ISAs. 548 bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() && 549 !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() && 550 !Subtarget.inMicroMipsMode(); 551 552 // Disable if either of the following is true: 553 // We do not generate PIC, the ABI is not O32, XGOT is being used. 554 if (!TM.isPositionIndependent() || !TM.getABI().IsO32() || 555 Subtarget.useXGOT()) 556 UseFastISel = false; 557 558 return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr; 559 } 560 561 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, 562 EVT VT) const { 563 if (!VT.isVector()) 564 return MVT::i32; 565 return VT.changeVectorElementTypeToInteger(); 566 } 567 568 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, 569 TargetLowering::DAGCombinerInfo &DCI, 570 const MipsSubtarget &Subtarget) { 571 if (DCI.isBeforeLegalizeOps()) 572 return SDValue(); 573 574 EVT Ty = N->getValueType(0); 575 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64; 576 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64; 577 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : 578 MipsISD::DivRemU16; 579 SDLoc DL(N); 580 581 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, 582 N->getOperand(0), N->getOperand(1)); 583 SDValue InChain = DAG.getEntryNode(); 584 SDValue InGlue = DivRem; 585 586 // insert MFLO 587 if (N->hasAnyUseOfValue(0)) { 588 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, 589 InGlue); 590 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 591 InChain = CopyFromLo.getValue(1); 592 InGlue = CopyFromLo.getValue(2); 593 } 594 595 // insert MFHI 596 if (N->hasAnyUseOfValue(1)) { 597 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, 598 HI, Ty, InGlue); 599 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 600 } 601 602 return SDValue(); 603 } 604 605 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { 606 switch (CC) { 607 default: llvm_unreachable("Unknown fp condition code!"); 608 case ISD::SETEQ: 609 case ISD::SETOEQ: return Mips::FCOND_OEQ; 610 case ISD::SETUNE: return Mips::FCOND_UNE; 611 case ISD::SETLT: 612 case ISD::SETOLT: return Mips::FCOND_OLT; 613 case ISD::SETGT: 614 case ISD::SETOGT: return Mips::FCOND_OGT; 615 case ISD::SETLE: 616 case ISD::SETOLE: return Mips::FCOND_OLE; 617 case ISD::SETGE: 618 case ISD::SETOGE: return Mips::FCOND_OGE; 619 case ISD::SETULT: return Mips::FCOND_ULT; 620 case ISD::SETULE: return Mips::FCOND_ULE; 621 case ISD::SETUGT: return Mips::FCOND_UGT; 622 case ISD::SETUGE: return Mips::FCOND_UGE; 623 case ISD::SETUO: return Mips::FCOND_UN; 624 case ISD::SETO: return Mips::FCOND_OR; 625 case ISD::SETNE: 626 case ISD::SETONE: return Mips::FCOND_ONE; 627 case ISD::SETUEQ: return Mips::FCOND_UEQ; 628 } 629 } 630 631 /// This function returns true if the floating point conditional branches and 632 /// conditional moves which use condition code CC should be inverted. 633 static bool invertFPCondCodeUser(Mips::CondCode CC) { 634 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 635 return false; 636 637 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 638 "Illegal Condition Code"); 639 640 return true; 641 } 642 643 // Creates and returns an FPCmp node from a setcc node. 644 // Returns Op if setcc is not a floating point comparison. 645 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { 646 // must be a SETCC node 647 if (Op.getOpcode() != ISD::SETCC) 648 return Op; 649 650 SDValue LHS = Op.getOperand(0); 651 652 if (!LHS.getValueType().isFloatingPoint()) 653 return Op; 654 655 SDValue RHS = Op.getOperand(1); 656 SDLoc DL(Op); 657 658 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 659 // node if necessary. 660 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 661 662 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, 663 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); 664 } 665 666 // Creates and returns a CMovFPT/F node. 667 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 668 SDValue False, const SDLoc &DL) { 669 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 670 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); 671 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 672 673 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 674 True.getValueType(), True, FCC0, False, Cond); 675 } 676 677 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, 678 TargetLowering::DAGCombinerInfo &DCI, 679 const MipsSubtarget &Subtarget) { 680 if (DCI.isBeforeLegalizeOps()) 681 return SDValue(); 682 683 SDValue SetCC = N->getOperand(0); 684 685 if ((SetCC.getOpcode() != ISD::SETCC) || 686 !SetCC.getOperand(0).getValueType().isInteger()) 687 return SDValue(); 688 689 SDValue False = N->getOperand(2); 690 EVT FalseTy = False.getValueType(); 691 692 if (!FalseTy.isInteger()) 693 return SDValue(); 694 695 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False); 696 697 // If the RHS (False) is 0, we swap the order of the operands 698 // of ISD::SELECT (obviously also inverting the condition) so that we can 699 // take advantage of conditional moves using the $0 register. 700 // Example: 701 // return (a != 0) ? x : 0; 702 // load $reg, x 703 // movz $reg, $0, a 704 if (!FalseC) 705 return SDValue(); 706 707 const SDLoc DL(N); 708 709 if (!FalseC->getZExtValue()) { 710 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 711 SDValue True = N->getOperand(1); 712 713 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 714 SetCC.getOperand(1), 715 ISD::getSetCCInverse(CC, SetCC.getValueType())); 716 717 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 718 } 719 720 // If both operands are integer constants there's a possibility that we 721 // can do some interesting optimizations. 722 SDValue True = N->getOperand(1); 723 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True); 724 725 if (!TrueC || !True.getValueType().isInteger()) 726 return SDValue(); 727 728 // We'll also ignore MVT::i64 operands as this optimizations proves 729 // to be ineffective because of the required sign extensions as the result 730 // of a SETCC operator is always MVT::i32 for non-vector types. 731 if (True.getValueType() == MVT::i64) 732 return SDValue(); 733 734 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue(); 735 736 // 1) (a < x) ? y : y-1 737 // slti $reg1, a, x 738 // addiu $reg2, $reg1, y-1 739 if (Diff == 1) 740 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); 741 742 // 2) (a < x) ? y-1 : y 743 // slti $reg1, a, x 744 // xor $reg1, $reg1, 1 745 // addiu $reg2, $reg1, y-1 746 if (Diff == -1) { 747 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 748 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 749 SetCC.getOperand(1), 750 ISD::getSetCCInverse(CC, SetCC.getValueType())); 751 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True); 752 } 753 754 // Could not optimize. 755 return SDValue(); 756 } 757 758 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, 759 TargetLowering::DAGCombinerInfo &DCI, 760 const MipsSubtarget &Subtarget) { 761 if (DCI.isBeforeLegalizeOps()) 762 return SDValue(); 763 764 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2); 765 766 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse); 767 if (!FalseC || FalseC->getZExtValue()) 768 return SDValue(); 769 770 // Since RHS (False) is 0, we swap the order of the True/False operands 771 // (obviously also inverting the condition) so that we can 772 // take advantage of conditional moves using the $0 register. 773 // Example: 774 // return (a != 0) ? x : 0; 775 // load $reg, x 776 // movz $reg, $0, a 777 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F : 778 MipsISD::CMovFP_T; 779 780 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3); 781 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(), 782 ValueIfFalse, FCC, ValueIfTrue, Glue); 783 } 784 785 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 786 TargetLowering::DAGCombinerInfo &DCI, 787 const MipsSubtarget &Subtarget) { 788 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 789 return SDValue(); 790 791 SDValue FirstOperand = N->getOperand(0); 792 unsigned FirstOperandOpc = FirstOperand.getOpcode(); 793 SDValue Mask = N->getOperand(1); 794 EVT ValTy = N->getValueType(0); 795 SDLoc DL(N); 796 797 uint64_t Pos = 0, SMPos, SMSize; 798 ConstantSDNode *CN; 799 SDValue NewOperand; 800 unsigned Opc; 801 802 // Op's second operand must be a shifted mask. 803 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 804 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 805 return SDValue(); 806 807 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { 808 // Pattern match EXT. 809 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 810 // => ext $dst, $src, pos, size 811 812 // The second operand of the shift must be an immediate. 813 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1)))) 814 return SDValue(); 815 816 Pos = CN->getZExtValue(); 817 818 // Return if the shifted mask does not start at bit 0 or the sum of its size 819 // and Pos exceeds the word's size. 820 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 821 return SDValue(); 822 823 Opc = MipsISD::Ext; 824 NewOperand = FirstOperand.getOperand(0); 825 } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) { 826 // Pattern match CINS. 827 // $dst = and (shl $src , pos), mask 828 // => cins $dst, $src, pos, size 829 // mask is a shifted mask with consecutive 1's, pos = shift amount, 830 // size = population count. 831 832 // The second operand of the shift must be an immediate. 833 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1)))) 834 return SDValue(); 835 836 Pos = CN->getZExtValue(); 837 838 if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 || 839 Pos + SMSize > ValTy.getSizeInBits()) 840 return SDValue(); 841 842 NewOperand = FirstOperand.getOperand(0); 843 // SMSize is 'location' (position) in this case, not size. 844 SMSize--; 845 Opc = MipsISD::CIns; 846 } else { 847 // Pattern match EXT. 848 // $dst = and $src, (2**size - 1) , if size > 16 849 // => ext $dst, $src, pos, size , pos = 0 850 851 // If the mask is <= 0xffff, andi can be used instead. 852 if (CN->getZExtValue() <= 0xffff) 853 return SDValue(); 854 855 // Return if the mask doesn't start at position 0. 856 if (SMPos) 857 return SDValue(); 858 859 Opc = MipsISD::Ext; 860 NewOperand = FirstOperand; 861 } 862 return DAG.getNode(Opc, DL, ValTy, NewOperand, 863 DAG.getConstant(Pos, DL, MVT::i32), 864 DAG.getConstant(SMSize, DL, MVT::i32)); 865 } 866 867 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 868 TargetLowering::DAGCombinerInfo &DCI, 869 const MipsSubtarget &Subtarget) { 870 // Pattern match INS. 871 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 872 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 873 // => ins $dst, $src, size, pos, $src1 874 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 875 return SDValue(); 876 877 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 878 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 879 ConstantSDNode *CN, *CN1; 880 881 // See if Op's first operand matches (and $src1 , mask0). 882 if (And0.getOpcode() != ISD::AND) 883 return SDValue(); 884 885 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 886 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 887 return SDValue(); 888 889 // See if Op's second operand matches (and (shl $src, pos), mask1). 890 if (And1.getOpcode() == ISD::AND && 891 And1.getOperand(0).getOpcode() == ISD::SHL) { 892 893 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 894 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 895 return SDValue(); 896 897 // The shift masks must have the same position and size. 898 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 899 return SDValue(); 900 901 SDValue Shl = And1.getOperand(0); 902 903 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 904 return SDValue(); 905 906 unsigned Shamt = CN->getZExtValue(); 907 908 // Return if the shift amount and the first bit position of mask are not the 909 // same. 910 EVT ValTy = N->getValueType(0); 911 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 912 return SDValue(); 913 914 SDLoc DL(N); 915 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0), 916 DAG.getConstant(SMPos0, DL, MVT::i32), 917 DAG.getConstant(SMSize0, DL, MVT::i32), 918 And0.getOperand(0)); 919 } else { 920 // Pattern match DINS. 921 // $dst = or (and $src, mask0), mask1 922 // where mask0 = ((1 << SMSize0) -1) << SMPos0 923 // => dins $dst, $src, pos, size 924 if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) && 925 ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) || 926 (SMSize0 + SMPos0 <= 32))) { 927 // Check if AND instruction has constant as argument 928 bool isConstCase = And1.getOpcode() != ISD::AND; 929 if (And1.getOpcode() == ISD::AND) { 930 if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1)))) 931 return SDValue(); 932 } else { 933 if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1)))) 934 return SDValue(); 935 } 936 // Don't generate INS if constant OR operand doesn't fit into bits 937 // cleared by constant AND operand. 938 if (CN->getSExtValue() & CN1->getSExtValue()) 939 return SDValue(); 940 941 SDLoc DL(N); 942 EVT ValTy = N->getOperand(0)->getValueType(0); 943 SDValue Const1; 944 SDValue SrlX; 945 if (!isConstCase) { 946 Const1 = DAG.getConstant(SMPos0, DL, MVT::i32); 947 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1); 948 } 949 return DAG.getNode( 950 MipsISD::Ins, DL, N->getValueType(0), 951 isConstCase 952 ? DAG.getConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy) 953 : SrlX, 954 DAG.getConstant(SMPos0, DL, MVT::i32), 955 DAG.getConstant(ValTy.getSizeInBits() / 8 < 8 ? SMSize0 & 31 956 : SMSize0, 957 DL, MVT::i32), 958 And0->getOperand(0)); 959 960 } 961 return SDValue(); 962 } 963 } 964 965 static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG, 966 const MipsSubtarget &Subtarget) { 967 // ROOTNode must have a multiplication as an operand for the match to be 968 // successful. 969 if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL && 970 ROOTNode->getOperand(1).getOpcode() != ISD::MUL) 971 return SDValue(); 972 973 // We don't handle vector types here. 974 if (ROOTNode->getValueType(0).isVector()) 975 return SDValue(); 976 977 // For MIPS64, madd / msub instructions are inefficent to use with 64 bit 978 // arithmetic. E.g. 979 // (add (mul a b) c) => 980 // let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in 981 // MIPS64: (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32) 982 // or 983 // MIPS64R2: (dins (mflo res) (mfhi res) 32 32) 984 // 985 // The overhead of setting up the Hi/Lo registers and reassembling the 986 // result makes this a dubious optimzation for MIPS64. The core of the 987 // problem is that Hi/Lo contain the upper and lower 32 bits of the 988 // operand and result. 989 // 990 // It requires a chain of 4 add/mul for MIPS64R2 to get better code 991 // density than doing it naively, 5 for MIPS64. Additionally, using 992 // madd/msub on MIPS64 requires the operands actually be 32 bit sign 993 // extended operands, not true 64 bit values. 994 // 995 // FIXME: For the moment, disable this completely for MIPS64. 996 if (Subtarget.hasMips64()) 997 return SDValue(); 998 999 SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL 1000 ? ROOTNode->getOperand(0) 1001 : ROOTNode->getOperand(1); 1002 1003 SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL 1004 ? ROOTNode->getOperand(1) 1005 : ROOTNode->getOperand(0); 1006 1007 // Transform this to a MADD only if the user of this node is the add. 1008 // If there are other users of the mul, this function returns here. 1009 if (!Mult.hasOneUse()) 1010 return SDValue(); 1011 1012 // maddu and madd are unusual instructions in that on MIPS64 bits 63..31 1013 // must be in canonical form, i.e. sign extended. For MIPS32, the operands 1014 // of the multiply must have 32 or more sign bits, otherwise we cannot 1015 // perform this optimization. We have to check this here as we're performing 1016 // this optimization pre-legalization. 1017 SDValue MultLHS = Mult->getOperand(0); 1018 SDValue MultRHS = Mult->getOperand(1); 1019 1020 bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND && 1021 MultRHS->getOpcode() == ISD::SIGN_EXTEND; 1022 bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND && 1023 MultRHS->getOpcode() == ISD::ZERO_EXTEND; 1024 1025 if (!IsSigned && !IsUnsigned) 1026 return SDValue(); 1027 1028 // Initialize accumulator. 1029 SDLoc DL(ROOTNode); 1030 SDValue TopHalf; 1031 SDValue BottomHalf; 1032 BottomHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand, 1033 CurDAG.getIntPtrConstant(0, DL)); 1034 1035 TopHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand, 1036 CurDAG.getIntPtrConstant(1, DL)); 1037 SDValue ACCIn = CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, 1038 BottomHalf, 1039 TopHalf); 1040 1041 // Create MipsMAdd(u) / MipsMSub(u) node. 1042 bool IsAdd = ROOTNode->getOpcode() == ISD::ADD; 1043 unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd) 1044 : (IsUnsigned ? MipsISD::MSubu : MipsISD::MSub); 1045 SDValue MAddOps[3] = { 1046 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)), 1047 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn}; 1048 EVT VTs[2] = {MVT::i32, MVT::i32}; 1049 SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps); 1050 1051 SDValue ResLo = CurDAG.getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); 1052 SDValue ResHi = CurDAG.getNode(MipsISD::MFHI, DL, MVT::i32, MAdd); 1053 SDValue Combined = 1054 CurDAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResLo, ResHi); 1055 return Combined; 1056 } 1057 1058 static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG, 1059 TargetLowering::DAGCombinerInfo &DCI, 1060 const MipsSubtarget &Subtarget) { 1061 // (sub v0 (mul v1, v2)) => (msub v1, v2, v0) 1062 if (DCI.isBeforeLegalizeOps()) { 1063 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && 1064 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) 1065 return performMADD_MSUBCombine(N, DAG, Subtarget); 1066 1067 return SDValue(); 1068 } 1069 1070 return SDValue(); 1071 } 1072 1073 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, 1074 TargetLowering::DAGCombinerInfo &DCI, 1075 const MipsSubtarget &Subtarget) { 1076 // (add v0 (mul v1, v2)) => (madd v1, v2, v0) 1077 if (DCI.isBeforeLegalizeOps()) { 1078 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && 1079 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) 1080 return performMADD_MSUBCombine(N, DAG, Subtarget); 1081 1082 return SDValue(); 1083 } 1084 1085 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 1086 SDValue Add = N->getOperand(1); 1087 1088 if (Add.getOpcode() != ISD::ADD) 1089 return SDValue(); 1090 1091 SDValue Lo = Add.getOperand(1); 1092 1093 if ((Lo.getOpcode() != MipsISD::Lo) || 1094 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 1095 return SDValue(); 1096 1097 EVT ValTy = N->getValueType(0); 1098 SDLoc DL(N); 1099 1100 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 1101 Add.getOperand(0)); 1102 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 1103 } 1104 1105 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, 1106 TargetLowering::DAGCombinerInfo &DCI, 1107 const MipsSubtarget &Subtarget) { 1108 // Pattern match CINS. 1109 // $dst = shl (and $src , imm), pos 1110 // => cins $dst, $src, pos, size 1111 1112 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips()) 1113 return SDValue(); 1114 1115 SDValue FirstOperand = N->getOperand(0); 1116 unsigned FirstOperandOpc = FirstOperand.getOpcode(); 1117 SDValue SecondOperand = N->getOperand(1); 1118 EVT ValTy = N->getValueType(0); 1119 SDLoc DL(N); 1120 1121 uint64_t Pos = 0, SMPos, SMSize; 1122 ConstantSDNode *CN; 1123 SDValue NewOperand; 1124 1125 // The second operand of the shift must be an immediate. 1126 if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand))) 1127 return SDValue(); 1128 1129 Pos = CN->getZExtValue(); 1130 1131 if (Pos >= ValTy.getSizeInBits()) 1132 return SDValue(); 1133 1134 if (FirstOperandOpc != ISD::AND) 1135 return SDValue(); 1136 1137 // AND's second operand must be a shifted mask. 1138 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) || 1139 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 1140 return SDValue(); 1141 1142 // Return if the shifted mask does not start at bit 0 or the sum of its size 1143 // and Pos exceeds the word's size. 1144 if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits()) 1145 return SDValue(); 1146 1147 NewOperand = FirstOperand.getOperand(0); 1148 // SMSize is 'location' (position) in this case, not size. 1149 SMSize--; 1150 1151 return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand, 1152 DAG.getConstant(Pos, DL, MVT::i32), 1153 DAG.getConstant(SMSize, DL, MVT::i32)); 1154 } 1155 1156 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 1157 const { 1158 SelectionDAG &DAG = DCI.DAG; 1159 unsigned Opc = N->getOpcode(); 1160 1161 switch (Opc) { 1162 default: break; 1163 case ISD::SDIVREM: 1164 case ISD::UDIVREM: 1165 return performDivRemCombine(N, DAG, DCI, Subtarget); 1166 case ISD::SELECT: 1167 return performSELECTCombine(N, DAG, DCI, Subtarget); 1168 case MipsISD::CMovFP_F: 1169 case MipsISD::CMovFP_T: 1170 return performCMovFPCombine(N, DAG, DCI, Subtarget); 1171 case ISD::AND: 1172 return performANDCombine(N, DAG, DCI, Subtarget); 1173 case ISD::OR: 1174 return performORCombine(N, DAG, DCI, Subtarget); 1175 case ISD::ADD: 1176 return performADDCombine(N, DAG, DCI, Subtarget); 1177 case ISD::SHL: 1178 return performSHLCombine(N, DAG, DCI, Subtarget); 1179 case ISD::SUB: 1180 return performSUBCombine(N, DAG, DCI, Subtarget); 1181 } 1182 1183 return SDValue(); 1184 } 1185 1186 bool MipsTargetLowering::isCheapToSpeculateCttz() const { 1187 return Subtarget.hasMips32(); 1188 } 1189 1190 bool MipsTargetLowering::isCheapToSpeculateCtlz() const { 1191 return Subtarget.hasMips32(); 1192 } 1193 1194 bool MipsTargetLowering::shouldFoldConstantShiftPairToMask( 1195 const SDNode *N, CombineLevel Level) const { 1196 if (N->getOperand(0).getValueType().isVector()) 1197 return false; 1198 return true; 1199 } 1200 1201 void 1202 MipsTargetLowering::ReplaceNodeResults(SDNode *N, 1203 SmallVectorImpl<SDValue> &Results, 1204 SelectionDAG &DAG) const { 1205 return LowerOperationWrapper(N, Results, DAG); 1206 } 1207 1208 SDValue MipsTargetLowering:: 1209 LowerOperation(SDValue Op, SelectionDAG &DAG) const 1210 { 1211 switch (Op.getOpcode()) 1212 { 1213 case ISD::BRCOND: return lowerBRCOND(Op, DAG); 1214 case ISD::ConstantPool: return lowerConstantPool(Op, DAG); 1215 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); 1216 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); 1217 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); 1218 case ISD::JumpTable: return lowerJumpTable(Op, DAG); 1219 case ISD::SELECT: return lowerSELECT(Op, DAG); 1220 case ISD::SETCC: return lowerSETCC(Op, DAG); 1221 case ISD::VASTART: return lowerVASTART(Op, DAG); 1222 case ISD::VAARG: return lowerVAARG(Op, DAG); 1223 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); 1224 case ISD::FABS: return lowerFABS(Op, DAG); 1225 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); 1226 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); 1227 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); 1228 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); 1229 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); 1230 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); 1231 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); 1232 case ISD::LOAD: return lowerLOAD(Op, DAG); 1233 case ISD::STORE: return lowerSTORE(Op, DAG); 1234 case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG); 1235 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); 1236 } 1237 return SDValue(); 1238 } 1239 1240 //===----------------------------------------------------------------------===// 1241 // Lower helper functions 1242 //===----------------------------------------------------------------------===// 1243 1244 // addLiveIn - This helper function adds the specified physical register to the 1245 // MachineFunction as a live in value. It also creates a corresponding 1246 // virtual register for it. 1247 static unsigned 1248 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 1249 { 1250 Register VReg = MF.getRegInfo().createVirtualRegister(RC); 1251 MF.getRegInfo().addLiveIn(PReg, VReg); 1252 return VReg; 1253 } 1254 1255 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI, 1256 MachineBasicBlock &MBB, 1257 const TargetInstrInfo &TII, 1258 bool Is64Bit, bool IsMicroMips) { 1259 if (NoZeroDivCheck) 1260 return &MBB; 1261 1262 // Insert instruction "teq $divisor_reg, $zero, 7". 1263 MachineBasicBlock::iterator I(MI); 1264 MachineInstrBuilder MIB; 1265 MachineOperand &Divisor = MI.getOperand(2); 1266 MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(), 1267 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ)) 1268 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill())) 1269 .addReg(Mips::ZERO) 1270 .addImm(7); 1271 1272 // Use the 32-bit sub-register if this is a 64-bit division. 1273 if (Is64Bit) 1274 MIB->getOperand(0).setSubReg(Mips::sub_32); 1275 1276 // Clear Divisor's kill flag. 1277 Divisor.setIsKill(false); 1278 1279 // We would normally delete the original instruction here but in this case 1280 // we only needed to inject an additional instruction rather than replace it. 1281 1282 return &MBB; 1283 } 1284 1285 MachineBasicBlock * 1286 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, 1287 MachineBasicBlock *BB) const { 1288 switch (MI.getOpcode()) { 1289 default: 1290 llvm_unreachable("Unexpected instr type to insert"); 1291 case Mips::ATOMIC_LOAD_ADD_I8: 1292 return emitAtomicBinaryPartword(MI, BB, 1); 1293 case Mips::ATOMIC_LOAD_ADD_I16: 1294 return emitAtomicBinaryPartword(MI, BB, 2); 1295 case Mips::ATOMIC_LOAD_ADD_I32: 1296 return emitAtomicBinary(MI, BB); 1297 case Mips::ATOMIC_LOAD_ADD_I64: 1298 return emitAtomicBinary(MI, BB); 1299 1300 case Mips::ATOMIC_LOAD_AND_I8: 1301 return emitAtomicBinaryPartword(MI, BB, 1); 1302 case Mips::ATOMIC_LOAD_AND_I16: 1303 return emitAtomicBinaryPartword(MI, BB, 2); 1304 case Mips::ATOMIC_LOAD_AND_I32: 1305 return emitAtomicBinary(MI, BB); 1306 case Mips::ATOMIC_LOAD_AND_I64: 1307 return emitAtomicBinary(MI, BB); 1308 1309 case Mips::ATOMIC_LOAD_OR_I8: 1310 return emitAtomicBinaryPartword(MI, BB, 1); 1311 case Mips::ATOMIC_LOAD_OR_I16: 1312 return emitAtomicBinaryPartword(MI, BB, 2); 1313 case Mips::ATOMIC_LOAD_OR_I32: 1314 return emitAtomicBinary(MI, BB); 1315 case Mips::ATOMIC_LOAD_OR_I64: 1316 return emitAtomicBinary(MI, BB); 1317 1318 case Mips::ATOMIC_LOAD_XOR_I8: 1319 return emitAtomicBinaryPartword(MI, BB, 1); 1320 case Mips::ATOMIC_LOAD_XOR_I16: 1321 return emitAtomicBinaryPartword(MI, BB, 2); 1322 case Mips::ATOMIC_LOAD_XOR_I32: 1323 return emitAtomicBinary(MI, BB); 1324 case Mips::ATOMIC_LOAD_XOR_I64: 1325 return emitAtomicBinary(MI, BB); 1326 1327 case Mips::ATOMIC_LOAD_NAND_I8: 1328 return emitAtomicBinaryPartword(MI, BB, 1); 1329 case Mips::ATOMIC_LOAD_NAND_I16: 1330 return emitAtomicBinaryPartword(MI, BB, 2); 1331 case Mips::ATOMIC_LOAD_NAND_I32: 1332 return emitAtomicBinary(MI, BB); 1333 case Mips::ATOMIC_LOAD_NAND_I64: 1334 return emitAtomicBinary(MI, BB); 1335 1336 case Mips::ATOMIC_LOAD_SUB_I8: 1337 return emitAtomicBinaryPartword(MI, BB, 1); 1338 case Mips::ATOMIC_LOAD_SUB_I16: 1339 return emitAtomicBinaryPartword(MI, BB, 2); 1340 case Mips::ATOMIC_LOAD_SUB_I32: 1341 return emitAtomicBinary(MI, BB); 1342 case Mips::ATOMIC_LOAD_SUB_I64: 1343 return emitAtomicBinary(MI, BB); 1344 1345 case Mips::ATOMIC_SWAP_I8: 1346 return emitAtomicBinaryPartword(MI, BB, 1); 1347 case Mips::ATOMIC_SWAP_I16: 1348 return emitAtomicBinaryPartword(MI, BB, 2); 1349 case Mips::ATOMIC_SWAP_I32: 1350 return emitAtomicBinary(MI, BB); 1351 case Mips::ATOMIC_SWAP_I64: 1352 return emitAtomicBinary(MI, BB); 1353 1354 case Mips::ATOMIC_CMP_SWAP_I8: 1355 return emitAtomicCmpSwapPartword(MI, BB, 1); 1356 case Mips::ATOMIC_CMP_SWAP_I16: 1357 return emitAtomicCmpSwapPartword(MI, BB, 2); 1358 case Mips::ATOMIC_CMP_SWAP_I32: 1359 return emitAtomicCmpSwap(MI, BB); 1360 case Mips::ATOMIC_CMP_SWAP_I64: 1361 return emitAtomicCmpSwap(MI, BB); 1362 1363 case Mips::ATOMIC_LOAD_MIN_I8: 1364 return emitAtomicBinaryPartword(MI, BB, 1); 1365 case Mips::ATOMIC_LOAD_MIN_I16: 1366 return emitAtomicBinaryPartword(MI, BB, 2); 1367 case Mips::ATOMIC_LOAD_MIN_I32: 1368 return emitAtomicBinary(MI, BB); 1369 case Mips::ATOMIC_LOAD_MIN_I64: 1370 return emitAtomicBinary(MI, BB); 1371 1372 case Mips::ATOMIC_LOAD_MAX_I8: 1373 return emitAtomicBinaryPartword(MI, BB, 1); 1374 case Mips::ATOMIC_LOAD_MAX_I16: 1375 return emitAtomicBinaryPartword(MI, BB, 2); 1376 case Mips::ATOMIC_LOAD_MAX_I32: 1377 return emitAtomicBinary(MI, BB); 1378 case Mips::ATOMIC_LOAD_MAX_I64: 1379 return emitAtomicBinary(MI, BB); 1380 1381 case Mips::ATOMIC_LOAD_UMIN_I8: 1382 return emitAtomicBinaryPartword(MI, BB, 1); 1383 case Mips::ATOMIC_LOAD_UMIN_I16: 1384 return emitAtomicBinaryPartword(MI, BB, 2); 1385 case Mips::ATOMIC_LOAD_UMIN_I32: 1386 return emitAtomicBinary(MI, BB); 1387 case Mips::ATOMIC_LOAD_UMIN_I64: 1388 return emitAtomicBinary(MI, BB); 1389 1390 case Mips::ATOMIC_LOAD_UMAX_I8: 1391 return emitAtomicBinaryPartword(MI, BB, 1); 1392 case Mips::ATOMIC_LOAD_UMAX_I16: 1393 return emitAtomicBinaryPartword(MI, BB, 2); 1394 case Mips::ATOMIC_LOAD_UMAX_I32: 1395 return emitAtomicBinary(MI, BB); 1396 case Mips::ATOMIC_LOAD_UMAX_I64: 1397 return emitAtomicBinary(MI, BB); 1398 1399 case Mips::PseudoSDIV: 1400 case Mips::PseudoUDIV: 1401 case Mips::DIV: 1402 case Mips::DIVU: 1403 case Mips::MOD: 1404 case Mips::MODU: 1405 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, 1406 false); 1407 case Mips::SDIV_MM_Pseudo: 1408 case Mips::UDIV_MM_Pseudo: 1409 case Mips::SDIV_MM: 1410 case Mips::UDIV_MM: 1411 case Mips::DIV_MMR6: 1412 case Mips::DIVU_MMR6: 1413 case Mips::MOD_MMR6: 1414 case Mips::MODU_MMR6: 1415 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true); 1416 case Mips::PseudoDSDIV: 1417 case Mips::PseudoDUDIV: 1418 case Mips::DDIV: 1419 case Mips::DDIVU: 1420 case Mips::DMOD: 1421 case Mips::DMODU: 1422 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false); 1423 1424 case Mips::PseudoSELECT_I: 1425 case Mips::PseudoSELECT_I64: 1426 case Mips::PseudoSELECT_S: 1427 case Mips::PseudoSELECT_D32: 1428 case Mips::PseudoSELECT_D64: 1429 return emitPseudoSELECT(MI, BB, false, Mips::BNE); 1430 case Mips::PseudoSELECTFP_F_I: 1431 case Mips::PseudoSELECTFP_F_I64: 1432 case Mips::PseudoSELECTFP_F_S: 1433 case Mips::PseudoSELECTFP_F_D32: 1434 case Mips::PseudoSELECTFP_F_D64: 1435 return emitPseudoSELECT(MI, BB, true, Mips::BC1F); 1436 case Mips::PseudoSELECTFP_T_I: 1437 case Mips::PseudoSELECTFP_T_I64: 1438 case Mips::PseudoSELECTFP_T_S: 1439 case Mips::PseudoSELECTFP_T_D32: 1440 case Mips::PseudoSELECTFP_T_D64: 1441 return emitPseudoSELECT(MI, BB, true, Mips::BC1T); 1442 case Mips::PseudoD_SELECT_I: 1443 case Mips::PseudoD_SELECT_I64: 1444 return emitPseudoD_SELECT(MI, BB); 1445 case Mips::LDR_W: 1446 return emitLDR_W(MI, BB); 1447 case Mips::LDR_D: 1448 return emitLDR_D(MI, BB); 1449 case Mips::STR_W: 1450 return emitSTR_W(MI, BB); 1451 case Mips::STR_D: 1452 return emitSTR_D(MI, BB); 1453 } 1454 } 1455 1456 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 1457 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 1458 MachineBasicBlock * 1459 MipsTargetLowering::emitAtomicBinary(MachineInstr &MI, 1460 MachineBasicBlock *BB) const { 1461 1462 MachineFunction *MF = BB->getParent(); 1463 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1464 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1465 DebugLoc DL = MI.getDebugLoc(); 1466 1467 unsigned AtomicOp; 1468 bool NeedsAdditionalReg = false; 1469 switch (MI.getOpcode()) { 1470 case Mips::ATOMIC_LOAD_ADD_I32: 1471 AtomicOp = Mips::ATOMIC_LOAD_ADD_I32_POSTRA; 1472 break; 1473 case Mips::ATOMIC_LOAD_SUB_I32: 1474 AtomicOp = Mips::ATOMIC_LOAD_SUB_I32_POSTRA; 1475 break; 1476 case Mips::ATOMIC_LOAD_AND_I32: 1477 AtomicOp = Mips::ATOMIC_LOAD_AND_I32_POSTRA; 1478 break; 1479 case Mips::ATOMIC_LOAD_OR_I32: 1480 AtomicOp = Mips::ATOMIC_LOAD_OR_I32_POSTRA; 1481 break; 1482 case Mips::ATOMIC_LOAD_XOR_I32: 1483 AtomicOp = Mips::ATOMIC_LOAD_XOR_I32_POSTRA; 1484 break; 1485 case Mips::ATOMIC_LOAD_NAND_I32: 1486 AtomicOp = Mips::ATOMIC_LOAD_NAND_I32_POSTRA; 1487 break; 1488 case Mips::ATOMIC_SWAP_I32: 1489 AtomicOp = Mips::ATOMIC_SWAP_I32_POSTRA; 1490 break; 1491 case Mips::ATOMIC_LOAD_ADD_I64: 1492 AtomicOp = Mips::ATOMIC_LOAD_ADD_I64_POSTRA; 1493 break; 1494 case Mips::ATOMIC_LOAD_SUB_I64: 1495 AtomicOp = Mips::ATOMIC_LOAD_SUB_I64_POSTRA; 1496 break; 1497 case Mips::ATOMIC_LOAD_AND_I64: 1498 AtomicOp = Mips::ATOMIC_LOAD_AND_I64_POSTRA; 1499 break; 1500 case Mips::ATOMIC_LOAD_OR_I64: 1501 AtomicOp = Mips::ATOMIC_LOAD_OR_I64_POSTRA; 1502 break; 1503 case Mips::ATOMIC_LOAD_XOR_I64: 1504 AtomicOp = Mips::ATOMIC_LOAD_XOR_I64_POSTRA; 1505 break; 1506 case Mips::ATOMIC_LOAD_NAND_I64: 1507 AtomicOp = Mips::ATOMIC_LOAD_NAND_I64_POSTRA; 1508 break; 1509 case Mips::ATOMIC_SWAP_I64: 1510 AtomicOp = Mips::ATOMIC_SWAP_I64_POSTRA; 1511 break; 1512 case Mips::ATOMIC_LOAD_MIN_I32: 1513 AtomicOp = Mips::ATOMIC_LOAD_MIN_I32_POSTRA; 1514 NeedsAdditionalReg = true; 1515 break; 1516 case Mips::ATOMIC_LOAD_MAX_I32: 1517 AtomicOp = Mips::ATOMIC_LOAD_MAX_I32_POSTRA; 1518 NeedsAdditionalReg = true; 1519 break; 1520 case Mips::ATOMIC_LOAD_UMIN_I32: 1521 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I32_POSTRA; 1522 NeedsAdditionalReg = true; 1523 break; 1524 case Mips::ATOMIC_LOAD_UMAX_I32: 1525 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I32_POSTRA; 1526 NeedsAdditionalReg = true; 1527 break; 1528 case Mips::ATOMIC_LOAD_MIN_I64: 1529 AtomicOp = Mips::ATOMIC_LOAD_MIN_I64_POSTRA; 1530 NeedsAdditionalReg = true; 1531 break; 1532 case Mips::ATOMIC_LOAD_MAX_I64: 1533 AtomicOp = Mips::ATOMIC_LOAD_MAX_I64_POSTRA; 1534 NeedsAdditionalReg = true; 1535 break; 1536 case Mips::ATOMIC_LOAD_UMIN_I64: 1537 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I64_POSTRA; 1538 NeedsAdditionalReg = true; 1539 break; 1540 case Mips::ATOMIC_LOAD_UMAX_I64: 1541 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I64_POSTRA; 1542 NeedsAdditionalReg = true; 1543 break; 1544 default: 1545 llvm_unreachable("Unknown pseudo atomic for replacement!"); 1546 } 1547 1548 Register OldVal = MI.getOperand(0).getReg(); 1549 Register Ptr = MI.getOperand(1).getReg(); 1550 Register Incr = MI.getOperand(2).getReg(); 1551 Register Scratch = RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal)); 1552 1553 MachineBasicBlock::iterator II(MI); 1554 1555 // The scratch registers here with the EarlyClobber | Define | Implicit 1556 // flags is used to persuade the register allocator and the machine 1557 // verifier to accept the usage of this register. This has to be a real 1558 // register which has an UNDEF value but is dead after the instruction which 1559 // is unique among the registers chosen for the instruction. 1560 1561 // The EarlyClobber flag has the semantic properties that the operand it is 1562 // attached to is clobbered before the rest of the inputs are read. Hence it 1563 // must be unique among the operands to the instruction. 1564 // The Define flag is needed to coerce the machine verifier that an Undef 1565 // value isn't a problem. 1566 // The Dead flag is needed as the value in scratch isn't used by any other 1567 // instruction. Kill isn't used as Dead is more precise. 1568 // The implicit flag is here due to the interaction between the other flags 1569 // and the machine verifier. 1570 1571 // For correctness purpose, a new pseudo is introduced here. We need this 1572 // new pseudo, so that FastRegisterAllocator does not see an ll/sc sequence 1573 // that is spread over >1 basic blocks. A register allocator which 1574 // introduces (or any codegen infact) a store, can violate the expectations 1575 // of the hardware. 1576 // 1577 // An atomic read-modify-write sequence starts with a linked load 1578 // instruction and ends with a store conditional instruction. The atomic 1579 // read-modify-write sequence fails if any of the following conditions 1580 // occur between the execution of ll and sc: 1581 // * A coherent store is completed by another process or coherent I/O 1582 // module into the block of synchronizable physical memory containing 1583 // the word. The size and alignment of the block is 1584 // implementation-dependent. 1585 // * A coherent store is executed between an LL and SC sequence on the 1586 // same processor to the block of synchornizable physical memory 1587 // containing the word. 1588 // 1589 1590 Register PtrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Ptr)); 1591 Register IncrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Incr)); 1592 1593 BuildMI(*BB, II, DL, TII->get(Mips::COPY), IncrCopy).addReg(Incr); 1594 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr); 1595 1596 MachineInstrBuilder MIB = 1597 BuildMI(*BB, II, DL, TII->get(AtomicOp)) 1598 .addReg(OldVal, RegState::Define | RegState::EarlyClobber) 1599 .addReg(PtrCopy) 1600 .addReg(IncrCopy) 1601 .addReg(Scratch, RegState::Define | RegState::EarlyClobber | 1602 RegState::Implicit | RegState::Dead); 1603 if (NeedsAdditionalReg) { 1604 Register Scratch2 = 1605 RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal)); 1606 MIB.addReg(Scratch2, RegState::Define | RegState::EarlyClobber | 1607 RegState::Implicit | RegState::Dead); 1608 } 1609 1610 MI.eraseFromParent(); 1611 1612 return BB; 1613 } 1614 1615 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg( 1616 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg, 1617 unsigned SrcReg) const { 1618 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1619 const DebugLoc &DL = MI.getDebugLoc(); 1620 1621 if (Subtarget.hasMips32r2() && Size == 1) { 1622 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); 1623 return BB; 1624 } 1625 1626 if (Subtarget.hasMips32r2() && Size == 2) { 1627 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg); 1628 return BB; 1629 } 1630 1631 MachineFunction *MF = BB->getParent(); 1632 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1633 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1634 Register ScrReg = RegInfo.createVirtualRegister(RC); 1635 1636 assert(Size < 32); 1637 int64_t ShiftImm = 32 - (Size * 8); 1638 1639 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); 1640 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); 1641 1642 return BB; 1643 } 1644 1645 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword( 1646 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const { 1647 assert((Size == 1 || Size == 2) && 1648 "Unsupported size for EmitAtomicBinaryPartial."); 1649 1650 MachineFunction *MF = BB->getParent(); 1651 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1652 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1653 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1654 const TargetRegisterClass *RCp = 1655 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1656 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1657 DebugLoc DL = MI.getDebugLoc(); 1658 1659 Register Dest = MI.getOperand(0).getReg(); 1660 Register Ptr = MI.getOperand(1).getReg(); 1661 Register Incr = MI.getOperand(2).getReg(); 1662 1663 Register AlignedAddr = RegInfo.createVirtualRegister(RCp); 1664 Register ShiftAmt = RegInfo.createVirtualRegister(RC); 1665 Register Mask = RegInfo.createVirtualRegister(RC); 1666 Register Mask2 = RegInfo.createVirtualRegister(RC); 1667 Register Incr2 = RegInfo.createVirtualRegister(RC); 1668 Register MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1669 Register PtrLSB2 = RegInfo.createVirtualRegister(RC); 1670 Register MaskUpper = RegInfo.createVirtualRegister(RC); 1671 Register Scratch = RegInfo.createVirtualRegister(RC); 1672 Register Scratch2 = RegInfo.createVirtualRegister(RC); 1673 Register Scratch3 = RegInfo.createVirtualRegister(RC); 1674 1675 unsigned AtomicOp = 0; 1676 bool NeedsAdditionalReg = false; 1677 switch (MI.getOpcode()) { 1678 case Mips::ATOMIC_LOAD_NAND_I8: 1679 AtomicOp = Mips::ATOMIC_LOAD_NAND_I8_POSTRA; 1680 break; 1681 case Mips::ATOMIC_LOAD_NAND_I16: 1682 AtomicOp = Mips::ATOMIC_LOAD_NAND_I16_POSTRA; 1683 break; 1684 case Mips::ATOMIC_SWAP_I8: 1685 AtomicOp = Mips::ATOMIC_SWAP_I8_POSTRA; 1686 break; 1687 case Mips::ATOMIC_SWAP_I16: 1688 AtomicOp = Mips::ATOMIC_SWAP_I16_POSTRA; 1689 break; 1690 case Mips::ATOMIC_LOAD_ADD_I8: 1691 AtomicOp = Mips::ATOMIC_LOAD_ADD_I8_POSTRA; 1692 break; 1693 case Mips::ATOMIC_LOAD_ADD_I16: 1694 AtomicOp = Mips::ATOMIC_LOAD_ADD_I16_POSTRA; 1695 break; 1696 case Mips::ATOMIC_LOAD_SUB_I8: 1697 AtomicOp = Mips::ATOMIC_LOAD_SUB_I8_POSTRA; 1698 break; 1699 case Mips::ATOMIC_LOAD_SUB_I16: 1700 AtomicOp = Mips::ATOMIC_LOAD_SUB_I16_POSTRA; 1701 break; 1702 case Mips::ATOMIC_LOAD_AND_I8: 1703 AtomicOp = Mips::ATOMIC_LOAD_AND_I8_POSTRA; 1704 break; 1705 case Mips::ATOMIC_LOAD_AND_I16: 1706 AtomicOp = Mips::ATOMIC_LOAD_AND_I16_POSTRA; 1707 break; 1708 case Mips::ATOMIC_LOAD_OR_I8: 1709 AtomicOp = Mips::ATOMIC_LOAD_OR_I8_POSTRA; 1710 break; 1711 case Mips::ATOMIC_LOAD_OR_I16: 1712 AtomicOp = Mips::ATOMIC_LOAD_OR_I16_POSTRA; 1713 break; 1714 case Mips::ATOMIC_LOAD_XOR_I8: 1715 AtomicOp = Mips::ATOMIC_LOAD_XOR_I8_POSTRA; 1716 break; 1717 case Mips::ATOMIC_LOAD_XOR_I16: 1718 AtomicOp = Mips::ATOMIC_LOAD_XOR_I16_POSTRA; 1719 break; 1720 case Mips::ATOMIC_LOAD_MIN_I8: 1721 AtomicOp = Mips::ATOMIC_LOAD_MIN_I8_POSTRA; 1722 NeedsAdditionalReg = true; 1723 break; 1724 case Mips::ATOMIC_LOAD_MIN_I16: 1725 AtomicOp = Mips::ATOMIC_LOAD_MIN_I16_POSTRA; 1726 NeedsAdditionalReg = true; 1727 break; 1728 case Mips::ATOMIC_LOAD_MAX_I8: 1729 AtomicOp = Mips::ATOMIC_LOAD_MAX_I8_POSTRA; 1730 NeedsAdditionalReg = true; 1731 break; 1732 case Mips::ATOMIC_LOAD_MAX_I16: 1733 AtomicOp = Mips::ATOMIC_LOAD_MAX_I16_POSTRA; 1734 NeedsAdditionalReg = true; 1735 break; 1736 case Mips::ATOMIC_LOAD_UMIN_I8: 1737 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I8_POSTRA; 1738 NeedsAdditionalReg = true; 1739 break; 1740 case Mips::ATOMIC_LOAD_UMIN_I16: 1741 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I16_POSTRA; 1742 NeedsAdditionalReg = true; 1743 break; 1744 case Mips::ATOMIC_LOAD_UMAX_I8: 1745 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I8_POSTRA; 1746 NeedsAdditionalReg = true; 1747 break; 1748 case Mips::ATOMIC_LOAD_UMAX_I16: 1749 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I16_POSTRA; 1750 NeedsAdditionalReg = true; 1751 break; 1752 default: 1753 llvm_unreachable("Unknown subword atomic pseudo for expansion!"); 1754 } 1755 1756 // insert new blocks after the current block 1757 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1758 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1759 MachineFunction::iterator It = ++BB->getIterator(); 1760 MF->insert(It, exitMBB); 1761 1762 // Transfer the remainder of BB and its successor edges to exitMBB. 1763 exitMBB->splice(exitMBB->begin(), BB, 1764 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1765 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1766 1767 BB->addSuccessor(exitMBB, BranchProbability::getOne()); 1768 1769 // thisMBB: 1770 // addiu masklsb2,$0,-4 # 0xfffffffc 1771 // and alignedaddr,ptr,masklsb2 1772 // andi ptrlsb2,ptr,3 1773 // sll shiftamt,ptrlsb2,3 1774 // ori maskupper,$0,255 # 0xff 1775 // sll mask,maskupper,shiftamt 1776 // nor mask2,$0,mask 1777 // sll incr2,incr,shiftamt 1778 1779 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1780 BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2) 1781 .addReg(ABI.GetNullPtr()).addImm(-4); 1782 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr) 1783 .addReg(Ptr).addReg(MaskLSB2); 1784 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1785 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1786 if (Subtarget.isLittle()) { 1787 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1788 } else { 1789 Register Off = RegInfo.createVirtualRegister(RC); 1790 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1791 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1792 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1793 } 1794 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1795 .addReg(Mips::ZERO).addImm(MaskImm); 1796 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1797 .addReg(MaskUpper).addReg(ShiftAmt); 1798 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1799 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1800 1801 1802 // The purposes of the flags on the scratch registers is explained in 1803 // emitAtomicBinary. In summary, we need a scratch register which is going to 1804 // be undef, that is unique among registers chosen for the instruction. 1805 1806 MachineInstrBuilder MIB = 1807 BuildMI(BB, DL, TII->get(AtomicOp)) 1808 .addReg(Dest, RegState::Define | RegState::EarlyClobber) 1809 .addReg(AlignedAddr) 1810 .addReg(Incr2) 1811 .addReg(Mask) 1812 .addReg(Mask2) 1813 .addReg(ShiftAmt) 1814 .addReg(Scratch, RegState::EarlyClobber | RegState::Define | 1815 RegState::Dead | RegState::Implicit) 1816 .addReg(Scratch2, RegState::EarlyClobber | RegState::Define | 1817 RegState::Dead | RegState::Implicit) 1818 .addReg(Scratch3, RegState::EarlyClobber | RegState::Define | 1819 RegState::Dead | RegState::Implicit); 1820 if (NeedsAdditionalReg) { 1821 Register Scratch4 = RegInfo.createVirtualRegister(RC); 1822 MIB.addReg(Scratch4, RegState::EarlyClobber | RegState::Define | 1823 RegState::Dead | RegState::Implicit); 1824 } 1825 1826 MI.eraseFromParent(); // The instruction is gone now. 1827 1828 return exitMBB; 1829 } 1830 1831 // Lower atomic compare and swap to a pseudo instruction, taking care to 1832 // define a scratch register for the pseudo instruction's expansion. The 1833 // instruction is expanded after the register allocator as to prevent 1834 // the insertion of stores between the linked load and the store conditional. 1835 1836 MachineBasicBlock * 1837 MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI, 1838 MachineBasicBlock *BB) const { 1839 1840 assert((MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 || 1841 MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I64) && 1842 "Unsupported atomic pseudo for EmitAtomicCmpSwap."); 1843 1844 const unsigned Size = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ? 4 : 8; 1845 1846 MachineFunction *MF = BB->getParent(); 1847 MachineRegisterInfo &MRI = MF->getRegInfo(); 1848 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1849 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1850 DebugLoc DL = MI.getDebugLoc(); 1851 1852 unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 1853 ? Mips::ATOMIC_CMP_SWAP_I32_POSTRA 1854 : Mips::ATOMIC_CMP_SWAP_I64_POSTRA; 1855 Register Dest = MI.getOperand(0).getReg(); 1856 Register Ptr = MI.getOperand(1).getReg(); 1857 Register OldVal = MI.getOperand(2).getReg(); 1858 Register NewVal = MI.getOperand(3).getReg(); 1859 1860 Register Scratch = MRI.createVirtualRegister(RC); 1861 MachineBasicBlock::iterator II(MI); 1862 1863 // We need to create copies of the various registers and kill them at the 1864 // atomic pseudo. If the copies are not made, when the atomic is expanded 1865 // after fast register allocation, the spills will end up outside of the 1866 // blocks that their values are defined in, causing livein errors. 1867 1868 Register PtrCopy = MRI.createVirtualRegister(MRI.getRegClass(Ptr)); 1869 Register OldValCopy = MRI.createVirtualRegister(MRI.getRegClass(OldVal)); 1870 Register NewValCopy = MRI.createVirtualRegister(MRI.getRegClass(NewVal)); 1871 1872 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr); 1873 BuildMI(*BB, II, DL, TII->get(Mips::COPY), OldValCopy).addReg(OldVal); 1874 BuildMI(*BB, II, DL, TII->get(Mips::COPY), NewValCopy).addReg(NewVal); 1875 1876 // The purposes of the flags on the scratch registers is explained in 1877 // emitAtomicBinary. In summary, we need a scratch register which is going to 1878 // be undef, that is unique among registers chosen for the instruction. 1879 1880 BuildMI(*BB, II, DL, TII->get(AtomicOp)) 1881 .addReg(Dest, RegState::Define | RegState::EarlyClobber) 1882 .addReg(PtrCopy, RegState::Kill) 1883 .addReg(OldValCopy, RegState::Kill) 1884 .addReg(NewValCopy, RegState::Kill) 1885 .addReg(Scratch, RegState::EarlyClobber | RegState::Define | 1886 RegState::Dead | RegState::Implicit); 1887 1888 MI.eraseFromParent(); // The instruction is gone now. 1889 1890 return BB; 1891 } 1892 1893 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword( 1894 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const { 1895 assert((Size == 1 || Size == 2) && 1896 "Unsupported size for EmitAtomicCmpSwapPartial."); 1897 1898 MachineFunction *MF = BB->getParent(); 1899 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1900 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1901 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1902 const TargetRegisterClass *RCp = 1903 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1904 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1905 DebugLoc DL = MI.getDebugLoc(); 1906 1907 Register Dest = MI.getOperand(0).getReg(); 1908 Register Ptr = MI.getOperand(1).getReg(); 1909 Register CmpVal = MI.getOperand(2).getReg(); 1910 Register NewVal = MI.getOperand(3).getReg(); 1911 1912 Register AlignedAddr = RegInfo.createVirtualRegister(RCp); 1913 Register ShiftAmt = RegInfo.createVirtualRegister(RC); 1914 Register Mask = RegInfo.createVirtualRegister(RC); 1915 Register Mask2 = RegInfo.createVirtualRegister(RC); 1916 Register ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1917 Register ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1918 Register MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1919 Register PtrLSB2 = RegInfo.createVirtualRegister(RC); 1920 Register MaskUpper = RegInfo.createVirtualRegister(RC); 1921 Register MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1922 Register MaskedNewVal = RegInfo.createVirtualRegister(RC); 1923 unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I8 1924 ? Mips::ATOMIC_CMP_SWAP_I8_POSTRA 1925 : Mips::ATOMIC_CMP_SWAP_I16_POSTRA; 1926 1927 // The scratch registers here with the EarlyClobber | Define | Dead | Implicit 1928 // flags are used to coerce the register allocator and the machine verifier to 1929 // accept the usage of these registers. 1930 // The EarlyClobber flag has the semantic properties that the operand it is 1931 // attached to is clobbered before the rest of the inputs are read. Hence it 1932 // must be unique among the operands to the instruction. 1933 // The Define flag is needed to coerce the machine verifier that an Undef 1934 // value isn't a problem. 1935 // The Dead flag is needed as the value in scratch isn't used by any other 1936 // instruction. Kill isn't used as Dead is more precise. 1937 Register Scratch = RegInfo.createVirtualRegister(RC); 1938 Register Scratch2 = RegInfo.createVirtualRegister(RC); 1939 1940 // insert new blocks after the current block 1941 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1942 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1943 MachineFunction::iterator It = ++BB->getIterator(); 1944 MF->insert(It, exitMBB); 1945 1946 // Transfer the remainder of BB and its successor edges to exitMBB. 1947 exitMBB->splice(exitMBB->begin(), BB, 1948 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1949 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1950 1951 BB->addSuccessor(exitMBB, BranchProbability::getOne()); 1952 1953 // thisMBB: 1954 // addiu masklsb2,$0,-4 # 0xfffffffc 1955 // and alignedaddr,ptr,masklsb2 1956 // andi ptrlsb2,ptr,3 1957 // xori ptrlsb2,ptrlsb2,3 # Only for BE 1958 // sll shiftamt,ptrlsb2,3 1959 // ori maskupper,$0,255 # 0xff 1960 // sll mask,maskupper,shiftamt 1961 // nor mask2,$0,mask 1962 // andi maskedcmpval,cmpval,255 1963 // sll shiftedcmpval,maskedcmpval,shiftamt 1964 // andi maskednewval,newval,255 1965 // sll shiftednewval,maskednewval,shiftamt 1966 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1967 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2) 1968 .addReg(ABI.GetNullPtr()).addImm(-4); 1969 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) 1970 .addReg(Ptr).addReg(MaskLSB2); 1971 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1972 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1973 if (Subtarget.isLittle()) { 1974 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1975 } else { 1976 Register Off = RegInfo.createVirtualRegister(RC); 1977 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1978 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1979 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1980 } 1981 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1982 .addReg(Mips::ZERO).addImm(MaskImm); 1983 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1984 .addReg(MaskUpper).addReg(ShiftAmt); 1985 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1986 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) 1987 .addReg(CmpVal).addImm(MaskImm); 1988 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) 1989 .addReg(MaskedCmpVal).addReg(ShiftAmt); 1990 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) 1991 .addReg(NewVal).addImm(MaskImm); 1992 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) 1993 .addReg(MaskedNewVal).addReg(ShiftAmt); 1994 1995 // The purposes of the flags on the scratch registers are explained in 1996 // emitAtomicBinary. In summary, we need a scratch register which is going to 1997 // be undef, that is unique among the register chosen for the instruction. 1998 1999 BuildMI(BB, DL, TII->get(AtomicOp)) 2000 .addReg(Dest, RegState::Define | RegState::EarlyClobber) 2001 .addReg(AlignedAddr) 2002 .addReg(Mask) 2003 .addReg(ShiftedCmpVal) 2004 .addReg(Mask2) 2005 .addReg(ShiftedNewVal) 2006 .addReg(ShiftAmt) 2007 .addReg(Scratch, RegState::EarlyClobber | RegState::Define | 2008 RegState::Dead | RegState::Implicit) 2009 .addReg(Scratch2, RegState::EarlyClobber | RegState::Define | 2010 RegState::Dead | RegState::Implicit); 2011 2012 MI.eraseFromParent(); // The instruction is gone now. 2013 2014 return exitMBB; 2015 } 2016 2017 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 2018 // The first operand is the chain, the second is the condition, the third is 2019 // the block to branch to if the condition is true. 2020 SDValue Chain = Op.getOperand(0); 2021 SDValue Dest = Op.getOperand(2); 2022 SDLoc DL(Op); 2023 2024 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 2025 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); 2026 2027 // Return if flag is not set by a floating point comparison. 2028 if (CondRes.getOpcode() != MipsISD::FPCmp) 2029 return Op; 2030 2031 SDValue CCNode = CondRes.getOperand(2); 2032 Mips::CondCode CC = 2033 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 2034 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; 2035 SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32); 2036 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 2037 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, 2038 FCC0, Dest, CondRes); 2039 } 2040 2041 SDValue MipsTargetLowering:: 2042 lowerSELECT(SDValue Op, SelectionDAG &DAG) const 2043 { 2044 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 2045 SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); 2046 2047 // Return if flag is not set by a floating point comparison. 2048 if (Cond.getOpcode() != MipsISD::FPCmp) 2049 return Op; 2050 2051 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 2052 SDLoc(Op)); 2053 } 2054 2055 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { 2056 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 2057 SDValue Cond = createFPCmp(DAG, Op); 2058 2059 assert(Cond.getOpcode() == MipsISD::FPCmp && 2060 "Floating point operand expected."); 2061 2062 SDLoc DL(Op); 2063 SDValue True = DAG.getConstant(1, DL, MVT::i32); 2064 SDValue False = DAG.getConstant(0, DL, MVT::i32); 2065 2066 return createCMovFP(DAG, Cond, True, False, DL); 2067 } 2068 2069 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, 2070 SelectionDAG &DAG) const { 2071 EVT Ty = Op.getValueType(); 2072 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); 2073 const GlobalValue *GV = N->getGlobal(); 2074 2075 if (!isPositionIndependent()) { 2076 const MipsTargetObjectFile *TLOF = 2077 static_cast<const MipsTargetObjectFile *>( 2078 getTargetMachine().getObjFileLowering()); 2079 const GlobalObject *GO = GV->getAliaseeObject(); 2080 if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine())) 2081 // %gp_rel relocation 2082 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); 2083 2084 // %hi/%lo relocation 2085 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2086 // %highest/%higher/%hi/%lo relocation 2087 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2088 } 2089 2090 // Every other architecture would use shouldAssumeDSOLocal in here, but 2091 // mips is special. 2092 // * In PIC code mips requires got loads even for local statics! 2093 // * To save on got entries, for local statics the got entry contains the 2094 // page and an additional add instruction takes care of the low bits. 2095 // * It is legal to access a hidden symbol with a non hidden undefined, 2096 // so one cannot guarantee that all access to a hidden symbol will know 2097 // it is hidden. 2098 // * Mips linkers don't support creating a page and a full got entry for 2099 // the same symbol. 2100 // * Given all that, we have to use a full got entry for hidden symbols :-( 2101 if (GV->hasLocalLinkage()) 2102 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2103 2104 if (Subtarget.useXGOT()) 2105 return getAddrGlobalLargeGOT( 2106 N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16, 2107 DAG.getEntryNode(), 2108 MachinePointerInfo::getGOT(DAG.getMachineFunction())); 2109 2110 return getAddrGlobal( 2111 N, SDLoc(N), Ty, DAG, 2112 (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT, 2113 DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction())); 2114 } 2115 2116 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, 2117 SelectionDAG &DAG) const { 2118 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); 2119 EVT Ty = Op.getValueType(); 2120 2121 if (!isPositionIndependent()) 2122 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2123 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2124 2125 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2126 } 2127 2128 SDValue MipsTargetLowering:: 2129 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 2130 { 2131 // If the relocation model is PIC, use the General Dynamic TLS Model or 2132 // Local Dynamic TLS model, otherwise use the Initial Exec or 2133 // Local Exec TLS Model. 2134 2135 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 2136 if (DAG.getTarget().useEmulatedTLS()) 2137 return LowerToTLSEmulatedModel(GA, DAG); 2138 2139 SDLoc DL(GA); 2140 const GlobalValue *GV = GA->getGlobal(); 2141 EVT PtrVT = getPointerTy(DAG.getDataLayout()); 2142 2143 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 2144 2145 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 2146 // General Dynamic and Local Dynamic TLS Model. 2147 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 2148 : MipsII::MO_TLSGD; 2149 2150 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); 2151 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, 2152 getGlobalReg(DAG, PtrVT), TGA); 2153 unsigned PtrSize = PtrVT.getSizeInBits(); 2154 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 2155 2156 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 2157 2158 ArgListTy Args; 2159 ArgListEntry Entry; 2160 Entry.Node = Argument; 2161 Entry.Ty = PtrTy; 2162 Args.push_back(Entry); 2163 2164 TargetLowering::CallLoweringInfo CLI(DAG); 2165 CLI.setDebugLoc(DL) 2166 .setChain(DAG.getEntryNode()) 2167 .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args)); 2168 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 2169 2170 SDValue Ret = CallResult.first; 2171 2172 if (model != TLSModel::LocalDynamic) 2173 return Ret; 2174 2175 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2176 MipsII::MO_DTPREL_HI); 2177 SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi); 2178 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2179 MipsII::MO_DTPREL_LO); 2180 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 2181 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); 2182 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); 2183 } 2184 2185 SDValue Offset; 2186 if (model == TLSModel::InitialExec) { 2187 // Initial Exec TLS Model 2188 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2189 MipsII::MO_GOTTPREL); 2190 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), 2191 TGA); 2192 Offset = 2193 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo()); 2194 } else { 2195 // Local Exec TLS Model 2196 assert(model == TLSModel::LocalExec); 2197 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2198 MipsII::MO_TPREL_HI); 2199 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2200 MipsII::MO_TPREL_LO); 2201 SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi); 2202 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 2203 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 2204 } 2205 2206 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); 2207 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); 2208 } 2209 2210 SDValue MipsTargetLowering:: 2211 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const 2212 { 2213 JumpTableSDNode *N = cast<JumpTableSDNode>(Op); 2214 EVT Ty = Op.getValueType(); 2215 2216 if (!isPositionIndependent()) 2217 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2218 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2219 2220 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2221 } 2222 2223 SDValue MipsTargetLowering:: 2224 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const 2225 { 2226 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 2227 EVT Ty = Op.getValueType(); 2228 2229 if (!isPositionIndependent()) { 2230 const MipsTargetObjectFile *TLOF = 2231 static_cast<const MipsTargetObjectFile *>( 2232 getTargetMachine().getObjFileLowering()); 2233 2234 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(), 2235 getTargetMachine())) 2236 // %gp_rel relocation 2237 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); 2238 2239 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2240 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2241 } 2242 2243 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2244 } 2245 2246 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 2247 MachineFunction &MF = DAG.getMachineFunction(); 2248 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2249 2250 SDLoc DL(Op); 2251 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 2252 getPointerTy(MF.getDataLayout())); 2253 2254 // vastart just stores the address of the VarArgsFrameIndex slot into the 2255 // memory location argument. 2256 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2257 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 2258 MachinePointerInfo(SV)); 2259 } 2260 2261 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const { 2262 SDNode *Node = Op.getNode(); 2263 EVT VT = Node->getValueType(0); 2264 SDValue Chain = Node->getOperand(0); 2265 SDValue VAListPtr = Node->getOperand(1); 2266 const Align Align = 2267 llvm::MaybeAlign(Node->getConstantOperandVal(3)).valueOrOne(); 2268 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2269 SDLoc DL(Node); 2270 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4; 2271 2272 SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, 2273 VAListPtr, MachinePointerInfo(SV)); 2274 SDValue VAList = VAListLoad; 2275 2276 // Re-align the pointer if necessary. 2277 // It should only ever be necessary for 64-bit types on O32 since the minimum 2278 // argument alignment is the same as the maximum type alignment for N32/N64. 2279 // 2280 // FIXME: We currently align too often. The code generator doesn't notice 2281 // when the pointer is still aligned from the last va_arg (or pair of 2282 // va_args for the i64 on O32 case). 2283 if (Align > getMinStackArgumentAlignment()) { 2284 VAList = DAG.getNode( 2285 ISD::ADD, DL, VAList.getValueType(), VAList, 2286 DAG.getConstant(Align.value() - 1, DL, VAList.getValueType())); 2287 2288 VAList = DAG.getNode( 2289 ISD::AND, DL, VAList.getValueType(), VAList, 2290 DAG.getConstant(-(int64_t)Align.value(), DL, VAList.getValueType())); 2291 } 2292 2293 // Increment the pointer, VAList, to the next vaarg. 2294 auto &TD = DAG.getDataLayout(); 2295 unsigned ArgSizeInBytes = 2296 TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())); 2297 SDValue Tmp3 = 2298 DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 2299 DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes), 2300 DL, VAList.getValueType())); 2301 // Store the incremented VAList to the legalized pointer 2302 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, 2303 MachinePointerInfo(SV)); 2304 2305 // In big-endian mode we must adjust the pointer when the load size is smaller 2306 // than the argument slot size. We must also reduce the known alignment to 2307 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get 2308 // the correct half of the slot, and reduce the alignment from 8 (slot 2309 // alignment) down to 4 (type alignment). 2310 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) { 2311 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes; 2312 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList, 2313 DAG.getIntPtrConstant(Adjustment, DL)); 2314 } 2315 // Load the actual argument out of the pointer VAList 2316 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo()); 2317 } 2318 2319 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, 2320 bool HasExtractInsert) { 2321 EVT TyX = Op.getOperand(0).getValueType(); 2322 EVT TyY = Op.getOperand(1).getValueType(); 2323 SDLoc DL(Op); 2324 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2325 SDValue Const31 = DAG.getConstant(31, DL, MVT::i32); 2326 SDValue Res; 2327 2328 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2329 // to i32. 2330 SDValue X = (TyX == MVT::f32) ? 2331 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 2332 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 2333 Const1); 2334 SDValue Y = (TyY == MVT::f32) ? 2335 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 2336 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 2337 Const1); 2338 2339 if (HasExtractInsert) { 2340 // ext E, Y, 31, 1 ; extract bit31 of Y 2341 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 2342 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 2343 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 2344 } else { 2345 // sll SllX, X, 1 2346 // srl SrlX, SllX, 1 2347 // srl SrlY, Y, 31 2348 // sll SllY, SrlX, 31 2349 // or Or, SrlX, SllY 2350 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2351 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2352 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 2353 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 2354 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 2355 } 2356 2357 if (TyX == MVT::f32) 2358 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 2359 2360 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2361 Op.getOperand(0), 2362 DAG.getConstant(0, DL, MVT::i32)); 2363 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2364 } 2365 2366 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, 2367 bool HasExtractInsert) { 2368 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 2369 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 2370 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 2371 SDLoc DL(Op); 2372 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2373 2374 // Bitcast to integer nodes. 2375 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 2376 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 2377 2378 if (HasExtractInsert) { 2379 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 2380 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 2381 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 2382 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1); 2383 2384 if (WidthX > WidthY) 2385 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 2386 else if (WidthY > WidthX) 2387 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 2388 2389 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 2390 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1, 2391 X); 2392 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 2393 } 2394 2395 // (d)sll SllX, X, 1 2396 // (d)srl SrlX, SllX, 1 2397 // (d)srl SrlY, Y, width(Y)-1 2398 // (d)sll SllY, SrlX, width(Y)-1 2399 // or Or, SrlX, SllY 2400 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 2401 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 2402 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 2403 DAG.getConstant(WidthY - 1, DL, MVT::i32)); 2404 2405 if (WidthX > WidthY) 2406 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 2407 else if (WidthY > WidthX) 2408 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 2409 2410 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 2411 DAG.getConstant(WidthX - 1, DL, MVT::i32)); 2412 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 2413 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 2414 } 2415 2416 SDValue 2417 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 2418 if (Subtarget.isGP64bit()) 2419 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert()); 2420 2421 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert()); 2422 } 2423 2424 static SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG, 2425 bool HasExtractInsert) { 2426 SDLoc DL(Op); 2427 SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32); 2428 2429 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2430 // to i32. 2431 SDValue X = (Op.getValueType() == MVT::f32) 2432 ? DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) 2433 : DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2434 Op.getOperand(0), Const1); 2435 2436 // Clear MSB. 2437 if (HasExtractInsert) 2438 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, 2439 DAG.getRegister(Mips::ZERO, MVT::i32), 2440 DAG.getConstant(31, DL, MVT::i32), Const1, X); 2441 else { 2442 // TODO: Provide DAG patterns which transform (and x, cst) 2443 // back to a (shl (srl x (clz cst)) (clz cst)) sequence. 2444 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2445 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2446 } 2447 2448 if (Op.getValueType() == MVT::f32) 2449 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res); 2450 2451 // FIXME: For mips32r2, the sequence of (BuildPairF64 (ins (ExtractElementF64 2452 // Op 1), $zero, 31 1) (ExtractElementF64 Op 0)) and the Op has one use, we 2453 // should be able to drop the usage of mfc1/mtc1 and rewrite the register in 2454 // place. 2455 SDValue LowX = 2456 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 2457 DAG.getConstant(0, DL, MVT::i32)); 2458 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2459 } 2460 2461 static SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG, 2462 bool HasExtractInsert) { 2463 SDLoc DL(Op); 2464 SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32); 2465 2466 // Bitcast to integer node. 2467 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0)); 2468 2469 // Clear MSB. 2470 if (HasExtractInsert) 2471 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64, 2472 DAG.getRegister(Mips::ZERO_64, MVT::i64), 2473 DAG.getConstant(63, DL, MVT::i32), Const1, X); 2474 else { 2475 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1); 2476 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); 2477 } 2478 2479 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res); 2480 } 2481 2482 SDValue MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const { 2483 if ((ABI.IsN32() || ABI.IsN64()) && (Op.getValueType() == MVT::f64)) 2484 return lowerFABS64(Op, DAG, Subtarget.hasExtractInsert()); 2485 2486 return lowerFABS32(Op, DAG, Subtarget.hasExtractInsert()); 2487 } 2488 2489 SDValue MipsTargetLowering:: 2490 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2491 // check the depth 2492 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() != 0) { 2493 DAG.getContext()->emitError( 2494 "return address can be determined only for current frame"); 2495 return SDValue(); 2496 } 2497 2498 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2499 MFI.setFrameAddressIsTaken(true); 2500 EVT VT = Op.getValueType(); 2501 SDLoc DL(Op); 2502 SDValue FrameAddr = DAG.getCopyFromReg( 2503 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT); 2504 return FrameAddr; 2505 } 2506 2507 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, 2508 SelectionDAG &DAG) const { 2509 if (verifyReturnAddressArgumentIsConstant(Op, DAG)) 2510 return SDValue(); 2511 2512 // check the depth 2513 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() != 0) { 2514 DAG.getContext()->emitError( 2515 "return address can be determined only for current frame"); 2516 return SDValue(); 2517 } 2518 2519 MachineFunction &MF = DAG.getMachineFunction(); 2520 MachineFrameInfo &MFI = MF.getFrameInfo(); 2521 MVT VT = Op.getSimpleValueType(); 2522 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; 2523 MFI.setReturnAddressIsTaken(true); 2524 2525 // Return RA, which contains the return address. Mark it an implicit live-in. 2526 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 2527 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); 2528 } 2529 2530 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is 2531 // generated from __builtin_eh_return (offset, handler) 2532 // The effect of this is to adjust the stack pointer by "offset" 2533 // and then branch to "handler". 2534 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 2535 const { 2536 MachineFunction &MF = DAG.getMachineFunction(); 2537 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2538 2539 MipsFI->setCallsEhReturn(); 2540 SDValue Chain = Op.getOperand(0); 2541 SDValue Offset = Op.getOperand(1); 2542 SDValue Handler = Op.getOperand(2); 2543 SDLoc DL(Op); 2544 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2545 2546 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 2547 // EH_RETURN nodes, so that instructions are emitted back-to-back. 2548 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; 2549 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 2550 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 2551 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 2552 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 2553 DAG.getRegister(OffsetReg, Ty), 2554 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())), 2555 Chain.getValue(1)); 2556 } 2557 2558 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 2559 SelectionDAG &DAG) const { 2560 // FIXME: Need pseudo-fence for 'singlethread' fences 2561 // FIXME: Set SType for weaker fences where supported/appropriate. 2562 unsigned SType = 0; 2563 SDLoc DL(Op); 2564 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), 2565 DAG.getConstant(SType, DL, MVT::i32)); 2566 } 2567 2568 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 2569 SelectionDAG &DAG) const { 2570 SDLoc DL(Op); 2571 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2572 2573 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2574 SDValue Shamt = Op.getOperand(2); 2575 // if shamt < (VT.bits): 2576 // lo = (shl lo, shamt) 2577 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 2578 // else: 2579 // lo = 0 2580 // hi = (shl lo, shamt[4:0]) 2581 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2582 DAG.getConstant(-1, DL, MVT::i32)); 2583 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, 2584 DAG.getConstant(1, DL, VT)); 2585 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); 2586 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); 2587 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2588 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); 2589 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2590 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2591 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2592 DAG.getConstant(0, DL, VT), ShiftLeftLo); 2593 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or); 2594 2595 SDValue Ops[2] = {Lo, Hi}; 2596 return DAG.getMergeValues(Ops, DL); 2597 } 2598 2599 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2600 bool IsSRA) const { 2601 SDLoc DL(Op); 2602 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2603 SDValue Shamt = Op.getOperand(2); 2604 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2605 2606 // if shamt < (VT.bits): 2607 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 2608 // if isSRA: 2609 // hi = (sra hi, shamt) 2610 // else: 2611 // hi = (srl hi, shamt) 2612 // else: 2613 // if isSRA: 2614 // lo = (sra hi, shamt[4:0]) 2615 // hi = (sra hi, 31) 2616 // else: 2617 // lo = (srl hi, shamt[4:0]) 2618 // hi = 0 2619 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2620 DAG.getConstant(-1, DL, MVT::i32)); 2621 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, 2622 DAG.getConstant(1, DL, VT)); 2623 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not); 2624 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); 2625 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2626 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, 2627 DL, VT, Hi, Shamt); 2628 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2629 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2630 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi, 2631 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT)); 2632 2633 if (!(Subtarget.hasMips4() || Subtarget.hasMips32())) { 2634 SDVTList VTList = DAG.getVTList(VT, VT); 2635 return DAG.getNode(Subtarget.isGP64bit() ? Mips::PseudoD_SELECT_I64 2636 : Mips::PseudoD_SELECT_I, 2637 DL, VTList, Cond, ShiftRightHi, 2638 IsSRA ? Ext : DAG.getConstant(0, DL, VT), Or, 2639 ShiftRightHi); 2640 } 2641 2642 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or); 2643 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2644 IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi); 2645 2646 SDValue Ops[2] = {Lo, Hi}; 2647 return DAG.getMergeValues(Ops, DL); 2648 } 2649 2650 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 2651 SDValue Chain, SDValue Src, unsigned Offset) { 2652 SDValue Ptr = LD->getBasePtr(); 2653 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 2654 EVT BasePtrVT = Ptr.getValueType(); 2655 SDLoc DL(LD); 2656 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 2657 2658 if (Offset) 2659 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2660 DAG.getConstant(Offset, DL, BasePtrVT)); 2661 2662 SDValue Ops[] = { Chain, Ptr, Src }; 2663 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2664 LD->getMemOperand()); 2665 } 2666 2667 // Expand an unaligned 32 or 64-bit integer load node. 2668 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 2669 LoadSDNode *LD = cast<LoadSDNode>(Op); 2670 EVT MemVT = LD->getMemoryVT(); 2671 2672 if (Subtarget.systemSupportsUnalignedAccess()) 2673 return Op; 2674 2675 // Return if load is aligned or if MemVT is neither i32 nor i64. 2676 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2677 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2678 return SDValue(); 2679 2680 bool IsLittle = Subtarget.isLittle(); 2681 EVT VT = Op.getValueType(); 2682 ISD::LoadExtType ExtType = LD->getExtensionType(); 2683 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2684 2685 assert((VT == MVT::i32) || (VT == MVT::i64)); 2686 2687 // Expand 2688 // (set dst, (i64 (load baseptr))) 2689 // to 2690 // (set tmp, (ldl (add baseptr, 7), undef)) 2691 // (set dst, (ldr baseptr, tmp)) 2692 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2693 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2694 IsLittle ? 7 : 0); 2695 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2696 IsLittle ? 0 : 7); 2697 } 2698 2699 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2700 IsLittle ? 3 : 0); 2701 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2702 IsLittle ? 0 : 3); 2703 2704 // Expand 2705 // (set dst, (i32 (load baseptr))) or 2706 // (set dst, (i64 (sextload baseptr))) or 2707 // (set dst, (i64 (extload baseptr))) 2708 // to 2709 // (set tmp, (lwl (add baseptr, 3), undef)) 2710 // (set dst, (lwr baseptr, tmp)) 2711 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2712 (ExtType == ISD::EXTLOAD)) 2713 return LWR; 2714 2715 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2716 2717 // Expand 2718 // (set dst, (i64 (zextload baseptr))) 2719 // to 2720 // (set tmp0, (lwl (add baseptr, 3), undef)) 2721 // (set tmp1, (lwr baseptr, tmp0)) 2722 // (set tmp2, (shl tmp1, 32)) 2723 // (set dst, (srl tmp2, 32)) 2724 SDLoc DL(LD); 2725 SDValue Const32 = DAG.getConstant(32, DL, MVT::i32); 2726 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2727 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2728 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2729 return DAG.getMergeValues(Ops, DL); 2730 } 2731 2732 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2733 SDValue Chain, unsigned Offset) { 2734 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2735 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2736 SDLoc DL(SD); 2737 SDVTList VTList = DAG.getVTList(MVT::Other); 2738 2739 if (Offset) 2740 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2741 DAG.getConstant(Offset, DL, BasePtrVT)); 2742 2743 SDValue Ops[] = { Chain, Value, Ptr }; 2744 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2745 SD->getMemOperand()); 2746 } 2747 2748 // Expand an unaligned 32 or 64-bit integer store node. 2749 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, 2750 bool IsLittle) { 2751 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2752 EVT VT = Value.getValueType(); 2753 2754 // Expand 2755 // (store val, baseptr) or 2756 // (truncstore val, baseptr) 2757 // to 2758 // (swl val, (add baseptr, 3)) 2759 // (swr val, baseptr) 2760 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2761 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, 2762 IsLittle ? 3 : 0); 2763 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2764 } 2765 2766 assert(VT == MVT::i64); 2767 2768 // Expand 2769 // (store val, baseptr) 2770 // to 2771 // (sdl val, (add baseptr, 7)) 2772 // (sdr val, baseptr) 2773 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2774 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2775 } 2776 2777 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2778 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG, 2779 bool SingleFloat) { 2780 SDValue Val = SD->getValue(); 2781 2782 if (Val.getOpcode() != ISD::FP_TO_SINT || 2783 (Val.getValueSizeInBits() > 32 && SingleFloat)) 2784 return SDValue(); 2785 2786 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits()); 2787 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy, 2788 Val.getOperand(0)); 2789 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), 2790 SD->getPointerInfo(), SD->getAlignment(), 2791 SD->getMemOperand()->getFlags()); 2792 } 2793 2794 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2795 StoreSDNode *SD = cast<StoreSDNode>(Op); 2796 EVT MemVT = SD->getMemoryVT(); 2797 2798 // Lower unaligned integer stores. 2799 if (!Subtarget.systemSupportsUnalignedAccess() && 2800 (SD->getAlignment() < MemVT.getSizeInBits() / 8) && 2801 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) 2802 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle()); 2803 2804 return lowerFP_TO_SINT_STORE(SD, DAG, Subtarget.isSingleFloat()); 2805 } 2806 2807 SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op, 2808 SelectionDAG &DAG) const { 2809 2810 // Return a fixed StackObject with offset 0 which points to the old stack 2811 // pointer. 2812 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2813 EVT ValTy = Op->getValueType(0); 2814 int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2815 return DAG.getFrameIndex(FI, ValTy); 2816 } 2817 2818 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, 2819 SelectionDAG &DAG) const { 2820 if (Op.getValueSizeInBits() > 32 && Subtarget.isSingleFloat()) 2821 return SDValue(); 2822 2823 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits()); 2824 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy, 2825 Op.getOperand(0)); 2826 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc); 2827 } 2828 2829 //===----------------------------------------------------------------------===// 2830 // Calling Convention Implementation 2831 //===----------------------------------------------------------------------===// 2832 2833 //===----------------------------------------------------------------------===// 2834 // TODO: Implement a generic logic using tblgen that can support this. 2835 // Mips O32 ABI rules: 2836 // --- 2837 // i32 - Passed in A0, A1, A2, A3 and stack 2838 // f32 - Only passed in f32 registers if no int reg has been used yet to hold 2839 // an argument. Otherwise, passed in A1, A2, A3 and stack. 2840 // f64 - Only passed in two aliased f32 registers if no int reg has been used 2841 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2842 // not used, it must be shadowed. If only A3 is available, shadow it and 2843 // go to stack. 2844 // vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack. 2845 // vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3} 2846 // with the remainder spilled to the stack. 2847 // vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases 2848 // spilling the remainder to the stack. 2849 // 2850 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2851 //===----------------------------------------------------------------------===// 2852 2853 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2854 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2855 CCState &State, ArrayRef<MCPhysReg> F64Regs) { 2856 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>( 2857 State.getMachineFunction().getSubtarget()); 2858 2859 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 }; 2860 2861 const MipsCCState * MipsState = static_cast<MipsCCState *>(&State); 2862 2863 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 }; 2864 2865 static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 }; 2866 2867 // Do not process byval args here. 2868 if (ArgFlags.isByVal()) 2869 return true; 2870 2871 // Promote i8 and i16 2872 if (ArgFlags.isInReg() && !Subtarget.isLittle()) { 2873 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) { 2874 LocVT = MVT::i32; 2875 if (ArgFlags.isSExt()) 2876 LocInfo = CCValAssign::SExtUpper; 2877 else if (ArgFlags.isZExt()) 2878 LocInfo = CCValAssign::ZExtUpper; 2879 else 2880 LocInfo = CCValAssign::AExtUpper; 2881 } 2882 } 2883 2884 // Promote i8 and i16 2885 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2886 LocVT = MVT::i32; 2887 if (ArgFlags.isSExt()) 2888 LocInfo = CCValAssign::SExt; 2889 else if (ArgFlags.isZExt()) 2890 LocInfo = CCValAssign::ZExt; 2891 else 2892 LocInfo = CCValAssign::AExt; 2893 } 2894 2895 unsigned Reg; 2896 2897 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2898 // is true: function is vararg, argument is 3rd or higher, there is previous 2899 // argument which is not f32 or f64. 2900 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 || 2901 State.getFirstUnallocated(F32Regs) != ValNo; 2902 Align OrigAlign = ArgFlags.getNonZeroOrigAlign(); 2903 bool isI64 = (ValVT == MVT::i32 && OrigAlign == Align(8)); 2904 bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo); 2905 2906 // The MIPS vector ABI for floats passes them in a pair of registers 2907 if (ValVT == MVT::i32 && isVectorFloat) { 2908 // This is the start of an vector that was scalarized into an unknown number 2909 // of components. It doesn't matter how many there are. Allocate one of the 2910 // notional 8 byte aligned registers which map onto the argument stack, and 2911 // shadow the register lost to alignment requirements. 2912 if (ArgFlags.isSplit()) { 2913 Reg = State.AllocateReg(FloatVectorIntRegs); 2914 if (Reg == Mips::A2) 2915 State.AllocateReg(Mips::A1); 2916 else if (Reg == 0) 2917 State.AllocateReg(Mips::A3); 2918 } else { 2919 // If we're an intermediate component of the split, we can just attempt to 2920 // allocate a register directly. 2921 Reg = State.AllocateReg(IntRegs); 2922 } 2923 } else if (ValVT == MVT::i32 || 2924 (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2925 Reg = State.AllocateReg(IntRegs); 2926 // If this is the first part of an i64 arg, 2927 // the allocated register must be either A0 or A2. 2928 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2929 Reg = State.AllocateReg(IntRegs); 2930 LocVT = MVT::i32; 2931 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2932 LocVT = MVT::i32; 2933 2934 // Allocate int register and shadow next int register. If first 2935 // available register is Mips::A1 or Mips::A3, shadow it too. 2936 Reg = State.AllocateReg(IntRegs); 2937 if (Reg == Mips::A1 || Reg == Mips::A3) 2938 Reg = State.AllocateReg(IntRegs); 2939 2940 if (Reg) { 2941 State.addLoc( 2942 CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2943 MCRegister HiReg = State.AllocateReg(IntRegs); 2944 assert(HiReg); 2945 State.addLoc( 2946 CCValAssign::getCustomReg(ValNo, ValVT, HiReg, LocVT, LocInfo)); 2947 return false; 2948 } 2949 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2950 // we are guaranteed to find an available float register 2951 if (ValVT == MVT::f32) { 2952 Reg = State.AllocateReg(F32Regs); 2953 // Shadow int register 2954 State.AllocateReg(IntRegs); 2955 } else { 2956 Reg = State.AllocateReg(F64Regs); 2957 // Shadow int registers 2958 unsigned Reg2 = State.AllocateReg(IntRegs); 2959 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2960 State.AllocateReg(IntRegs); 2961 State.AllocateReg(IntRegs); 2962 } 2963 } else 2964 llvm_unreachable("Cannot handle this ValVT."); 2965 2966 if (!Reg) { 2967 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(), OrigAlign); 2968 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2969 } else 2970 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2971 2972 return false; 2973 } 2974 2975 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, 2976 MVT LocVT, CCValAssign::LocInfo LocInfo, 2977 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2978 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 }; 2979 2980 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2981 } 2982 2983 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, 2984 MVT LocVT, CCValAssign::LocInfo LocInfo, 2985 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2986 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 }; 2987 2988 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2989 } 2990 2991 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2992 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2993 CCState &State) LLVM_ATTRIBUTE_UNUSED; 2994 2995 #include "MipsGenCallingConv.inc" 2996 2997 CCAssignFn *MipsTargetLowering::CCAssignFnForCall() const{ 2998 return CC_Mips_FixedArg; 2999 } 3000 3001 CCAssignFn *MipsTargetLowering::CCAssignFnForReturn() const{ 3002 return RetCC_Mips; 3003 } 3004 //===----------------------------------------------------------------------===// 3005 // Call Calling Convention Implementation 3006 //===----------------------------------------------------------------------===// 3007 3008 SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 3009 SDValue Chain, SDValue Arg, 3010 const SDLoc &DL, bool IsTailCall, 3011 SelectionDAG &DAG) const { 3012 if (!IsTailCall) { 3013 SDValue PtrOff = 3014 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr, 3015 DAG.getIntPtrConstant(Offset, DL)); 3016 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()); 3017 } 3018 3019 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 3020 int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 3021 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3022 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), MaybeAlign(), 3023 MachineMemOperand::MOVolatile); 3024 } 3025 3026 void MipsTargetLowering:: 3027 getOpndList(SmallVectorImpl<SDValue> &Ops, 3028 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 3029 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 3030 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 3031 SDValue Chain) const { 3032 // Insert node "GP copy globalreg" before call to function. 3033 // 3034 // R_MIPS_CALL* operators (emitted when non-internal functions are called 3035 // in PIC mode) allow symbols to be resolved via lazy binding. 3036 // The lazy binding stub requires GP to point to the GOT. 3037 // Note that we don't need GP to point to the GOT for indirect calls 3038 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates 3039 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs 3040 // used for the function (that is, Mips linker doesn't generate lazy binding 3041 // stub for a function whose address is taken in the program). 3042 if (IsPICCall && !InternalLinkage && IsCallReloc) { 3043 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP; 3044 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 3045 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); 3046 } 3047 3048 // Build a sequence of copy-to-reg nodes chained together with token 3049 // chain and flag operands which copy the outgoing args into registers. 3050 // The InFlag in necessary since all emitted instructions must be 3051 // stuck together. 3052 SDValue InFlag; 3053 3054 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 3055 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first, 3056 RegsToPass[i].second, InFlag); 3057 InFlag = Chain.getValue(1); 3058 } 3059 3060 // Add argument registers to the end of the list so that they are 3061 // known live into the call. 3062 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 3063 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first, 3064 RegsToPass[i].second.getValueType())); 3065 3066 // Add a register mask operand representing the call-preserved registers. 3067 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 3068 const uint32_t *Mask = 3069 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv); 3070 assert(Mask && "Missing call preserved mask for calling convention"); 3071 if (Subtarget.inMips16HardFloat()) { 3072 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 3073 StringRef Sym = G->getGlobal()->getName(); 3074 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 3075 if (F && F->hasFnAttribute("__Mips16RetHelper")) { 3076 Mask = MipsRegisterInfo::getMips16RetHelperMask(); 3077 } 3078 } 3079 } 3080 Ops.push_back(CLI.DAG.getRegisterMask(Mask)); 3081 3082 if (InFlag.getNode()) 3083 Ops.push_back(InFlag); 3084 } 3085 3086 void MipsTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI, 3087 SDNode *Node) const { 3088 switch (MI.getOpcode()) { 3089 default: 3090 return; 3091 case Mips::JALR: 3092 case Mips::JALRPseudo: 3093 case Mips::JALR64: 3094 case Mips::JALR64Pseudo: 3095 case Mips::JALR16_MM: 3096 case Mips::JALRC16_MMR6: 3097 case Mips::TAILCALLREG: 3098 case Mips::TAILCALLREG64: 3099 case Mips::TAILCALLR6REG: 3100 case Mips::TAILCALL64R6REG: 3101 case Mips::TAILCALLREG_MM: 3102 case Mips::TAILCALLREG_MMR6: { 3103 if (!EmitJalrReloc || 3104 Subtarget.inMips16Mode() || 3105 !isPositionIndependent() || 3106 Node->getNumOperands() < 1 || 3107 Node->getOperand(0).getNumOperands() < 2) { 3108 return; 3109 } 3110 // We are after the callee address, set by LowerCall(). 3111 // If added to MI, asm printer will emit .reloc R_MIPS_JALR for the 3112 // symbol. 3113 const SDValue TargetAddr = Node->getOperand(0).getOperand(1); 3114 StringRef Sym; 3115 if (const GlobalAddressSDNode *G = 3116 dyn_cast_or_null<const GlobalAddressSDNode>(TargetAddr)) { 3117 // We must not emit the R_MIPS_JALR relocation against data symbols 3118 // since this will cause run-time crashes if the linker replaces the 3119 // call instruction with a relative branch to the data symbol. 3120 if (!isa<Function>(G->getGlobal())) { 3121 LLVM_DEBUG(dbgs() << "Not adding R_MIPS_JALR against data symbol " 3122 << G->getGlobal()->getName() << "\n"); 3123 return; 3124 } 3125 Sym = G->getGlobal()->getName(); 3126 } 3127 else if (const ExternalSymbolSDNode *ES = 3128 dyn_cast_or_null<const ExternalSymbolSDNode>(TargetAddr)) { 3129 Sym = ES->getSymbol(); 3130 } 3131 3132 if (Sym.empty()) 3133 return; 3134 3135 MachineFunction *MF = MI.getParent()->getParent(); 3136 MCSymbol *S = MF->getContext().getOrCreateSymbol(Sym); 3137 LLVM_DEBUG(dbgs() << "Adding R_MIPS_JALR against " << Sym << "\n"); 3138 MI.addOperand(MachineOperand::CreateMCSymbol(S, MipsII::MO_JALR)); 3139 } 3140 } 3141 } 3142 3143 /// LowerCall - functions arguments are copied from virtual regs to 3144 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 3145 SDValue 3146 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 3147 SmallVectorImpl<SDValue> &InVals) const { 3148 SelectionDAG &DAG = CLI.DAG; 3149 SDLoc DL = CLI.DL; 3150 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 3151 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 3152 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 3153 SDValue Chain = CLI.Chain; 3154 SDValue Callee = CLI.Callee; 3155 bool &IsTailCall = CLI.IsTailCall; 3156 CallingConv::ID CallConv = CLI.CallConv; 3157 bool IsVarArg = CLI.IsVarArg; 3158 3159 MachineFunction &MF = DAG.getMachineFunction(); 3160 MachineFrameInfo &MFI = MF.getFrameInfo(); 3161 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 3162 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 3163 bool IsPIC = isPositionIndependent(); 3164 3165 // Analyze operands of the call, assigning locations to each operand. 3166 SmallVector<CCValAssign, 16> ArgLocs; 3167 MipsCCState CCInfo( 3168 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(), 3169 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget)); 3170 3171 const ExternalSymbolSDNode *ES = 3172 dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode()); 3173 3174 // There is one case where CALLSEQ_START..CALLSEQ_END can be nested, which 3175 // is during the lowering of a call with a byval argument which produces 3176 // a call to memcpy. For the O32 case, this causes the caller to allocate 3177 // stack space for the reserved argument area for the callee, then recursively 3178 // again for the memcpy call. In the NEWABI case, this doesn't occur as those 3179 // ABIs mandate that the callee allocates the reserved argument area. We do 3180 // still produce nested CALLSEQ_START..CALLSEQ_END with zero space though. 3181 // 3182 // If the callee has a byval argument and memcpy is used, we are mandated 3183 // to already have produced a reserved argument area for the callee for O32. 3184 // Therefore, the reserved argument area can be reused for both calls. 3185 // 3186 // Other cases of calling memcpy cannot have a chain with a CALLSEQ_START 3187 // present, as we have yet to hook that node onto the chain. 3188 // 3189 // Hence, the CALLSEQ_START and CALLSEQ_END nodes can be eliminated in this 3190 // case. GCC does a similar trick, in that wherever possible, it calculates 3191 // the maximum out going argument area (including the reserved area), and 3192 // preallocates the stack space on entrance to the caller. 3193 // 3194 // FIXME: We should do the same for efficiency and space. 3195 3196 // Note: The check on the calling convention below must match 3197 // MipsABIInfo::GetCalleeAllocdArgSizeInBytes(). 3198 bool MemcpyInByVal = ES && 3199 StringRef(ES->getSymbol()) == StringRef("memcpy") && 3200 CallConv != CallingConv::Fast && 3201 Chain.getOpcode() == ISD::CALLSEQ_START; 3202 3203 // Allocate the reserved argument area. It seems strange to do this from the 3204 // caller side but removing it breaks the frame size calculation. 3205 unsigned ReservedArgArea = 3206 MemcpyInByVal ? 0 : ABI.GetCalleeAllocdArgSizeInBytes(CallConv); 3207 CCInfo.AllocateStack(ReservedArgArea, Align(1)); 3208 3209 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), 3210 ES ? ES->getSymbol() : nullptr); 3211 3212 // Get a count of how many bytes are to be pushed on the stack. 3213 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 3214 3215 // Call site info for function parameters tracking. 3216 MachineFunction::CallSiteInfo CSInfo; 3217 3218 // Check if it's really possible to do a tail call. Restrict it to functions 3219 // that are part of this compilation unit. 3220 bool InternalLinkage = false; 3221 if (IsTailCall) { 3222 IsTailCall = isEligibleForTailCallOptimization( 3223 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>()); 3224 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3225 InternalLinkage = G->getGlobal()->hasInternalLinkage(); 3226 IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() || 3227 G->getGlobal()->hasPrivateLinkage() || 3228 G->getGlobal()->hasHiddenVisibility() || 3229 G->getGlobal()->hasProtectedVisibility()); 3230 } 3231 } 3232 if (!IsTailCall && CLI.CB && CLI.CB->isMustTailCall()) 3233 report_fatal_error("failed to perform tail call elimination on a call " 3234 "site marked musttail"); 3235 3236 if (IsTailCall) 3237 ++NumTailCalls; 3238 3239 // Chain is the output chain of the last Load/Store or CopyToReg node. 3240 // ByValChain is the output chain of the last Memcpy node created for copying 3241 // byval arguments to the stack. 3242 unsigned StackAlignment = TFL->getStackAlignment(); 3243 NextStackOffset = alignTo(NextStackOffset, StackAlignment); 3244 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true); 3245 3246 if (!(IsTailCall || MemcpyInByVal)) 3247 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL); 3248 3249 SDValue StackPtr = 3250 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP, 3251 getPointerTy(DAG.getDataLayout())); 3252 3253 std::deque<std::pair<unsigned, SDValue>> RegsToPass; 3254 SmallVector<SDValue, 8> MemOpChains; 3255 3256 CCInfo.rewindByValRegsInfo(); 3257 3258 // Walk the register/memloc assignments, inserting copies/loads. 3259 for (unsigned i = 0, e = ArgLocs.size(), OutIdx = 0; i != e; ++i, ++OutIdx) { 3260 SDValue Arg = OutVals[OutIdx]; 3261 CCValAssign &VA = ArgLocs[i]; 3262 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 3263 ISD::ArgFlagsTy Flags = Outs[OutIdx].Flags; 3264 bool UseUpperBits = false; 3265 3266 // ByVal Arg. 3267 if (Flags.isByVal()) { 3268 unsigned FirstByValReg, LastByValReg; 3269 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 3270 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 3271 3272 assert(Flags.getByValSize() && 3273 "ByVal args of size 0 should have been ignored by front-end."); 3274 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 3275 assert(!IsTailCall && 3276 "Do not tail-call optimize if there is a byval argument."); 3277 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 3278 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(), 3279 VA); 3280 CCInfo.nextInRegsParam(); 3281 continue; 3282 } 3283 3284 // Promote the value if needed. 3285 switch (VA.getLocInfo()) { 3286 default: 3287 llvm_unreachable("Unknown loc info!"); 3288 case CCValAssign::Full: 3289 if (VA.isRegLoc()) { 3290 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 3291 (ValVT == MVT::f64 && LocVT == MVT::i64) || 3292 (ValVT == MVT::i64 && LocVT == MVT::f64)) 3293 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 3294 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 3295 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 3296 Arg, DAG.getConstant(0, DL, MVT::i32)); 3297 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 3298 Arg, DAG.getConstant(1, DL, MVT::i32)); 3299 if (!Subtarget.isLittle()) 3300 std::swap(Lo, Hi); 3301 3302 assert(VA.needsCustom()); 3303 3304 Register LocRegLo = VA.getLocReg(); 3305 Register LocRegHigh = ArgLocs[++i].getLocReg(); 3306 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 3307 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 3308 continue; 3309 } 3310 } 3311 break; 3312 case CCValAssign::BCvt: 3313 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 3314 break; 3315 case CCValAssign::SExtUpper: 3316 UseUpperBits = true; 3317 LLVM_FALLTHROUGH; 3318 case CCValAssign::SExt: 3319 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); 3320 break; 3321 case CCValAssign::ZExtUpper: 3322 UseUpperBits = true; 3323 LLVM_FALLTHROUGH; 3324 case CCValAssign::ZExt: 3325 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); 3326 break; 3327 case CCValAssign::AExtUpper: 3328 UseUpperBits = true; 3329 LLVM_FALLTHROUGH; 3330 case CCValAssign::AExt: 3331 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); 3332 break; 3333 } 3334 3335 if (UseUpperBits) { 3336 unsigned ValSizeInBits = Outs[OutIdx].ArgVT.getSizeInBits(); 3337 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3338 Arg = DAG.getNode( 3339 ISD::SHL, DL, VA.getLocVT(), Arg, 3340 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3341 } 3342 3343 // Arguments that can be passed on register must be kept at 3344 // RegsToPass vector 3345 if (VA.isRegLoc()) { 3346 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 3347 3348 // If the parameter is passed through reg $D, which splits into 3349 // two physical registers, avoid creating call site info. 3350 if (Mips::AFGR64RegClass.contains(VA.getLocReg())) 3351 continue; 3352 3353 // Collect CSInfo about which register passes which parameter. 3354 const TargetOptions &Options = DAG.getTarget().Options; 3355 if (Options.SupportsDebugEntryValues) 3356 CSInfo.emplace_back(VA.getLocReg(), i); 3357 3358 continue; 3359 } 3360 3361 // Register can't get to this point... 3362 assert(VA.isMemLoc()); 3363 3364 // emit ISD::STORE whichs stores the 3365 // parameter value to a stack Location 3366 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 3367 Chain, Arg, DL, IsTailCall, DAG)); 3368 } 3369 3370 // Transform all store nodes into one single node because all store 3371 // nodes are independent of each other. 3372 if (!MemOpChains.empty()) 3373 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); 3374 3375 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 3376 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 3377 // node so that legalize doesn't hack it. 3378 3379 EVT Ty = Callee.getValueType(); 3380 bool GlobalOrExternal = false, IsCallReloc = false; 3381 3382 // The long-calls feature is ignored in case of PIC. 3383 // While we do not support -mshared / -mno-shared properly, 3384 // ignore long-calls in case of -mabicalls too. 3385 if (!Subtarget.isABICalls() && !IsPIC) { 3386 // If the function should be called using "long call", 3387 // get its address into a register to prevent using 3388 // of the `jal` instruction for the direct call. 3389 if (auto *N = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3390 if (Subtarget.useLongCalls()) 3391 Callee = Subtarget.hasSym32() 3392 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 3393 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 3394 } else if (auto *N = dyn_cast<GlobalAddressSDNode>(Callee)) { 3395 bool UseLongCalls = Subtarget.useLongCalls(); 3396 // If the function has long-call/far/near attribute 3397 // it overrides command line switch pased to the backend. 3398 if (auto *F = dyn_cast<Function>(N->getGlobal())) { 3399 if (F->hasFnAttribute("long-call")) 3400 UseLongCalls = true; 3401 else if (F->hasFnAttribute("short-call")) 3402 UseLongCalls = false; 3403 } 3404 if (UseLongCalls) 3405 Callee = Subtarget.hasSym32() 3406 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 3407 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 3408 } 3409 } 3410 3411 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3412 if (IsPIC) { 3413 const GlobalValue *Val = G->getGlobal(); 3414 InternalLinkage = Val->hasInternalLinkage(); 3415 3416 if (InternalLinkage) 3417 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64()); 3418 else if (Subtarget.useXGOT()) { 3419 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16, 3420 MipsII::MO_CALL_LO16, Chain, 3421 FuncInfo->callPtrInfo(MF, Val)); 3422 IsCallReloc = true; 3423 } else { 3424 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 3425 FuncInfo->callPtrInfo(MF, Val)); 3426 IsCallReloc = true; 3427 } 3428 } else 3429 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, 3430 getPointerTy(DAG.getDataLayout()), 0, 3431 MipsII::MO_NO_FLAG); 3432 GlobalOrExternal = true; 3433 } 3434 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3435 const char *Sym = S->getSymbol(); 3436 3437 if (!IsPIC) // static 3438 Callee = DAG.getTargetExternalSymbol( 3439 Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG); 3440 else if (Subtarget.useXGOT()) { 3441 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16, 3442 MipsII::MO_CALL_LO16, Chain, 3443 FuncInfo->callPtrInfo(MF, Sym)); 3444 IsCallReloc = true; 3445 } else { // PIC 3446 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 3447 FuncInfo->callPtrInfo(MF, Sym)); 3448 IsCallReloc = true; 3449 } 3450 3451 GlobalOrExternal = true; 3452 } 3453 3454 SmallVector<SDValue, 8> Ops(1, Chain); 3455 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 3456 3457 getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage, 3458 IsCallReloc, CLI, Callee, Chain); 3459 3460 if (IsTailCall) { 3461 MF.getFrameInfo().setHasTailCall(); 3462 SDValue Ret = DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops); 3463 DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo)); 3464 return Ret; 3465 } 3466 3467 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops); 3468 SDValue InFlag = Chain.getValue(1); 3469 3470 DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo)); 3471 3472 // Create the CALLSEQ_END node in the case of where it is not a call to 3473 // memcpy. 3474 if (!(MemcpyInByVal)) { 3475 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 3476 DAG.getIntPtrConstant(0, DL, true), InFlag, DL); 3477 InFlag = Chain.getValue(1); 3478 } 3479 3480 // Handle result values, copying them out of physregs into vregs that we 3481 // return. 3482 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG, 3483 InVals, CLI); 3484 } 3485 3486 /// LowerCallResult - Lower the result values of a call into the 3487 /// appropriate copies out of appropriate physical registers. 3488 SDValue MipsTargetLowering::LowerCallResult( 3489 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, 3490 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3491 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, 3492 TargetLowering::CallLoweringInfo &CLI) const { 3493 // Assign locations to each value returned by this call. 3494 SmallVector<CCValAssign, 16> RVLocs; 3495 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 3496 *DAG.getContext()); 3497 3498 const ExternalSymbolSDNode *ES = 3499 dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.Callee.getNode()); 3500 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.RetTy, 3501 ES ? ES->getSymbol() : nullptr); 3502 3503 // Copy all of the result registers out of their specified physreg. 3504 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3505 CCValAssign &VA = RVLocs[i]; 3506 assert(VA.isRegLoc() && "Can only return in registers!"); 3507 3508 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 3509 RVLocs[i].getLocVT(), InFlag); 3510 Chain = Val.getValue(1); 3511 InFlag = Val.getValue(2); 3512 3513 if (VA.isUpperBitsInLoc()) { 3514 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits(); 3515 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3516 unsigned Shift = 3517 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 3518 Val = DAG.getNode( 3519 Shift, DL, VA.getLocVT(), Val, 3520 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3521 } 3522 3523 switch (VA.getLocInfo()) { 3524 default: 3525 llvm_unreachable("Unknown loc info!"); 3526 case CCValAssign::Full: 3527 break; 3528 case CCValAssign::BCvt: 3529 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); 3530 break; 3531 case CCValAssign::AExt: 3532 case CCValAssign::AExtUpper: 3533 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3534 break; 3535 case CCValAssign::ZExt: 3536 case CCValAssign::ZExtUpper: 3537 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, 3538 DAG.getValueType(VA.getValVT())); 3539 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3540 break; 3541 case CCValAssign::SExt: 3542 case CCValAssign::SExtUpper: 3543 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, 3544 DAG.getValueType(VA.getValVT())); 3545 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3546 break; 3547 } 3548 3549 InVals.push_back(Val); 3550 } 3551 3552 return Chain; 3553 } 3554 3555 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, 3556 EVT ArgVT, const SDLoc &DL, 3557 SelectionDAG &DAG) { 3558 MVT LocVT = VA.getLocVT(); 3559 EVT ValVT = VA.getValVT(); 3560 3561 // Shift into the upper bits if necessary. 3562 switch (VA.getLocInfo()) { 3563 default: 3564 break; 3565 case CCValAssign::AExtUpper: 3566 case CCValAssign::SExtUpper: 3567 case CCValAssign::ZExtUpper: { 3568 unsigned ValSizeInBits = ArgVT.getSizeInBits(); 3569 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3570 unsigned Opcode = 3571 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 3572 Val = DAG.getNode( 3573 Opcode, DL, VA.getLocVT(), Val, 3574 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3575 break; 3576 } 3577 } 3578 3579 // If this is an value smaller than the argument slot size (32-bit for O32, 3580 // 64-bit for N32/N64), it has been promoted in some way to the argument slot 3581 // size. Extract the value and insert any appropriate assertions regarding 3582 // sign/zero extension. 3583 switch (VA.getLocInfo()) { 3584 default: 3585 llvm_unreachable("Unknown loc info!"); 3586 case CCValAssign::Full: 3587 break; 3588 case CCValAssign::AExtUpper: 3589 case CCValAssign::AExt: 3590 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3591 break; 3592 case CCValAssign::SExtUpper: 3593 case CCValAssign::SExt: 3594 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3595 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3596 break; 3597 case CCValAssign::ZExtUpper: 3598 case CCValAssign::ZExt: 3599 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3600 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3601 break; 3602 case CCValAssign::BCvt: 3603 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val); 3604 break; 3605 } 3606 3607 return Val; 3608 } 3609 3610 //===----------------------------------------------------------------------===// 3611 // Formal Arguments Calling Convention Implementation 3612 //===----------------------------------------------------------------------===// 3613 /// LowerFormalArguments - transform physical registers into virtual registers 3614 /// and generate load operations for arguments places on the stack. 3615 SDValue MipsTargetLowering::LowerFormalArguments( 3616 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 3617 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3618 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 3619 MachineFunction &MF = DAG.getMachineFunction(); 3620 MachineFrameInfo &MFI = MF.getFrameInfo(); 3621 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3622 3623 MipsFI->setVarArgsFrameIndex(0); 3624 3625 // Used with vargs to acumulate store chains. 3626 std::vector<SDValue> OutChains; 3627 3628 // Assign locations to all of the incoming arguments. 3629 SmallVector<CCValAssign, 16> ArgLocs; 3630 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, 3631 *DAG.getContext()); 3632 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), Align(1)); 3633 const Function &Func = DAG.getMachineFunction().getFunction(); 3634 Function::const_arg_iterator FuncArg = Func.arg_begin(); 3635 3636 if (Func.hasFnAttribute("interrupt") && !Func.arg_empty()) 3637 report_fatal_error( 3638 "Functions with the interrupt attribute cannot have arguments!"); 3639 3640 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg); 3641 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 3642 CCInfo.getInRegsParamsCount() > 0); 3643 3644 unsigned CurArgIdx = 0; 3645 CCInfo.rewindByValRegsInfo(); 3646 3647 for (unsigned i = 0, e = ArgLocs.size(), InsIdx = 0; i != e; ++i, ++InsIdx) { 3648 CCValAssign &VA = ArgLocs[i]; 3649 if (Ins[InsIdx].isOrigArg()) { 3650 std::advance(FuncArg, Ins[InsIdx].getOrigArgIndex() - CurArgIdx); 3651 CurArgIdx = Ins[InsIdx].getOrigArgIndex(); 3652 } 3653 EVT ValVT = VA.getValVT(); 3654 ISD::ArgFlagsTy Flags = Ins[InsIdx].Flags; 3655 bool IsRegLoc = VA.isRegLoc(); 3656 3657 if (Flags.isByVal()) { 3658 assert(Ins[InsIdx].isOrigArg() && "Byval arguments cannot be implicit"); 3659 unsigned FirstByValReg, LastByValReg; 3660 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 3661 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 3662 3663 assert(Flags.getByValSize() && 3664 "ByVal args of size 0 should have been ignored by front-end."); 3665 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 3666 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, 3667 FirstByValReg, LastByValReg, VA, CCInfo); 3668 CCInfo.nextInRegsParam(); 3669 continue; 3670 } 3671 3672 // Arguments stored on registers 3673 if (IsRegLoc) { 3674 MVT RegVT = VA.getLocVT(); 3675 Register ArgReg = VA.getLocReg(); 3676 const TargetRegisterClass *RC = getRegClassFor(RegVT); 3677 3678 // Transform the arguments stored on 3679 // physical registers into virtual ones 3680 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); 3681 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 3682 3683 ArgValue = 3684 UnpackFromArgumentSlot(ArgValue, VA, Ins[InsIdx].ArgVT, DL, DAG); 3685 3686 // Handle floating point arguments passed in integer registers and 3687 // long double arguments passed in floating point registers. 3688 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 3689 (RegVT == MVT::i64 && ValVT == MVT::f64) || 3690 (RegVT == MVT::f64 && ValVT == MVT::i64)) 3691 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); 3692 else if (ABI.IsO32() && RegVT == MVT::i32 && 3693 ValVT == MVT::f64) { 3694 assert(VA.needsCustom() && "Expected custom argument for f64 split"); 3695 CCValAssign &NextVA = ArgLocs[++i]; 3696 unsigned Reg2 = 3697 addLiveIn(DAG.getMachineFunction(), NextVA.getLocReg(), RC); 3698 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); 3699 if (!Subtarget.isLittle()) 3700 std::swap(ArgValue, ArgValue2); 3701 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, 3702 ArgValue, ArgValue2); 3703 } 3704 3705 InVals.push_back(ArgValue); 3706 } else { // VA.isRegLoc() 3707 MVT LocVT = VA.getLocVT(); 3708 3709 assert(!VA.needsCustom() && "unexpected custom memory argument"); 3710 3711 if (ABI.IsO32()) { 3712 // We ought to be able to use LocVT directly but O32 sets it to i32 3713 // when allocating floating point values to integer registers. 3714 // This shouldn't influence how we load the value into registers unless 3715 // we are targeting softfloat. 3716 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat()) 3717 LocVT = VA.getValVT(); 3718 } 3719 3720 // Only arguments pased on the stack should make it here. 3721 assert(VA.isMemLoc()); 3722 3723 // The stack pointer offset is relative to the caller stack frame. 3724 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8, 3725 VA.getLocMemOffset(), true); 3726 3727 // Create load nodes to retrieve arguments from the stack 3728 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3729 SDValue ArgValue = DAG.getLoad( 3730 LocVT, DL, Chain, FIN, 3731 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)); 3732 OutChains.push_back(ArgValue.getValue(1)); 3733 3734 ArgValue = 3735 UnpackFromArgumentSlot(ArgValue, VA, Ins[InsIdx].ArgVT, DL, DAG); 3736 3737 InVals.push_back(ArgValue); 3738 } 3739 } 3740 3741 for (unsigned i = 0, e = ArgLocs.size(), InsIdx = 0; i != e; ++i, ++InsIdx) { 3742 3743 if (ArgLocs[i].needsCustom()) { 3744 ++i; 3745 continue; 3746 } 3747 3748 // The mips ABIs for returning structs by value requires that we copy 3749 // the sret argument into $v0 for the return. Save the argument into 3750 // a virtual register so that we can access it from the return points. 3751 if (Ins[InsIdx].Flags.isSRet()) { 3752 unsigned Reg = MipsFI->getSRetReturnReg(); 3753 if (!Reg) { 3754 Reg = MF.getRegInfo().createVirtualRegister( 3755 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); 3756 MipsFI->setSRetReturnReg(Reg); 3757 } 3758 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]); 3759 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); 3760 break; 3761 } 3762 } 3763 3764 if (IsVarArg) 3765 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo); 3766 3767 // All stores are grouped in one node to allow the matching between 3768 // the size of Ins and InVals. This only happens when on varg functions 3769 if (!OutChains.empty()) { 3770 OutChains.push_back(Chain); 3771 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); 3772 } 3773 3774 return Chain; 3775 } 3776 3777 //===----------------------------------------------------------------------===// 3778 // Return Value Calling Convention Implementation 3779 //===----------------------------------------------------------------------===// 3780 3781 bool 3782 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 3783 MachineFunction &MF, bool IsVarArg, 3784 const SmallVectorImpl<ISD::OutputArg> &Outs, 3785 LLVMContext &Context) const { 3786 SmallVector<CCValAssign, 16> RVLocs; 3787 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 3788 return CCInfo.CheckReturn(Outs, RetCC_Mips); 3789 } 3790 3791 bool MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, 3792 bool IsSigned) const { 3793 if ((ABI.IsN32() || ABI.IsN64()) && Type == MVT::i32) 3794 return true; 3795 3796 return IsSigned; 3797 } 3798 3799 SDValue 3800 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, 3801 const SDLoc &DL, 3802 SelectionDAG &DAG) const { 3803 MachineFunction &MF = DAG.getMachineFunction(); 3804 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3805 3806 MipsFI->setISR(); 3807 3808 return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps); 3809 } 3810 3811 SDValue 3812 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 3813 bool IsVarArg, 3814 const SmallVectorImpl<ISD::OutputArg> &Outs, 3815 const SmallVectorImpl<SDValue> &OutVals, 3816 const SDLoc &DL, SelectionDAG &DAG) const { 3817 // CCValAssign - represent the assignment of 3818 // the return value to a location 3819 SmallVector<CCValAssign, 16> RVLocs; 3820 MachineFunction &MF = DAG.getMachineFunction(); 3821 3822 // CCState - Info about the registers and stack slot. 3823 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 3824 3825 // Analyze return values. 3826 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 3827 3828 SDValue Flag; 3829 SmallVector<SDValue, 4> RetOps(1, Chain); 3830 3831 // Copy the result values into the output registers. 3832 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3833 SDValue Val = OutVals[i]; 3834 CCValAssign &VA = RVLocs[i]; 3835 assert(VA.isRegLoc() && "Can only return in registers!"); 3836 bool UseUpperBits = false; 3837 3838 switch (VA.getLocInfo()) { 3839 default: 3840 llvm_unreachable("Unknown loc info!"); 3841 case CCValAssign::Full: 3842 break; 3843 case CCValAssign::BCvt: 3844 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val); 3845 break; 3846 case CCValAssign::AExtUpper: 3847 UseUpperBits = true; 3848 LLVM_FALLTHROUGH; 3849 case CCValAssign::AExt: 3850 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val); 3851 break; 3852 case CCValAssign::ZExtUpper: 3853 UseUpperBits = true; 3854 LLVM_FALLTHROUGH; 3855 case CCValAssign::ZExt: 3856 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val); 3857 break; 3858 case CCValAssign::SExtUpper: 3859 UseUpperBits = true; 3860 LLVM_FALLTHROUGH; 3861 case CCValAssign::SExt: 3862 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val); 3863 break; 3864 } 3865 3866 if (UseUpperBits) { 3867 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 3868 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3869 Val = DAG.getNode( 3870 ISD::SHL, DL, VA.getLocVT(), Val, 3871 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3872 } 3873 3874 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); 3875 3876 // Guarantee that all emitted copies are stuck together with flags. 3877 Flag = Chain.getValue(1); 3878 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 3879 } 3880 3881 // The mips ABIs for returning structs by value requires that we copy 3882 // the sret argument into $v0 for the return. We saved the argument into 3883 // a virtual register in the entry block, so now we copy the value out 3884 // and into $v0. 3885 if (MF.getFunction().hasStructRetAttr()) { 3886 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3887 unsigned Reg = MipsFI->getSRetReturnReg(); 3888 3889 if (!Reg) 3890 llvm_unreachable("sret virtual register not created in the entry block"); 3891 SDValue Val = 3892 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout())); 3893 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 3894 3895 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); 3896 Flag = Chain.getValue(1); 3897 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout()))); 3898 } 3899 3900 RetOps[0] = Chain; // Update chain. 3901 3902 // Add the flag if we have it. 3903 if (Flag.getNode()) 3904 RetOps.push_back(Flag); 3905 3906 // ISRs must use "eret". 3907 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt")) 3908 return LowerInterruptReturn(RetOps, DL, DAG); 3909 3910 // Standard return on Mips is a "jr $ra" 3911 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps); 3912 } 3913 3914 //===----------------------------------------------------------------------===// 3915 // Mips Inline Assembly Support 3916 //===----------------------------------------------------------------------===// 3917 3918 /// getConstraintType - Given a constraint letter, return the type of 3919 /// constraint it is for this target. 3920 MipsTargetLowering::ConstraintType 3921 MipsTargetLowering::getConstraintType(StringRef Constraint) const { 3922 // Mips specific constraints 3923 // GCC config/mips/constraints.md 3924 // 3925 // 'd' : An address register. Equivalent to r 3926 // unless generating MIPS16 code. 3927 // 'y' : Equivalent to r; retained for 3928 // backwards compatibility. 3929 // 'c' : A register suitable for use in an indirect 3930 // jump. This will always be $25 for -mabicalls. 3931 // 'l' : The lo register. 1 word storage. 3932 // 'x' : The hilo register pair. Double word storage. 3933 if (Constraint.size() == 1) { 3934 switch (Constraint[0]) { 3935 default : break; 3936 case 'd': 3937 case 'y': 3938 case 'f': 3939 case 'c': 3940 case 'l': 3941 case 'x': 3942 return C_RegisterClass; 3943 case 'R': 3944 return C_Memory; 3945 } 3946 } 3947 3948 if (Constraint == "ZC") 3949 return C_Memory; 3950 3951 return TargetLowering::getConstraintType(Constraint); 3952 } 3953 3954 /// Examine constraint type and operand type and determine a weight value. 3955 /// This object must already have been set up with the operand type 3956 /// and the current alternative constraint selected. 3957 TargetLowering::ConstraintWeight 3958 MipsTargetLowering::getSingleConstraintMatchWeight( 3959 AsmOperandInfo &info, const char *constraint) const { 3960 ConstraintWeight weight = CW_Invalid; 3961 Value *CallOperandVal = info.CallOperandVal; 3962 // If we don't have a value, we can't do a match, 3963 // but allow it at the lowest weight. 3964 if (!CallOperandVal) 3965 return CW_Default; 3966 Type *type = CallOperandVal->getType(); 3967 // Look at the constraint type. 3968 switch (*constraint) { 3969 default: 3970 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3971 break; 3972 case 'd': 3973 case 'y': 3974 if (type->isIntegerTy()) 3975 weight = CW_Register; 3976 break; 3977 case 'f': // FPU or MSA register 3978 if (Subtarget.hasMSA() && type->isVectorTy() && 3979 type->getPrimitiveSizeInBits().getFixedSize() == 128) 3980 weight = CW_Register; 3981 else if (type->isFloatTy()) 3982 weight = CW_Register; 3983 break; 3984 case 'c': // $25 for indirect jumps 3985 case 'l': // lo register 3986 case 'x': // hilo register pair 3987 if (type->isIntegerTy()) 3988 weight = CW_SpecificReg; 3989 break; 3990 case 'I': // signed 16 bit immediate 3991 case 'J': // integer zero 3992 case 'K': // unsigned 16 bit immediate 3993 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3994 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3995 case 'O': // signed 15 bit immediate (+- 16383) 3996 case 'P': // immediate in the range of 65535 to 1 (inclusive) 3997 if (isa<ConstantInt>(CallOperandVal)) 3998 weight = CW_Constant; 3999 break; 4000 case 'R': 4001 weight = CW_Memory; 4002 break; 4003 } 4004 return weight; 4005 } 4006 4007 /// This is a helper function to parse a physical register string and split it 4008 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag 4009 /// that is returned indicates whether parsing was successful. The second flag 4010 /// is true if the numeric part exists. 4011 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix, 4012 unsigned long long &Reg) { 4013 if (C.front() != '{' || C.back() != '}') 4014 return std::make_pair(false, false); 4015 4016 // Search for the first numeric character. 4017 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1; 4018 I = std::find_if(B, E, isdigit); 4019 4020 Prefix = StringRef(B, I - B); 4021 4022 // The second flag is set to false if no numeric characters were found. 4023 if (I == E) 4024 return std::make_pair(true, false); 4025 4026 // Parse the numeric characters. 4027 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg), 4028 true); 4029 } 4030 4031 EVT MipsTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT, 4032 ISD::NodeType) const { 4033 bool Cond = !Subtarget.isABI_O32() && VT.getSizeInBits() == 32; 4034 EVT MinVT = getRegisterType(Context, Cond ? MVT::i64 : MVT::i32); 4035 return VT.bitsLT(MinVT) ? MinVT : VT; 4036 } 4037 4038 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering:: 4039 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const { 4040 const TargetRegisterInfo *TRI = 4041 Subtarget.getRegisterInfo(); 4042 const TargetRegisterClass *RC; 4043 StringRef Prefix; 4044 unsigned long long Reg; 4045 4046 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg); 4047 4048 if (!R.first) 4049 return std::make_pair(0U, nullptr); 4050 4051 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo. 4052 // No numeric characters follow "hi" or "lo". 4053 if (R.second) 4054 return std::make_pair(0U, nullptr); 4055 4056 RC = TRI->getRegClass(Prefix == "hi" ? 4057 Mips::HI32RegClassID : Mips::LO32RegClassID); 4058 return std::make_pair(*(RC->begin()), RC); 4059 } else if (Prefix.startswith("$msa")) { 4060 // Parse $msa(ir|csr|access|save|modify|request|map|unmap) 4061 4062 // No numeric characters follow the name. 4063 if (R.second) 4064 return std::make_pair(0U, nullptr); 4065 4066 Reg = StringSwitch<unsigned long long>(Prefix) 4067 .Case("$msair", Mips::MSAIR) 4068 .Case("$msacsr", Mips::MSACSR) 4069 .Case("$msaaccess", Mips::MSAAccess) 4070 .Case("$msasave", Mips::MSASave) 4071 .Case("$msamodify", Mips::MSAModify) 4072 .Case("$msarequest", Mips::MSARequest) 4073 .Case("$msamap", Mips::MSAMap) 4074 .Case("$msaunmap", Mips::MSAUnmap) 4075 .Default(0); 4076 4077 if (!Reg) 4078 return std::make_pair(0U, nullptr); 4079 4080 RC = TRI->getRegClass(Mips::MSACtrlRegClassID); 4081 return std::make_pair(Reg, RC); 4082 } 4083 4084 if (!R.second) 4085 return std::make_pair(0U, nullptr); 4086 4087 if (Prefix == "$f") { // Parse $f0-$f31. 4088 // If the size of FP registers is 64-bit or Reg is an even number, select 4089 // the 64-bit register class. Otherwise, select the 32-bit register class. 4090 if (VT == MVT::Other) 4091 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; 4092 4093 RC = getRegClassFor(VT); 4094 4095 if (RC == &Mips::AFGR64RegClass) { 4096 assert(Reg % 2 == 0); 4097 Reg >>= 1; 4098 } 4099 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7. 4100 RC = TRI->getRegClass(Mips::FCCRegClassID); 4101 else if (Prefix == "$w") { // Parse $w0-$w31. 4102 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT); 4103 } else { // Parse $0-$31. 4104 assert(Prefix == "$"); 4105 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); 4106 } 4107 4108 assert(Reg < RC->getNumRegs()); 4109 return std::make_pair(*(RC->begin() + Reg), RC); 4110 } 4111 4112 /// Given a register class constraint, like 'r', if this corresponds directly 4113 /// to an LLVM register class, return a register of 0 and the register class 4114 /// pointer. 4115 std::pair<unsigned, const TargetRegisterClass *> 4116 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 4117 StringRef Constraint, 4118 MVT VT) const { 4119 if (Constraint.size() == 1) { 4120 switch (Constraint[0]) { 4121 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 4122 case 'y': // Same as 'r'. Exists for compatibility. 4123 case 'r': 4124 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 4125 if (Subtarget.inMips16Mode()) 4126 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 4127 return std::make_pair(0U, &Mips::GPR32RegClass); 4128 } 4129 if (VT == MVT::i64 && !Subtarget.isGP64bit()) 4130 return std::make_pair(0U, &Mips::GPR32RegClass); 4131 if (VT == MVT::i64 && Subtarget.isGP64bit()) 4132 return std::make_pair(0U, &Mips::GPR64RegClass); 4133 // This will generate an error message 4134 return std::make_pair(0U, nullptr); 4135 case 'f': // FPU or MSA register 4136 if (VT == MVT::v16i8) 4137 return std::make_pair(0U, &Mips::MSA128BRegClass); 4138 else if (VT == MVT::v8i16 || VT == MVT::v8f16) 4139 return std::make_pair(0U, &Mips::MSA128HRegClass); 4140 else if (VT == MVT::v4i32 || VT == MVT::v4f32) 4141 return std::make_pair(0U, &Mips::MSA128WRegClass); 4142 else if (VT == MVT::v2i64 || VT == MVT::v2f64) 4143 return std::make_pair(0U, &Mips::MSA128DRegClass); 4144 else if (VT == MVT::f32) 4145 return std::make_pair(0U, &Mips::FGR32RegClass); 4146 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) { 4147 if (Subtarget.isFP64bit()) 4148 return std::make_pair(0U, &Mips::FGR64RegClass); 4149 return std::make_pair(0U, &Mips::AFGR64RegClass); 4150 } 4151 break; 4152 case 'c': // register suitable for indirect jump 4153 if (VT == MVT::i32) 4154 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); 4155 if (VT == MVT::i64) 4156 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); 4157 // This will generate an error message 4158 return std::make_pair(0U, nullptr); 4159 case 'l': // use the `lo` register to store values 4160 // that are no bigger than a word 4161 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) 4162 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); 4163 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); 4164 case 'x': // use the concatenated `hi` and `lo` registers 4165 // to store doubleword values 4166 // Fixme: Not triggering the use of both hi and low 4167 // This will generate an error message 4168 return std::make_pair(0U, nullptr); 4169 } 4170 } 4171 4172 if (!Constraint.empty()) { 4173 std::pair<unsigned, const TargetRegisterClass *> R; 4174 R = parseRegForInlineAsmConstraint(Constraint, VT); 4175 4176 if (R.second) 4177 return R; 4178 } 4179 4180 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 4181 } 4182 4183 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 4184 /// vector. If it is invalid, don't add anything to Ops. 4185 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 4186 std::string &Constraint, 4187 std::vector<SDValue>&Ops, 4188 SelectionDAG &DAG) const { 4189 SDLoc DL(Op); 4190 SDValue Result; 4191 4192 // Only support length 1 constraints for now. 4193 if (Constraint.length() > 1) return; 4194 4195 char ConstraintLetter = Constraint[0]; 4196 switch (ConstraintLetter) { 4197 default: break; // This will fall through to the generic implementation 4198 case 'I': // Signed 16 bit constant 4199 // If this fails, the parent routine will give an error 4200 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4201 EVT Type = Op.getValueType(); 4202 int64_t Val = C->getSExtValue(); 4203 if (isInt<16>(Val)) { 4204 Result = DAG.getTargetConstant(Val, DL, Type); 4205 break; 4206 } 4207 } 4208 return; 4209 case 'J': // integer zero 4210 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4211 EVT Type = Op.getValueType(); 4212 int64_t Val = C->getZExtValue(); 4213 if (Val == 0) { 4214 Result = DAG.getTargetConstant(0, DL, Type); 4215 break; 4216 } 4217 } 4218 return; 4219 case 'K': // unsigned 16 bit immediate 4220 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4221 EVT Type = Op.getValueType(); 4222 uint64_t Val = (uint64_t)C->getZExtValue(); 4223 if (isUInt<16>(Val)) { 4224 Result = DAG.getTargetConstant(Val, DL, Type); 4225 break; 4226 } 4227 } 4228 return; 4229 case 'L': // signed 32 bit immediate where lower 16 bits are 0 4230 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4231 EVT Type = Op.getValueType(); 4232 int64_t Val = C->getSExtValue(); 4233 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 4234 Result = DAG.getTargetConstant(Val, DL, Type); 4235 break; 4236 } 4237 } 4238 return; 4239 case 'N': // immediate in the range of -65535 to -1 (inclusive) 4240 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4241 EVT Type = Op.getValueType(); 4242 int64_t Val = C->getSExtValue(); 4243 if ((Val >= -65535) && (Val <= -1)) { 4244 Result = DAG.getTargetConstant(Val, DL, Type); 4245 break; 4246 } 4247 } 4248 return; 4249 case 'O': // signed 15 bit immediate 4250 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4251 EVT Type = Op.getValueType(); 4252 int64_t Val = C->getSExtValue(); 4253 if ((isInt<15>(Val))) { 4254 Result = DAG.getTargetConstant(Val, DL, Type); 4255 break; 4256 } 4257 } 4258 return; 4259 case 'P': // immediate in the range of 1 to 65535 (inclusive) 4260 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4261 EVT Type = Op.getValueType(); 4262 int64_t Val = C->getSExtValue(); 4263 if ((Val <= 65535) && (Val >= 1)) { 4264 Result = DAG.getTargetConstant(Val, DL, Type); 4265 break; 4266 } 4267 } 4268 return; 4269 } 4270 4271 if (Result.getNode()) { 4272 Ops.push_back(Result); 4273 return; 4274 } 4275 4276 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 4277 } 4278 4279 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL, 4280 const AddrMode &AM, Type *Ty, 4281 unsigned AS, 4282 Instruction *I) const { 4283 // No global is ever allowed as a base. 4284 if (AM.BaseGV) 4285 return false; 4286 4287 switch (AM.Scale) { 4288 case 0: // "r+i" or just "i", depending on HasBaseReg. 4289 break; 4290 case 1: 4291 if (!AM.HasBaseReg) // allow "r+i". 4292 break; 4293 return false; // disallow "r+r" or "r+r+i". 4294 default: 4295 return false; 4296 } 4297 4298 return true; 4299 } 4300 4301 bool 4302 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 4303 // The Mips target isn't yet aware of offsets. 4304 return false; 4305 } 4306 4307 EVT MipsTargetLowering::getOptimalMemOpType( 4308 const MemOp &Op, const AttributeList &FuncAttributes) const { 4309 if (Subtarget.hasMips64()) 4310 return MVT::i64; 4311 4312 return MVT::i32; 4313 } 4314 4315 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, 4316 bool ForCodeSize) const { 4317 if (VT != MVT::f32 && VT != MVT::f64) 4318 return false; 4319 if (Imm.isNegZero()) 4320 return false; 4321 return Imm.isZero(); 4322 } 4323 4324 unsigned MipsTargetLowering::getJumpTableEncoding() const { 4325 4326 // FIXME: For space reasons this should be: EK_GPRel32BlockAddress. 4327 if (ABI.IsN64() && isPositionIndependent()) 4328 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 4329 4330 return TargetLowering::getJumpTableEncoding(); 4331 } 4332 4333 bool MipsTargetLowering::useSoftFloat() const { 4334 return Subtarget.useSoftFloat(); 4335 } 4336 4337 void MipsTargetLowering::copyByValRegs( 4338 SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains, 4339 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 4340 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 4341 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, 4342 MipsCCState &State) const { 4343 MachineFunction &MF = DAG.getMachineFunction(); 4344 MachineFrameInfo &MFI = MF.getFrameInfo(); 4345 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes(); 4346 unsigned NumRegs = LastReg - FirstReg; 4347 unsigned RegAreaSize = NumRegs * GPRSizeInBytes; 4348 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 4349 int FrameObjOffset; 4350 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs(); 4351 4352 if (RegAreaSize) 4353 FrameObjOffset = 4354 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 4355 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); 4356 else 4357 FrameObjOffset = VA.getLocMemOffset(); 4358 4359 // Create frame object. 4360 EVT PtrTy = getPointerTy(DAG.getDataLayout()); 4361 // Make the fixed object stored to mutable so that the load instructions 4362 // referencing it have their memory dependencies added. 4363 // Set the frame object as isAliased which clears the underlying objects 4364 // vector in ScheduleDAGInstrs::buildSchedGraph() resulting in addition of all 4365 // stores as dependencies for loads referencing this fixed object. 4366 int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, false, true); 4367 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4368 InVals.push_back(FIN); 4369 4370 if (!NumRegs) 4371 return; 4372 4373 // Copy arg registers. 4374 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); 4375 const TargetRegisterClass *RC = getRegClassFor(RegTy); 4376 4377 for (unsigned I = 0; I < NumRegs; ++I) { 4378 unsigned ArgReg = ByValArgRegs[FirstReg + I]; 4379 unsigned VReg = addLiveIn(MF, ArgReg, RC); 4380 unsigned Offset = I * GPRSizeInBytes; 4381 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 4382 DAG.getConstant(Offset, DL, PtrTy)); 4383 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 4384 StorePtr, MachinePointerInfo(FuncArg, Offset)); 4385 OutChains.push_back(Store); 4386 } 4387 } 4388 4389 // Copy byVal arg to registers and stack. 4390 void MipsTargetLowering::passByValArg( 4391 SDValue Chain, const SDLoc &DL, 4392 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 4393 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 4394 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, 4395 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle, 4396 const CCValAssign &VA) const { 4397 unsigned ByValSizeInBytes = Flags.getByValSize(); 4398 unsigned OffsetInBytes = 0; // From beginning of struct 4399 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4400 Align Alignment = 4401 std::min(Flags.getNonZeroByValAlign(), Align(RegSizeInBytes)); 4402 EVT PtrTy = getPointerTy(DAG.getDataLayout()), 4403 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 4404 unsigned NumRegs = LastReg - FirstReg; 4405 4406 if (NumRegs) { 4407 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); 4408 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes); 4409 unsigned I = 0; 4410 4411 // Copy words to registers. 4412 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) { 4413 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4414 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 4415 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 4416 MachinePointerInfo(), Alignment); 4417 MemOpChains.push_back(LoadVal.getValue(1)); 4418 unsigned ArgReg = ArgRegs[FirstReg + I]; 4419 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 4420 } 4421 4422 // Return if the struct has been fully copied. 4423 if (ByValSizeInBytes == OffsetInBytes) 4424 return; 4425 4426 // Copy the remainder of the byval argument with sub-word loads and shifts. 4427 if (LeftoverBytes) { 4428 SDValue Val; 4429 4430 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0; 4431 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) { 4432 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes; 4433 4434 if (RemainingSizeInBytes < LoadSizeInBytes) 4435 continue; 4436 4437 // Load subword. 4438 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4439 DAG.getConstant(OffsetInBytes, DL, 4440 PtrTy)); 4441 SDValue LoadVal = DAG.getExtLoad( 4442 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), 4443 MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment); 4444 MemOpChains.push_back(LoadVal.getValue(1)); 4445 4446 // Shift the loaded value. 4447 unsigned Shamt; 4448 4449 if (isLittle) 4450 Shamt = TotalBytesLoaded * 8; 4451 else 4452 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8; 4453 4454 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 4455 DAG.getConstant(Shamt, DL, MVT::i32)); 4456 4457 if (Val.getNode()) 4458 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 4459 else 4460 Val = Shift; 4461 4462 OffsetInBytes += LoadSizeInBytes; 4463 TotalBytesLoaded += LoadSizeInBytes; 4464 Alignment = std::min(Alignment, Align(LoadSizeInBytes)); 4465 } 4466 4467 unsigned ArgReg = ArgRegs[FirstReg + I]; 4468 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 4469 return; 4470 } 4471 } 4472 4473 // Copy remainder of byval arg to it with memcpy. 4474 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes; 4475 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4476 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 4477 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 4478 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); 4479 Chain = DAG.getMemcpy( 4480 Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, DL, PtrTy), 4481 Align(Alignment), /*isVolatile=*/false, /*AlwaysInline=*/false, 4482 /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo()); 4483 MemOpChains.push_back(Chain); 4484 } 4485 4486 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 4487 SDValue Chain, const SDLoc &DL, 4488 SelectionDAG &DAG, 4489 CCState &State) const { 4490 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); 4491 unsigned Idx = State.getFirstUnallocated(ArgRegs); 4492 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4493 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 4494 const TargetRegisterClass *RC = getRegClassFor(RegTy); 4495 MachineFunction &MF = DAG.getMachineFunction(); 4496 MachineFrameInfo &MFI = MF.getFrameInfo(); 4497 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 4498 4499 // Offset of the first variable argument from stack pointer. 4500 int VaArgOffset; 4501 4502 if (ArgRegs.size() == Idx) 4503 VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes); 4504 else { 4505 VaArgOffset = 4506 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 4507 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); 4508 } 4509 4510 // Record the frame index of the first variable argument 4511 // which is a value necessary to VASTART. 4512 int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 4513 MipsFI->setVarArgsFrameIndex(FI); 4514 4515 // Copy the integer registers that have not been used for argument passing 4516 // to the argument register save area. For O32, the save area is allocated 4517 // in the caller's stack frame, while for N32/64, it is allocated in the 4518 // callee's stack frame. 4519 for (unsigned I = Idx; I < ArgRegs.size(); 4520 ++I, VaArgOffset += RegSizeInBytes) { 4521 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); 4522 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 4523 FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 4524 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 4525 SDValue Store = 4526 DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo()); 4527 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue( 4528 (Value *)nullptr); 4529 OutChains.push_back(Store); 4530 } 4531 } 4532 4533 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size, 4534 Align Alignment) const { 4535 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 4536 4537 assert(Size && "Byval argument's size shouldn't be 0."); 4538 4539 Alignment = std::min(Alignment, TFL->getStackAlign()); 4540 4541 unsigned FirstReg = 0; 4542 unsigned NumRegs = 0; 4543 4544 if (State->getCallingConv() != CallingConv::Fast) { 4545 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4546 ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs(); 4547 // FIXME: The O32 case actually describes no shadow registers. 4548 const MCPhysReg *ShadowRegs = 4549 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs; 4550 4551 // We used to check the size as well but we can't do that anymore since 4552 // CCState::HandleByVal() rounds up the size after calling this function. 4553 assert( 4554 Alignment >= Align(RegSizeInBytes) && 4555 "Byval argument's alignment should be a multiple of RegSizeInBytes."); 4556 4557 FirstReg = State->getFirstUnallocated(IntArgRegs); 4558 4559 // If Alignment > RegSizeInBytes, the first arg register must be even. 4560 // FIXME: This condition happens to do the right thing but it's not the 4561 // right way to test it. We want to check that the stack frame offset 4562 // of the register is aligned. 4563 if ((Alignment > RegSizeInBytes) && (FirstReg % 2)) { 4564 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]); 4565 ++FirstReg; 4566 } 4567 4568 // Mark the registers allocated. 4569 Size = alignTo(Size, RegSizeInBytes); 4570 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size()); 4571 Size -= RegSizeInBytes, ++I, ++NumRegs) 4572 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]); 4573 } 4574 4575 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs); 4576 } 4577 4578 MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI, 4579 MachineBasicBlock *BB, 4580 bool isFPCmp, 4581 unsigned Opc) const { 4582 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 4583 "Subtarget already supports SELECT nodes with the use of" 4584 "conditional-move instructions."); 4585 4586 const TargetInstrInfo *TII = 4587 Subtarget.getInstrInfo(); 4588 DebugLoc DL = MI.getDebugLoc(); 4589 4590 // To "insert" a SELECT instruction, we actually have to insert the 4591 // diamond control-flow pattern. The incoming instruction knows the 4592 // destination vreg to set, the condition code register to branch on, the 4593 // true/false values to select between, and a branch opcode to use. 4594 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4595 MachineFunction::iterator It = ++BB->getIterator(); 4596 4597 // thisMBB: 4598 // ... 4599 // TrueVal = ... 4600 // setcc r1, r2, r3 4601 // bNE r1, r0, copy1MBB 4602 // fallthrough --> copy0MBB 4603 MachineBasicBlock *thisMBB = BB; 4604 MachineFunction *F = BB->getParent(); 4605 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4606 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4607 F->insert(It, copy0MBB); 4608 F->insert(It, sinkMBB); 4609 4610 // Transfer the remainder of BB and its successor edges to sinkMBB. 4611 sinkMBB->splice(sinkMBB->begin(), BB, 4612 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 4613 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 4614 4615 // Next, add the true and fallthrough blocks as its successors. 4616 BB->addSuccessor(copy0MBB); 4617 BB->addSuccessor(sinkMBB); 4618 4619 if (isFPCmp) { 4620 // bc1[tf] cc, sinkMBB 4621 BuildMI(BB, DL, TII->get(Opc)) 4622 .addReg(MI.getOperand(1).getReg()) 4623 .addMBB(sinkMBB); 4624 } else { 4625 // bne rs, $0, sinkMBB 4626 BuildMI(BB, DL, TII->get(Opc)) 4627 .addReg(MI.getOperand(1).getReg()) 4628 .addReg(Mips::ZERO) 4629 .addMBB(sinkMBB); 4630 } 4631 4632 // copy0MBB: 4633 // %FalseValue = ... 4634 // # fallthrough to sinkMBB 4635 BB = copy0MBB; 4636 4637 // Update machine-CFG edges 4638 BB->addSuccessor(sinkMBB); 4639 4640 // sinkMBB: 4641 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 4642 // ... 4643 BB = sinkMBB; 4644 4645 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) 4646 .addReg(MI.getOperand(2).getReg()) 4647 .addMBB(thisMBB) 4648 .addReg(MI.getOperand(3).getReg()) 4649 .addMBB(copy0MBB); 4650 4651 MI.eraseFromParent(); // The pseudo instruction is gone now. 4652 4653 return BB; 4654 } 4655 4656 MachineBasicBlock * 4657 MipsTargetLowering::emitPseudoD_SELECT(MachineInstr &MI, 4658 MachineBasicBlock *BB) const { 4659 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 4660 "Subtarget already supports SELECT nodes with the use of" 4661 "conditional-move instructions."); 4662 4663 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 4664 DebugLoc DL = MI.getDebugLoc(); 4665 4666 // D_SELECT substitutes two SELECT nodes that goes one after another and 4667 // have the same condition operand. On machines which don't have 4668 // conditional-move instruction, it reduces unnecessary branch instructions 4669 // which are result of using two diamond patterns that are result of two 4670 // SELECT pseudo instructions. 4671 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4672 MachineFunction::iterator It = ++BB->getIterator(); 4673 4674 // thisMBB: 4675 // ... 4676 // TrueVal = ... 4677 // setcc r1, r2, r3 4678 // bNE r1, r0, copy1MBB 4679 // fallthrough --> copy0MBB 4680 MachineBasicBlock *thisMBB = BB; 4681 MachineFunction *F = BB->getParent(); 4682 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4683 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4684 F->insert(It, copy0MBB); 4685 F->insert(It, sinkMBB); 4686 4687 // Transfer the remainder of BB and its successor edges to sinkMBB. 4688 sinkMBB->splice(sinkMBB->begin(), BB, 4689 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 4690 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 4691 4692 // Next, add the true and fallthrough blocks as its successors. 4693 BB->addSuccessor(copy0MBB); 4694 BB->addSuccessor(sinkMBB); 4695 4696 // bne rs, $0, sinkMBB 4697 BuildMI(BB, DL, TII->get(Mips::BNE)) 4698 .addReg(MI.getOperand(2).getReg()) 4699 .addReg(Mips::ZERO) 4700 .addMBB(sinkMBB); 4701 4702 // copy0MBB: 4703 // %FalseValue = ... 4704 // # fallthrough to sinkMBB 4705 BB = copy0MBB; 4706 4707 // Update machine-CFG edges 4708 BB->addSuccessor(sinkMBB); 4709 4710 // sinkMBB: 4711 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 4712 // ... 4713 BB = sinkMBB; 4714 4715 // Use two PHI nodes to select two reults 4716 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) 4717 .addReg(MI.getOperand(3).getReg()) 4718 .addMBB(thisMBB) 4719 .addReg(MI.getOperand(5).getReg()) 4720 .addMBB(copy0MBB); 4721 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(1).getReg()) 4722 .addReg(MI.getOperand(4).getReg()) 4723 .addMBB(thisMBB) 4724 .addReg(MI.getOperand(6).getReg()) 4725 .addMBB(copy0MBB); 4726 4727 MI.eraseFromParent(); // The pseudo instruction is gone now. 4728 4729 return BB; 4730 } 4731 4732 // FIXME? Maybe this could be a TableGen attribute on some registers and 4733 // this table could be generated automatically from RegInfo. 4734 Register 4735 MipsTargetLowering::getRegisterByName(const char *RegName, LLT VT, 4736 const MachineFunction &MF) const { 4737 // Named registers is expected to be fairly rare. For now, just support $28 4738 // since the linux kernel uses it. 4739 if (Subtarget.isGP64bit()) { 4740 Register Reg = StringSwitch<Register>(RegName) 4741 .Case("$28", Mips::GP_64) 4742 .Default(Register()); 4743 if (Reg) 4744 return Reg; 4745 } else { 4746 Register Reg = StringSwitch<Register>(RegName) 4747 .Case("$28", Mips::GP) 4748 .Default(Register()); 4749 if (Reg) 4750 return Reg; 4751 } 4752 report_fatal_error("Invalid register name global variable"); 4753 } 4754 4755 MachineBasicBlock *MipsTargetLowering::emitLDR_W(MachineInstr &MI, 4756 MachineBasicBlock *BB) const { 4757 MachineFunction *MF = BB->getParent(); 4758 MachineRegisterInfo &MRI = MF->getRegInfo(); 4759 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 4760 const bool IsLittle = Subtarget.isLittle(); 4761 DebugLoc DL = MI.getDebugLoc(); 4762 4763 Register Dest = MI.getOperand(0).getReg(); 4764 Register Address = MI.getOperand(1).getReg(); 4765 unsigned Imm = MI.getOperand(2).getImm(); 4766 4767 MachineBasicBlock::iterator I(MI); 4768 4769 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { 4770 // Mips release 6 can load from adress that is not naturally-aligned. 4771 Register Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4772 BuildMI(*BB, I, DL, TII->get(Mips::LW)) 4773 .addDef(Temp) 4774 .addUse(Address) 4775 .addImm(Imm); 4776 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(Temp); 4777 } else { 4778 // Mips release 5 needs to use instructions that can load from an unaligned 4779 // memory address. 4780 Register LoadHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4781 Register LoadFull = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4782 Register Undef = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4783 BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(Undef); 4784 BuildMI(*BB, I, DL, TII->get(Mips::LWR)) 4785 .addDef(LoadHalf) 4786 .addUse(Address) 4787 .addImm(Imm + (IsLittle ? 0 : 3)) 4788 .addUse(Undef); 4789 BuildMI(*BB, I, DL, TII->get(Mips::LWL)) 4790 .addDef(LoadFull) 4791 .addUse(Address) 4792 .addImm(Imm + (IsLittle ? 3 : 0)) 4793 .addUse(LoadHalf); 4794 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(LoadFull); 4795 } 4796 4797 MI.eraseFromParent(); 4798 return BB; 4799 } 4800 4801 MachineBasicBlock *MipsTargetLowering::emitLDR_D(MachineInstr &MI, 4802 MachineBasicBlock *BB) const { 4803 MachineFunction *MF = BB->getParent(); 4804 MachineRegisterInfo &MRI = MF->getRegInfo(); 4805 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 4806 const bool IsLittle = Subtarget.isLittle(); 4807 DebugLoc DL = MI.getDebugLoc(); 4808 4809 Register Dest = MI.getOperand(0).getReg(); 4810 Register Address = MI.getOperand(1).getReg(); 4811 unsigned Imm = MI.getOperand(2).getImm(); 4812 4813 MachineBasicBlock::iterator I(MI); 4814 4815 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { 4816 // Mips release 6 can load from adress that is not naturally-aligned. 4817 if (Subtarget.isGP64bit()) { 4818 Register Temp = MRI.createVirtualRegister(&Mips::GPR64RegClass); 4819 BuildMI(*BB, I, DL, TII->get(Mips::LD)) 4820 .addDef(Temp) 4821 .addUse(Address) 4822 .addImm(Imm); 4823 BuildMI(*BB, I, DL, TII->get(Mips::FILL_D)).addDef(Dest).addUse(Temp); 4824 } else { 4825 Register Wtemp = MRI.createVirtualRegister(&Mips::MSA128WRegClass); 4826 Register Lo = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4827 Register Hi = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4828 BuildMI(*BB, I, DL, TII->get(Mips::LW)) 4829 .addDef(Lo) 4830 .addUse(Address) 4831 .addImm(Imm + (IsLittle ? 0 : 4)); 4832 BuildMI(*BB, I, DL, TII->get(Mips::LW)) 4833 .addDef(Hi) 4834 .addUse(Address) 4835 .addImm(Imm + (IsLittle ? 4 : 0)); 4836 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Wtemp).addUse(Lo); 4837 BuildMI(*BB, I, DL, TII->get(Mips::INSERT_W), Dest) 4838 .addUse(Wtemp) 4839 .addUse(Hi) 4840 .addImm(1); 4841 } 4842 } else { 4843 // Mips release 5 needs to use instructions that can load from an unaligned 4844 // memory address. 4845 Register LoHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4846 Register LoFull = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4847 Register LoUndef = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4848 Register HiHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4849 Register HiFull = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4850 Register HiUndef = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4851 Register Wtemp = MRI.createVirtualRegister(&Mips::MSA128WRegClass); 4852 BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(LoUndef); 4853 BuildMI(*BB, I, DL, TII->get(Mips::LWR)) 4854 .addDef(LoHalf) 4855 .addUse(Address) 4856 .addImm(Imm + (IsLittle ? 0 : 7)) 4857 .addUse(LoUndef); 4858 BuildMI(*BB, I, DL, TII->get(Mips::LWL)) 4859 .addDef(LoFull) 4860 .addUse(Address) 4861 .addImm(Imm + (IsLittle ? 3 : 4)) 4862 .addUse(LoHalf); 4863 BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(HiUndef); 4864 BuildMI(*BB, I, DL, TII->get(Mips::LWR)) 4865 .addDef(HiHalf) 4866 .addUse(Address) 4867 .addImm(Imm + (IsLittle ? 4 : 3)) 4868 .addUse(HiUndef); 4869 BuildMI(*BB, I, DL, TII->get(Mips::LWL)) 4870 .addDef(HiFull) 4871 .addUse(Address) 4872 .addImm(Imm + (IsLittle ? 7 : 0)) 4873 .addUse(HiHalf); 4874 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Wtemp).addUse(LoFull); 4875 BuildMI(*BB, I, DL, TII->get(Mips::INSERT_W), Dest) 4876 .addUse(Wtemp) 4877 .addUse(HiFull) 4878 .addImm(1); 4879 } 4880 4881 MI.eraseFromParent(); 4882 return BB; 4883 } 4884 4885 MachineBasicBlock *MipsTargetLowering::emitSTR_W(MachineInstr &MI, 4886 MachineBasicBlock *BB) const { 4887 MachineFunction *MF = BB->getParent(); 4888 MachineRegisterInfo &MRI = MF->getRegInfo(); 4889 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 4890 const bool IsLittle = Subtarget.isLittle(); 4891 DebugLoc DL = MI.getDebugLoc(); 4892 4893 Register StoreVal = MI.getOperand(0).getReg(); 4894 Register Address = MI.getOperand(1).getReg(); 4895 unsigned Imm = MI.getOperand(2).getImm(); 4896 4897 MachineBasicBlock::iterator I(MI); 4898 4899 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { 4900 // Mips release 6 can store to adress that is not naturally-aligned. 4901 Register BitcastW = MRI.createVirtualRegister(&Mips::MSA128WRegClass); 4902 Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4903 BuildMI(*BB, I, DL, TII->get(Mips::COPY)).addDef(BitcastW).addUse(StoreVal); 4904 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) 4905 .addDef(Tmp) 4906 .addUse(BitcastW) 4907 .addImm(0); 4908 BuildMI(*BB, I, DL, TII->get(Mips::SW)) 4909 .addUse(Tmp) 4910 .addUse(Address) 4911 .addImm(Imm); 4912 } else { 4913 // Mips release 5 needs to use instructions that can store to an unaligned 4914 // memory address. 4915 Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4916 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) 4917 .addDef(Tmp) 4918 .addUse(StoreVal) 4919 .addImm(0); 4920 BuildMI(*BB, I, DL, TII->get(Mips::SWR)) 4921 .addUse(Tmp) 4922 .addUse(Address) 4923 .addImm(Imm + (IsLittle ? 0 : 3)); 4924 BuildMI(*BB, I, DL, TII->get(Mips::SWL)) 4925 .addUse(Tmp) 4926 .addUse(Address) 4927 .addImm(Imm + (IsLittle ? 3 : 0)); 4928 } 4929 4930 MI.eraseFromParent(); 4931 4932 return BB; 4933 } 4934 4935 MachineBasicBlock *MipsTargetLowering::emitSTR_D(MachineInstr &MI, 4936 MachineBasicBlock *BB) const { 4937 MachineFunction *MF = BB->getParent(); 4938 MachineRegisterInfo &MRI = MF->getRegInfo(); 4939 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 4940 const bool IsLittle = Subtarget.isLittle(); 4941 DebugLoc DL = MI.getDebugLoc(); 4942 4943 Register StoreVal = MI.getOperand(0).getReg(); 4944 Register Address = MI.getOperand(1).getReg(); 4945 unsigned Imm = MI.getOperand(2).getImm(); 4946 4947 MachineBasicBlock::iterator I(MI); 4948 4949 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { 4950 // Mips release 6 can store to adress that is not naturally-aligned. 4951 if (Subtarget.isGP64bit()) { 4952 Register BitcastD = MRI.createVirtualRegister(&Mips::MSA128DRegClass); 4953 Register Lo = MRI.createVirtualRegister(&Mips::GPR64RegClass); 4954 BuildMI(*BB, I, DL, TII->get(Mips::COPY)) 4955 .addDef(BitcastD) 4956 .addUse(StoreVal); 4957 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_D)) 4958 .addDef(Lo) 4959 .addUse(BitcastD) 4960 .addImm(0); 4961 BuildMI(*BB, I, DL, TII->get(Mips::SD)) 4962 .addUse(Lo) 4963 .addUse(Address) 4964 .addImm(Imm); 4965 } else { 4966 Register BitcastW = MRI.createVirtualRegister(&Mips::MSA128WRegClass); 4967 Register Lo = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4968 Register Hi = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4969 BuildMI(*BB, I, DL, TII->get(Mips::COPY)) 4970 .addDef(BitcastW) 4971 .addUse(StoreVal); 4972 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) 4973 .addDef(Lo) 4974 .addUse(BitcastW) 4975 .addImm(0); 4976 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) 4977 .addDef(Hi) 4978 .addUse(BitcastW) 4979 .addImm(1); 4980 BuildMI(*BB, I, DL, TII->get(Mips::SW)) 4981 .addUse(Lo) 4982 .addUse(Address) 4983 .addImm(Imm + (IsLittle ? 0 : 4)); 4984 BuildMI(*BB, I, DL, TII->get(Mips::SW)) 4985 .addUse(Hi) 4986 .addUse(Address) 4987 .addImm(Imm + (IsLittle ? 4 : 0)); 4988 } 4989 } else { 4990 // Mips release 5 needs to use instructions that can store to an unaligned 4991 // memory address. 4992 Register Bitcast = MRI.createVirtualRegister(&Mips::MSA128WRegClass); 4993 Register Lo = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4994 Register Hi = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4995 BuildMI(*BB, I, DL, TII->get(Mips::COPY)).addDef(Bitcast).addUse(StoreVal); 4996 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) 4997 .addDef(Lo) 4998 .addUse(Bitcast) 4999 .addImm(0); 5000 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) 5001 .addDef(Hi) 5002 .addUse(Bitcast) 5003 .addImm(1); 5004 BuildMI(*BB, I, DL, TII->get(Mips::SWR)) 5005 .addUse(Lo) 5006 .addUse(Address) 5007 .addImm(Imm + (IsLittle ? 0 : 3)); 5008 BuildMI(*BB, I, DL, TII->get(Mips::SWL)) 5009 .addUse(Lo) 5010 .addUse(Address) 5011 .addImm(Imm + (IsLittle ? 3 : 0)); 5012 BuildMI(*BB, I, DL, TII->get(Mips::SWR)) 5013 .addUse(Hi) 5014 .addUse(Address) 5015 .addImm(Imm + (IsLittle ? 4 : 7)); 5016 BuildMI(*BB, I, DL, TII->get(Mips::SWL)) 5017 .addUse(Hi) 5018 .addUse(Address) 5019 .addImm(Imm + (IsLittle ? 7 : 4)); 5020 } 5021 5022 MI.eraseFromParent(); 5023 return BB; 5024 } 5025