xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelLowering.cpp (revision 162ae9c834f6d9f9cb443bd62cceb23e0b5fef48)
1 //===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that Mips uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsISelLowering.h"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "MCTargetDesc/MipsInstPrinter.h"
17 #include "MCTargetDesc/MipsMCTargetDesc.h"
18 #include "MipsCCState.h"
19 #include "MipsInstrInfo.h"
20 #include "MipsMachineFunction.h"
21 #include "MipsRegisterInfo.h"
22 #include "MipsSubtarget.h"
23 #include "MipsTargetMachine.h"
24 #include "MipsTargetObjectFile.h"
25 #include "llvm/ADT/APFloat.h"
26 #include "llvm/ADT/ArrayRef.h"
27 #include "llvm/ADT/SmallVector.h"
28 #include "llvm/ADT/Statistic.h"
29 #include "llvm/ADT/StringRef.h"
30 #include "llvm/ADT/StringSwitch.h"
31 #include "llvm/CodeGen/CallingConvLower.h"
32 #include "llvm/CodeGen/FunctionLoweringInfo.h"
33 #include "llvm/CodeGen/ISDOpcodes.h"
34 #include "llvm/CodeGen/MachineBasicBlock.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineFunction.h"
37 #include "llvm/CodeGen/MachineInstr.h"
38 #include "llvm/CodeGen/MachineInstrBuilder.h"
39 #include "llvm/CodeGen/MachineJumpTableInfo.h"
40 #include "llvm/CodeGen/MachineMemOperand.h"
41 #include "llvm/CodeGen/MachineOperand.h"
42 #include "llvm/CodeGen/MachineRegisterInfo.h"
43 #include "llvm/CodeGen/RuntimeLibcalls.h"
44 #include "llvm/CodeGen/SelectionDAG.h"
45 #include "llvm/CodeGen/SelectionDAGNodes.h"
46 #include "llvm/CodeGen/TargetFrameLowering.h"
47 #include "llvm/CodeGen/TargetInstrInfo.h"
48 #include "llvm/CodeGen/TargetRegisterInfo.h"
49 #include "llvm/CodeGen/ValueTypes.h"
50 #include "llvm/IR/CallingConv.h"
51 #include "llvm/IR/Constants.h"
52 #include "llvm/IR/DataLayout.h"
53 #include "llvm/IR/DebugLoc.h"
54 #include "llvm/IR/DerivedTypes.h"
55 #include "llvm/IR/Function.h"
56 #include "llvm/IR/GlobalValue.h"
57 #include "llvm/IR/Type.h"
58 #include "llvm/IR/Value.h"
59 #include "llvm/MC/MCContext.h"
60 #include "llvm/MC/MCRegisterInfo.h"
61 #include "llvm/Support/Casting.h"
62 #include "llvm/Support/CodeGen.h"
63 #include "llvm/Support/CommandLine.h"
64 #include "llvm/Support/Compiler.h"
65 #include "llvm/Support/ErrorHandling.h"
66 #include "llvm/Support/MachineValueType.h"
67 #include "llvm/Support/MathExtras.h"
68 #include "llvm/Target/TargetMachine.h"
69 #include "llvm/Target/TargetOptions.h"
70 #include <algorithm>
71 #include <cassert>
72 #include <cctype>
73 #include <cstdint>
74 #include <deque>
75 #include <iterator>
76 #include <utility>
77 #include <vector>
78 
79 using namespace llvm;
80 
81 #define DEBUG_TYPE "mips-lower"
82 
83 STATISTIC(NumTailCalls, "Number of tail calls");
84 
85 static cl::opt<bool>
86 LargeGOT("mxgot", cl::Hidden,
87          cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
88 
89 static cl::opt<bool>
90 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
91                cl::desc("MIPS: Don't trap on integer division by zero."),
92                cl::init(false));
93 
94 extern cl::opt<bool> EmitJalrReloc;
95 
96 static const MCPhysReg Mips64DPRegs[8] = {
97   Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
98   Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
99 };
100 
101 // If I is a shifted mask, set the size (Size) and the first bit of the
102 // mask (Pos), and return true.
103 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
104 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
105   if (!isShiftedMask_64(I))
106     return false;
107 
108   Size = countPopulation(I);
109   Pos = countTrailingZeros(I);
110   return true;
111 }
112 
113 // The MIPS MSA ABI passes vector arguments in the integer register set.
114 // The number of integer registers used is dependant on the ABI used.
115 MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
116                                                       CallingConv::ID CC,
117                                                       EVT VT) const {
118   if (VT.isVector()) {
119       if (Subtarget.isABI_O32()) {
120         return MVT::i32;
121       } else {
122         return (VT.getSizeInBits() == 32) ? MVT::i32 : MVT::i64;
123       }
124   }
125   return MipsTargetLowering::getRegisterType(Context, VT);
126 }
127 
128 unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
129                                                            CallingConv::ID CC,
130                                                            EVT VT) const {
131   if (VT.isVector())
132     return std::max((VT.getSizeInBits() / (Subtarget.isABI_O32() ? 32 : 64)),
133                     1U);
134   return MipsTargetLowering::getNumRegisters(Context, VT);
135 }
136 
137 unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv(
138     LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
139     unsigned &NumIntermediates, MVT &RegisterVT) const {
140   // Break down vector types to either 2 i64s or 4 i32s.
141   RegisterVT = getRegisterTypeForCallingConv(Context, CC, VT);
142   IntermediateVT = RegisterVT;
143   NumIntermediates = VT.getSizeInBits() < RegisterVT.getSizeInBits()
144                          ? VT.getVectorNumElements()
145                          : VT.getSizeInBits() / RegisterVT.getSizeInBits();
146 
147   return NumIntermediates;
148 }
149 
150 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
151   MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
152   return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
153 }
154 
155 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
156                                           SelectionDAG &DAG,
157                                           unsigned Flag) const {
158   return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
159 }
160 
161 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
162                                           SelectionDAG &DAG,
163                                           unsigned Flag) const {
164   return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
165 }
166 
167 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
168                                           SelectionDAG &DAG,
169                                           unsigned Flag) const {
170   return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
171 }
172 
173 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
174                                           SelectionDAG &DAG,
175                                           unsigned Flag) const {
176   return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
177 }
178 
179 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
180                                           SelectionDAG &DAG,
181                                           unsigned Flag) const {
182   return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
183                                    N->getOffset(), Flag);
184 }
185 
186 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
187   switch ((MipsISD::NodeType)Opcode) {
188   case MipsISD::FIRST_NUMBER:      break;
189   case MipsISD::JmpLink:           return "MipsISD::JmpLink";
190   case MipsISD::TailCall:          return "MipsISD::TailCall";
191   case MipsISD::Highest:           return "MipsISD::Highest";
192   case MipsISD::Higher:            return "MipsISD::Higher";
193   case MipsISD::Hi:                return "MipsISD::Hi";
194   case MipsISD::Lo:                return "MipsISD::Lo";
195   case MipsISD::GotHi:             return "MipsISD::GotHi";
196   case MipsISD::TlsHi:             return "MipsISD::TlsHi";
197   case MipsISD::GPRel:             return "MipsISD::GPRel";
198   case MipsISD::ThreadPointer:     return "MipsISD::ThreadPointer";
199   case MipsISD::Ret:               return "MipsISD::Ret";
200   case MipsISD::ERet:              return "MipsISD::ERet";
201   case MipsISD::EH_RETURN:         return "MipsISD::EH_RETURN";
202   case MipsISD::FMS:               return "MipsISD::FMS";
203   case MipsISD::FPBrcond:          return "MipsISD::FPBrcond";
204   case MipsISD::FPCmp:             return "MipsISD::FPCmp";
205   case MipsISD::FSELECT:           return "MipsISD::FSELECT";
206   case MipsISD::MTC1_D64:          return "MipsISD::MTC1_D64";
207   case MipsISD::CMovFP_T:          return "MipsISD::CMovFP_T";
208   case MipsISD::CMovFP_F:          return "MipsISD::CMovFP_F";
209   case MipsISD::TruncIntFP:        return "MipsISD::TruncIntFP";
210   case MipsISD::MFHI:              return "MipsISD::MFHI";
211   case MipsISD::MFLO:              return "MipsISD::MFLO";
212   case MipsISD::MTLOHI:            return "MipsISD::MTLOHI";
213   case MipsISD::Mult:              return "MipsISD::Mult";
214   case MipsISD::Multu:             return "MipsISD::Multu";
215   case MipsISD::MAdd:              return "MipsISD::MAdd";
216   case MipsISD::MAddu:             return "MipsISD::MAddu";
217   case MipsISD::MSub:              return "MipsISD::MSub";
218   case MipsISD::MSubu:             return "MipsISD::MSubu";
219   case MipsISD::DivRem:            return "MipsISD::DivRem";
220   case MipsISD::DivRemU:           return "MipsISD::DivRemU";
221   case MipsISD::DivRem16:          return "MipsISD::DivRem16";
222   case MipsISD::DivRemU16:         return "MipsISD::DivRemU16";
223   case MipsISD::BuildPairF64:      return "MipsISD::BuildPairF64";
224   case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
225   case MipsISD::Wrapper:           return "MipsISD::Wrapper";
226   case MipsISD::DynAlloc:          return "MipsISD::DynAlloc";
227   case MipsISD::Sync:              return "MipsISD::Sync";
228   case MipsISD::Ext:               return "MipsISD::Ext";
229   case MipsISD::Ins:               return "MipsISD::Ins";
230   case MipsISD::CIns:              return "MipsISD::CIns";
231   case MipsISD::LWL:               return "MipsISD::LWL";
232   case MipsISD::LWR:               return "MipsISD::LWR";
233   case MipsISD::SWL:               return "MipsISD::SWL";
234   case MipsISD::SWR:               return "MipsISD::SWR";
235   case MipsISD::LDL:               return "MipsISD::LDL";
236   case MipsISD::LDR:               return "MipsISD::LDR";
237   case MipsISD::SDL:               return "MipsISD::SDL";
238   case MipsISD::SDR:               return "MipsISD::SDR";
239   case MipsISD::EXTP:              return "MipsISD::EXTP";
240   case MipsISD::EXTPDP:            return "MipsISD::EXTPDP";
241   case MipsISD::EXTR_S_H:          return "MipsISD::EXTR_S_H";
242   case MipsISD::EXTR_W:            return "MipsISD::EXTR_W";
243   case MipsISD::EXTR_R_W:          return "MipsISD::EXTR_R_W";
244   case MipsISD::EXTR_RS_W:         return "MipsISD::EXTR_RS_W";
245   case MipsISD::SHILO:             return "MipsISD::SHILO";
246   case MipsISD::MTHLIP:            return "MipsISD::MTHLIP";
247   case MipsISD::MULSAQ_S_W_PH:     return "MipsISD::MULSAQ_S_W_PH";
248   case MipsISD::MAQ_S_W_PHL:       return "MipsISD::MAQ_S_W_PHL";
249   case MipsISD::MAQ_S_W_PHR:       return "MipsISD::MAQ_S_W_PHR";
250   case MipsISD::MAQ_SA_W_PHL:      return "MipsISD::MAQ_SA_W_PHL";
251   case MipsISD::MAQ_SA_W_PHR:      return "MipsISD::MAQ_SA_W_PHR";
252   case MipsISD::DPAU_H_QBL:        return "MipsISD::DPAU_H_QBL";
253   case MipsISD::DPAU_H_QBR:        return "MipsISD::DPAU_H_QBR";
254   case MipsISD::DPSU_H_QBL:        return "MipsISD::DPSU_H_QBL";
255   case MipsISD::DPSU_H_QBR:        return "MipsISD::DPSU_H_QBR";
256   case MipsISD::DPAQ_S_W_PH:       return "MipsISD::DPAQ_S_W_PH";
257   case MipsISD::DPSQ_S_W_PH:       return "MipsISD::DPSQ_S_W_PH";
258   case MipsISD::DPAQ_SA_L_W:       return "MipsISD::DPAQ_SA_L_W";
259   case MipsISD::DPSQ_SA_L_W:       return "MipsISD::DPSQ_SA_L_W";
260   case MipsISD::DPA_W_PH:          return "MipsISD::DPA_W_PH";
261   case MipsISD::DPS_W_PH:          return "MipsISD::DPS_W_PH";
262   case MipsISD::DPAQX_S_W_PH:      return "MipsISD::DPAQX_S_W_PH";
263   case MipsISD::DPAQX_SA_W_PH:     return "MipsISD::DPAQX_SA_W_PH";
264   case MipsISD::DPAX_W_PH:         return "MipsISD::DPAX_W_PH";
265   case MipsISD::DPSX_W_PH:         return "MipsISD::DPSX_W_PH";
266   case MipsISD::DPSQX_S_W_PH:      return "MipsISD::DPSQX_S_W_PH";
267   case MipsISD::DPSQX_SA_W_PH:     return "MipsISD::DPSQX_SA_W_PH";
268   case MipsISD::MULSA_W_PH:        return "MipsISD::MULSA_W_PH";
269   case MipsISD::MULT:              return "MipsISD::MULT";
270   case MipsISD::MULTU:             return "MipsISD::MULTU";
271   case MipsISD::MADD_DSP:          return "MipsISD::MADD_DSP";
272   case MipsISD::MADDU_DSP:         return "MipsISD::MADDU_DSP";
273   case MipsISD::MSUB_DSP:          return "MipsISD::MSUB_DSP";
274   case MipsISD::MSUBU_DSP:         return "MipsISD::MSUBU_DSP";
275   case MipsISD::SHLL_DSP:          return "MipsISD::SHLL_DSP";
276   case MipsISD::SHRA_DSP:          return "MipsISD::SHRA_DSP";
277   case MipsISD::SHRL_DSP:          return "MipsISD::SHRL_DSP";
278   case MipsISD::SETCC_DSP:         return "MipsISD::SETCC_DSP";
279   case MipsISD::SELECT_CC_DSP:     return "MipsISD::SELECT_CC_DSP";
280   case MipsISD::VALL_ZERO:         return "MipsISD::VALL_ZERO";
281   case MipsISD::VANY_ZERO:         return "MipsISD::VANY_ZERO";
282   case MipsISD::VALL_NONZERO:      return "MipsISD::VALL_NONZERO";
283   case MipsISD::VANY_NONZERO:      return "MipsISD::VANY_NONZERO";
284   case MipsISD::VCEQ:              return "MipsISD::VCEQ";
285   case MipsISD::VCLE_S:            return "MipsISD::VCLE_S";
286   case MipsISD::VCLE_U:            return "MipsISD::VCLE_U";
287   case MipsISD::VCLT_S:            return "MipsISD::VCLT_S";
288   case MipsISD::VCLT_U:            return "MipsISD::VCLT_U";
289   case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
290   case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
291   case MipsISD::VNOR:              return "MipsISD::VNOR";
292   case MipsISD::VSHF:              return "MipsISD::VSHF";
293   case MipsISD::SHF:               return "MipsISD::SHF";
294   case MipsISD::ILVEV:             return "MipsISD::ILVEV";
295   case MipsISD::ILVOD:             return "MipsISD::ILVOD";
296   case MipsISD::ILVL:              return "MipsISD::ILVL";
297   case MipsISD::ILVR:              return "MipsISD::ILVR";
298   case MipsISD::PCKEV:             return "MipsISD::PCKEV";
299   case MipsISD::PCKOD:             return "MipsISD::PCKOD";
300   case MipsISD::INSVE:             return "MipsISD::INSVE";
301   }
302   return nullptr;
303 }
304 
305 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
306                                        const MipsSubtarget &STI)
307     : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
308   // Mips does not have i1 type, so use i32 for
309   // setcc operations results (slt, sgt, ...).
310   setBooleanContents(ZeroOrOneBooleanContent);
311   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
312   // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
313   // does. Integer booleans still use 0 and 1.
314   if (Subtarget.hasMips32r6())
315     setBooleanContents(ZeroOrOneBooleanContent,
316                        ZeroOrNegativeOneBooleanContent);
317 
318   // Load extented operations for i1 types must be promoted
319   for (MVT VT : MVT::integer_valuetypes()) {
320     setLoadExtAction(ISD::EXTLOAD,  VT, MVT::i1,  Promote);
321     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1,  Promote);
322     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1,  Promote);
323   }
324 
325   // MIPS doesn't have extending float->double load/store.  Set LoadExtAction
326   // for f32, f16
327   for (MVT VT : MVT::fp_valuetypes()) {
328     setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
329     setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
330   }
331 
332   // Set LoadExtAction for f16 vectors to Expand
333   for (MVT VT : MVT::fp_vector_valuetypes()) {
334     MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements());
335     if (F16VT.isValid())
336       setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand);
337   }
338 
339   setTruncStoreAction(MVT::f32, MVT::f16, Expand);
340   setTruncStoreAction(MVT::f64, MVT::f16, Expand);
341 
342   setTruncStoreAction(MVT::f64, MVT::f32, Expand);
343 
344   // Used by legalize types to correctly generate the setcc result.
345   // Without this, every float setcc comes with a AND/OR with the result,
346   // we don't want this, since the fpcmp result goes to a flag register,
347   // which is used implicitly by brcond and select operations.
348   AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
349 
350   // Mips Custom Operations
351   setOperationAction(ISD::BR_JT,              MVT::Other, Expand);
352   setOperationAction(ISD::GlobalAddress,      MVT::i32,   Custom);
353   setOperationAction(ISD::BlockAddress,       MVT::i32,   Custom);
354   setOperationAction(ISD::GlobalTLSAddress,   MVT::i32,   Custom);
355   setOperationAction(ISD::JumpTable,          MVT::i32,   Custom);
356   setOperationAction(ISD::ConstantPool,       MVT::i32,   Custom);
357   setOperationAction(ISD::SELECT,             MVT::f32,   Custom);
358   setOperationAction(ISD::SELECT,             MVT::f64,   Custom);
359   setOperationAction(ISD::SELECT,             MVT::i32,   Custom);
360   setOperationAction(ISD::SETCC,              MVT::f32,   Custom);
361   setOperationAction(ISD::SETCC,              MVT::f64,   Custom);
362   setOperationAction(ISD::BRCOND,             MVT::Other, Custom);
363   setOperationAction(ISD::FCOPYSIGN,          MVT::f32,   Custom);
364   setOperationAction(ISD::FCOPYSIGN,          MVT::f64,   Custom);
365   setOperationAction(ISD::FP_TO_SINT,         MVT::i32,   Custom);
366 
367   if (!(TM.Options.NoNaNsFPMath || Subtarget.inAbs2008Mode())) {
368     setOperationAction(ISD::FABS, MVT::f32, Custom);
369     setOperationAction(ISD::FABS, MVT::f64, Custom);
370   }
371 
372   if (Subtarget.isGP64bit()) {
373     setOperationAction(ISD::GlobalAddress,      MVT::i64,   Custom);
374     setOperationAction(ISD::BlockAddress,       MVT::i64,   Custom);
375     setOperationAction(ISD::GlobalTLSAddress,   MVT::i64,   Custom);
376     setOperationAction(ISD::JumpTable,          MVT::i64,   Custom);
377     setOperationAction(ISD::ConstantPool,       MVT::i64,   Custom);
378     setOperationAction(ISD::SELECT,             MVT::i64,   Custom);
379     setOperationAction(ISD::LOAD,               MVT::i64,   Custom);
380     setOperationAction(ISD::STORE,              MVT::i64,   Custom);
381     setOperationAction(ISD::FP_TO_SINT,         MVT::i64,   Custom);
382     setOperationAction(ISD::SHL_PARTS,          MVT::i64,   Custom);
383     setOperationAction(ISD::SRA_PARTS,          MVT::i64,   Custom);
384     setOperationAction(ISD::SRL_PARTS,          MVT::i64,   Custom);
385   }
386 
387   if (!Subtarget.isGP64bit()) {
388     setOperationAction(ISD::SHL_PARTS,          MVT::i32,   Custom);
389     setOperationAction(ISD::SRA_PARTS,          MVT::i32,   Custom);
390     setOperationAction(ISD::SRL_PARTS,          MVT::i32,   Custom);
391   }
392 
393   setOperationAction(ISD::EH_DWARF_CFA,         MVT::i32,   Custom);
394   if (Subtarget.isGP64bit())
395     setOperationAction(ISD::EH_DWARF_CFA,       MVT::i64,   Custom);
396 
397   setOperationAction(ISD::SDIV, MVT::i32, Expand);
398   setOperationAction(ISD::SREM, MVT::i32, Expand);
399   setOperationAction(ISD::UDIV, MVT::i32, Expand);
400   setOperationAction(ISD::UREM, MVT::i32, Expand);
401   setOperationAction(ISD::SDIV, MVT::i64, Expand);
402   setOperationAction(ISD::SREM, MVT::i64, Expand);
403   setOperationAction(ISD::UDIV, MVT::i64, Expand);
404   setOperationAction(ISD::UREM, MVT::i64, Expand);
405 
406   // Operations not directly supported by Mips.
407   setOperationAction(ISD::BR_CC,             MVT::f32,   Expand);
408   setOperationAction(ISD::BR_CC,             MVT::f64,   Expand);
409   setOperationAction(ISD::BR_CC,             MVT::i32,   Expand);
410   setOperationAction(ISD::BR_CC,             MVT::i64,   Expand);
411   setOperationAction(ISD::SELECT_CC,         MVT::i32,   Expand);
412   setOperationAction(ISD::SELECT_CC,         MVT::i64,   Expand);
413   setOperationAction(ISD::SELECT_CC,         MVT::f32,   Expand);
414   setOperationAction(ISD::SELECT_CC,         MVT::f64,   Expand);
415   setOperationAction(ISD::UINT_TO_FP,        MVT::i32,   Expand);
416   setOperationAction(ISD::UINT_TO_FP,        MVT::i64,   Expand);
417   setOperationAction(ISD::FP_TO_UINT,        MVT::i32,   Expand);
418   setOperationAction(ISD::FP_TO_UINT,        MVT::i64,   Expand);
419   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,    Expand);
420   if (Subtarget.hasCnMips()) {
421     setOperationAction(ISD::CTPOP,           MVT::i32,   Legal);
422     setOperationAction(ISD::CTPOP,           MVT::i64,   Legal);
423   } else {
424     setOperationAction(ISD::CTPOP,           MVT::i32,   Expand);
425     setOperationAction(ISD::CTPOP,           MVT::i64,   Expand);
426   }
427   setOperationAction(ISD::CTTZ,              MVT::i32,   Expand);
428   setOperationAction(ISD::CTTZ,              MVT::i64,   Expand);
429   setOperationAction(ISD::ROTL,              MVT::i32,   Expand);
430   setOperationAction(ISD::ROTL,              MVT::i64,   Expand);
431   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32,  Expand);
432   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64,  Expand);
433 
434   if (!Subtarget.hasMips32r2())
435     setOperationAction(ISD::ROTR, MVT::i32,   Expand);
436 
437   if (!Subtarget.hasMips64r2())
438     setOperationAction(ISD::ROTR, MVT::i64,   Expand);
439 
440   setOperationAction(ISD::FSIN,              MVT::f32,   Expand);
441   setOperationAction(ISD::FSIN,              MVT::f64,   Expand);
442   setOperationAction(ISD::FCOS,              MVT::f32,   Expand);
443   setOperationAction(ISD::FCOS,              MVT::f64,   Expand);
444   setOperationAction(ISD::FSINCOS,           MVT::f32,   Expand);
445   setOperationAction(ISD::FSINCOS,           MVT::f64,   Expand);
446   setOperationAction(ISD::FPOW,              MVT::f32,   Expand);
447   setOperationAction(ISD::FPOW,              MVT::f64,   Expand);
448   setOperationAction(ISD::FLOG,              MVT::f32,   Expand);
449   setOperationAction(ISD::FLOG2,             MVT::f32,   Expand);
450   setOperationAction(ISD::FLOG10,            MVT::f32,   Expand);
451   setOperationAction(ISD::FEXP,              MVT::f32,   Expand);
452   setOperationAction(ISD::FMA,               MVT::f32,   Expand);
453   setOperationAction(ISD::FMA,               MVT::f64,   Expand);
454   setOperationAction(ISD::FREM,              MVT::f32,   Expand);
455   setOperationAction(ISD::FREM,              MVT::f64,   Expand);
456 
457   // Lower f16 conversion operations into library calls
458   setOperationAction(ISD::FP16_TO_FP,        MVT::f32,   Expand);
459   setOperationAction(ISD::FP_TO_FP16,        MVT::f32,   Expand);
460   setOperationAction(ISD::FP16_TO_FP,        MVT::f64,   Expand);
461   setOperationAction(ISD::FP_TO_FP16,        MVT::f64,   Expand);
462 
463   setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
464 
465   setOperationAction(ISD::VASTART,           MVT::Other, Custom);
466   setOperationAction(ISD::VAARG,             MVT::Other, Custom);
467   setOperationAction(ISD::VACOPY,            MVT::Other, Expand);
468   setOperationAction(ISD::VAEND,             MVT::Other, Expand);
469 
470   // Use the default for now
471   setOperationAction(ISD::STACKSAVE,         MVT::Other, Expand);
472   setOperationAction(ISD::STACKRESTORE,      MVT::Other, Expand);
473 
474   if (!Subtarget.isGP64bit()) {
475     setOperationAction(ISD::ATOMIC_LOAD,     MVT::i64,   Expand);
476     setOperationAction(ISD::ATOMIC_STORE,    MVT::i64,   Expand);
477   }
478 
479   if (!Subtarget.hasMips32r2()) {
480     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);
481     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
482   }
483 
484   // MIPS16 lacks MIPS32's clz and clo instructions.
485   if (!Subtarget.hasMips32() || Subtarget.inMips16Mode())
486     setOperationAction(ISD::CTLZ, MVT::i32, Expand);
487   if (!Subtarget.hasMips64())
488     setOperationAction(ISD::CTLZ, MVT::i64, Expand);
489 
490   if (!Subtarget.hasMips32r2())
491     setOperationAction(ISD::BSWAP, MVT::i32, Expand);
492   if (!Subtarget.hasMips64r2())
493     setOperationAction(ISD::BSWAP, MVT::i64, Expand);
494 
495   if (Subtarget.isGP64bit()) {
496     setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom);
497     setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom);
498     setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom);
499     setTruncStoreAction(MVT::i64, MVT::i32, Custom);
500   }
501 
502   setOperationAction(ISD::TRAP, MVT::Other, Legal);
503 
504   setTargetDAGCombine(ISD::SDIVREM);
505   setTargetDAGCombine(ISD::UDIVREM);
506   setTargetDAGCombine(ISD::SELECT);
507   setTargetDAGCombine(ISD::AND);
508   setTargetDAGCombine(ISD::OR);
509   setTargetDAGCombine(ISD::ADD);
510   setTargetDAGCombine(ISD::SUB);
511   setTargetDAGCombine(ISD::AssertZext);
512   setTargetDAGCombine(ISD::SHL);
513 
514   if (ABI.IsO32()) {
515     // These libcalls are not available in 32-bit.
516     setLibcallName(RTLIB::SHL_I128, nullptr);
517     setLibcallName(RTLIB::SRL_I128, nullptr);
518     setLibcallName(RTLIB::SRA_I128, nullptr);
519   }
520 
521   setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);
522 
523   // The arguments on the stack are defined in terms of 4-byte slots on O32
524   // and 8-byte slots on N32/N64.
525   setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4);
526 
527   setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP);
528 
529   MaxStoresPerMemcpy = 16;
530 
531   isMicroMips = Subtarget.inMicroMipsMode();
532 }
533 
534 const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM,
535                                                      const MipsSubtarget &STI) {
536   if (STI.inMips16Mode())
537     return createMips16TargetLowering(TM, STI);
538 
539   return createMipsSETargetLowering(TM, STI);
540 }
541 
542 // Create a fast isel object.
543 FastISel *
544 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
545                                   const TargetLibraryInfo *libInfo) const {
546   const MipsTargetMachine &TM =
547       static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget());
548 
549   // We support only the standard encoding [MIPS32,MIPS32R5] ISAs.
550   bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() &&
551                      !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() &&
552                      !Subtarget.inMicroMipsMode();
553 
554   // Disable if either of the following is true:
555   // We do not generate PIC, the ABI is not O32, LargeGOT is being used.
556   if (!TM.isPositionIndependent() || !TM.getABI().IsO32() || LargeGOT)
557     UseFastISel = false;
558 
559   return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr;
560 }
561 
562 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
563                                            EVT VT) const {
564   if (!VT.isVector())
565     return MVT::i32;
566   return VT.changeVectorElementTypeToInteger();
567 }
568 
569 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
570                                     TargetLowering::DAGCombinerInfo &DCI,
571                                     const MipsSubtarget &Subtarget) {
572   if (DCI.isBeforeLegalizeOps())
573     return SDValue();
574 
575   EVT Ty = N->getValueType(0);
576   unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
577   unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
578   unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
579                                                   MipsISD::DivRemU16;
580   SDLoc DL(N);
581 
582   SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
583                                N->getOperand(0), N->getOperand(1));
584   SDValue InChain = DAG.getEntryNode();
585   SDValue InGlue = DivRem;
586 
587   // insert MFLO
588   if (N->hasAnyUseOfValue(0)) {
589     SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
590                                             InGlue);
591     DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
592     InChain = CopyFromLo.getValue(1);
593     InGlue = CopyFromLo.getValue(2);
594   }
595 
596   // insert MFHI
597   if (N->hasAnyUseOfValue(1)) {
598     SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
599                                             HI, Ty, InGlue);
600     DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
601   }
602 
603   return SDValue();
604 }
605 
606 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
607   switch (CC) {
608   default: llvm_unreachable("Unknown fp condition code!");
609   case ISD::SETEQ:
610   case ISD::SETOEQ: return Mips::FCOND_OEQ;
611   case ISD::SETUNE: return Mips::FCOND_UNE;
612   case ISD::SETLT:
613   case ISD::SETOLT: return Mips::FCOND_OLT;
614   case ISD::SETGT:
615   case ISD::SETOGT: return Mips::FCOND_OGT;
616   case ISD::SETLE:
617   case ISD::SETOLE: return Mips::FCOND_OLE;
618   case ISD::SETGE:
619   case ISD::SETOGE: return Mips::FCOND_OGE;
620   case ISD::SETULT: return Mips::FCOND_ULT;
621   case ISD::SETULE: return Mips::FCOND_ULE;
622   case ISD::SETUGT: return Mips::FCOND_UGT;
623   case ISD::SETUGE: return Mips::FCOND_UGE;
624   case ISD::SETUO:  return Mips::FCOND_UN;
625   case ISD::SETO:   return Mips::FCOND_OR;
626   case ISD::SETNE:
627   case ISD::SETONE: return Mips::FCOND_ONE;
628   case ISD::SETUEQ: return Mips::FCOND_UEQ;
629   }
630 }
631 
632 /// This function returns true if the floating point conditional branches and
633 /// conditional moves which use condition code CC should be inverted.
634 static bool invertFPCondCodeUser(Mips::CondCode CC) {
635   if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
636     return false;
637 
638   assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
639          "Illegal Condition Code");
640 
641   return true;
642 }
643 
644 // Creates and returns an FPCmp node from a setcc node.
645 // Returns Op if setcc is not a floating point comparison.
646 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
647   // must be a SETCC node
648   if (Op.getOpcode() != ISD::SETCC)
649     return Op;
650 
651   SDValue LHS = Op.getOperand(0);
652 
653   if (!LHS.getValueType().isFloatingPoint())
654     return Op;
655 
656   SDValue RHS = Op.getOperand(1);
657   SDLoc DL(Op);
658 
659   // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
660   // node if necessary.
661   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
662 
663   return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
664                      DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32));
665 }
666 
667 // Creates and returns a CMovFPT/F node.
668 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
669                             SDValue False, const SDLoc &DL) {
670   ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
671   bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
672   SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
673 
674   return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
675                      True.getValueType(), True, FCC0, False, Cond);
676 }
677 
678 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
679                                     TargetLowering::DAGCombinerInfo &DCI,
680                                     const MipsSubtarget &Subtarget) {
681   if (DCI.isBeforeLegalizeOps())
682     return SDValue();
683 
684   SDValue SetCC = N->getOperand(0);
685 
686   if ((SetCC.getOpcode() != ISD::SETCC) ||
687       !SetCC.getOperand(0).getValueType().isInteger())
688     return SDValue();
689 
690   SDValue False = N->getOperand(2);
691   EVT FalseTy = False.getValueType();
692 
693   if (!FalseTy.isInteger())
694     return SDValue();
695 
696   ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
697 
698   // If the RHS (False) is 0, we swap the order of the operands
699   // of ISD::SELECT (obviously also inverting the condition) so that we can
700   // take advantage of conditional moves using the $0 register.
701   // Example:
702   //   return (a != 0) ? x : 0;
703   //     load $reg, x
704   //     movz $reg, $0, a
705   if (!FalseC)
706     return SDValue();
707 
708   const SDLoc DL(N);
709 
710   if (!FalseC->getZExtValue()) {
711     ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
712     SDValue True = N->getOperand(1);
713 
714     SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
715                          SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
716 
717     return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
718   }
719 
720   // If both operands are integer constants there's a possibility that we
721   // can do some interesting optimizations.
722   SDValue True = N->getOperand(1);
723   ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
724 
725   if (!TrueC || !True.getValueType().isInteger())
726     return SDValue();
727 
728   // We'll also ignore MVT::i64 operands as this optimizations proves
729   // to be ineffective because of the required sign extensions as the result
730   // of a SETCC operator is always MVT::i32 for non-vector types.
731   if (True.getValueType() == MVT::i64)
732     return SDValue();
733 
734   int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
735 
736   // 1)  (a < x) ? y : y-1
737   //  slti $reg1, a, x
738   //  addiu $reg2, $reg1, y-1
739   if (Diff == 1)
740     return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
741 
742   // 2)  (a < x) ? y-1 : y
743   //  slti $reg1, a, x
744   //  xor $reg1, $reg1, 1
745   //  addiu $reg2, $reg1, y-1
746   if (Diff == -1) {
747     ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
748     SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
749                          SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
750     return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
751   }
752 
753   // Could not optimize.
754   return SDValue();
755 }
756 
757 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG,
758                                     TargetLowering::DAGCombinerInfo &DCI,
759                                     const MipsSubtarget &Subtarget) {
760   if (DCI.isBeforeLegalizeOps())
761     return SDValue();
762 
763   SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2);
764 
765   ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse);
766   if (!FalseC || FalseC->getZExtValue())
767     return SDValue();
768 
769   // Since RHS (False) is 0, we swap the order of the True/False operands
770   // (obviously also inverting the condition) so that we can
771   // take advantage of conditional moves using the $0 register.
772   // Example:
773   //   return (a != 0) ? x : 0;
774   //     load $reg, x
775   //     movz $reg, $0, a
776   unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F :
777                                                          MipsISD::CMovFP_T;
778 
779   SDValue FCC = N->getOperand(1), Glue = N->getOperand(3);
780   return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(),
781                      ValueIfFalse, FCC, ValueIfTrue, Glue);
782 }
783 
784 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
785                                  TargetLowering::DAGCombinerInfo &DCI,
786                                  const MipsSubtarget &Subtarget) {
787   if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
788     return SDValue();
789 
790   SDValue FirstOperand = N->getOperand(0);
791   unsigned FirstOperandOpc = FirstOperand.getOpcode();
792   SDValue Mask = N->getOperand(1);
793   EVT ValTy = N->getValueType(0);
794   SDLoc DL(N);
795 
796   uint64_t Pos = 0, SMPos, SMSize;
797   ConstantSDNode *CN;
798   SDValue NewOperand;
799   unsigned Opc;
800 
801   // Op's second operand must be a shifted mask.
802   if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
803       !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
804     return SDValue();
805 
806   if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) {
807     // Pattern match EXT.
808     //  $dst = and ((sra or srl) $src , pos), (2**size - 1)
809     //  => ext $dst, $src, pos, size
810 
811     // The second operand of the shift must be an immediate.
812     if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
813       return SDValue();
814 
815     Pos = CN->getZExtValue();
816 
817     // Return if the shifted mask does not start at bit 0 or the sum of its size
818     // and Pos exceeds the word's size.
819     if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
820       return SDValue();
821 
822     Opc = MipsISD::Ext;
823     NewOperand = FirstOperand.getOperand(0);
824   } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) {
825     // Pattern match CINS.
826     //  $dst = and (shl $src , pos), mask
827     //  => cins $dst, $src, pos, size
828     // mask is a shifted mask with consecutive 1's, pos = shift amount,
829     // size = population count.
830 
831     // The second operand of the shift must be an immediate.
832     if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
833       return SDValue();
834 
835     Pos = CN->getZExtValue();
836 
837     if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 ||
838         Pos + SMSize > ValTy.getSizeInBits())
839       return SDValue();
840 
841     NewOperand = FirstOperand.getOperand(0);
842     // SMSize is 'location' (position) in this case, not size.
843     SMSize--;
844     Opc = MipsISD::CIns;
845   } else {
846     // Pattern match EXT.
847     //  $dst = and $src, (2**size - 1) , if size > 16
848     //  => ext $dst, $src, pos, size , pos = 0
849 
850     // If the mask is <= 0xffff, andi can be used instead.
851     if (CN->getZExtValue() <= 0xffff)
852       return SDValue();
853 
854     // Return if the mask doesn't start at position 0.
855     if (SMPos)
856       return SDValue();
857 
858     Opc = MipsISD::Ext;
859     NewOperand = FirstOperand;
860   }
861   return DAG.getNode(Opc, DL, ValTy, NewOperand,
862                      DAG.getConstant(Pos, DL, MVT::i32),
863                      DAG.getConstant(SMSize, DL, MVT::i32));
864 }
865 
866 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
867                                 TargetLowering::DAGCombinerInfo &DCI,
868                                 const MipsSubtarget &Subtarget) {
869   // Pattern match INS.
870   //  $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
871   //  where mask1 = (2**size - 1) << pos, mask0 = ~mask1
872   //  => ins $dst, $src, size, pos, $src1
873   if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
874     return SDValue();
875 
876   SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
877   uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
878   ConstantSDNode *CN, *CN1;
879 
880   // See if Op's first operand matches (and $src1 , mask0).
881   if (And0.getOpcode() != ISD::AND)
882     return SDValue();
883 
884   if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
885       !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
886     return SDValue();
887 
888   // See if Op's second operand matches (and (shl $src, pos), mask1).
889   if (And1.getOpcode() == ISD::AND &&
890       And1.getOperand(0).getOpcode() == ISD::SHL) {
891 
892     if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
893         !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
894       return SDValue();
895 
896     // The shift masks must have the same position and size.
897     if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
898       return SDValue();
899 
900     SDValue Shl = And1.getOperand(0);
901 
902     if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
903       return SDValue();
904 
905     unsigned Shamt = CN->getZExtValue();
906 
907     // Return if the shift amount and the first bit position of mask are not the
908     // same.
909     EVT ValTy = N->getValueType(0);
910     if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
911       return SDValue();
912 
913     SDLoc DL(N);
914     return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0),
915                        DAG.getConstant(SMPos0, DL, MVT::i32),
916                        DAG.getConstant(SMSize0, DL, MVT::i32),
917                        And0.getOperand(0));
918   } else {
919     // Pattern match DINS.
920     //  $dst = or (and $src, mask0), mask1
921     //  where mask0 = ((1 << SMSize0) -1) << SMPos0
922     //  => dins $dst, $src, pos, size
923     if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) &&
924         ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) ||
925          (SMSize0 + SMPos0 <= 32))) {
926       // Check if AND instruction has constant as argument
927       bool isConstCase = And1.getOpcode() != ISD::AND;
928       if (And1.getOpcode() == ISD::AND) {
929         if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1))))
930           return SDValue();
931       } else {
932         if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1))))
933           return SDValue();
934       }
935       // Don't generate INS if constant OR operand doesn't fit into bits
936       // cleared by constant AND operand.
937       if (CN->getSExtValue() & CN1->getSExtValue())
938         return SDValue();
939 
940       SDLoc DL(N);
941       EVT ValTy = N->getOperand(0)->getValueType(0);
942       SDValue Const1;
943       SDValue SrlX;
944       if (!isConstCase) {
945         Const1 = DAG.getConstant(SMPos0, DL, MVT::i32);
946         SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1);
947       }
948       return DAG.getNode(
949           MipsISD::Ins, DL, N->getValueType(0),
950           isConstCase
951               ? DAG.getConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy)
952               : SrlX,
953           DAG.getConstant(SMPos0, DL, MVT::i32),
954           DAG.getConstant(ValTy.getSizeInBits() / 8 < 8 ? SMSize0 & 31
955                                                         : SMSize0,
956                           DL, MVT::i32),
957           And0->getOperand(0));
958 
959     }
960     return SDValue();
961   }
962 }
963 
964 static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG,
965                                        const MipsSubtarget &Subtarget) {
966   // ROOTNode must have a multiplication as an operand for the match to be
967   // successful.
968   if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL &&
969       ROOTNode->getOperand(1).getOpcode() != ISD::MUL)
970     return SDValue();
971 
972   // We don't handle vector types here.
973   if (ROOTNode->getValueType(0).isVector())
974     return SDValue();
975 
976   // For MIPS64, madd / msub instructions are inefficent to use with 64 bit
977   // arithmetic. E.g.
978   // (add (mul a b) c) =>
979   //   let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in
980   //   MIPS64:   (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32)
981   //   or
982   //   MIPS64R2: (dins (mflo res) (mfhi res) 32 32)
983   //
984   // The overhead of setting up the Hi/Lo registers and reassembling the
985   // result makes this a dubious optimzation for MIPS64. The core of the
986   // problem is that Hi/Lo contain the upper and lower 32 bits of the
987   // operand and result.
988   //
989   // It requires a chain of 4 add/mul for MIPS64R2 to get better code
990   // density than doing it naively, 5 for MIPS64. Additionally, using
991   // madd/msub on MIPS64 requires the operands actually be 32 bit sign
992   // extended operands, not true 64 bit values.
993   //
994   // FIXME: For the moment, disable this completely for MIPS64.
995   if (Subtarget.hasMips64())
996     return SDValue();
997 
998   SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
999                      ? ROOTNode->getOperand(0)
1000                      : ROOTNode->getOperand(1);
1001 
1002   SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
1003                      ? ROOTNode->getOperand(1)
1004                      : ROOTNode->getOperand(0);
1005 
1006   // Transform this to a MADD only if the user of this node is the add.
1007   // If there are other users of the mul, this function returns here.
1008   if (!Mult.hasOneUse())
1009     return SDValue();
1010 
1011   // maddu and madd are unusual instructions in that on MIPS64 bits 63..31
1012   // must be in canonical form, i.e. sign extended. For MIPS32, the operands
1013   // of the multiply must have 32 or more sign bits, otherwise we cannot
1014   // perform this optimization. We have to check this here as we're performing
1015   // this optimization pre-legalization.
1016   SDValue MultLHS = Mult->getOperand(0);
1017   SDValue MultRHS = Mult->getOperand(1);
1018 
1019   bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND &&
1020                   MultRHS->getOpcode() == ISD::SIGN_EXTEND;
1021   bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND &&
1022                     MultRHS->getOpcode() == ISD::ZERO_EXTEND;
1023 
1024   if (!IsSigned && !IsUnsigned)
1025     return SDValue();
1026 
1027   // Initialize accumulator.
1028   SDLoc DL(ROOTNode);
1029   SDValue TopHalf;
1030   SDValue BottomHalf;
1031   BottomHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand,
1032                               CurDAG.getIntPtrConstant(0, DL));
1033 
1034   TopHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand,
1035                            CurDAG.getIntPtrConstant(1, DL));
1036   SDValue ACCIn = CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
1037                                   BottomHalf,
1038                                   TopHalf);
1039 
1040   // Create MipsMAdd(u) / MipsMSub(u) node.
1041   bool IsAdd = ROOTNode->getOpcode() == ISD::ADD;
1042   unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd)
1043                           : (IsUnsigned ? MipsISD::MSubu : MipsISD::MSub);
1044   SDValue MAddOps[3] = {
1045       CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)),
1046       CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn};
1047   EVT VTs[2] = {MVT::i32, MVT::i32};
1048   SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps);
1049 
1050   SDValue ResLo = CurDAG.getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
1051   SDValue ResHi = CurDAG.getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
1052   SDValue Combined =
1053       CurDAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResLo, ResHi);
1054   return Combined;
1055 }
1056 
1057 static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG,
1058                                  TargetLowering::DAGCombinerInfo &DCI,
1059                                  const MipsSubtarget &Subtarget) {
1060   // (sub v0 (mul v1, v2)) => (msub v1, v2, v0)
1061   if (DCI.isBeforeLegalizeOps()) {
1062     if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
1063         !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64)
1064       return performMADD_MSUBCombine(N, DAG, Subtarget);
1065 
1066     return SDValue();
1067   }
1068 
1069   return SDValue();
1070 }
1071 
1072 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
1073                                  TargetLowering::DAGCombinerInfo &DCI,
1074                                  const MipsSubtarget &Subtarget) {
1075   // (add v0 (mul v1, v2)) => (madd v1, v2, v0)
1076   if (DCI.isBeforeLegalizeOps()) {
1077     if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
1078         !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64)
1079       return performMADD_MSUBCombine(N, DAG, Subtarget);
1080 
1081     return SDValue();
1082   }
1083 
1084   // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
1085   SDValue Add = N->getOperand(1);
1086 
1087   if (Add.getOpcode() != ISD::ADD)
1088     return SDValue();
1089 
1090   SDValue Lo = Add.getOperand(1);
1091 
1092   if ((Lo.getOpcode() != MipsISD::Lo) ||
1093       (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
1094     return SDValue();
1095 
1096   EVT ValTy = N->getValueType(0);
1097   SDLoc DL(N);
1098 
1099   SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
1100                              Add.getOperand(0));
1101   return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
1102 }
1103 
1104 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
1105                                  TargetLowering::DAGCombinerInfo &DCI,
1106                                  const MipsSubtarget &Subtarget) {
1107   // Pattern match CINS.
1108   //  $dst = shl (and $src , imm), pos
1109   //  => cins $dst, $src, pos, size
1110 
1111   if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips())
1112     return SDValue();
1113 
1114   SDValue FirstOperand = N->getOperand(0);
1115   unsigned FirstOperandOpc = FirstOperand.getOpcode();
1116   SDValue SecondOperand = N->getOperand(1);
1117   EVT ValTy = N->getValueType(0);
1118   SDLoc DL(N);
1119 
1120   uint64_t Pos = 0, SMPos, SMSize;
1121   ConstantSDNode *CN;
1122   SDValue NewOperand;
1123 
1124   // The second operand of the shift must be an immediate.
1125   if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand)))
1126     return SDValue();
1127 
1128   Pos = CN->getZExtValue();
1129 
1130   if (Pos >= ValTy.getSizeInBits())
1131     return SDValue();
1132 
1133   if (FirstOperandOpc != ISD::AND)
1134     return SDValue();
1135 
1136   // AND's second operand must be a shifted mask.
1137   if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) ||
1138       !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
1139     return SDValue();
1140 
1141   // Return if the shifted mask does not start at bit 0 or the sum of its size
1142   // and Pos exceeds the word's size.
1143   if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits())
1144     return SDValue();
1145 
1146   NewOperand = FirstOperand.getOperand(0);
1147   // SMSize is 'location' (position) in this case, not size.
1148   SMSize--;
1149 
1150   return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand,
1151                      DAG.getConstant(Pos, DL, MVT::i32),
1152                      DAG.getConstant(SMSize, DL, MVT::i32));
1153 }
1154 
1155 SDValue  MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
1156   const {
1157   SelectionDAG &DAG = DCI.DAG;
1158   unsigned Opc = N->getOpcode();
1159 
1160   switch (Opc) {
1161   default: break;
1162   case ISD::SDIVREM:
1163   case ISD::UDIVREM:
1164     return performDivRemCombine(N, DAG, DCI, Subtarget);
1165   case ISD::SELECT:
1166     return performSELECTCombine(N, DAG, DCI, Subtarget);
1167   case MipsISD::CMovFP_F:
1168   case MipsISD::CMovFP_T:
1169     return performCMovFPCombine(N, DAG, DCI, Subtarget);
1170   case ISD::AND:
1171     return performANDCombine(N, DAG, DCI, Subtarget);
1172   case ISD::OR:
1173     return performORCombine(N, DAG, DCI, Subtarget);
1174   case ISD::ADD:
1175     return performADDCombine(N, DAG, DCI, Subtarget);
1176   case ISD::SHL:
1177     return performSHLCombine(N, DAG, DCI, Subtarget);
1178   case ISD::SUB:
1179     return performSUBCombine(N, DAG, DCI, Subtarget);
1180   }
1181 
1182   return SDValue();
1183 }
1184 
1185 bool MipsTargetLowering::isCheapToSpeculateCttz() const {
1186   return Subtarget.hasMips32();
1187 }
1188 
1189 bool MipsTargetLowering::isCheapToSpeculateCtlz() const {
1190   return Subtarget.hasMips32();
1191 }
1192 
1193 bool MipsTargetLowering::shouldFoldConstantShiftPairToMask(
1194     const SDNode *N, CombineLevel Level) const {
1195   if (N->getOperand(0).getValueType().isVector())
1196     return false;
1197   return true;
1198 }
1199 
1200 void
1201 MipsTargetLowering::LowerOperationWrapper(SDNode *N,
1202                                           SmallVectorImpl<SDValue> &Results,
1203                                           SelectionDAG &DAG) const {
1204   SDValue Res = LowerOperation(SDValue(N, 0), DAG);
1205 
1206   if (Res)
1207     for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
1208       Results.push_back(Res.getValue(I));
1209 }
1210 
1211 void
1212 MipsTargetLowering::ReplaceNodeResults(SDNode *N,
1213                                        SmallVectorImpl<SDValue> &Results,
1214                                        SelectionDAG &DAG) const {
1215   return LowerOperationWrapper(N, Results, DAG);
1216 }
1217 
1218 SDValue MipsTargetLowering::
1219 LowerOperation(SDValue Op, SelectionDAG &DAG) const
1220 {
1221   switch (Op.getOpcode())
1222   {
1223   case ISD::BRCOND:             return lowerBRCOND(Op, DAG);
1224   case ISD::ConstantPool:       return lowerConstantPool(Op, DAG);
1225   case ISD::GlobalAddress:      return lowerGlobalAddress(Op, DAG);
1226   case ISD::BlockAddress:       return lowerBlockAddress(Op, DAG);
1227   case ISD::GlobalTLSAddress:   return lowerGlobalTLSAddress(Op, DAG);
1228   case ISD::JumpTable:          return lowerJumpTable(Op, DAG);
1229   case ISD::SELECT:             return lowerSELECT(Op, DAG);
1230   case ISD::SETCC:              return lowerSETCC(Op, DAG);
1231   case ISD::VASTART:            return lowerVASTART(Op, DAG);
1232   case ISD::VAARG:              return lowerVAARG(Op, DAG);
1233   case ISD::FCOPYSIGN:          return lowerFCOPYSIGN(Op, DAG);
1234   case ISD::FABS:               return lowerFABS(Op, DAG);
1235   case ISD::FRAMEADDR:          return lowerFRAMEADDR(Op, DAG);
1236   case ISD::RETURNADDR:         return lowerRETURNADDR(Op, DAG);
1237   case ISD::EH_RETURN:          return lowerEH_RETURN(Op, DAG);
1238   case ISD::ATOMIC_FENCE:       return lowerATOMIC_FENCE(Op, DAG);
1239   case ISD::SHL_PARTS:          return lowerShiftLeftParts(Op, DAG);
1240   case ISD::SRA_PARTS:          return lowerShiftRightParts(Op, DAG, true);
1241   case ISD::SRL_PARTS:          return lowerShiftRightParts(Op, DAG, false);
1242   case ISD::LOAD:               return lowerLOAD(Op, DAG);
1243   case ISD::STORE:              return lowerSTORE(Op, DAG);
1244   case ISD::EH_DWARF_CFA:       return lowerEH_DWARF_CFA(Op, DAG);
1245   case ISD::FP_TO_SINT:         return lowerFP_TO_SINT(Op, DAG);
1246   }
1247   return SDValue();
1248 }
1249 
1250 //===----------------------------------------------------------------------===//
1251 //  Lower helper functions
1252 //===----------------------------------------------------------------------===//
1253 
1254 // addLiveIn - This helper function adds the specified physical register to the
1255 // MachineFunction as a live in value.  It also creates a corresponding
1256 // virtual register for it.
1257 static unsigned
1258 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
1259 {
1260   unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1261   MF.getRegInfo().addLiveIn(PReg, VReg);
1262   return VReg;
1263 }
1264 
1265 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI,
1266                                               MachineBasicBlock &MBB,
1267                                               const TargetInstrInfo &TII,
1268                                               bool Is64Bit, bool IsMicroMips) {
1269   if (NoZeroDivCheck)
1270     return &MBB;
1271 
1272   // Insert instruction "teq $divisor_reg, $zero, 7".
1273   MachineBasicBlock::iterator I(MI);
1274   MachineInstrBuilder MIB;
1275   MachineOperand &Divisor = MI.getOperand(2);
1276   MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(),
1277                 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
1278             .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
1279             .addReg(Mips::ZERO)
1280             .addImm(7);
1281 
1282   // Use the 32-bit sub-register if this is a 64-bit division.
1283   if (Is64Bit)
1284     MIB->getOperand(0).setSubReg(Mips::sub_32);
1285 
1286   // Clear Divisor's kill flag.
1287   Divisor.setIsKill(false);
1288 
1289   // We would normally delete the original instruction here but in this case
1290   // we only needed to inject an additional instruction rather than replace it.
1291 
1292   return &MBB;
1293 }
1294 
1295 MachineBasicBlock *
1296 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1297                                                 MachineBasicBlock *BB) const {
1298   switch (MI.getOpcode()) {
1299   default:
1300     llvm_unreachable("Unexpected instr type to insert");
1301   case Mips::ATOMIC_LOAD_ADD_I8:
1302     return emitAtomicBinaryPartword(MI, BB, 1);
1303   case Mips::ATOMIC_LOAD_ADD_I16:
1304     return emitAtomicBinaryPartword(MI, BB, 2);
1305   case Mips::ATOMIC_LOAD_ADD_I32:
1306     return emitAtomicBinary(MI, BB);
1307   case Mips::ATOMIC_LOAD_ADD_I64:
1308     return emitAtomicBinary(MI, BB);
1309 
1310   case Mips::ATOMIC_LOAD_AND_I8:
1311     return emitAtomicBinaryPartword(MI, BB, 1);
1312   case Mips::ATOMIC_LOAD_AND_I16:
1313     return emitAtomicBinaryPartword(MI, BB, 2);
1314   case Mips::ATOMIC_LOAD_AND_I32:
1315     return emitAtomicBinary(MI, BB);
1316   case Mips::ATOMIC_LOAD_AND_I64:
1317     return emitAtomicBinary(MI, BB);
1318 
1319   case Mips::ATOMIC_LOAD_OR_I8:
1320     return emitAtomicBinaryPartword(MI, BB, 1);
1321   case Mips::ATOMIC_LOAD_OR_I16:
1322     return emitAtomicBinaryPartword(MI, BB, 2);
1323   case Mips::ATOMIC_LOAD_OR_I32:
1324     return emitAtomicBinary(MI, BB);
1325   case Mips::ATOMIC_LOAD_OR_I64:
1326     return emitAtomicBinary(MI, BB);
1327 
1328   case Mips::ATOMIC_LOAD_XOR_I8:
1329     return emitAtomicBinaryPartword(MI, BB, 1);
1330   case Mips::ATOMIC_LOAD_XOR_I16:
1331     return emitAtomicBinaryPartword(MI, BB, 2);
1332   case Mips::ATOMIC_LOAD_XOR_I32:
1333     return emitAtomicBinary(MI, BB);
1334   case Mips::ATOMIC_LOAD_XOR_I64:
1335     return emitAtomicBinary(MI, BB);
1336 
1337   case Mips::ATOMIC_LOAD_NAND_I8:
1338     return emitAtomicBinaryPartword(MI, BB, 1);
1339   case Mips::ATOMIC_LOAD_NAND_I16:
1340     return emitAtomicBinaryPartword(MI, BB, 2);
1341   case Mips::ATOMIC_LOAD_NAND_I32:
1342     return emitAtomicBinary(MI, BB);
1343   case Mips::ATOMIC_LOAD_NAND_I64:
1344     return emitAtomicBinary(MI, BB);
1345 
1346   case Mips::ATOMIC_LOAD_SUB_I8:
1347     return emitAtomicBinaryPartword(MI, BB, 1);
1348   case Mips::ATOMIC_LOAD_SUB_I16:
1349     return emitAtomicBinaryPartword(MI, BB, 2);
1350   case Mips::ATOMIC_LOAD_SUB_I32:
1351     return emitAtomicBinary(MI, BB);
1352   case Mips::ATOMIC_LOAD_SUB_I64:
1353     return emitAtomicBinary(MI, BB);
1354 
1355   case Mips::ATOMIC_SWAP_I8:
1356     return emitAtomicBinaryPartword(MI, BB, 1);
1357   case Mips::ATOMIC_SWAP_I16:
1358     return emitAtomicBinaryPartword(MI, BB, 2);
1359   case Mips::ATOMIC_SWAP_I32:
1360     return emitAtomicBinary(MI, BB);
1361   case Mips::ATOMIC_SWAP_I64:
1362     return emitAtomicBinary(MI, BB);
1363 
1364   case Mips::ATOMIC_CMP_SWAP_I8:
1365     return emitAtomicCmpSwapPartword(MI, BB, 1);
1366   case Mips::ATOMIC_CMP_SWAP_I16:
1367     return emitAtomicCmpSwapPartword(MI, BB, 2);
1368   case Mips::ATOMIC_CMP_SWAP_I32:
1369     return emitAtomicCmpSwap(MI, BB);
1370   case Mips::ATOMIC_CMP_SWAP_I64:
1371     return emitAtomicCmpSwap(MI, BB);
1372   case Mips::PseudoSDIV:
1373   case Mips::PseudoUDIV:
1374   case Mips::DIV:
1375   case Mips::DIVU:
1376   case Mips::MOD:
1377   case Mips::MODU:
1378     return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false,
1379                                false);
1380   case Mips::SDIV_MM_Pseudo:
1381   case Mips::UDIV_MM_Pseudo:
1382   case Mips::SDIV_MM:
1383   case Mips::UDIV_MM:
1384   case Mips::DIV_MMR6:
1385   case Mips::DIVU_MMR6:
1386   case Mips::MOD_MMR6:
1387   case Mips::MODU_MMR6:
1388     return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true);
1389   case Mips::PseudoDSDIV:
1390   case Mips::PseudoDUDIV:
1391   case Mips::DDIV:
1392   case Mips::DDIVU:
1393   case Mips::DMOD:
1394   case Mips::DMODU:
1395     return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false);
1396 
1397   case Mips::PseudoSELECT_I:
1398   case Mips::PseudoSELECT_I64:
1399   case Mips::PseudoSELECT_S:
1400   case Mips::PseudoSELECT_D32:
1401   case Mips::PseudoSELECT_D64:
1402     return emitPseudoSELECT(MI, BB, false, Mips::BNE);
1403   case Mips::PseudoSELECTFP_F_I:
1404   case Mips::PseudoSELECTFP_F_I64:
1405   case Mips::PseudoSELECTFP_F_S:
1406   case Mips::PseudoSELECTFP_F_D32:
1407   case Mips::PseudoSELECTFP_F_D64:
1408     return emitPseudoSELECT(MI, BB, true, Mips::BC1F);
1409   case Mips::PseudoSELECTFP_T_I:
1410   case Mips::PseudoSELECTFP_T_I64:
1411   case Mips::PseudoSELECTFP_T_S:
1412   case Mips::PseudoSELECTFP_T_D32:
1413   case Mips::PseudoSELECTFP_T_D64:
1414     return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
1415   case Mips::PseudoD_SELECT_I:
1416   case Mips::PseudoD_SELECT_I64:
1417     return emitPseudoD_SELECT(MI, BB);
1418   }
1419 }
1420 
1421 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1422 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1423 MachineBasicBlock *
1424 MipsTargetLowering::emitAtomicBinary(MachineInstr &MI,
1425                                      MachineBasicBlock *BB) const {
1426 
1427   MachineFunction *MF = BB->getParent();
1428   MachineRegisterInfo &RegInfo = MF->getRegInfo();
1429   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1430   DebugLoc DL = MI.getDebugLoc();
1431 
1432   unsigned AtomicOp;
1433   switch (MI.getOpcode()) {
1434   case Mips::ATOMIC_LOAD_ADD_I32:
1435     AtomicOp = Mips::ATOMIC_LOAD_ADD_I32_POSTRA;
1436     break;
1437   case Mips::ATOMIC_LOAD_SUB_I32:
1438     AtomicOp = Mips::ATOMIC_LOAD_SUB_I32_POSTRA;
1439     break;
1440   case Mips::ATOMIC_LOAD_AND_I32:
1441     AtomicOp = Mips::ATOMIC_LOAD_AND_I32_POSTRA;
1442     break;
1443   case Mips::ATOMIC_LOAD_OR_I32:
1444     AtomicOp = Mips::ATOMIC_LOAD_OR_I32_POSTRA;
1445     break;
1446   case Mips::ATOMIC_LOAD_XOR_I32:
1447     AtomicOp = Mips::ATOMIC_LOAD_XOR_I32_POSTRA;
1448     break;
1449   case Mips::ATOMIC_LOAD_NAND_I32:
1450     AtomicOp = Mips::ATOMIC_LOAD_NAND_I32_POSTRA;
1451     break;
1452   case Mips::ATOMIC_SWAP_I32:
1453     AtomicOp = Mips::ATOMIC_SWAP_I32_POSTRA;
1454     break;
1455   case Mips::ATOMIC_LOAD_ADD_I64:
1456     AtomicOp = Mips::ATOMIC_LOAD_ADD_I64_POSTRA;
1457     break;
1458   case Mips::ATOMIC_LOAD_SUB_I64:
1459     AtomicOp = Mips::ATOMIC_LOAD_SUB_I64_POSTRA;
1460     break;
1461   case Mips::ATOMIC_LOAD_AND_I64:
1462     AtomicOp = Mips::ATOMIC_LOAD_AND_I64_POSTRA;
1463     break;
1464   case Mips::ATOMIC_LOAD_OR_I64:
1465     AtomicOp = Mips::ATOMIC_LOAD_OR_I64_POSTRA;
1466     break;
1467   case Mips::ATOMIC_LOAD_XOR_I64:
1468     AtomicOp = Mips::ATOMIC_LOAD_XOR_I64_POSTRA;
1469     break;
1470   case Mips::ATOMIC_LOAD_NAND_I64:
1471     AtomicOp = Mips::ATOMIC_LOAD_NAND_I64_POSTRA;
1472     break;
1473   case Mips::ATOMIC_SWAP_I64:
1474     AtomicOp = Mips::ATOMIC_SWAP_I64_POSTRA;
1475     break;
1476   default:
1477     llvm_unreachable("Unknown pseudo atomic for replacement!");
1478   }
1479 
1480   unsigned OldVal = MI.getOperand(0).getReg();
1481   unsigned Ptr = MI.getOperand(1).getReg();
1482   unsigned Incr = MI.getOperand(2).getReg();
1483   unsigned Scratch = RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal));
1484 
1485   MachineBasicBlock::iterator II(MI);
1486 
1487   // The scratch registers here with the EarlyClobber | Define | Implicit
1488   // flags is used to persuade the register allocator and the machine
1489   // verifier to accept the usage of this register. This has to be a real
1490   // register which has an UNDEF value but is dead after the instruction which
1491   // is unique among the registers chosen for the instruction.
1492 
1493   // The EarlyClobber flag has the semantic properties that the operand it is
1494   // attached to is clobbered before the rest of the inputs are read. Hence it
1495   // must be unique among the operands to the instruction.
1496   // The Define flag is needed to coerce the machine verifier that an Undef
1497   // value isn't a problem.
1498   // The Dead flag is needed as the value in scratch isn't used by any other
1499   // instruction. Kill isn't used as Dead is more precise.
1500   // The implicit flag is here due to the interaction between the other flags
1501   // and the machine verifier.
1502 
1503   // For correctness purpose, a new pseudo is introduced here. We need this
1504   // new pseudo, so that FastRegisterAllocator does not see an ll/sc sequence
1505   // that is spread over >1 basic blocks. A register allocator which
1506   // introduces (or any codegen infact) a store, can violate the expectations
1507   // of the hardware.
1508   //
1509   // An atomic read-modify-write sequence starts with a linked load
1510   // instruction and ends with a store conditional instruction. The atomic
1511   // read-modify-write sequence fails if any of the following conditions
1512   // occur between the execution of ll and sc:
1513   //   * A coherent store is completed by another process or coherent I/O
1514   //     module into the block of synchronizable physical memory containing
1515   //     the word. The size and alignment of the block is
1516   //     implementation-dependent.
1517   //   * A coherent store is executed between an LL and SC sequence on the
1518   //     same processor to the block of synchornizable physical memory
1519   //     containing the word.
1520   //
1521 
1522   unsigned PtrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Ptr));
1523   unsigned IncrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Incr));
1524 
1525   BuildMI(*BB, II, DL, TII->get(Mips::COPY), IncrCopy).addReg(Incr);
1526   BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
1527 
1528   BuildMI(*BB, II, DL, TII->get(AtomicOp))
1529       .addReg(OldVal, RegState::Define | RegState::EarlyClobber)
1530       .addReg(PtrCopy)
1531       .addReg(IncrCopy)
1532       .addReg(Scratch, RegState::Define | RegState::EarlyClobber |
1533                            RegState::Implicit | RegState::Dead);
1534 
1535   MI.eraseFromParent();
1536 
1537   return BB;
1538 }
1539 
1540 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
1541     MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg,
1542     unsigned SrcReg) const {
1543   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1544   const DebugLoc &DL = MI.getDebugLoc();
1545 
1546   if (Subtarget.hasMips32r2() && Size == 1) {
1547     BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1548     return BB;
1549   }
1550 
1551   if (Subtarget.hasMips32r2() && Size == 2) {
1552     BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1553     return BB;
1554   }
1555 
1556   MachineFunction *MF = BB->getParent();
1557   MachineRegisterInfo &RegInfo = MF->getRegInfo();
1558   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1559   unsigned ScrReg = RegInfo.createVirtualRegister(RC);
1560 
1561   assert(Size < 32);
1562   int64_t ShiftImm = 32 - (Size * 8);
1563 
1564   BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1565   BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1566 
1567   return BB;
1568 }
1569 
1570 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
1571     MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const {
1572   assert((Size == 1 || Size == 2) &&
1573          "Unsupported size for EmitAtomicBinaryPartial.");
1574 
1575   MachineFunction *MF = BB->getParent();
1576   MachineRegisterInfo &RegInfo = MF->getRegInfo();
1577   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1578   const bool ArePtrs64bit = ABI.ArePtrs64bit();
1579   const TargetRegisterClass *RCp =
1580     getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1581   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1582   DebugLoc DL = MI.getDebugLoc();
1583 
1584   unsigned Dest = MI.getOperand(0).getReg();
1585   unsigned Ptr = MI.getOperand(1).getReg();
1586   unsigned Incr = MI.getOperand(2).getReg();
1587 
1588   unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
1589   unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1590   unsigned Mask = RegInfo.createVirtualRegister(RC);
1591   unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1592   unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1593   unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1594   unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1595   unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1596   unsigned Scratch = RegInfo.createVirtualRegister(RC);
1597   unsigned Scratch2 = RegInfo.createVirtualRegister(RC);
1598   unsigned Scratch3 = RegInfo.createVirtualRegister(RC);
1599 
1600   unsigned AtomicOp = 0;
1601   switch (MI.getOpcode()) {
1602   case Mips::ATOMIC_LOAD_NAND_I8:
1603     AtomicOp = Mips::ATOMIC_LOAD_NAND_I8_POSTRA;
1604     break;
1605   case Mips::ATOMIC_LOAD_NAND_I16:
1606     AtomicOp = Mips::ATOMIC_LOAD_NAND_I16_POSTRA;
1607     break;
1608   case Mips::ATOMIC_SWAP_I8:
1609     AtomicOp = Mips::ATOMIC_SWAP_I8_POSTRA;
1610     break;
1611   case Mips::ATOMIC_SWAP_I16:
1612     AtomicOp = Mips::ATOMIC_SWAP_I16_POSTRA;
1613     break;
1614   case Mips::ATOMIC_LOAD_ADD_I8:
1615     AtomicOp = Mips::ATOMIC_LOAD_ADD_I8_POSTRA;
1616     break;
1617   case Mips::ATOMIC_LOAD_ADD_I16:
1618     AtomicOp = Mips::ATOMIC_LOAD_ADD_I16_POSTRA;
1619     break;
1620   case Mips::ATOMIC_LOAD_SUB_I8:
1621     AtomicOp = Mips::ATOMIC_LOAD_SUB_I8_POSTRA;
1622     break;
1623   case Mips::ATOMIC_LOAD_SUB_I16:
1624     AtomicOp = Mips::ATOMIC_LOAD_SUB_I16_POSTRA;
1625     break;
1626   case Mips::ATOMIC_LOAD_AND_I8:
1627     AtomicOp = Mips::ATOMIC_LOAD_AND_I8_POSTRA;
1628     break;
1629   case Mips::ATOMIC_LOAD_AND_I16:
1630     AtomicOp = Mips::ATOMIC_LOAD_AND_I16_POSTRA;
1631     break;
1632   case Mips::ATOMIC_LOAD_OR_I8:
1633     AtomicOp = Mips::ATOMIC_LOAD_OR_I8_POSTRA;
1634     break;
1635   case Mips::ATOMIC_LOAD_OR_I16:
1636     AtomicOp = Mips::ATOMIC_LOAD_OR_I16_POSTRA;
1637     break;
1638   case Mips::ATOMIC_LOAD_XOR_I8:
1639     AtomicOp = Mips::ATOMIC_LOAD_XOR_I8_POSTRA;
1640     break;
1641   case Mips::ATOMIC_LOAD_XOR_I16:
1642     AtomicOp = Mips::ATOMIC_LOAD_XOR_I16_POSTRA;
1643     break;
1644   default:
1645     llvm_unreachable("Unknown subword atomic pseudo for expansion!");
1646   }
1647 
1648   // insert new blocks after the current block
1649   const BasicBlock *LLVM_BB = BB->getBasicBlock();
1650   MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1651   MachineFunction::iterator It = ++BB->getIterator();
1652   MF->insert(It, exitMBB);
1653 
1654   // Transfer the remainder of BB and its successor edges to exitMBB.
1655   exitMBB->splice(exitMBB->begin(), BB,
1656                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
1657   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1658 
1659   BB->addSuccessor(exitMBB, BranchProbability::getOne());
1660 
1661   //  thisMBB:
1662   //    addiu   masklsb2,$0,-4                # 0xfffffffc
1663   //    and     alignedaddr,ptr,masklsb2
1664   //    andi    ptrlsb2,ptr,3
1665   //    sll     shiftamt,ptrlsb2,3
1666   //    ori     maskupper,$0,255               # 0xff
1667   //    sll     mask,maskupper,shiftamt
1668   //    nor     mask2,$0,mask
1669   //    sll     incr2,incr,shiftamt
1670 
1671   int64_t MaskImm = (Size == 1) ? 255 : 65535;
1672   BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2)
1673     .addReg(ABI.GetNullPtr()).addImm(-4);
1674   BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr)
1675     .addReg(Ptr).addReg(MaskLSB2);
1676   BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1677       .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1678   if (Subtarget.isLittle()) {
1679     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1680   } else {
1681     unsigned Off = RegInfo.createVirtualRegister(RC);
1682     BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1683       .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1684     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1685   }
1686   BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1687     .addReg(Mips::ZERO).addImm(MaskImm);
1688   BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1689     .addReg(MaskUpper).addReg(ShiftAmt);
1690   BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1691   BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1692 
1693 
1694   // The purposes of the flags on the scratch registers is explained in
1695   // emitAtomicBinary. In summary, we need a scratch register which is going to
1696   // be undef, that is unique among registers chosen for the instruction.
1697 
1698   BuildMI(BB, DL, TII->get(AtomicOp))
1699       .addReg(Dest, RegState::Define | RegState::EarlyClobber)
1700       .addReg(AlignedAddr)
1701       .addReg(Incr2)
1702       .addReg(Mask)
1703       .addReg(Mask2)
1704       .addReg(ShiftAmt)
1705       .addReg(Scratch, RegState::EarlyClobber | RegState::Define |
1706                            RegState::Dead | RegState::Implicit)
1707       .addReg(Scratch2, RegState::EarlyClobber | RegState::Define |
1708                             RegState::Dead | RegState::Implicit)
1709       .addReg(Scratch3, RegState::EarlyClobber | RegState::Define |
1710                             RegState::Dead | RegState::Implicit);
1711 
1712   MI.eraseFromParent(); // The instruction is gone now.
1713 
1714   return exitMBB;
1715 }
1716 
1717 // Lower atomic compare and swap to a pseudo instruction, taking care to
1718 // define a scratch register for the pseudo instruction's expansion. The
1719 // instruction is expanded after the register allocator as to prevent
1720 // the insertion of stores between the linked load and the store conditional.
1721 
1722 MachineBasicBlock *
1723 MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI,
1724                                       MachineBasicBlock *BB) const {
1725 
1726   assert((MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ||
1727           MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I64) &&
1728          "Unsupported atomic pseudo for EmitAtomicCmpSwap.");
1729 
1730   const unsigned Size = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ? 4 : 8;
1731 
1732   MachineFunction *MF = BB->getParent();
1733   MachineRegisterInfo &MRI = MF->getRegInfo();
1734   const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1735   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1736   DebugLoc DL = MI.getDebugLoc();
1737 
1738   unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32
1739                           ? Mips::ATOMIC_CMP_SWAP_I32_POSTRA
1740                           : Mips::ATOMIC_CMP_SWAP_I64_POSTRA;
1741   unsigned Dest = MI.getOperand(0).getReg();
1742   unsigned Ptr = MI.getOperand(1).getReg();
1743   unsigned OldVal = MI.getOperand(2).getReg();
1744   unsigned NewVal = MI.getOperand(3).getReg();
1745 
1746   unsigned Scratch = MRI.createVirtualRegister(RC);
1747   MachineBasicBlock::iterator II(MI);
1748 
1749   // We need to create copies of the various registers and kill them at the
1750   // atomic pseudo. If the copies are not made, when the atomic is expanded
1751   // after fast register allocation, the spills will end up outside of the
1752   // blocks that their values are defined in, causing livein errors.
1753 
1754   unsigned PtrCopy = MRI.createVirtualRegister(MRI.getRegClass(Ptr));
1755   unsigned OldValCopy = MRI.createVirtualRegister(MRI.getRegClass(OldVal));
1756   unsigned NewValCopy = MRI.createVirtualRegister(MRI.getRegClass(NewVal));
1757 
1758   BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
1759   BuildMI(*BB, II, DL, TII->get(Mips::COPY), OldValCopy).addReg(OldVal);
1760   BuildMI(*BB, II, DL, TII->get(Mips::COPY), NewValCopy).addReg(NewVal);
1761 
1762   // The purposes of the flags on the scratch registers is explained in
1763   // emitAtomicBinary. In summary, we need a scratch register which is going to
1764   // be undef, that is unique among registers chosen for the instruction.
1765 
1766   BuildMI(*BB, II, DL, TII->get(AtomicOp))
1767       .addReg(Dest, RegState::Define | RegState::EarlyClobber)
1768       .addReg(PtrCopy, RegState::Kill)
1769       .addReg(OldValCopy, RegState::Kill)
1770       .addReg(NewValCopy, RegState::Kill)
1771       .addReg(Scratch, RegState::EarlyClobber | RegState::Define |
1772                            RegState::Dead | RegState::Implicit);
1773 
1774   MI.eraseFromParent(); // The instruction is gone now.
1775 
1776   return BB;
1777 }
1778 
1779 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
1780     MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const {
1781   assert((Size == 1 || Size == 2) &&
1782       "Unsupported size for EmitAtomicCmpSwapPartial.");
1783 
1784   MachineFunction *MF = BB->getParent();
1785   MachineRegisterInfo &RegInfo = MF->getRegInfo();
1786   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1787   const bool ArePtrs64bit = ABI.ArePtrs64bit();
1788   const TargetRegisterClass *RCp =
1789     getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1790   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1791   DebugLoc DL = MI.getDebugLoc();
1792 
1793   unsigned Dest = MI.getOperand(0).getReg();
1794   unsigned Ptr = MI.getOperand(1).getReg();
1795   unsigned CmpVal = MI.getOperand(2).getReg();
1796   unsigned NewVal = MI.getOperand(3).getReg();
1797 
1798   unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
1799   unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1800   unsigned Mask = RegInfo.createVirtualRegister(RC);
1801   unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1802   unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1803   unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1804   unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1805   unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1806   unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1807   unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1808   unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1809   unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I8
1810                           ? Mips::ATOMIC_CMP_SWAP_I8_POSTRA
1811                           : Mips::ATOMIC_CMP_SWAP_I16_POSTRA;
1812 
1813   // The scratch registers here with the EarlyClobber | Define | Dead | Implicit
1814   // flags are used to coerce the register allocator and the machine verifier to
1815   // accept the usage of these registers.
1816   // The EarlyClobber flag has the semantic properties that the operand it is
1817   // attached to is clobbered before the rest of the inputs are read. Hence it
1818   // must be unique among the operands to the instruction.
1819   // The Define flag is needed to coerce the machine verifier that an Undef
1820   // value isn't a problem.
1821   // The Dead flag is needed as the value in scratch isn't used by any other
1822   // instruction. Kill isn't used as Dead is more precise.
1823   unsigned Scratch = RegInfo.createVirtualRegister(RC);
1824   unsigned Scratch2 = RegInfo.createVirtualRegister(RC);
1825 
1826   // insert new blocks after the current block
1827   const BasicBlock *LLVM_BB = BB->getBasicBlock();
1828   MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1829   MachineFunction::iterator It = ++BB->getIterator();
1830   MF->insert(It, exitMBB);
1831 
1832   // Transfer the remainder of BB and its successor edges to exitMBB.
1833   exitMBB->splice(exitMBB->begin(), BB,
1834                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
1835   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1836 
1837   BB->addSuccessor(exitMBB, BranchProbability::getOne());
1838 
1839   //  thisMBB:
1840   //    addiu   masklsb2,$0,-4                # 0xfffffffc
1841   //    and     alignedaddr,ptr,masklsb2
1842   //    andi    ptrlsb2,ptr,3
1843   //    xori    ptrlsb2,ptrlsb2,3              # Only for BE
1844   //    sll     shiftamt,ptrlsb2,3
1845   //    ori     maskupper,$0,255               # 0xff
1846   //    sll     mask,maskupper,shiftamt
1847   //    nor     mask2,$0,mask
1848   //    andi    maskedcmpval,cmpval,255
1849   //    sll     shiftedcmpval,maskedcmpval,shiftamt
1850   //    andi    maskednewval,newval,255
1851   //    sll     shiftednewval,maskednewval,shiftamt
1852   int64_t MaskImm = (Size == 1) ? 255 : 65535;
1853   BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
1854     .addReg(ABI.GetNullPtr()).addImm(-4);
1855   BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
1856     .addReg(Ptr).addReg(MaskLSB2);
1857   BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1858       .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1859   if (Subtarget.isLittle()) {
1860     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1861   } else {
1862     unsigned Off = RegInfo.createVirtualRegister(RC);
1863     BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1864       .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1865     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1866   }
1867   BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1868     .addReg(Mips::ZERO).addImm(MaskImm);
1869   BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1870     .addReg(MaskUpper).addReg(ShiftAmt);
1871   BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1872   BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1873     .addReg(CmpVal).addImm(MaskImm);
1874   BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1875     .addReg(MaskedCmpVal).addReg(ShiftAmt);
1876   BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1877     .addReg(NewVal).addImm(MaskImm);
1878   BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1879     .addReg(MaskedNewVal).addReg(ShiftAmt);
1880 
1881   // The purposes of the flags on the scratch registers are explained in
1882   // emitAtomicBinary. In summary, we need a scratch register which is going to
1883   // be undef, that is unique among the register chosen for the instruction.
1884 
1885   BuildMI(BB, DL, TII->get(AtomicOp))
1886       .addReg(Dest, RegState::Define | RegState::EarlyClobber)
1887       .addReg(AlignedAddr)
1888       .addReg(Mask)
1889       .addReg(ShiftedCmpVal)
1890       .addReg(Mask2)
1891       .addReg(ShiftedNewVal)
1892       .addReg(ShiftAmt)
1893       .addReg(Scratch, RegState::EarlyClobber | RegState::Define |
1894                            RegState::Dead | RegState::Implicit)
1895       .addReg(Scratch2, RegState::EarlyClobber | RegState::Define |
1896                             RegState::Dead | RegState::Implicit);
1897 
1898   MI.eraseFromParent(); // The instruction is gone now.
1899 
1900   return exitMBB;
1901 }
1902 
1903 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1904   // The first operand is the chain, the second is the condition, the third is
1905   // the block to branch to if the condition is true.
1906   SDValue Chain = Op.getOperand(0);
1907   SDValue Dest = Op.getOperand(2);
1908   SDLoc DL(Op);
1909 
1910   assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1911   SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
1912 
1913   // Return if flag is not set by a floating point comparison.
1914   if (CondRes.getOpcode() != MipsISD::FPCmp)
1915     return Op;
1916 
1917   SDValue CCNode  = CondRes.getOperand(2);
1918   Mips::CondCode CC =
1919     (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1920   unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
1921   SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32);
1922   SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
1923   return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
1924                      FCC0, Dest, CondRes);
1925 }
1926 
1927 SDValue MipsTargetLowering::
1928 lowerSELECT(SDValue Op, SelectionDAG &DAG) const
1929 {
1930   assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1931   SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
1932 
1933   // Return if flag is not set by a floating point comparison.
1934   if (Cond.getOpcode() != MipsISD::FPCmp)
1935     return Op;
1936 
1937   return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1938                       SDLoc(Op));
1939 }
1940 
1941 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1942   assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1943   SDValue Cond = createFPCmp(DAG, Op);
1944 
1945   assert(Cond.getOpcode() == MipsISD::FPCmp &&
1946          "Floating point operand expected.");
1947 
1948   SDLoc DL(Op);
1949   SDValue True  = DAG.getConstant(1, DL, MVT::i32);
1950   SDValue False = DAG.getConstant(0, DL, MVT::i32);
1951 
1952   return createCMovFP(DAG, Cond, True, False, DL);
1953 }
1954 
1955 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
1956                                                SelectionDAG &DAG) const {
1957   EVT Ty = Op.getValueType();
1958   GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
1959   const GlobalValue *GV = N->getGlobal();
1960 
1961   if (!isPositionIndependent()) {
1962     const MipsTargetObjectFile *TLOF =
1963         static_cast<const MipsTargetObjectFile *>(
1964             getTargetMachine().getObjFileLowering());
1965     const GlobalObject *GO = GV->getBaseObject();
1966     if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine()))
1967       // %gp_rel relocation
1968       return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
1969 
1970                                  // %hi/%lo relocation
1971     return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
1972                                  // %highest/%higher/%hi/%lo relocation
1973                                  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
1974   }
1975 
1976   // Every other architecture would use shouldAssumeDSOLocal in here, but
1977   // mips is special.
1978   // * In PIC code mips requires got loads even for local statics!
1979   // * To save on got entries, for local statics the got entry contains the
1980   //   page and an additional add instruction takes care of the low bits.
1981   // * It is legal to access a hidden symbol with a non hidden undefined,
1982   //   so one cannot guarantee that all access to a hidden symbol will know
1983   //   it is hidden.
1984   // * Mips linkers don't support creating a page and a full got entry for
1985   //   the same symbol.
1986   // * Given all that, we have to use a full got entry for hidden symbols :-(
1987   if (GV->hasLocalLinkage())
1988     return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
1989 
1990   if (LargeGOT)
1991     return getAddrGlobalLargeGOT(
1992         N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16,
1993         DAG.getEntryNode(),
1994         MachinePointerInfo::getGOT(DAG.getMachineFunction()));
1995 
1996   return getAddrGlobal(
1997       N, SDLoc(N), Ty, DAG,
1998       (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT,
1999       DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2000 }
2001 
2002 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
2003                                               SelectionDAG &DAG) const {
2004   BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
2005   EVT Ty = Op.getValueType();
2006 
2007   if (!isPositionIndependent())
2008     return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2009                                 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2010 
2011   return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2012 }
2013 
2014 SDValue MipsTargetLowering::
2015 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
2016 {
2017   // If the relocation model is PIC, use the General Dynamic TLS Model or
2018   // Local Dynamic TLS model, otherwise use the Initial Exec or
2019   // Local Exec TLS Model.
2020 
2021   GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2022   if (DAG.getTarget().useEmulatedTLS())
2023     return LowerToTLSEmulatedModel(GA, DAG);
2024 
2025   SDLoc DL(GA);
2026   const GlobalValue *GV = GA->getGlobal();
2027   EVT PtrVT = getPointerTy(DAG.getDataLayout());
2028 
2029   TLSModel::Model model = getTargetMachine().getTLSModel(GV);
2030 
2031   if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
2032     // General Dynamic and Local Dynamic TLS Model.
2033     unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
2034                                                       : MipsII::MO_TLSGD;
2035 
2036     SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
2037     SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
2038                                    getGlobalReg(DAG, PtrVT), TGA);
2039     unsigned PtrSize = PtrVT.getSizeInBits();
2040     IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
2041 
2042     SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
2043 
2044     ArgListTy Args;
2045     ArgListEntry Entry;
2046     Entry.Node = Argument;
2047     Entry.Ty = PtrTy;
2048     Args.push_back(Entry);
2049 
2050     TargetLowering::CallLoweringInfo CLI(DAG);
2051     CLI.setDebugLoc(DL)
2052         .setChain(DAG.getEntryNode())
2053         .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args));
2054     std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2055 
2056     SDValue Ret = CallResult.first;
2057 
2058     if (model != TLSModel::LocalDynamic)
2059       return Ret;
2060 
2061     SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2062                                                MipsII::MO_DTPREL_HI);
2063     SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi);
2064     SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2065                                                MipsII::MO_DTPREL_LO);
2066     SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
2067     SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
2068     return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
2069   }
2070 
2071   SDValue Offset;
2072   if (model == TLSModel::InitialExec) {
2073     // Initial Exec TLS Model
2074     SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2075                                              MipsII::MO_GOTTPREL);
2076     TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
2077                       TGA);
2078     Offset =
2079         DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo());
2080   } else {
2081     // Local Exec TLS Model
2082     assert(model == TLSModel::LocalExec);
2083     SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2084                                                MipsII::MO_TPREL_HI);
2085     SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2086                                                MipsII::MO_TPREL_LO);
2087     SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi);
2088     SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
2089     Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
2090   }
2091 
2092   SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
2093   return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
2094 }
2095 
2096 SDValue MipsTargetLowering::
2097 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
2098 {
2099   JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
2100   EVT Ty = Op.getValueType();
2101 
2102   if (!isPositionIndependent())
2103     return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2104                                 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2105 
2106   return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2107 }
2108 
2109 SDValue MipsTargetLowering::
2110 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
2111 {
2112   ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
2113   EVT Ty = Op.getValueType();
2114 
2115   if (!isPositionIndependent()) {
2116     const MipsTargetObjectFile *TLOF =
2117         static_cast<const MipsTargetObjectFile *>(
2118             getTargetMachine().getObjFileLowering());
2119 
2120     if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(),
2121                                        getTargetMachine()))
2122       // %gp_rel relocation
2123       return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
2124 
2125     return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2126                                 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2127   }
2128 
2129  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2130 }
2131 
2132 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2133   MachineFunction &MF = DAG.getMachineFunction();
2134   MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2135 
2136   SDLoc DL(Op);
2137   SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2138                                  getPointerTy(MF.getDataLayout()));
2139 
2140   // vastart just stores the address of the VarArgsFrameIndex slot into the
2141   // memory location argument.
2142   const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2143   return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
2144                       MachinePointerInfo(SV));
2145 }
2146 
2147 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
2148   SDNode *Node = Op.getNode();
2149   EVT VT = Node->getValueType(0);
2150   SDValue Chain = Node->getOperand(0);
2151   SDValue VAListPtr = Node->getOperand(1);
2152   unsigned Align = Node->getConstantOperandVal(3);
2153   const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2154   SDLoc DL(Node);
2155   unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4;
2156 
2157   SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain,
2158                                    VAListPtr, MachinePointerInfo(SV));
2159   SDValue VAList = VAListLoad;
2160 
2161   // Re-align the pointer if necessary.
2162   // It should only ever be necessary for 64-bit types on O32 since the minimum
2163   // argument alignment is the same as the maximum type alignment for N32/N64.
2164   //
2165   // FIXME: We currently align too often. The code generator doesn't notice
2166   //        when the pointer is still aligned from the last va_arg (or pair of
2167   //        va_args for the i64 on O32 case).
2168   if (Align > getMinStackArgumentAlignment()) {
2169     assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
2170 
2171     VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
2172                          DAG.getConstant(Align - 1, DL, VAList.getValueType()));
2173 
2174     VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList,
2175                          DAG.getConstant(-(int64_t)Align, DL,
2176                                          VAList.getValueType()));
2177   }
2178 
2179   // Increment the pointer, VAList, to the next vaarg.
2180   auto &TD = DAG.getDataLayout();
2181   unsigned ArgSizeInBytes =
2182       TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
2183   SDValue Tmp3 =
2184       DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
2185                   DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes),
2186                                   DL, VAList.getValueType()));
2187   // Store the incremented VAList to the legalized pointer
2188   Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
2189                        MachinePointerInfo(SV));
2190 
2191   // In big-endian mode we must adjust the pointer when the load size is smaller
2192   // than the argument slot size. We must also reduce the known alignment to
2193   // match. For example in the N64 ABI, we must add 4 bytes to the offset to get
2194   // the correct half of the slot, and reduce the alignment from 8 (slot
2195   // alignment) down to 4 (type alignment).
2196   if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
2197     unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
2198     VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
2199                          DAG.getIntPtrConstant(Adjustment, DL));
2200   }
2201   // Load the actual argument out of the pointer VAList
2202   return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo());
2203 }
2204 
2205 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
2206                                 bool HasExtractInsert) {
2207   EVT TyX = Op.getOperand(0).getValueType();
2208   EVT TyY = Op.getOperand(1).getValueType();
2209   SDLoc DL(Op);
2210   SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2211   SDValue Const31 = DAG.getConstant(31, DL, MVT::i32);
2212   SDValue Res;
2213 
2214   // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2215   // to i32.
2216   SDValue X = (TyX == MVT::f32) ?
2217     DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2218     DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2219                 Const1);
2220   SDValue Y = (TyY == MVT::f32) ?
2221     DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
2222     DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
2223                 Const1);
2224 
2225   if (HasExtractInsert) {
2226     // ext  E, Y, 31, 1  ; extract bit31 of Y
2227     // ins  X, E, 31, 1  ; insert extracted bit at bit31 of X
2228     SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
2229     Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
2230   } else {
2231     // sll SllX, X, 1
2232     // srl SrlX, SllX, 1
2233     // srl SrlY, Y, 31
2234     // sll SllY, SrlX, 31
2235     // or  Or, SrlX, SllY
2236     SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2237     SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2238     SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
2239     SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
2240     Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
2241   }
2242 
2243   if (TyX == MVT::f32)
2244     return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
2245 
2246   SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2247                              Op.getOperand(0),
2248                              DAG.getConstant(0, DL, MVT::i32));
2249   return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2250 }
2251 
2252 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
2253                                 bool HasExtractInsert) {
2254   unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
2255   unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
2256   EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
2257   SDLoc DL(Op);
2258   SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2259 
2260   // Bitcast to integer nodes.
2261   SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
2262   SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
2263 
2264   if (HasExtractInsert) {
2265     // ext  E, Y, width(Y) - 1, 1  ; extract bit width(Y)-1 of Y
2266     // ins  X, E, width(X) - 1, 1  ; insert extracted bit at bit width(X)-1 of X
2267     SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
2268                             DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1);
2269 
2270     if (WidthX > WidthY)
2271       E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
2272     else if (WidthY > WidthX)
2273       E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
2274 
2275     SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
2276                             DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1,
2277                             X);
2278     return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
2279   }
2280 
2281   // (d)sll SllX, X, 1
2282   // (d)srl SrlX, SllX, 1
2283   // (d)srl SrlY, Y, width(Y)-1
2284   // (d)sll SllY, SrlX, width(Y)-1
2285   // or     Or, SrlX, SllY
2286   SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
2287   SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
2288   SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2289                              DAG.getConstant(WidthY - 1, DL, MVT::i32));
2290 
2291   if (WidthX > WidthY)
2292     SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
2293   else if (WidthY > WidthX)
2294     SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
2295 
2296   SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2297                              DAG.getConstant(WidthX - 1, DL, MVT::i32));
2298   SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2299   return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2300 }
2301 
2302 SDValue
2303 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2304   if (Subtarget.isGP64bit())
2305     return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert());
2306 
2307   return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert());
2308 }
2309 
2310 static SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG,
2311                            bool HasExtractInsert) {
2312   SDLoc DL(Op);
2313   SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32);
2314 
2315   // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2316   // to i32.
2317   SDValue X = (Op.getValueType() == MVT::f32)
2318                   ? DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0))
2319                   : DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2320                                 Op.getOperand(0), Const1);
2321 
2322   // Clear MSB.
2323   if (HasExtractInsert)
2324     Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
2325                       DAG.getRegister(Mips::ZERO, MVT::i32),
2326                       DAG.getConstant(31, DL, MVT::i32), Const1, X);
2327   else {
2328     // TODO: Provide DAG patterns which transform (and x, cst)
2329     // back to a (shl (srl x (clz cst)) (clz cst)) sequence.
2330     SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2331     Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2332   }
2333 
2334   if (Op.getValueType() == MVT::f32)
2335     return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
2336 
2337   // FIXME: For mips32r2, the sequence of (BuildPairF64 (ins (ExtractElementF64
2338   // Op 1), $zero, 31 1) (ExtractElementF64 Op 0)) and the Op has one use, we
2339   // should be able to drop the usage of mfc1/mtc1 and rewrite the register in
2340   // place.
2341   SDValue LowX =
2342       DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2343                   DAG.getConstant(0, DL, MVT::i32));
2344   return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2345 }
2346 
2347 static SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG,
2348                            bool HasExtractInsert) {
2349   SDLoc DL(Op);
2350   SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32);
2351 
2352   // Bitcast to integer node.
2353   SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
2354 
2355   // Clear MSB.
2356   if (HasExtractInsert)
2357     Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
2358                       DAG.getRegister(Mips::ZERO_64, MVT::i64),
2359                       DAG.getConstant(63, DL, MVT::i32), Const1, X);
2360   else {
2361     SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
2362     Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
2363   }
2364 
2365   return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
2366 }
2367 
2368 SDValue MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const {
2369   if ((ABI.IsN32() || ABI.IsN64()) && (Op.getValueType() == MVT::f64))
2370     return lowerFABS64(Op, DAG, Subtarget.hasExtractInsert());
2371 
2372   return lowerFABS32(Op, DAG, Subtarget.hasExtractInsert());
2373 }
2374 
2375 SDValue MipsTargetLowering::
2376 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2377   // check the depth
2378   if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() != 0) {
2379     DAG.getContext()->emitError(
2380         "return address can be determined only for current frame");
2381     return SDValue();
2382   }
2383 
2384   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2385   MFI.setFrameAddressIsTaken(true);
2386   EVT VT = Op.getValueType();
2387   SDLoc DL(Op);
2388   SDValue FrameAddr = DAG.getCopyFromReg(
2389       DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT);
2390   return FrameAddr;
2391 }
2392 
2393 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
2394                                             SelectionDAG &DAG) const {
2395   if (verifyReturnAddressArgumentIsConstant(Op, DAG))
2396     return SDValue();
2397 
2398   // check the depth
2399   if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() != 0) {
2400     DAG.getContext()->emitError(
2401         "return address can be determined only for current frame");
2402     return SDValue();
2403   }
2404 
2405   MachineFunction &MF = DAG.getMachineFunction();
2406   MachineFrameInfo &MFI = MF.getFrameInfo();
2407   MVT VT = Op.getSimpleValueType();
2408   unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
2409   MFI.setReturnAddressIsTaken(true);
2410 
2411   // Return RA, which contains the return address. Mark it an implicit live-in.
2412   unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2413   return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
2414 }
2415 
2416 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is
2417 // generated from __builtin_eh_return (offset, handler)
2418 // The effect of this is to adjust the stack pointer by "offset"
2419 // and then branch to "handler".
2420 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2421                                                                      const {
2422   MachineFunction &MF = DAG.getMachineFunction();
2423   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2424 
2425   MipsFI->setCallsEhReturn();
2426   SDValue Chain     = Op.getOperand(0);
2427   SDValue Offset    = Op.getOperand(1);
2428   SDValue Handler   = Op.getOperand(2);
2429   SDLoc DL(Op);
2430   EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2431 
2432   // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2433   // EH_RETURN nodes, so that instructions are emitted back-to-back.
2434   unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1;
2435   unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
2436   Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2437   Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2438   return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
2439                      DAG.getRegister(OffsetReg, Ty),
2440                      DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())),
2441                      Chain.getValue(1));
2442 }
2443 
2444 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
2445                                               SelectionDAG &DAG) const {
2446   // FIXME: Need pseudo-fence for 'singlethread' fences
2447   // FIXME: Set SType for weaker fences where supported/appropriate.
2448   unsigned SType = 0;
2449   SDLoc DL(Op);
2450   return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
2451                      DAG.getConstant(SType, DL, MVT::i32));
2452 }
2453 
2454 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
2455                                                 SelectionDAG &DAG) const {
2456   SDLoc DL(Op);
2457   MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2458 
2459   SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2460   SDValue Shamt = Op.getOperand(2);
2461   // if shamt < (VT.bits):
2462   //  lo = (shl lo, shamt)
2463   //  hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2464   // else:
2465   //  lo = 0
2466   //  hi = (shl lo, shamt[4:0])
2467   SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2468                             DAG.getConstant(-1, DL, MVT::i32));
2469   SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2470                                       DAG.getConstant(1, DL, VT));
2471   SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
2472   SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2473   SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2474   SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
2475   SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2476                              DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2477   Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2478                    DAG.getConstant(0, DL, VT), ShiftLeftLo);
2479   Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
2480 
2481   SDValue Ops[2] = {Lo, Hi};
2482   return DAG.getMergeValues(Ops, DL);
2483 }
2484 
2485 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2486                                                  bool IsSRA) const {
2487   SDLoc DL(Op);
2488   SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2489   SDValue Shamt = Op.getOperand(2);
2490   MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2491 
2492   // if shamt < (VT.bits):
2493   //  lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2494   //  if isSRA:
2495   //    hi = (sra hi, shamt)
2496   //  else:
2497   //    hi = (srl hi, shamt)
2498   // else:
2499   //  if isSRA:
2500   //   lo = (sra hi, shamt[4:0])
2501   //   hi = (sra hi, 31)
2502   //  else:
2503   //   lo = (srl hi, shamt[4:0])
2504   //   hi = 0
2505   SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2506                             DAG.getConstant(-1, DL, MVT::i32));
2507   SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
2508                                      DAG.getConstant(1, DL, VT));
2509   SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
2510   SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2511   SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2512   SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
2513                                      DL, VT, Hi, Shamt);
2514   SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2515                              DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2516   SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
2517                             DAG.getConstant(VT.getSizeInBits() - 1, DL, VT));
2518 
2519   if (!(Subtarget.hasMips4() || Subtarget.hasMips32())) {
2520     SDVTList VTList = DAG.getVTList(VT, VT);
2521     return DAG.getNode(Subtarget.isGP64bit() ? Mips::PseudoD_SELECT_I64
2522                                              : Mips::PseudoD_SELECT_I,
2523                        DL, VTList, Cond, ShiftRightHi,
2524                        IsSRA ? Ext : DAG.getConstant(0, DL, VT), Or,
2525                        ShiftRightHi);
2526   }
2527 
2528   Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
2529   Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2530                    IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi);
2531 
2532   SDValue Ops[2] = {Lo, Hi};
2533   return DAG.getMergeValues(Ops, DL);
2534 }
2535 
2536 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2537                             SDValue Chain, SDValue Src, unsigned Offset) {
2538   SDValue Ptr = LD->getBasePtr();
2539   EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2540   EVT BasePtrVT = Ptr.getValueType();
2541   SDLoc DL(LD);
2542   SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2543 
2544   if (Offset)
2545     Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2546                       DAG.getConstant(Offset, DL, BasePtrVT));
2547 
2548   SDValue Ops[] = { Chain, Ptr, Src };
2549   return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2550                                  LD->getMemOperand());
2551 }
2552 
2553 // Expand an unaligned 32 or 64-bit integer load node.
2554 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2555   LoadSDNode *LD = cast<LoadSDNode>(Op);
2556   EVT MemVT = LD->getMemoryVT();
2557 
2558   if (Subtarget.systemSupportsUnalignedAccess())
2559     return Op;
2560 
2561   // Return if load is aligned or if MemVT is neither i32 nor i64.
2562   if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2563       ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2564     return SDValue();
2565 
2566   bool IsLittle = Subtarget.isLittle();
2567   EVT VT = Op.getValueType();
2568   ISD::LoadExtType ExtType = LD->getExtensionType();
2569   SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2570 
2571   assert((VT == MVT::i32) || (VT == MVT::i64));
2572 
2573   // Expand
2574   //  (set dst, (i64 (load baseptr)))
2575   // to
2576   //  (set tmp, (ldl (add baseptr, 7), undef))
2577   //  (set dst, (ldr baseptr, tmp))
2578   if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2579     SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2580                                IsLittle ? 7 : 0);
2581     return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2582                         IsLittle ? 0 : 7);
2583   }
2584 
2585   SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2586                              IsLittle ? 3 : 0);
2587   SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2588                              IsLittle ? 0 : 3);
2589 
2590   // Expand
2591   //  (set dst, (i32 (load baseptr))) or
2592   //  (set dst, (i64 (sextload baseptr))) or
2593   //  (set dst, (i64 (extload baseptr)))
2594   // to
2595   //  (set tmp, (lwl (add baseptr, 3), undef))
2596   //  (set dst, (lwr baseptr, tmp))
2597   if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2598       (ExtType == ISD::EXTLOAD))
2599     return LWR;
2600 
2601   assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2602 
2603   // Expand
2604   //  (set dst, (i64 (zextload baseptr)))
2605   // to
2606   //  (set tmp0, (lwl (add baseptr, 3), undef))
2607   //  (set tmp1, (lwr baseptr, tmp0))
2608   //  (set tmp2, (shl tmp1, 32))
2609   //  (set dst, (srl tmp2, 32))
2610   SDLoc DL(LD);
2611   SDValue Const32 = DAG.getConstant(32, DL, MVT::i32);
2612   SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2613   SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2614   SDValue Ops[] = { SRL, LWR.getValue(1) };
2615   return DAG.getMergeValues(Ops, DL);
2616 }
2617 
2618 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2619                              SDValue Chain, unsigned Offset) {
2620   SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2621   EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2622   SDLoc DL(SD);
2623   SDVTList VTList = DAG.getVTList(MVT::Other);
2624 
2625   if (Offset)
2626     Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2627                       DAG.getConstant(Offset, DL, BasePtrVT));
2628 
2629   SDValue Ops[] = { Chain, Value, Ptr };
2630   return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2631                                  SD->getMemOperand());
2632 }
2633 
2634 // Expand an unaligned 32 or 64-bit integer store node.
2635 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
2636                                       bool IsLittle) {
2637   SDValue Value = SD->getValue(), Chain = SD->getChain();
2638   EVT VT = Value.getValueType();
2639 
2640   // Expand
2641   //  (store val, baseptr) or
2642   //  (truncstore val, baseptr)
2643   // to
2644   //  (swl val, (add baseptr, 3))
2645   //  (swr val, baseptr)
2646   if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2647     SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2648                                 IsLittle ? 3 : 0);
2649     return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2650   }
2651 
2652   assert(VT == MVT::i64);
2653 
2654   // Expand
2655   //  (store val, baseptr)
2656   // to
2657   //  (sdl val, (add baseptr, 7))
2658   //  (sdr val, baseptr)
2659   SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2660   return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2661 }
2662 
2663 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
2664 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG,
2665                                      bool SingleFloat) {
2666   SDValue Val = SD->getValue();
2667 
2668   if (Val.getOpcode() != ISD::FP_TO_SINT ||
2669       (Val.getValueSizeInBits() > 32 && SingleFloat))
2670     return SDValue();
2671 
2672   EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
2673   SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2674                            Val.getOperand(0));
2675   return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2676                       SD->getPointerInfo(), SD->getAlignment(),
2677                       SD->getMemOperand()->getFlags());
2678 }
2679 
2680 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2681   StoreSDNode *SD = cast<StoreSDNode>(Op);
2682   EVT MemVT = SD->getMemoryVT();
2683 
2684   // Lower unaligned integer stores.
2685   if (!Subtarget.systemSupportsUnalignedAccess() &&
2686       (SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
2687       ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2688     return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle());
2689 
2690   return lowerFP_TO_SINT_STORE(SD, DAG, Subtarget.isSingleFloat());
2691 }
2692 
2693 SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op,
2694                                               SelectionDAG &DAG) const {
2695 
2696   // Return a fixed StackObject with offset 0 which points to the old stack
2697   // pointer.
2698   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2699   EVT ValTy = Op->getValueType(0);
2700   int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2701   return DAG.getFrameIndex(FI, ValTy);
2702 }
2703 
2704 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2705                                             SelectionDAG &DAG) const {
2706   if (Op.getValueSizeInBits() > 32 && Subtarget.isSingleFloat())
2707     return SDValue();
2708 
2709   EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
2710   SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2711                               Op.getOperand(0));
2712   return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2713 }
2714 
2715 //===----------------------------------------------------------------------===//
2716 //                      Calling Convention Implementation
2717 //===----------------------------------------------------------------------===//
2718 
2719 //===----------------------------------------------------------------------===//
2720 // TODO: Implement a generic logic using tblgen that can support this.
2721 // Mips O32 ABI rules:
2722 // ---
2723 // i32 - Passed in A0, A1, A2, A3 and stack
2724 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
2725 //       an argument. Otherwise, passed in A1, A2, A3 and stack.
2726 // f64 - Only passed in two aliased f32 registers if no int reg has been used
2727 //       yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2728 //       not used, it must be shadowed. If only A3 is available, shadow it and
2729 //       go to stack.
2730 // vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack.
2731 // vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3}
2732 //         with the remainder spilled to the stack.
2733 // vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases
2734 //         spilling the remainder to the stack.
2735 //
2736 //  For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2737 //===----------------------------------------------------------------------===//
2738 
2739 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2740                        CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2741                        CCState &State, ArrayRef<MCPhysReg> F64Regs) {
2742   const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>(
2743       State.getMachineFunction().getSubtarget());
2744 
2745   static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2746 
2747   const MipsCCState * MipsState = static_cast<MipsCCState *>(&State);
2748 
2749   static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
2750 
2751   static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 };
2752 
2753   // Do not process byval args here.
2754   if (ArgFlags.isByVal())
2755     return true;
2756 
2757   // Promote i8 and i16
2758   if (ArgFlags.isInReg() && !Subtarget.isLittle()) {
2759     if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
2760       LocVT = MVT::i32;
2761       if (ArgFlags.isSExt())
2762         LocInfo = CCValAssign::SExtUpper;
2763       else if (ArgFlags.isZExt())
2764         LocInfo = CCValAssign::ZExtUpper;
2765       else
2766         LocInfo = CCValAssign::AExtUpper;
2767     }
2768   }
2769 
2770   // Promote i8 and i16
2771   if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2772     LocVT = MVT::i32;
2773     if (ArgFlags.isSExt())
2774       LocInfo = CCValAssign::SExt;
2775     else if (ArgFlags.isZExt())
2776       LocInfo = CCValAssign::ZExt;
2777     else
2778       LocInfo = CCValAssign::AExt;
2779   }
2780 
2781   unsigned Reg;
2782 
2783   // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2784   // is true: function is vararg, argument is 3rd or higher, there is previous
2785   // argument which is not f32 or f64.
2786   bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 ||
2787                                 State.getFirstUnallocated(F32Regs) != ValNo;
2788   unsigned OrigAlign = ArgFlags.getOrigAlign();
2789   bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2790   bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo);
2791 
2792   // The MIPS vector ABI for floats passes them in a pair of registers
2793   if (ValVT == MVT::i32 && isVectorFloat) {
2794     // This is the start of an vector that was scalarized into an unknown number
2795     // of components. It doesn't matter how many there are. Allocate one of the
2796     // notional 8 byte aligned registers which map onto the argument stack, and
2797     // shadow the register lost to alignment requirements.
2798     if (ArgFlags.isSplit()) {
2799       Reg = State.AllocateReg(FloatVectorIntRegs);
2800       if (Reg == Mips::A2)
2801         State.AllocateReg(Mips::A1);
2802       else if (Reg == 0)
2803         State.AllocateReg(Mips::A3);
2804     } else {
2805       // If we're an intermediate component of the split, we can just attempt to
2806       // allocate a register directly.
2807       Reg = State.AllocateReg(IntRegs);
2808     }
2809   } else if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2810     Reg = State.AllocateReg(IntRegs);
2811     // If this is the first part of an i64 arg,
2812     // the allocated register must be either A0 or A2.
2813     if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2814       Reg = State.AllocateReg(IntRegs);
2815     LocVT = MVT::i32;
2816   } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2817     // Allocate int register and shadow next int register. If first
2818     // available register is Mips::A1 or Mips::A3, shadow it too.
2819     Reg = State.AllocateReg(IntRegs);
2820     if (Reg == Mips::A1 || Reg == Mips::A3)
2821       Reg = State.AllocateReg(IntRegs);
2822     State.AllocateReg(IntRegs);
2823     LocVT = MVT::i32;
2824   } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2825     // we are guaranteed to find an available float register
2826     if (ValVT == MVT::f32) {
2827       Reg = State.AllocateReg(F32Regs);
2828       // Shadow int register
2829       State.AllocateReg(IntRegs);
2830     } else {
2831       Reg = State.AllocateReg(F64Regs);
2832       // Shadow int registers
2833       unsigned Reg2 = State.AllocateReg(IntRegs);
2834       if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2835         State.AllocateReg(IntRegs);
2836       State.AllocateReg(IntRegs);
2837     }
2838   } else
2839     llvm_unreachable("Cannot handle this ValVT.");
2840 
2841   if (!Reg) {
2842     unsigned Offset = State.AllocateStack(ValVT.getStoreSize(), OrigAlign);
2843     State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2844   } else
2845     State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2846 
2847   return false;
2848 }
2849 
2850 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
2851                             MVT LocVT, CCValAssign::LocInfo LocInfo,
2852                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
2853   static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
2854 
2855   return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2856 }
2857 
2858 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
2859                             MVT LocVT, CCValAssign::LocInfo LocInfo,
2860                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
2861   static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
2862 
2863   return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2864 }
2865 
2866 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2867                        CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2868                        CCState &State) LLVM_ATTRIBUTE_UNUSED;
2869 
2870 #include "MipsGenCallingConv.inc"
2871 
2872  CCAssignFn *MipsTargetLowering::CCAssignFnForCall() const{
2873    return CC_Mips;
2874  }
2875 
2876  CCAssignFn *MipsTargetLowering::CCAssignFnForReturn() const{
2877    return RetCC_Mips;
2878  }
2879 //===----------------------------------------------------------------------===//
2880 //                  Call Calling Convention Implementation
2881 //===----------------------------------------------------------------------===//
2882 
2883 // Return next O32 integer argument register.
2884 static unsigned getNextIntArgReg(unsigned Reg) {
2885   assert((Reg == Mips::A0) || (Reg == Mips::A2));
2886   return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2887 }
2888 
2889 SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
2890                                            SDValue Chain, SDValue Arg,
2891                                            const SDLoc &DL, bool IsTailCall,
2892                                            SelectionDAG &DAG) const {
2893   if (!IsTailCall) {
2894     SDValue PtrOff =
2895         DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
2896                     DAG.getIntPtrConstant(Offset, DL));
2897     return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo());
2898   }
2899 
2900   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2901   int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
2902   SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2903   return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
2904                       /* Alignment = */ 0, MachineMemOperand::MOVolatile);
2905 }
2906 
2907 void MipsTargetLowering::
2908 getOpndList(SmallVectorImpl<SDValue> &Ops,
2909             std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
2910             bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
2911             bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
2912             SDValue Chain) const {
2913   // Insert node "GP copy globalreg" before call to function.
2914   //
2915   // R_MIPS_CALL* operators (emitted when non-internal functions are called
2916   // in PIC mode) allow symbols to be resolved via lazy binding.
2917   // The lazy binding stub requires GP to point to the GOT.
2918   // Note that we don't need GP to point to the GOT for indirect calls
2919   // (when R_MIPS_CALL* is not used for the call) because Mips linker generates
2920   // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs
2921   // used for the function (that is, Mips linker doesn't generate lazy binding
2922   // stub for a function whose address is taken in the program).
2923   if (IsPICCall && !InternalLinkage && IsCallReloc) {
2924     unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP;
2925     EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2926     RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
2927   }
2928 
2929   // Build a sequence of copy-to-reg nodes chained together with token
2930   // chain and flag operands which copy the outgoing args into registers.
2931   // The InFlag in necessary since all emitted instructions must be
2932   // stuck together.
2933   SDValue InFlag;
2934 
2935   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2936     Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
2937                                  RegsToPass[i].second, InFlag);
2938     InFlag = Chain.getValue(1);
2939   }
2940 
2941   // Add argument registers to the end of the list so that they are
2942   // known live into the call.
2943   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2944     Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
2945                                       RegsToPass[i].second.getValueType()));
2946 
2947   // Add a register mask operand representing the call-preserved registers.
2948   const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2949   const uint32_t *Mask =
2950       TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv);
2951   assert(Mask && "Missing call preserved mask for calling convention");
2952   if (Subtarget.inMips16HardFloat()) {
2953     if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
2954       StringRef Sym = G->getGlobal()->getName();
2955       Function *F = G->getGlobal()->getParent()->getFunction(Sym);
2956       if (F && F->hasFnAttribute("__Mips16RetHelper")) {
2957         Mask = MipsRegisterInfo::getMips16RetHelperMask();
2958       }
2959     }
2960   }
2961   Ops.push_back(CLI.DAG.getRegisterMask(Mask));
2962 
2963   if (InFlag.getNode())
2964     Ops.push_back(InFlag);
2965 }
2966 
2967 void MipsTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
2968                                                        SDNode *Node) const {
2969   switch (MI.getOpcode()) {
2970     default:
2971       return;
2972     case Mips::JALR:
2973     case Mips::JALRPseudo:
2974     case Mips::JALR64:
2975     case Mips::JALR64Pseudo:
2976     case Mips::JALR16_MM:
2977     case Mips::JALRC16_MMR6:
2978     case Mips::TAILCALLREG:
2979     case Mips::TAILCALLREG64:
2980     case Mips::TAILCALLR6REG:
2981     case Mips::TAILCALL64R6REG:
2982     case Mips::TAILCALLREG_MM:
2983     case Mips::TAILCALLREG_MMR6: {
2984       if (!EmitJalrReloc ||
2985           Subtarget.inMips16Mode() ||
2986           !isPositionIndependent() ||
2987           Node->getNumOperands() < 1 ||
2988           Node->getOperand(0).getNumOperands() < 2) {
2989         return;
2990       }
2991       // We are after the callee address, set by LowerCall().
2992       // If added to MI, asm printer will emit .reloc R_MIPS_JALR for the
2993       // symbol.
2994       const SDValue TargetAddr = Node->getOperand(0).getOperand(1);
2995       StringRef Sym;
2996       if (const GlobalAddressSDNode *G =
2997               dyn_cast_or_null<const GlobalAddressSDNode>(TargetAddr)) {
2998         // We must not emit the R_MIPS_JALR relocation against data symbols
2999         // since this will cause run-time crashes if the linker replaces the
3000         // call instruction with a relative branch to the data symbol.
3001         if (!isa<Function>(G->getGlobal())) {
3002           LLVM_DEBUG(dbgs() << "Not adding R_MIPS_JALR against data symbol "
3003                             << G->getGlobal()->getName() << "\n");
3004           return;
3005         }
3006         Sym = G->getGlobal()->getName();
3007       }
3008       else if (const ExternalSymbolSDNode *ES =
3009                    dyn_cast_or_null<const ExternalSymbolSDNode>(TargetAddr)) {
3010         Sym = ES->getSymbol();
3011       }
3012 
3013       if (Sym.empty())
3014         return;
3015 
3016       MachineFunction *MF = MI.getParent()->getParent();
3017       MCSymbol *S = MF->getContext().getOrCreateSymbol(Sym);
3018       LLVM_DEBUG(dbgs() << "Adding R_MIPS_JALR against " << Sym << "\n");
3019       MI.addOperand(MachineOperand::CreateMCSymbol(S, MipsII::MO_JALR));
3020     }
3021   }
3022 }
3023 
3024 /// LowerCall - functions arguments are copied from virtual regs to
3025 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
3026 SDValue
3027 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3028                               SmallVectorImpl<SDValue> &InVals) const {
3029   SelectionDAG &DAG                     = CLI.DAG;
3030   SDLoc DL                              = CLI.DL;
3031   SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3032   SmallVectorImpl<SDValue> &OutVals     = CLI.OutVals;
3033   SmallVectorImpl<ISD::InputArg> &Ins   = CLI.Ins;
3034   SDValue Chain                         = CLI.Chain;
3035   SDValue Callee                        = CLI.Callee;
3036   bool &IsTailCall                      = CLI.IsTailCall;
3037   CallingConv::ID CallConv              = CLI.CallConv;
3038   bool IsVarArg                         = CLI.IsVarArg;
3039 
3040   MachineFunction &MF = DAG.getMachineFunction();
3041   MachineFrameInfo &MFI = MF.getFrameInfo();
3042   const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
3043   MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
3044   bool IsPIC = isPositionIndependent();
3045 
3046   // Analyze operands of the call, assigning locations to each operand.
3047   SmallVector<CCValAssign, 16> ArgLocs;
3048   MipsCCState CCInfo(
3049       CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
3050       MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget));
3051 
3052   const ExternalSymbolSDNode *ES =
3053       dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode());
3054 
3055   // There is one case where CALLSEQ_START..CALLSEQ_END can be nested, which
3056   // is during the lowering of a call with a byval argument which produces
3057   // a call to memcpy. For the O32 case, this causes the caller to allocate
3058   // stack space for the reserved argument area for the callee, then recursively
3059   // again for the memcpy call. In the NEWABI case, this doesn't occur as those
3060   // ABIs mandate that the callee allocates the reserved argument area. We do
3061   // still produce nested CALLSEQ_START..CALLSEQ_END with zero space though.
3062   //
3063   // If the callee has a byval argument and memcpy is used, we are mandated
3064   // to already have produced a reserved argument area for the callee for O32.
3065   // Therefore, the reserved argument area can be reused for both calls.
3066   //
3067   // Other cases of calling memcpy cannot have a chain with a CALLSEQ_START
3068   // present, as we have yet to hook that node onto the chain.
3069   //
3070   // Hence, the CALLSEQ_START and CALLSEQ_END nodes can be eliminated in this
3071   // case. GCC does a similar trick, in that wherever possible, it calculates
3072   // the maximum out going argument area (including the reserved area), and
3073   // preallocates the stack space on entrance to the caller.
3074   //
3075   // FIXME: We should do the same for efficiency and space.
3076 
3077   // Note: The check on the calling convention below must match
3078   //       MipsABIInfo::GetCalleeAllocdArgSizeInBytes().
3079   bool MemcpyInByVal = ES &&
3080                        StringRef(ES->getSymbol()) == StringRef("memcpy") &&
3081                        CallConv != CallingConv::Fast &&
3082                        Chain.getOpcode() == ISD::CALLSEQ_START;
3083 
3084   // Allocate the reserved argument area. It seems strange to do this from the
3085   // caller side but removing it breaks the frame size calculation.
3086   unsigned ReservedArgArea =
3087       MemcpyInByVal ? 0 : ABI.GetCalleeAllocdArgSizeInBytes(CallConv);
3088   CCInfo.AllocateStack(ReservedArgArea, 1);
3089 
3090   CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(),
3091                              ES ? ES->getSymbol() : nullptr);
3092 
3093   // Get a count of how many bytes are to be pushed on the stack.
3094   unsigned NextStackOffset = CCInfo.getNextStackOffset();
3095 
3096   // Check if it's really possible to do a tail call. Restrict it to functions
3097   // that are part of this compilation unit.
3098   bool InternalLinkage = false;
3099   if (IsTailCall) {
3100     IsTailCall = isEligibleForTailCallOptimization(
3101         CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>());
3102      if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3103       InternalLinkage = G->getGlobal()->hasInternalLinkage();
3104       IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() ||
3105                      G->getGlobal()->hasPrivateLinkage() ||
3106                      G->getGlobal()->hasHiddenVisibility() ||
3107                      G->getGlobal()->hasProtectedVisibility());
3108      }
3109   }
3110   if (!IsTailCall && CLI.CS && CLI.CS.isMustTailCall())
3111     report_fatal_error("failed to perform tail call elimination on a call "
3112                        "site marked musttail");
3113 
3114   if (IsTailCall)
3115     ++NumTailCalls;
3116 
3117   // Chain is the output chain of the last Load/Store or CopyToReg node.
3118   // ByValChain is the output chain of the last Memcpy node created for copying
3119   // byval arguments to the stack.
3120   unsigned StackAlignment = TFL->getStackAlignment();
3121   NextStackOffset = alignTo(NextStackOffset, StackAlignment);
3122   SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
3123 
3124   if (!(IsTailCall || MemcpyInByVal))
3125     Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL);
3126 
3127   SDValue StackPtr =
3128       DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
3129                          getPointerTy(DAG.getDataLayout()));
3130 
3131   std::deque<std::pair<unsigned, SDValue>> RegsToPass;
3132   SmallVector<SDValue, 8> MemOpChains;
3133 
3134   CCInfo.rewindByValRegsInfo();
3135 
3136   // Walk the register/memloc assignments, inserting copies/loads.
3137   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3138     SDValue Arg = OutVals[i];
3139     CCValAssign &VA = ArgLocs[i];
3140     MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
3141     ISD::ArgFlagsTy Flags = Outs[i].Flags;
3142     bool UseUpperBits = false;
3143 
3144     // ByVal Arg.
3145     if (Flags.isByVal()) {
3146       unsigned FirstByValReg, LastByValReg;
3147       unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3148       CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3149 
3150       assert(Flags.getByValSize() &&
3151              "ByVal args of size 0 should have been ignored by front-end.");
3152       assert(ByValIdx < CCInfo.getInRegsParamsCount());
3153       assert(!IsTailCall &&
3154              "Do not tail-call optimize if there is a byval argument.");
3155       passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
3156                    FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(),
3157                    VA);
3158       CCInfo.nextInRegsParam();
3159       continue;
3160     }
3161 
3162     // Promote the value if needed.
3163     switch (VA.getLocInfo()) {
3164     default:
3165       llvm_unreachable("Unknown loc info!");
3166     case CCValAssign::Full:
3167       if (VA.isRegLoc()) {
3168         if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
3169             (ValVT == MVT::f64 && LocVT == MVT::i64) ||
3170             (ValVT == MVT::i64 && LocVT == MVT::f64))
3171           Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
3172         else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
3173           SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
3174                                    Arg, DAG.getConstant(0, DL, MVT::i32));
3175           SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
3176                                    Arg, DAG.getConstant(1, DL, MVT::i32));
3177           if (!Subtarget.isLittle())
3178             std::swap(Lo, Hi);
3179           unsigned LocRegLo = VA.getLocReg();
3180           unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
3181           RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
3182           RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
3183           continue;
3184         }
3185       }
3186       break;
3187     case CCValAssign::BCvt:
3188       Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
3189       break;
3190     case CCValAssign::SExtUpper:
3191       UseUpperBits = true;
3192       LLVM_FALLTHROUGH;
3193     case CCValAssign::SExt:
3194       Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
3195       break;
3196     case CCValAssign::ZExtUpper:
3197       UseUpperBits = true;
3198       LLVM_FALLTHROUGH;
3199     case CCValAssign::ZExt:
3200       Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
3201       break;
3202     case CCValAssign::AExtUpper:
3203       UseUpperBits = true;
3204       LLVM_FALLTHROUGH;
3205     case CCValAssign::AExt:
3206       Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
3207       break;
3208     }
3209 
3210     if (UseUpperBits) {
3211       unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3212       unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3213       Arg = DAG.getNode(
3214           ISD::SHL, DL, VA.getLocVT(), Arg,
3215           DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3216     }
3217 
3218     // Arguments that can be passed on register must be kept at
3219     // RegsToPass vector
3220     if (VA.isRegLoc()) {
3221       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3222       continue;
3223     }
3224 
3225     // Register can't get to this point...
3226     assert(VA.isMemLoc());
3227 
3228     // emit ISD::STORE whichs stores the
3229     // parameter value to a stack Location
3230     MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
3231                                          Chain, Arg, DL, IsTailCall, DAG));
3232   }
3233 
3234   // Transform all store nodes into one single node because all store
3235   // nodes are independent of each other.
3236   if (!MemOpChains.empty())
3237     Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
3238 
3239   // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
3240   // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3241   // node so that legalize doesn't hack it.
3242 
3243   EVT Ty = Callee.getValueType();
3244   bool GlobalOrExternal = false, IsCallReloc = false;
3245 
3246   // The long-calls feature is ignored in case of PIC.
3247   // While we do not support -mshared / -mno-shared properly,
3248   // ignore long-calls in case of -mabicalls too.
3249   if (!Subtarget.isABICalls() && !IsPIC) {
3250     // If the function should be called using "long call",
3251     // get its address into a register to prevent using
3252     // of the `jal` instruction for the direct call.
3253     if (auto *N = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3254       if (Subtarget.useLongCalls())
3255         Callee = Subtarget.hasSym32()
3256                      ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
3257                      : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
3258     } else if (auto *N = dyn_cast<GlobalAddressSDNode>(Callee)) {
3259       bool UseLongCalls = Subtarget.useLongCalls();
3260       // If the function has long-call/far/near attribute
3261       // it overrides command line switch pased to the backend.
3262       if (auto *F = dyn_cast<Function>(N->getGlobal())) {
3263         if (F->hasFnAttribute("long-call"))
3264           UseLongCalls = true;
3265         else if (F->hasFnAttribute("short-call"))
3266           UseLongCalls = false;
3267       }
3268       if (UseLongCalls)
3269         Callee = Subtarget.hasSym32()
3270                      ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
3271                      : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
3272     }
3273   }
3274 
3275   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3276     if (IsPIC) {
3277       const GlobalValue *Val = G->getGlobal();
3278       InternalLinkage = Val->hasInternalLinkage();
3279 
3280       if (InternalLinkage)
3281         Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64());
3282       else if (LargeGOT) {
3283         Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16,
3284                                        MipsII::MO_CALL_LO16, Chain,
3285                                        FuncInfo->callPtrInfo(Val));
3286         IsCallReloc = true;
3287       } else {
3288         Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
3289                                FuncInfo->callPtrInfo(Val));
3290         IsCallReloc = true;
3291       }
3292     } else
3293       Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL,
3294                                           getPointerTy(DAG.getDataLayout()), 0,
3295                                           MipsII::MO_NO_FLAG);
3296     GlobalOrExternal = true;
3297   }
3298   else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3299     const char *Sym = S->getSymbol();
3300 
3301     if (!IsPIC) // static
3302       Callee = DAG.getTargetExternalSymbol(
3303           Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG);
3304     else if (LargeGOT) {
3305       Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16,
3306                                      MipsII::MO_CALL_LO16, Chain,
3307                                      FuncInfo->callPtrInfo(Sym));
3308       IsCallReloc = true;
3309     } else { // PIC
3310       Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
3311                              FuncInfo->callPtrInfo(Sym));
3312       IsCallReloc = true;
3313     }
3314 
3315     GlobalOrExternal = true;
3316   }
3317 
3318   SmallVector<SDValue, 8> Ops(1, Chain);
3319   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3320 
3321   getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage,
3322               IsCallReloc, CLI, Callee, Chain);
3323 
3324   if (IsTailCall) {
3325     MF.getFrameInfo().setHasTailCall();
3326     return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
3327   }
3328 
3329   Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
3330   SDValue InFlag = Chain.getValue(1);
3331 
3332   // Create the CALLSEQ_END node in the case of where it is not a call to
3333   // memcpy.
3334   if (!(MemcpyInByVal)) {
3335     Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
3336                                DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
3337     InFlag = Chain.getValue(1);
3338   }
3339 
3340   // Handle result values, copying them out of physregs into vregs that we
3341   // return.
3342   return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
3343                          InVals, CLI);
3344 }
3345 
3346 /// LowerCallResult - Lower the result values of a call into the
3347 /// appropriate copies out of appropriate physical registers.
3348 SDValue MipsTargetLowering::LowerCallResult(
3349     SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
3350     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3351     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
3352     TargetLowering::CallLoweringInfo &CLI) const {
3353   // Assign locations to each value returned by this call.
3354   SmallVector<CCValAssign, 16> RVLocs;
3355   MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
3356                      *DAG.getContext());
3357 
3358   const ExternalSymbolSDNode *ES =
3359       dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.Callee.getNode());
3360   CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.RetTy,
3361                            ES ? ES->getSymbol() : nullptr);
3362 
3363   // Copy all of the result registers out of their specified physreg.
3364   for (unsigned i = 0; i != RVLocs.size(); ++i) {
3365     CCValAssign &VA = RVLocs[i];
3366     assert(VA.isRegLoc() && "Can only return in registers!");
3367 
3368     SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
3369                                      RVLocs[i].getLocVT(), InFlag);
3370     Chain = Val.getValue(1);
3371     InFlag = Val.getValue(2);
3372 
3373     if (VA.isUpperBitsInLoc()) {
3374       unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits();
3375       unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3376       unsigned Shift =
3377           VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
3378       Val = DAG.getNode(
3379           Shift, DL, VA.getLocVT(), Val,
3380           DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3381     }
3382 
3383     switch (VA.getLocInfo()) {
3384     default:
3385       llvm_unreachable("Unknown loc info!");
3386     case CCValAssign::Full:
3387       break;
3388     case CCValAssign::BCvt:
3389       Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
3390       break;
3391     case CCValAssign::AExt:
3392     case CCValAssign::AExtUpper:
3393       Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3394       break;
3395     case CCValAssign::ZExt:
3396     case CCValAssign::ZExtUpper:
3397       Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
3398                         DAG.getValueType(VA.getValVT()));
3399       Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3400       break;
3401     case CCValAssign::SExt:
3402     case CCValAssign::SExtUpper:
3403       Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
3404                         DAG.getValueType(VA.getValVT()));
3405       Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3406       break;
3407     }
3408 
3409     InVals.push_back(Val);
3410   }
3411 
3412   return Chain;
3413 }
3414 
3415 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA,
3416                                       EVT ArgVT, const SDLoc &DL,
3417                                       SelectionDAG &DAG) {
3418   MVT LocVT = VA.getLocVT();
3419   EVT ValVT = VA.getValVT();
3420 
3421   // Shift into the upper bits if necessary.
3422   switch (VA.getLocInfo()) {
3423   default:
3424     break;
3425   case CCValAssign::AExtUpper:
3426   case CCValAssign::SExtUpper:
3427   case CCValAssign::ZExtUpper: {
3428     unsigned ValSizeInBits = ArgVT.getSizeInBits();
3429     unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3430     unsigned Opcode =
3431         VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
3432     Val = DAG.getNode(
3433         Opcode, DL, VA.getLocVT(), Val,
3434         DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3435     break;
3436   }
3437   }
3438 
3439   // If this is an value smaller than the argument slot size (32-bit for O32,
3440   // 64-bit for N32/N64), it has been promoted in some way to the argument slot
3441   // size. Extract the value and insert any appropriate assertions regarding
3442   // sign/zero extension.
3443   switch (VA.getLocInfo()) {
3444   default:
3445     llvm_unreachable("Unknown loc info!");
3446   case CCValAssign::Full:
3447     break;
3448   case CCValAssign::AExtUpper:
3449   case CCValAssign::AExt:
3450     Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3451     break;
3452   case CCValAssign::SExtUpper:
3453   case CCValAssign::SExt:
3454     Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT));
3455     Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3456     break;
3457   case CCValAssign::ZExtUpper:
3458   case CCValAssign::ZExt:
3459     Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT));
3460     Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3461     break;
3462   case CCValAssign::BCvt:
3463     Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
3464     break;
3465   }
3466 
3467   return Val;
3468 }
3469 
3470 //===----------------------------------------------------------------------===//
3471 //             Formal Arguments Calling Convention Implementation
3472 //===----------------------------------------------------------------------===//
3473 /// LowerFormalArguments - transform physical registers into virtual registers
3474 /// and generate load operations for arguments places on the stack.
3475 SDValue MipsTargetLowering::LowerFormalArguments(
3476     SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
3477     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3478     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3479   MachineFunction &MF = DAG.getMachineFunction();
3480   MachineFrameInfo &MFI = MF.getFrameInfo();
3481   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3482 
3483   MipsFI->setVarArgsFrameIndex(0);
3484 
3485   // Used with vargs to acumulate store chains.
3486   std::vector<SDValue> OutChains;
3487 
3488   // Assign locations to all of the incoming arguments.
3489   SmallVector<CCValAssign, 16> ArgLocs;
3490   MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
3491                      *DAG.getContext());
3492   CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
3493   const Function &Func = DAG.getMachineFunction().getFunction();
3494   Function::const_arg_iterator FuncArg = Func.arg_begin();
3495 
3496   if (Func.hasFnAttribute("interrupt") && !Func.arg_empty())
3497     report_fatal_error(
3498         "Functions with the interrupt attribute cannot have arguments!");
3499 
3500   CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
3501   MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
3502                            CCInfo.getInRegsParamsCount() > 0);
3503 
3504   unsigned CurArgIdx = 0;
3505   CCInfo.rewindByValRegsInfo();
3506 
3507   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3508     CCValAssign &VA = ArgLocs[i];
3509     if (Ins[i].isOrigArg()) {
3510       std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx);
3511       CurArgIdx = Ins[i].getOrigArgIndex();
3512     }
3513     EVT ValVT = VA.getValVT();
3514     ISD::ArgFlagsTy Flags = Ins[i].Flags;
3515     bool IsRegLoc = VA.isRegLoc();
3516 
3517     if (Flags.isByVal()) {
3518       assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit");
3519       unsigned FirstByValReg, LastByValReg;
3520       unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3521       CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3522 
3523       assert(Flags.getByValSize() &&
3524              "ByVal args of size 0 should have been ignored by front-end.");
3525       assert(ByValIdx < CCInfo.getInRegsParamsCount());
3526       copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
3527                     FirstByValReg, LastByValReg, VA, CCInfo);
3528       CCInfo.nextInRegsParam();
3529       continue;
3530     }
3531 
3532     // Arguments stored on registers
3533     if (IsRegLoc) {
3534       MVT RegVT = VA.getLocVT();
3535       unsigned ArgReg = VA.getLocReg();
3536       const TargetRegisterClass *RC = getRegClassFor(RegVT);
3537 
3538       // Transform the arguments stored on
3539       // physical registers into virtual ones
3540       unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
3541       SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
3542 
3543       ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3544 
3545       // Handle floating point arguments passed in integer registers and
3546       // long double arguments passed in floating point registers.
3547       if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3548           (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3549           (RegVT == MVT::f64 && ValVT == MVT::i64))
3550         ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
3551       else if (ABI.IsO32() && RegVT == MVT::i32 &&
3552                ValVT == MVT::f64) {
3553         unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
3554                                   getNextIntArgReg(ArgReg), RC);
3555         SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
3556         if (!Subtarget.isLittle())
3557           std::swap(ArgValue, ArgValue2);
3558         ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
3559                                ArgValue, ArgValue2);
3560       }
3561 
3562       InVals.push_back(ArgValue);
3563     } else { // VA.isRegLoc()
3564       MVT LocVT = VA.getLocVT();
3565 
3566       if (ABI.IsO32()) {
3567         // We ought to be able to use LocVT directly but O32 sets it to i32
3568         // when allocating floating point values to integer registers.
3569         // This shouldn't influence how we load the value into registers unless
3570         // we are targeting softfloat.
3571         if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat())
3572           LocVT = VA.getValVT();
3573       }
3574 
3575       // sanity check
3576       assert(VA.isMemLoc());
3577 
3578       // The stack pointer offset is relative to the caller stack frame.
3579       int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
3580                                      VA.getLocMemOffset(), true);
3581 
3582       // Create load nodes to retrieve arguments from the stack
3583       SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3584       SDValue ArgValue = DAG.getLoad(
3585           LocVT, DL, Chain, FIN,
3586           MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3587       OutChains.push_back(ArgValue.getValue(1));
3588 
3589       ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3590 
3591       InVals.push_back(ArgValue);
3592     }
3593   }
3594 
3595   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3596     // The mips ABIs for returning structs by value requires that we copy
3597     // the sret argument into $v0 for the return. Save the argument into
3598     // a virtual register so that we can access it from the return points.
3599     if (Ins[i].Flags.isSRet()) {
3600       unsigned Reg = MipsFI->getSRetReturnReg();
3601       if (!Reg) {
3602         Reg = MF.getRegInfo().createVirtualRegister(
3603             getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32));
3604         MipsFI->setSRetReturnReg(Reg);
3605       }
3606       SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
3607       Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
3608       break;
3609     }
3610   }
3611 
3612   if (IsVarArg)
3613     writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo);
3614 
3615   // All stores are grouped in one node to allow the matching between
3616   // the size of Ins and InVals. This only happens when on varg functions
3617   if (!OutChains.empty()) {
3618     OutChains.push_back(Chain);
3619     Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
3620   }
3621 
3622   return Chain;
3623 }
3624 
3625 //===----------------------------------------------------------------------===//
3626 //               Return Value Calling Convention Implementation
3627 //===----------------------------------------------------------------------===//
3628 
3629 bool
3630 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3631                                    MachineFunction &MF, bool IsVarArg,
3632                                    const SmallVectorImpl<ISD::OutputArg> &Outs,
3633                                    LLVMContext &Context) const {
3634   SmallVector<CCValAssign, 16> RVLocs;
3635   MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3636   return CCInfo.CheckReturn(Outs, RetCC_Mips);
3637 }
3638 
3639 bool
3640 MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
3641   if ((ABI.IsN32() || ABI.IsN64()) && Type == MVT::i32)
3642       return true;
3643 
3644   return IsSigned;
3645 }
3646 
3647 SDValue
3648 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
3649                                          const SDLoc &DL,
3650                                          SelectionDAG &DAG) const {
3651   MachineFunction &MF = DAG.getMachineFunction();
3652   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3653 
3654   MipsFI->setISR();
3655 
3656   return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps);
3657 }
3658 
3659 SDValue
3660 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3661                                 bool IsVarArg,
3662                                 const SmallVectorImpl<ISD::OutputArg> &Outs,
3663                                 const SmallVectorImpl<SDValue> &OutVals,
3664                                 const SDLoc &DL, SelectionDAG &DAG) const {
3665   // CCValAssign - represent the assignment of
3666   // the return value to a location
3667   SmallVector<CCValAssign, 16> RVLocs;
3668   MachineFunction &MF = DAG.getMachineFunction();
3669 
3670   // CCState - Info about the registers and stack slot.
3671   MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
3672 
3673   // Analyze return values.
3674   CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3675 
3676   SDValue Flag;
3677   SmallVector<SDValue, 4> RetOps(1, Chain);
3678 
3679   // Copy the result values into the output registers.
3680   for (unsigned i = 0; i != RVLocs.size(); ++i) {
3681     SDValue Val = OutVals[i];
3682     CCValAssign &VA = RVLocs[i];
3683     assert(VA.isRegLoc() && "Can only return in registers!");
3684     bool UseUpperBits = false;
3685 
3686     switch (VA.getLocInfo()) {
3687     default:
3688       llvm_unreachable("Unknown loc info!");
3689     case CCValAssign::Full:
3690       break;
3691     case CCValAssign::BCvt:
3692       Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val);
3693       break;
3694     case CCValAssign::AExtUpper:
3695       UseUpperBits = true;
3696       LLVM_FALLTHROUGH;
3697     case CCValAssign::AExt:
3698       Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);
3699       break;
3700     case CCValAssign::ZExtUpper:
3701       UseUpperBits = true;
3702       LLVM_FALLTHROUGH;
3703     case CCValAssign::ZExt:
3704       Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
3705       break;
3706     case CCValAssign::SExtUpper:
3707       UseUpperBits = true;
3708       LLVM_FALLTHROUGH;
3709     case CCValAssign::SExt:
3710       Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
3711       break;
3712     }
3713 
3714     if (UseUpperBits) {
3715       unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3716       unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3717       Val = DAG.getNode(
3718           ISD::SHL, DL, VA.getLocVT(), Val,
3719           DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3720     }
3721 
3722     Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
3723 
3724     // Guarantee that all emitted copies are stuck together with flags.
3725     Flag = Chain.getValue(1);
3726     RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3727   }
3728 
3729   // The mips ABIs for returning structs by value requires that we copy
3730   // the sret argument into $v0 for the return. We saved the argument into
3731   // a virtual register in the entry block, so now we copy the value out
3732   // and into $v0.
3733   if (MF.getFunction().hasStructRetAttr()) {
3734     MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3735     unsigned Reg = MipsFI->getSRetReturnReg();
3736 
3737     if (!Reg)
3738       llvm_unreachable("sret virtual register not created in the entry block");
3739     SDValue Val =
3740         DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
3741     unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
3742 
3743     Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
3744     Flag = Chain.getValue(1);
3745     RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout())));
3746   }
3747 
3748   RetOps[0] = Chain;  // Update chain.
3749 
3750   // Add the flag if we have it.
3751   if (Flag.getNode())
3752     RetOps.push_back(Flag);
3753 
3754   // ISRs must use "eret".
3755   if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt"))
3756     return LowerInterruptReturn(RetOps, DL, DAG);
3757 
3758   // Standard return on Mips is a "jr $ra"
3759   return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
3760 }
3761 
3762 //===----------------------------------------------------------------------===//
3763 //                           Mips Inline Assembly Support
3764 //===----------------------------------------------------------------------===//
3765 
3766 /// getConstraintType - Given a constraint letter, return the type of
3767 /// constraint it is for this target.
3768 MipsTargetLowering::ConstraintType
3769 MipsTargetLowering::getConstraintType(StringRef Constraint) const {
3770   // Mips specific constraints
3771   // GCC config/mips/constraints.md
3772   //
3773   // 'd' : An address register. Equivalent to r
3774   //       unless generating MIPS16 code.
3775   // 'y' : Equivalent to r; retained for
3776   //       backwards compatibility.
3777   // 'c' : A register suitable for use in an indirect
3778   //       jump. This will always be $25 for -mabicalls.
3779   // 'l' : The lo register. 1 word storage.
3780   // 'x' : The hilo register pair. Double word storage.
3781   if (Constraint.size() == 1) {
3782     switch (Constraint[0]) {
3783       default : break;
3784       case 'd':
3785       case 'y':
3786       case 'f':
3787       case 'c':
3788       case 'l':
3789       case 'x':
3790         return C_RegisterClass;
3791       case 'R':
3792         return C_Memory;
3793     }
3794   }
3795 
3796   if (Constraint == "ZC")
3797     return C_Memory;
3798 
3799   return TargetLowering::getConstraintType(Constraint);
3800 }
3801 
3802 /// Examine constraint type and operand type and determine a weight value.
3803 /// This object must already have been set up with the operand type
3804 /// and the current alternative constraint selected.
3805 TargetLowering::ConstraintWeight
3806 MipsTargetLowering::getSingleConstraintMatchWeight(
3807     AsmOperandInfo &info, const char *constraint) const {
3808   ConstraintWeight weight = CW_Invalid;
3809   Value *CallOperandVal = info.CallOperandVal;
3810     // If we don't have a value, we can't do a match,
3811     // but allow it at the lowest weight.
3812   if (!CallOperandVal)
3813     return CW_Default;
3814   Type *type = CallOperandVal->getType();
3815   // Look at the constraint type.
3816   switch (*constraint) {
3817   default:
3818     weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3819     break;
3820   case 'd':
3821   case 'y':
3822     if (type->isIntegerTy())
3823       weight = CW_Register;
3824     break;
3825   case 'f': // FPU or MSA register
3826     if (Subtarget.hasMSA() && type->isVectorTy() &&
3827         cast<VectorType>(type)->getBitWidth() == 128)
3828       weight = CW_Register;
3829     else if (type->isFloatTy())
3830       weight = CW_Register;
3831     break;
3832   case 'c': // $25 for indirect jumps
3833   case 'l': // lo register
3834   case 'x': // hilo register pair
3835     if (type->isIntegerTy())
3836       weight = CW_SpecificReg;
3837     break;
3838   case 'I': // signed 16 bit immediate
3839   case 'J': // integer zero
3840   case 'K': // unsigned 16 bit immediate
3841   case 'L': // signed 32 bit immediate where lower 16 bits are 0
3842   case 'N': // immediate in the range of -65535 to -1 (inclusive)
3843   case 'O': // signed 15 bit immediate (+- 16383)
3844   case 'P': // immediate in the range of 65535 to 1 (inclusive)
3845     if (isa<ConstantInt>(CallOperandVal))
3846       weight = CW_Constant;
3847     break;
3848   case 'R':
3849     weight = CW_Memory;
3850     break;
3851   }
3852   return weight;
3853 }
3854 
3855 /// This is a helper function to parse a physical register string and split it
3856 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
3857 /// that is returned indicates whether parsing was successful. The second flag
3858 /// is true if the numeric part exists.
3859 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,
3860                                               unsigned long long &Reg) {
3861   if (C.front() != '{' || C.back() != '}')
3862     return std::make_pair(false, false);
3863 
3864   // Search for the first numeric character.
3865   StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
3866   I = std::find_if(B, E, isdigit);
3867 
3868   Prefix = StringRef(B, I - B);
3869 
3870   // The second flag is set to false if no numeric characters were found.
3871   if (I == E)
3872     return std::make_pair(true, false);
3873 
3874   // Parse the numeric characters.
3875   return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
3876                         true);
3877 }
3878 
3879 EVT MipsTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
3880                                             ISD::NodeType) const {
3881   bool Cond = !Subtarget.isABI_O32() && VT.getSizeInBits() == 32;
3882   EVT MinVT = getRegisterType(Context, Cond ? MVT::i64 : MVT::i32);
3883   return VT.bitsLT(MinVT) ? MinVT : VT;
3884 }
3885 
3886 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
3887 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
3888   const TargetRegisterInfo *TRI =
3889       Subtarget.getRegisterInfo();
3890   const TargetRegisterClass *RC;
3891   StringRef Prefix;
3892   unsigned long long Reg;
3893 
3894   std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
3895 
3896   if (!R.first)
3897     return std::make_pair(0U, nullptr);
3898 
3899   if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo.
3900     // No numeric characters follow "hi" or "lo".
3901     if (R.second)
3902       return std::make_pair(0U, nullptr);
3903 
3904     RC = TRI->getRegClass(Prefix == "hi" ?
3905                           Mips::HI32RegClassID : Mips::LO32RegClassID);
3906     return std::make_pair(*(RC->begin()), RC);
3907   } else if (Prefix.startswith("$msa")) {
3908     // Parse $msa(ir|csr|access|save|modify|request|map|unmap)
3909 
3910     // No numeric characters follow the name.
3911     if (R.second)
3912       return std::make_pair(0U, nullptr);
3913 
3914     Reg = StringSwitch<unsigned long long>(Prefix)
3915               .Case("$msair", Mips::MSAIR)
3916               .Case("$msacsr", Mips::MSACSR)
3917               .Case("$msaaccess", Mips::MSAAccess)
3918               .Case("$msasave", Mips::MSASave)
3919               .Case("$msamodify", Mips::MSAModify)
3920               .Case("$msarequest", Mips::MSARequest)
3921               .Case("$msamap", Mips::MSAMap)
3922               .Case("$msaunmap", Mips::MSAUnmap)
3923               .Default(0);
3924 
3925     if (!Reg)
3926       return std::make_pair(0U, nullptr);
3927 
3928     RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
3929     return std::make_pair(Reg, RC);
3930   }
3931 
3932   if (!R.second)
3933     return std::make_pair(0U, nullptr);
3934 
3935   if (Prefix == "$f") { // Parse $f0-$f31.
3936     // If the size of FP registers is 64-bit or Reg is an even number, select
3937     // the 64-bit register class. Otherwise, select the 32-bit register class.
3938     if (VT == MVT::Other)
3939       VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
3940 
3941     RC = getRegClassFor(VT);
3942 
3943     if (RC == &Mips::AFGR64RegClass) {
3944       assert(Reg % 2 == 0);
3945       Reg >>= 1;
3946     }
3947   } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7.
3948     RC = TRI->getRegClass(Mips::FCCRegClassID);
3949   else if (Prefix == "$w") { // Parse $w0-$w31.
3950     RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
3951   } else { // Parse $0-$31.
3952     assert(Prefix == "$");
3953     RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
3954   }
3955 
3956   assert(Reg < RC->getNumRegs());
3957   return std::make_pair(*(RC->begin() + Reg), RC);
3958 }
3959 
3960 /// Given a register class constraint, like 'r', if this corresponds directly
3961 /// to an LLVM register class, return a register of 0 and the register class
3962 /// pointer.
3963 std::pair<unsigned, const TargetRegisterClass *>
3964 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3965                                                  StringRef Constraint,
3966                                                  MVT VT) const {
3967   if (Constraint.size() == 1) {
3968     switch (Constraint[0]) {
3969     case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3970     case 'y': // Same as 'r'. Exists for compatibility.
3971     case 'r':
3972       if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3973         if (Subtarget.inMips16Mode())
3974           return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3975         return std::make_pair(0U, &Mips::GPR32RegClass);
3976       }
3977       if (VT == MVT::i64 && !Subtarget.isGP64bit())
3978         return std::make_pair(0U, &Mips::GPR32RegClass);
3979       if (VT == MVT::i64 && Subtarget.isGP64bit())
3980         return std::make_pair(0U, &Mips::GPR64RegClass);
3981       // This will generate an error message
3982       return std::make_pair(0U, nullptr);
3983     case 'f': // FPU or MSA register
3984       if (VT == MVT::v16i8)
3985         return std::make_pair(0U, &Mips::MSA128BRegClass);
3986       else if (VT == MVT::v8i16 || VT == MVT::v8f16)
3987         return std::make_pair(0U, &Mips::MSA128HRegClass);
3988       else if (VT == MVT::v4i32 || VT == MVT::v4f32)
3989         return std::make_pair(0U, &Mips::MSA128WRegClass);
3990       else if (VT == MVT::v2i64 || VT == MVT::v2f64)
3991         return std::make_pair(0U, &Mips::MSA128DRegClass);
3992       else if (VT == MVT::f32)
3993         return std::make_pair(0U, &Mips::FGR32RegClass);
3994       else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) {
3995         if (Subtarget.isFP64bit())
3996           return std::make_pair(0U, &Mips::FGR64RegClass);
3997         return std::make_pair(0U, &Mips::AFGR64RegClass);
3998       }
3999       break;
4000     case 'c': // register suitable for indirect jump
4001       if (VT == MVT::i32)
4002         return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
4003       if (VT == MVT::i64)
4004         return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
4005       // This will generate an error message
4006       return std::make_pair(0U, nullptr);
4007     case 'l': // use the `lo` register to store values
4008               // that are no bigger than a word
4009       if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
4010         return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
4011       return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
4012     case 'x': // use the concatenated `hi` and `lo` registers
4013               // to store doubleword values
4014       // Fixme: Not triggering the use of both hi and low
4015       // This will generate an error message
4016       return std::make_pair(0U, nullptr);
4017     }
4018   }
4019 
4020   std::pair<unsigned, const TargetRegisterClass *> R;
4021   R = parseRegForInlineAsmConstraint(Constraint, VT);
4022 
4023   if (R.second)
4024     return R;
4025 
4026   return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
4027 }
4028 
4029 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4030 /// vector.  If it is invalid, don't add anything to Ops.
4031 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
4032                                                      std::string &Constraint,
4033                                                      std::vector<SDValue>&Ops,
4034                                                      SelectionDAG &DAG) const {
4035   SDLoc DL(Op);
4036   SDValue Result;
4037 
4038   // Only support length 1 constraints for now.
4039   if (Constraint.length() > 1) return;
4040 
4041   char ConstraintLetter = Constraint[0];
4042   switch (ConstraintLetter) {
4043   default: break; // This will fall through to the generic implementation
4044   case 'I': // Signed 16 bit constant
4045     // If this fails, the parent routine will give an error
4046     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4047       EVT Type = Op.getValueType();
4048       int64_t Val = C->getSExtValue();
4049       if (isInt<16>(Val)) {
4050         Result = DAG.getTargetConstant(Val, DL, Type);
4051         break;
4052       }
4053     }
4054     return;
4055   case 'J': // integer zero
4056     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4057       EVT Type = Op.getValueType();
4058       int64_t Val = C->getZExtValue();
4059       if (Val == 0) {
4060         Result = DAG.getTargetConstant(0, DL, Type);
4061         break;
4062       }
4063     }
4064     return;
4065   case 'K': // unsigned 16 bit immediate
4066     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4067       EVT Type = Op.getValueType();
4068       uint64_t Val = (uint64_t)C->getZExtValue();
4069       if (isUInt<16>(Val)) {
4070         Result = DAG.getTargetConstant(Val, DL, Type);
4071         break;
4072       }
4073     }
4074     return;
4075   case 'L': // signed 32 bit immediate where lower 16 bits are 0
4076     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4077       EVT Type = Op.getValueType();
4078       int64_t Val = C->getSExtValue();
4079       if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
4080         Result = DAG.getTargetConstant(Val, DL, Type);
4081         break;
4082       }
4083     }
4084     return;
4085   case 'N': // immediate in the range of -65535 to -1 (inclusive)
4086     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4087       EVT Type = Op.getValueType();
4088       int64_t Val = C->getSExtValue();
4089       if ((Val >= -65535) && (Val <= -1)) {
4090         Result = DAG.getTargetConstant(Val, DL, Type);
4091         break;
4092       }
4093     }
4094     return;
4095   case 'O': // signed 15 bit immediate
4096     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4097       EVT Type = Op.getValueType();
4098       int64_t Val = C->getSExtValue();
4099       if ((isInt<15>(Val))) {
4100         Result = DAG.getTargetConstant(Val, DL, Type);
4101         break;
4102       }
4103     }
4104     return;
4105   case 'P': // immediate in the range of 1 to 65535 (inclusive)
4106     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4107       EVT Type = Op.getValueType();
4108       int64_t Val = C->getSExtValue();
4109       if ((Val <= 65535) && (Val >= 1)) {
4110         Result = DAG.getTargetConstant(Val, DL, Type);
4111         break;
4112       }
4113     }
4114     return;
4115   }
4116 
4117   if (Result.getNode()) {
4118     Ops.push_back(Result);
4119     return;
4120   }
4121 
4122   TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4123 }
4124 
4125 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL,
4126                                                const AddrMode &AM, Type *Ty,
4127                                                unsigned AS, Instruction *I) const {
4128   // No global is ever allowed as a base.
4129   if (AM.BaseGV)
4130     return false;
4131 
4132   switch (AM.Scale) {
4133   case 0: // "r+i" or just "i", depending on HasBaseReg.
4134     break;
4135   case 1:
4136     if (!AM.HasBaseReg) // allow "r+i".
4137       break;
4138     return false; // disallow "r+r" or "r+r+i".
4139   default:
4140     return false;
4141   }
4142 
4143   return true;
4144 }
4145 
4146 bool
4147 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4148   // The Mips target isn't yet aware of offsets.
4149   return false;
4150 }
4151 
4152 EVT MipsTargetLowering::getOptimalMemOpType(
4153     uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset,
4154     bool ZeroMemset, bool MemcpyStrSrc,
4155     const AttributeList &FuncAttributes) const {
4156   if (Subtarget.hasMips64())
4157     return MVT::i64;
4158 
4159   return MVT::i32;
4160 }
4161 
4162 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
4163                                       bool ForCodeSize) const {
4164   if (VT != MVT::f32 && VT != MVT::f64)
4165     return false;
4166   if (Imm.isNegZero())
4167     return false;
4168   return Imm.isZero();
4169 }
4170 
4171 unsigned MipsTargetLowering::getJumpTableEncoding() const {
4172 
4173   // FIXME: For space reasons this should be: EK_GPRel32BlockAddress.
4174   if (ABI.IsN64() && isPositionIndependent())
4175     return MachineJumpTableInfo::EK_GPRel64BlockAddress;
4176 
4177   return TargetLowering::getJumpTableEncoding();
4178 }
4179 
4180 bool MipsTargetLowering::useSoftFloat() const {
4181   return Subtarget.useSoftFloat();
4182 }
4183 
4184 void MipsTargetLowering::copyByValRegs(
4185     SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains,
4186     SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
4187     SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
4188     unsigned FirstReg, unsigned LastReg, const CCValAssign &VA,
4189     MipsCCState &State) const {
4190   MachineFunction &MF = DAG.getMachineFunction();
4191   MachineFrameInfo &MFI = MF.getFrameInfo();
4192   unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes();
4193   unsigned NumRegs = LastReg - FirstReg;
4194   unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
4195   unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
4196   int FrameObjOffset;
4197   ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs();
4198 
4199   if (RegAreaSize)
4200     FrameObjOffset =
4201         (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
4202         (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes);
4203   else
4204     FrameObjOffset = VA.getLocMemOffset();
4205 
4206   // Create frame object.
4207   EVT PtrTy = getPointerTy(DAG.getDataLayout());
4208   // Make the fixed object stored to mutable so that the load instructions
4209   // referencing it have their memory dependencies added.
4210   // Set the frame object as isAliased which clears the underlying objects
4211   // vector in ScheduleDAGInstrs::buildSchedGraph() resulting in addition of all
4212   // stores as dependencies for loads referencing this fixed object.
4213   int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, false, true);
4214   SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4215   InVals.push_back(FIN);
4216 
4217   if (!NumRegs)
4218     return;
4219 
4220   // Copy arg registers.
4221   MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8);
4222   const TargetRegisterClass *RC = getRegClassFor(RegTy);
4223 
4224   for (unsigned I = 0; I < NumRegs; ++I) {
4225     unsigned ArgReg = ByValArgRegs[FirstReg + I];
4226     unsigned VReg = addLiveIn(MF, ArgReg, RC);
4227     unsigned Offset = I * GPRSizeInBytes;
4228     SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
4229                                    DAG.getConstant(Offset, DL, PtrTy));
4230     SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
4231                                  StorePtr, MachinePointerInfo(FuncArg, Offset));
4232     OutChains.push_back(Store);
4233   }
4234 }
4235 
4236 // Copy byVal arg to registers and stack.
4237 void MipsTargetLowering::passByValArg(
4238     SDValue Chain, const SDLoc &DL,
4239     std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
4240     SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
4241     MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
4242     unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle,
4243     const CCValAssign &VA) const {
4244   unsigned ByValSizeInBytes = Flags.getByValSize();
4245   unsigned OffsetInBytes = 0; // From beginning of struct
4246   unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4247   unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes);
4248   EVT PtrTy = getPointerTy(DAG.getDataLayout()),
4249       RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
4250   unsigned NumRegs = LastReg - FirstReg;
4251 
4252   if (NumRegs) {
4253     ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs();
4254     bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
4255     unsigned I = 0;
4256 
4257     // Copy words to registers.
4258     for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) {
4259       SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4260                                     DAG.getConstant(OffsetInBytes, DL, PtrTy));
4261       SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
4262                                     MachinePointerInfo(), Alignment);
4263       MemOpChains.push_back(LoadVal.getValue(1));
4264       unsigned ArgReg = ArgRegs[FirstReg + I];
4265       RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
4266     }
4267 
4268     // Return if the struct has been fully copied.
4269     if (ByValSizeInBytes == OffsetInBytes)
4270       return;
4271 
4272     // Copy the remainder of the byval argument with sub-word loads and shifts.
4273     if (LeftoverBytes) {
4274       SDValue Val;
4275 
4276       for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
4277            OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
4278         unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
4279 
4280         if (RemainingSizeInBytes < LoadSizeInBytes)
4281           continue;
4282 
4283         // Load subword.
4284         SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4285                                       DAG.getConstant(OffsetInBytes, DL,
4286                                                       PtrTy));
4287         SDValue LoadVal = DAG.getExtLoad(
4288             ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
4289             MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment);
4290         MemOpChains.push_back(LoadVal.getValue(1));
4291 
4292         // Shift the loaded value.
4293         unsigned Shamt;
4294 
4295         if (isLittle)
4296           Shamt = TotalBytesLoaded * 8;
4297         else
4298           Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
4299 
4300         SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
4301                                     DAG.getConstant(Shamt, DL, MVT::i32));
4302 
4303         if (Val.getNode())
4304           Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
4305         else
4306           Val = Shift;
4307 
4308         OffsetInBytes += LoadSizeInBytes;
4309         TotalBytesLoaded += LoadSizeInBytes;
4310         Alignment = std::min(Alignment, LoadSizeInBytes);
4311       }
4312 
4313       unsigned ArgReg = ArgRegs[FirstReg + I];
4314       RegsToPass.push_back(std::make_pair(ArgReg, Val));
4315       return;
4316     }
4317   }
4318 
4319   // Copy remainder of byval arg to it with memcpy.
4320   unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
4321   SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4322                             DAG.getConstant(OffsetInBytes, DL, PtrTy));
4323   SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
4324                             DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
4325   Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
4326                         DAG.getConstant(MemCpySize, DL, PtrTy),
4327                         Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
4328                         /*isTailCall=*/false,
4329                         MachinePointerInfo(), MachinePointerInfo());
4330   MemOpChains.push_back(Chain);
4331 }
4332 
4333 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
4334                                          SDValue Chain, const SDLoc &DL,
4335                                          SelectionDAG &DAG,
4336                                          CCState &State) const {
4337   ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
4338   unsigned Idx = State.getFirstUnallocated(ArgRegs);
4339   unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4340   MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
4341   const TargetRegisterClass *RC = getRegClassFor(RegTy);
4342   MachineFunction &MF = DAG.getMachineFunction();
4343   MachineFrameInfo &MFI = MF.getFrameInfo();
4344   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
4345 
4346   // Offset of the first variable argument from stack pointer.
4347   int VaArgOffset;
4348 
4349   if (ArgRegs.size() == Idx)
4350     VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes);
4351   else {
4352     VaArgOffset =
4353         (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
4354         (int)(RegSizeInBytes * (ArgRegs.size() - Idx));
4355   }
4356 
4357   // Record the frame index of the first variable argument
4358   // which is a value necessary to VASTART.
4359   int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
4360   MipsFI->setVarArgsFrameIndex(FI);
4361 
4362   // Copy the integer registers that have not been used for argument passing
4363   // to the argument register save area. For O32, the save area is allocated
4364   // in the caller's stack frame, while for N32/64, it is allocated in the
4365   // callee's stack frame.
4366   for (unsigned I = Idx; I < ArgRegs.size();
4367        ++I, VaArgOffset += RegSizeInBytes) {
4368     unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
4369     SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
4370     FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
4371     SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
4372     SDValue Store =
4373         DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo());
4374     cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(
4375         (Value *)nullptr);
4376     OutChains.push_back(Store);
4377   }
4378 }
4379 
4380 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size,
4381                                      unsigned Align) const {
4382   const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
4383 
4384   assert(Size && "Byval argument's size shouldn't be 0.");
4385 
4386   Align = std::min(Align, TFL->getStackAlignment());
4387 
4388   unsigned FirstReg = 0;
4389   unsigned NumRegs = 0;
4390 
4391   if (State->getCallingConv() != CallingConv::Fast) {
4392     unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4393     ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs();
4394     // FIXME: The O32 case actually describes no shadow registers.
4395     const MCPhysReg *ShadowRegs =
4396         ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs;
4397 
4398     // We used to check the size as well but we can't do that anymore since
4399     // CCState::HandleByVal() rounds up the size after calling this function.
4400     assert(!(Align % RegSizeInBytes) &&
4401            "Byval argument's alignment should be a multiple of"
4402            "RegSizeInBytes.");
4403 
4404     FirstReg = State->getFirstUnallocated(IntArgRegs);
4405 
4406     // If Align > RegSizeInBytes, the first arg register must be even.
4407     // FIXME: This condition happens to do the right thing but it's not the
4408     //        right way to test it. We want to check that the stack frame offset
4409     //        of the register is aligned.
4410     if ((Align > RegSizeInBytes) && (FirstReg % 2)) {
4411       State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
4412       ++FirstReg;
4413     }
4414 
4415     // Mark the registers allocated.
4416     Size = alignTo(Size, RegSizeInBytes);
4417     for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size());
4418          Size -= RegSizeInBytes, ++I, ++NumRegs)
4419       State->AllocateReg(IntArgRegs[I], ShadowRegs[I]);
4420   }
4421 
4422   State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs);
4423 }
4424 
4425 MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI,
4426                                                         MachineBasicBlock *BB,
4427                                                         bool isFPCmp,
4428                                                         unsigned Opc) const {
4429   assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
4430          "Subtarget already supports SELECT nodes with the use of"
4431          "conditional-move instructions.");
4432 
4433   const TargetInstrInfo *TII =
4434       Subtarget.getInstrInfo();
4435   DebugLoc DL = MI.getDebugLoc();
4436 
4437   // To "insert" a SELECT instruction, we actually have to insert the
4438   // diamond control-flow pattern.  The incoming instruction knows the
4439   // destination vreg to set, the condition code register to branch on, the
4440   // true/false values to select between, and a branch opcode to use.
4441   const BasicBlock *LLVM_BB = BB->getBasicBlock();
4442   MachineFunction::iterator It = ++BB->getIterator();
4443 
4444   //  thisMBB:
4445   //  ...
4446   //   TrueVal = ...
4447   //   setcc r1, r2, r3
4448   //   bNE   r1, r0, copy1MBB
4449   //   fallthrough --> copy0MBB
4450   MachineBasicBlock *thisMBB  = BB;
4451   MachineFunction *F = BB->getParent();
4452   MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4453   MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
4454   F->insert(It, copy0MBB);
4455   F->insert(It, sinkMBB);
4456 
4457   // Transfer the remainder of BB and its successor edges to sinkMBB.
4458   sinkMBB->splice(sinkMBB->begin(), BB,
4459                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
4460   sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4461 
4462   // Next, add the true and fallthrough blocks as its successors.
4463   BB->addSuccessor(copy0MBB);
4464   BB->addSuccessor(sinkMBB);
4465 
4466   if (isFPCmp) {
4467     // bc1[tf] cc, sinkMBB
4468     BuildMI(BB, DL, TII->get(Opc))
4469         .addReg(MI.getOperand(1).getReg())
4470         .addMBB(sinkMBB);
4471   } else {
4472     // bne rs, $0, sinkMBB
4473     BuildMI(BB, DL, TII->get(Opc))
4474         .addReg(MI.getOperand(1).getReg())
4475         .addReg(Mips::ZERO)
4476         .addMBB(sinkMBB);
4477   }
4478 
4479   //  copy0MBB:
4480   //   %FalseValue = ...
4481   //   # fallthrough to sinkMBB
4482   BB = copy0MBB;
4483 
4484   // Update machine-CFG edges
4485   BB->addSuccessor(sinkMBB);
4486 
4487   //  sinkMBB:
4488   //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
4489   //  ...
4490   BB = sinkMBB;
4491 
4492   BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4493       .addReg(MI.getOperand(2).getReg())
4494       .addMBB(thisMBB)
4495       .addReg(MI.getOperand(3).getReg())
4496       .addMBB(copy0MBB);
4497 
4498   MI.eraseFromParent(); // The pseudo instruction is gone now.
4499 
4500   return BB;
4501 }
4502 
4503 MachineBasicBlock *MipsTargetLowering::emitPseudoD_SELECT(MachineInstr &MI,
4504                                                           MachineBasicBlock *BB) const {
4505   assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
4506          "Subtarget already supports SELECT nodes with the use of"
4507          "conditional-move instructions.");
4508 
4509   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
4510   DebugLoc DL = MI.getDebugLoc();
4511 
4512   // D_SELECT substitutes two SELECT nodes that goes one after another and
4513   // have the same condition operand. On machines which don't have
4514   // conditional-move instruction, it reduces unnecessary branch instructions
4515   // which are result of using two diamond patterns that are result of two
4516   // SELECT pseudo instructions.
4517   const BasicBlock *LLVM_BB = BB->getBasicBlock();
4518   MachineFunction::iterator It = ++BB->getIterator();
4519 
4520   //  thisMBB:
4521   //  ...
4522   //   TrueVal = ...
4523   //   setcc r1, r2, r3
4524   //   bNE   r1, r0, copy1MBB
4525   //   fallthrough --> copy0MBB
4526   MachineBasicBlock *thisMBB = BB;
4527   MachineFunction *F = BB->getParent();
4528   MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4529   MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4530   F->insert(It, copy0MBB);
4531   F->insert(It, sinkMBB);
4532 
4533   // Transfer the remainder of BB and its successor edges to sinkMBB.
4534   sinkMBB->splice(sinkMBB->begin(), BB,
4535                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
4536   sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4537 
4538   // Next, add the true and fallthrough blocks as its successors.
4539   BB->addSuccessor(copy0MBB);
4540   BB->addSuccessor(sinkMBB);
4541 
4542   // bne rs, $0, sinkMBB
4543   BuildMI(BB, DL, TII->get(Mips::BNE))
4544       .addReg(MI.getOperand(2).getReg())
4545       .addReg(Mips::ZERO)
4546       .addMBB(sinkMBB);
4547 
4548   //  copy0MBB:
4549   //   %FalseValue = ...
4550   //   # fallthrough to sinkMBB
4551   BB = copy0MBB;
4552 
4553   // Update machine-CFG edges
4554   BB->addSuccessor(sinkMBB);
4555 
4556   //  sinkMBB:
4557   //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
4558   //  ...
4559   BB = sinkMBB;
4560 
4561   // Use two PHI nodes to select two reults
4562   BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4563       .addReg(MI.getOperand(3).getReg())
4564       .addMBB(thisMBB)
4565       .addReg(MI.getOperand(5).getReg())
4566       .addMBB(copy0MBB);
4567   BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(1).getReg())
4568       .addReg(MI.getOperand(4).getReg())
4569       .addMBB(thisMBB)
4570       .addReg(MI.getOperand(6).getReg())
4571       .addMBB(copy0MBB);
4572 
4573   MI.eraseFromParent(); // The pseudo instruction is gone now.
4574 
4575   return BB;
4576 }
4577 
4578 // FIXME? Maybe this could be a TableGen attribute on some registers and
4579 // this table could be generated automatically from RegInfo.
4580 unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT,
4581                                                SelectionDAG &DAG) const {
4582   // Named registers is expected to be fairly rare. For now, just support $28
4583   // since the linux kernel uses it.
4584   if (Subtarget.isGP64bit()) {
4585     unsigned Reg = StringSwitch<unsigned>(RegName)
4586                          .Case("$28", Mips::GP_64)
4587                          .Default(0);
4588     if (Reg)
4589       return Reg;
4590   } else {
4591     unsigned Reg = StringSwitch<unsigned>(RegName)
4592                          .Case("$28", Mips::GP)
4593                          .Default(0);
4594     if (Reg)
4595       return Reg;
4596   }
4597   report_fatal_error("Invalid register name global variable");
4598 }
4599