1 //===---- MipsISelDAGToDAG.h - A Dag to Dag Inst Selector for Mips --------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines an instruction selector for the MIPS target. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELDAGTODAG_H 14 #define LLVM_LIB_TARGET_MIPS_MIPSISELDAGTODAG_H 15 16 #include "Mips.h" 17 #include "MipsSubtarget.h" 18 #include "MipsTargetMachine.h" 19 #include "llvm/CodeGen/SelectionDAGISel.h" 20 21 //===----------------------------------------------------------------------===// 22 // Instruction Selector Implementation 23 //===----------------------------------------------------------------------===// 24 25 //===----------------------------------------------------------------------===// 26 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine 27 // instructions for SelectionDAG operations. 28 //===----------------------------------------------------------------------===// 29 namespace llvm { 30 31 class MipsDAGToDAGISel : public SelectionDAGISel { 32 public: 33 static char ID; 34 35 MipsDAGToDAGISel() = delete; 36 37 explicit MipsDAGToDAGISel(MipsTargetMachine &TM, CodeGenOptLevel OL) 38 : SelectionDAGISel(ID, TM, OL), Subtarget(nullptr) {} 39 40 bool runOnMachineFunction(MachineFunction &MF) override; 41 42 void getAnalysisUsage(AnalysisUsage &AU) const override; 43 44 protected: 45 SDNode *getGlobalBaseReg(); 46 47 /// Keep a pointer to the MipsSubtarget around so that we can make the right 48 /// decision when generating code for different targets. 49 const MipsSubtarget *Subtarget; 50 51 private: 52 // Include the pieces autogenerated from the target description. 53 #include "MipsGenDAGISel.inc" 54 55 // Complex Pattern. 56 /// (reg + imm). 57 virtual bool selectAddrRegImm(SDValue Addr, SDValue &Base, 58 SDValue &Offset) const; 59 60 /// Fall back on this function if all else fails. 61 virtual bool selectAddrDefault(SDValue Addr, SDValue &Base, 62 SDValue &Offset) const; 63 64 /// Match integer address pattern. 65 virtual bool selectIntAddr(SDValue Addr, SDValue &Base, 66 SDValue &Offset) const; 67 68 virtual bool selectIntAddr11MM(SDValue Addr, SDValue &Base, 69 SDValue &Offset) const; 70 71 virtual bool selectIntAddr12MM(SDValue Addr, SDValue &Base, 72 SDValue &Offset) const; 73 74 virtual bool selectIntAddr16MM(SDValue Addr, SDValue &Base, 75 SDValue &Offset) const; 76 77 virtual bool selectIntAddrLSL2MM(SDValue Addr, SDValue &Base, 78 SDValue &Offset) const; 79 80 /// Match addr+simm10 and addr 81 virtual bool selectIntAddrSImm10(SDValue Addr, SDValue &Base, 82 SDValue &Offset) const; 83 84 virtual bool selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base, 85 SDValue &Offset) const; 86 87 virtual bool selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base, 88 SDValue &Offset) const; 89 90 virtual bool selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base, 91 SDValue &Offset) const; 92 93 virtual bool selectAddr16(SDValue Addr, SDValue &Base, SDValue &Offset); 94 virtual bool selectAddr16SP(SDValue Addr, SDValue &Base, SDValue &Offset); 95 96 /// Select constant vector splats. 97 virtual bool selectVSplat(SDNode *N, APInt &Imm, 98 unsigned MinSizeInBits) const; 99 /// Select constant vector splats whose value fits in a uimm1. 100 virtual bool selectVSplatUimm1(SDValue N, SDValue &Imm) const; 101 /// Select constant vector splats whose value fits in a uimm2. 102 virtual bool selectVSplatUimm2(SDValue N, SDValue &Imm) const; 103 /// Select constant vector splats whose value fits in a uimm3. 104 virtual bool selectVSplatUimm3(SDValue N, SDValue &Imm) const; 105 /// Select constant vector splats whose value fits in a uimm4. 106 virtual bool selectVSplatUimm4(SDValue N, SDValue &Imm) const; 107 /// Select constant vector splats whose value fits in a uimm5. 108 virtual bool selectVSplatUimm5(SDValue N, SDValue &Imm) const; 109 /// Select constant vector splats whose value fits in a uimm6. 110 virtual bool selectVSplatUimm6(SDValue N, SDValue &Imm) const; 111 /// Select constant vector splats whose value fits in a uimm8. 112 virtual bool selectVSplatUimm8(SDValue N, SDValue &Imm) const; 113 /// Select constant vector splats whose value fits in a simm5. 114 virtual bool selectVSplatSimm5(SDValue N, SDValue &Imm) const; 115 /// Select constant vector splats whose value is a power of 2. 116 virtual bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) const; 117 /// Select constant vector splats whose value is the inverse of a 118 /// power of 2. 119 virtual bool selectVSplatUimmInvPow2(SDValue N, SDValue &Imm) const; 120 /// Select constant vector splats whose value is a run of set bits 121 /// ending at the most significant bit 122 virtual bool selectVSplatMaskL(SDValue N, SDValue &Imm) const; 123 /// Select constant vector splats whose value is a run of set bits 124 /// starting at bit zero. 125 virtual bool selectVSplatMaskR(SDValue N, SDValue &Imm) const; 126 127 /// Convert vector addition with vector subtraction if that allows to encode 128 /// constant as an immediate and thus avoid extra 'ldi' instruction. 129 /// add X, <-1, -1...> --> sub X, <1, 1...> 130 bool selectVecAddAsVecSubIfProfitable(SDNode *Node); 131 132 void Select(SDNode *N) override; 133 134 virtual bool trySelect(SDNode *Node) = 0; 135 136 // getImm - Return a target constant with the specified value. 137 inline SDValue getImm(const SDNode *Node, uint64_t Imm) { 138 return CurDAG->getTargetConstant(Imm, SDLoc(Node), Node->getValueType(0)); 139 } 140 141 virtual void processFunctionAfterISel(MachineFunction &MF) = 0; 142 143 bool SelectInlineAsmMemoryOperand(const SDValue &Op, 144 InlineAsm::ConstraintCode ConstraintID, 145 std::vector<SDValue> &OutOps) override; 146 bool isUnneededShiftMask(SDNode *N, unsigned ShAmtBits) const; 147 }; 148 } 149 150 #endif 151