1 //===---- MipsISelDAGToDAG.h - A Dag to Dag Inst Selector for Mips --------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines an instruction selector for the MIPS target. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELDAGTODAG_H 14 #define LLVM_LIB_TARGET_MIPS_MIPSISELDAGTODAG_H 15 16 #include "Mips.h" 17 #include "MipsSubtarget.h" 18 #include "MipsTargetMachine.h" 19 #include "llvm/CodeGen/SelectionDAGISel.h" 20 21 //===----------------------------------------------------------------------===// 22 // Instruction Selector Implementation 23 //===----------------------------------------------------------------------===// 24 25 //===----------------------------------------------------------------------===// 26 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine 27 // instructions for SelectionDAG operations. 28 //===----------------------------------------------------------------------===// 29 namespace llvm { 30 31 class MipsDAGToDAGISel : public SelectionDAGISel { 32 public: 33 explicit MipsDAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL) 34 : SelectionDAGISel(TM, OL), Subtarget(nullptr) {} 35 36 // Pass Name 37 StringRef getPassName() const override { 38 return "MIPS DAG->DAG Pattern Instruction Selection"; 39 } 40 41 bool runOnMachineFunction(MachineFunction &MF) override; 42 43 void getAnalysisUsage(AnalysisUsage &AU) const override; 44 45 protected: 46 SDNode *getGlobalBaseReg(); 47 48 /// Keep a pointer to the MipsSubtarget around so that we can make the right 49 /// decision when generating code for different targets. 50 const MipsSubtarget *Subtarget; 51 52 private: 53 // Include the pieces autogenerated from the target description. 54 #include "MipsGenDAGISel.inc" 55 56 // Complex Pattern. 57 /// (reg + imm). 58 virtual bool selectAddrRegImm(SDValue Addr, SDValue &Base, 59 SDValue &Offset) const; 60 61 /// Fall back on this function if all else fails. 62 virtual bool selectAddrDefault(SDValue Addr, SDValue &Base, 63 SDValue &Offset) const; 64 65 /// Match integer address pattern. 66 virtual bool selectIntAddr(SDValue Addr, SDValue &Base, 67 SDValue &Offset) const; 68 69 virtual bool selectIntAddr11MM(SDValue Addr, SDValue &Base, 70 SDValue &Offset) const; 71 72 virtual bool selectIntAddr12MM(SDValue Addr, SDValue &Base, 73 SDValue &Offset) const; 74 75 virtual bool selectIntAddr16MM(SDValue Addr, SDValue &Base, 76 SDValue &Offset) const; 77 78 virtual bool selectIntAddrLSL2MM(SDValue Addr, SDValue &Base, 79 SDValue &Offset) const; 80 81 /// Match addr+simm10 and addr 82 virtual bool selectIntAddrSImm10(SDValue Addr, SDValue &Base, 83 SDValue &Offset) const; 84 85 virtual bool selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base, 86 SDValue &Offset) const; 87 88 virtual bool selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base, 89 SDValue &Offset) const; 90 91 virtual bool selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base, 92 SDValue &Offset) const; 93 94 virtual bool selectAddr16(SDValue Addr, SDValue &Base, SDValue &Offset); 95 virtual bool selectAddr16SP(SDValue Addr, SDValue &Base, SDValue &Offset); 96 97 /// Select constant vector splats. 98 virtual bool selectVSplat(SDNode *N, APInt &Imm, 99 unsigned MinSizeInBits) const; 100 /// Select constant vector splats whose value fits in a uimm1. 101 virtual bool selectVSplatUimm1(SDValue N, SDValue &Imm) const; 102 /// Select constant vector splats whose value fits in a uimm2. 103 virtual bool selectVSplatUimm2(SDValue N, SDValue &Imm) const; 104 /// Select constant vector splats whose value fits in a uimm3. 105 virtual bool selectVSplatUimm3(SDValue N, SDValue &Imm) const; 106 /// Select constant vector splats whose value fits in a uimm4. 107 virtual bool selectVSplatUimm4(SDValue N, SDValue &Imm) const; 108 /// Select constant vector splats whose value fits in a uimm5. 109 virtual bool selectVSplatUimm5(SDValue N, SDValue &Imm) const; 110 /// Select constant vector splats whose value fits in a uimm6. 111 virtual bool selectVSplatUimm6(SDValue N, SDValue &Imm) const; 112 /// Select constant vector splats whose value fits in a uimm8. 113 virtual bool selectVSplatUimm8(SDValue N, SDValue &Imm) const; 114 /// Select constant vector splats whose value fits in a simm5. 115 virtual bool selectVSplatSimm5(SDValue N, SDValue &Imm) const; 116 /// Select constant vector splats whose value is a power of 2. 117 virtual bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) const; 118 /// Select constant vector splats whose value is the inverse of a 119 /// power of 2. 120 virtual bool selectVSplatUimmInvPow2(SDValue N, SDValue &Imm) const; 121 /// Select constant vector splats whose value is a run of set bits 122 /// ending at the most significant bit 123 virtual bool selectVSplatMaskL(SDValue N, SDValue &Imm) const; 124 /// Select constant vector splats whose value is a run of set bits 125 /// starting at bit zero. 126 virtual bool selectVSplatMaskR(SDValue N, SDValue &Imm) const; 127 128 /// Convert vector addition with vector subtraction if that allows to encode 129 /// constant as an immediate and thus avoid extra 'ldi' instruction. 130 /// add X, <-1, -1...> --> sub X, <1, 1...> 131 bool selectVecAddAsVecSubIfProfitable(SDNode *Node); 132 133 void Select(SDNode *N) override; 134 135 virtual bool trySelect(SDNode *Node) = 0; 136 137 // getImm - Return a target constant with the specified value. 138 inline SDValue getImm(const SDNode *Node, uint64_t Imm) { 139 return CurDAG->getTargetConstant(Imm, SDLoc(Node), Node->getValueType(0)); 140 } 141 142 virtual void processFunctionAfterISel(MachineFunction &MF) = 0; 143 144 bool SelectInlineAsmMemoryOperand(const SDValue &Op, 145 unsigned ConstraintID, 146 std::vector<SDValue> &OutOps) override; 147 }; 148 } 149 150 #endif 151