1//===- MipsEVAInstrInfo.td - EVA ASE instructions -*- tablegen ------------*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes Mips EVA ASE instructions. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// 15// Instruction encodings 16// 17//===----------------------------------------------------------------------===// 18 19// Memory Load/Store EVA encodings 20class LBE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LBE>; 21class LBuE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LBuE>; 22class LHE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LHE>; 23class LHuE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LHuE>; 24class LWE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LWE>; 25 26class SBE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SBE>; 27class SHE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SHE>; 28class SWE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SWE>; 29 30// load/store left/right EVA encodings 31class LWLE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LWLE>; 32class LWRE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LWRE>; 33class SWLE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SWLE>; 34class SWRE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SWRE>; 35 36// Load-linked EVA, Store-conditional EVA encodings 37class LLE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LLE>; 38class SCE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SCE>; 39 40class TLBINV_ENC : TLB_FM<OPCODE6_TLBINV>; 41class TLBINVF_ENC : TLB_FM<OPCODE6_TLBINVF>; 42 43class CACHEE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_CACHEE>; 44class PREFE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_PREFE>; 45 46//===----------------------------------------------------------------------===// 47// 48// Instruction descriptions 49// 50//===----------------------------------------------------------------------===// 51 52// Memory Load/Store EVA descriptions 53class LOAD_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 54 InstrItinClass itin = NoItinerary> { 55 dag OutOperandList = (outs GPROpnd:$rt); 56 dag InOperandList = (ins mem_simm9:$addr); 57 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 58 list<dag> Pattern = []; 59 string DecoderMethod = "DecodeMemEVA"; 60 bit canFoldAsLoad = 1; 61 string BaseOpcode = instr_asm; 62 bit mayLoad = 1; 63 InstrItinClass Itinerary = itin; 64} 65 66class LBE_DESC : LOAD_EVA_DESC_BASE<"lbe", GPR32Opnd, II_LBE>; 67class LBuE_DESC : LOAD_EVA_DESC_BASE<"lbue", GPR32Opnd, II_LBUE>; 68class LHE_DESC : LOAD_EVA_DESC_BASE<"lhe", GPR32Opnd, II_LHE>; 69class LHuE_DESC : LOAD_EVA_DESC_BASE<"lhue", GPR32Opnd, II_LHUE>; 70class LWE_DESC : LOAD_EVA_DESC_BASE<"lwe", GPR32Opnd, II_LWE>; 71 72class STORE_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 73 InstrItinClass itin> { 74 dag OutOperandList = (outs); 75 dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr); 76 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 77 list<dag> Pattern = []; 78 string DecoderMethod = "DecodeMemEVA"; 79 string BaseOpcode = instr_asm; 80 bit mayStore = 1; 81 InstrItinClass Itinerary = itin; 82} 83 84class SBE_DESC : STORE_EVA_DESC_BASE<"sbe", GPR32Opnd, II_SBE>; 85class SHE_DESC : STORE_EVA_DESC_BASE<"she", GPR32Opnd, II_SHE>; 86class SWE_DESC : STORE_EVA_DESC_BASE<"swe", GPR32Opnd, II_SWE>; 87 88// Load/Store Left/Right EVA descriptions 89class LOAD_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 90 InstrItinClass itin = NoItinerary> { 91 dag OutOperandList = (outs GPROpnd:$rt); 92 dag InOperandList = (ins mem_simm9:$addr, GPROpnd:$src); 93 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 94 list<dag> Pattern = []; 95 string DecoderMethod = "DecodeMemEVA"; 96 string BaseOpcode = instr_asm; 97 string Constraints = "$src = $rt"; 98 bit canFoldAsLoad = 1; 99 InstrItinClass Itinerary = itin; 100 bit mayLoad = 1; 101 bit mayStore = 0; 102} 103 104class LWLE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"lwle", GPR32Opnd, II_LWLE>; 105class LWRE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"lwre", GPR32Opnd, II_LWRE>; 106 107class STORE_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 108 InstrItinClass itin = NoItinerary> { 109 dag OutOperandList = (outs); 110 dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr); 111 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 112 list<dag> Pattern = []; 113 string DecoderMethod = "DecodeMemEVA"; 114 string BaseOpcode = instr_asm; 115 InstrItinClass Itinerary = itin; 116 bit mayLoad = 0; 117 bit mayStore = 1; 118} 119 120class SWLE_DESC : STORE_LEFT_RIGHT_EVA_DESC_BASE<"swle", GPR32Opnd, II_SWLE>; 121class SWRE_DESC : STORE_LEFT_RIGHT_EVA_DESC_BASE<"swre", GPR32Opnd, II_SWRE>; 122 123// Load-linked EVA, Store-conditional EVA descriptions 124class LLE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 125 InstrItinClass itin = NoItinerary> { 126 dag OutOperandList = (outs GPROpnd:$rt); 127 dag InOperandList = (ins mem_simm9:$addr); 128 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 129 list<dag> Pattern = []; 130 string BaseOpcode = instr_asm; 131 bit mayLoad = 1; 132 string DecoderMethod = "DecodeMemEVA"; 133 InstrItinClass Itinerary = itin; 134} 135 136class LLE_DESC : LLE_DESC_BASE<"lle", GPR32Opnd, II_LLE>; 137 138class SCE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 139 InstrItinClass itin = NoItinerary> { 140 dag OutOperandList = (outs GPROpnd:$dst); 141 dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr); 142 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 143 list<dag> Pattern = []; 144 string BaseOpcode = instr_asm; 145 bit mayStore = 1; 146 string Constraints = "$rt = $dst"; 147 string DecoderMethod = "DecodeMemEVA"; 148 InstrItinClass Itinerary = itin; 149} 150 151class SCE_DESC : SCE_DESC_BASE<"sce", GPR32Opnd, II_SCE>; 152 153class TLB_DESC_BASE<string instr_asm, InstrItinClass itin = NoItinerary> { 154 dag OutOperandList = (outs); 155 dag InOperandList = (ins); 156 string AsmString = instr_asm; 157 list<dag> Pattern = []; 158 InstrItinClass Itinerary = itin; 159} 160 161class TLBINV_DESC : TLB_DESC_BASE<"tlbinv", II_TLBINV>; 162class TLBINVF_DESC : TLB_DESC_BASE<"tlbinvf", II_TLBINVF>; 163 164class CACHEE_DESC_BASE<string instr_asm, Operand MemOpnd, 165 InstrItinClass itin = NoItinerary> { 166 // CACHEE puts the "hint" immediate where the encoding would otherwise have "rt" 167 bits<5> hint; 168 bits<5> rt = hint; 169 170 dag OutOperandList = (outs); 171 dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint); 172 string AsmString = !strconcat(instr_asm, "\t$hint, $addr"); 173 list<dag> Pattern = []; 174 string BaseOpcode = instr_asm; 175 string DecoderMethod = "DecodeCacheeOp_CacheOpR6"; 176 InstrItinClass Itinerary = itin; 177} 178 179class CACHEE_DESC : CACHEE_DESC_BASE<"cachee", mem_simm9, II_CACHEE>; 180class PREFE_DESC : CACHEE_DESC_BASE<"prefe", mem_simm9, II_PREFE>; 181 182//===----------------------------------------------------------------------===// 183// 184// Instruction definitions 185// 186//===----------------------------------------------------------------------===// 187 188let AdditionalPredicates = [NotInMicroMips] in { 189 /// Load and Store EVA Instructions 190 def LBE : MMRel, LBE_ENC, LBE_DESC, ISA_MIPS32R2, ASE_EVA; 191 def LBuE : MMRel, LBuE_ENC, LBuE_DESC, ISA_MIPS32R2, ASE_EVA; 192 def LHE : MMRel, LHE_ENC, LHE_DESC, ISA_MIPS32R2, ASE_EVA; 193 def LHuE : MMRel, LHuE_ENC, LHuE_DESC, ISA_MIPS32R2, ASE_EVA; 194 def LWE : MMRel, LWE_ENC, LWE_DESC, ISA_MIPS32R2, ASE_EVA; 195 def SBE : MMRel, SBE_ENC, SBE_DESC, ISA_MIPS32R2, ASE_EVA; 196 def SHE : MMRel, SHE_ENC, SHE_DESC, ISA_MIPS32R2, ASE_EVA; 197 def SWE : MMRel, SWE_ENC, SWE_DESC, ISA_MIPS32R2, ASE_EVA; 198 199 /// load/store left/right EVA 200 def LWLE : MMRel, LWLE_ENC, LWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA; 201 def LWRE : MMRel, LWRE_ENC, LWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA; 202 def SWLE : MMRel, SWLE_ENC, SWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA; 203 def SWRE : MMRel, SWRE_ENC, SWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA; 204 205 /// Load-linked EVA, Store-conditional EVA 206 def LLE : MMRel, LLE_ENC, LLE_DESC, ISA_MIPS32R2, ASE_EVA; 207 def SCE : MMRel, SCE_ENC, SCE_DESC, ISA_MIPS32R2, ASE_EVA; 208 209 /// TLB invalidate instructions 210 def TLBINV : TLBINV_ENC, TLBINV_DESC, ISA_MIPS32R2, ASE_EVA; 211 def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, ISA_MIPS32R2, ASE_EVA; 212 213 /// EVA versions of cache and pref 214 def CACHEE : MMRel, CACHEE_ENC, CACHEE_DESC, ISA_MIPS32R2, ASE_EVA; 215 def PREFE : MMRel, PREFE_ENC, PREFE_DESC, ISA_MIPS32R2, ASE_EVA; 216} 217