xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp (revision cfd6422a5217410fbd66f7a7a8a64d9d85e61229)
1 //===- MipsDelaySlotFiller.cpp - Mips Delay Slot Filler -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Simple pass to fill delay slots with useful instructions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MCTargetDesc/MipsMCNaCl.h"
14 #include "Mips.h"
15 #include "MipsInstrInfo.h"
16 #include "MipsRegisterInfo.h"
17 #include "MipsSubtarget.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/PointerUnion.h"
21 #include "llvm/ADT/SmallPtrSet.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/Analysis/ValueTracking.h"
27 #include "llvm/CodeGen/MachineBasicBlock.h"
28 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineFunctionPass.h"
31 #include "llvm/CodeGen/MachineInstr.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineOperand.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/PseudoSourceValue.h"
36 #include "llvm/CodeGen/TargetRegisterInfo.h"
37 #include "llvm/CodeGen/TargetSubtargetInfo.h"
38 #include "llvm/MC/MCInstrDesc.h"
39 #include "llvm/MC/MCRegisterInfo.h"
40 #include "llvm/Support/Casting.h"
41 #include "llvm/Support/CodeGen.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include <algorithm>
46 #include <cassert>
47 #include <iterator>
48 #include <memory>
49 #include <utility>
50 
51 using namespace llvm;
52 
53 #define DEBUG_TYPE "mips-delay-slot-filler"
54 
55 STATISTIC(FilledSlots, "Number of delay slots filled");
56 STATISTIC(UsefulSlots, "Number of delay slots filled with instructions that"
57                        " are not NOP.");
58 
59 static cl::opt<bool> DisableDelaySlotFiller(
60   "disable-mips-delay-filler",
61   cl::init(false),
62   cl::desc("Fill all delay slots with NOPs."),
63   cl::Hidden);
64 
65 static cl::opt<bool> DisableForwardSearch(
66   "disable-mips-df-forward-search",
67   cl::init(true),
68   cl::desc("Disallow MIPS delay filler to search forward."),
69   cl::Hidden);
70 
71 static cl::opt<bool> DisableSuccBBSearch(
72   "disable-mips-df-succbb-search",
73   cl::init(true),
74   cl::desc("Disallow MIPS delay filler to search successor basic blocks."),
75   cl::Hidden);
76 
77 static cl::opt<bool> DisableBackwardSearch(
78   "disable-mips-df-backward-search",
79   cl::init(false),
80   cl::desc("Disallow MIPS delay filler to search backward."),
81   cl::Hidden);
82 
83 enum CompactBranchPolicy {
84   CB_Never,   ///< The policy 'never' may in some circumstances or for some
85               ///< ISAs not be absolutely adhered to.
86   CB_Optimal, ///< Optimal is the default and will produce compact branches
87               ///< when delay slots cannot be filled.
88   CB_Always   ///< 'always' may in some circumstances may not be
89               ///< absolutely adhered to there may not be a corresponding
90               ///< compact form of a branch.
91 };
92 
93 static cl::opt<CompactBranchPolicy> MipsCompactBranchPolicy(
94     "mips-compact-branches", cl::Optional, cl::init(CB_Optimal),
95     cl::desc("MIPS Specific: Compact branch policy."),
96     cl::values(clEnumValN(CB_Never, "never",
97                           "Do not use compact branches if possible."),
98                clEnumValN(CB_Optimal, "optimal",
99                           "Use compact branches where appropriate (default)."),
100                clEnumValN(CB_Always, "always",
101                           "Always use compact branches if possible.")));
102 
103 namespace {
104 
105   using Iter = MachineBasicBlock::iterator;
106   using ReverseIter = MachineBasicBlock::reverse_iterator;
107   using BB2BrMap = SmallDenseMap<MachineBasicBlock *, MachineInstr *, 2>;
108 
109   class RegDefsUses {
110   public:
111     RegDefsUses(const TargetRegisterInfo &TRI);
112 
113     void init(const MachineInstr &MI);
114 
115     /// This function sets all caller-saved registers in Defs.
116     void setCallerSaved(const MachineInstr &MI);
117 
118     /// This function sets all unallocatable registers in Defs.
119     void setUnallocatableRegs(const MachineFunction &MF);
120 
121     /// Set bits in Uses corresponding to MBB's live-out registers except for
122     /// the registers that are live-in to SuccBB.
123     void addLiveOut(const MachineBasicBlock &MBB,
124                     const MachineBasicBlock &SuccBB);
125 
126     bool update(const MachineInstr &MI, unsigned Begin, unsigned End);
127 
128   private:
129     bool checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses, unsigned Reg,
130                           bool IsDef) const;
131 
132     /// Returns true if Reg or its alias is in RegSet.
133     bool isRegInSet(const BitVector &RegSet, unsigned Reg) const;
134 
135     const TargetRegisterInfo &TRI;
136     BitVector Defs, Uses;
137   };
138 
139   /// Base class for inspecting loads and stores.
140   class InspectMemInstr {
141   public:
142     InspectMemInstr(bool ForbidMemInstr_) : ForbidMemInstr(ForbidMemInstr_) {}
143     virtual ~InspectMemInstr() = default;
144 
145     /// Return true if MI cannot be moved to delay slot.
146     bool hasHazard(const MachineInstr &MI);
147 
148   protected:
149     /// Flags indicating whether loads or stores have been seen.
150     bool OrigSeenLoad = false;
151     bool OrigSeenStore = false;
152     bool SeenLoad = false;
153     bool SeenStore = false;
154 
155     /// Memory instructions are not allowed to move to delay slot if this flag
156     /// is true.
157     bool ForbidMemInstr;
158 
159   private:
160     virtual bool hasHazard_(const MachineInstr &MI) = 0;
161   };
162 
163   /// This subclass rejects any memory instructions.
164   class NoMemInstr : public InspectMemInstr {
165   public:
166     NoMemInstr() : InspectMemInstr(true) {}
167 
168   private:
169     bool hasHazard_(const MachineInstr &MI) override { return true; }
170   };
171 
172   /// This subclass accepts loads from stacks and constant loads.
173   class LoadFromStackOrConst : public InspectMemInstr {
174   public:
175     LoadFromStackOrConst() : InspectMemInstr(false) {}
176 
177   private:
178     bool hasHazard_(const MachineInstr &MI) override;
179   };
180 
181   /// This subclass uses memory dependence information to determine whether a
182   /// memory instruction can be moved to a delay slot.
183   class MemDefsUses : public InspectMemInstr {
184   public:
185     MemDefsUses(const DataLayout &DL, const MachineFrameInfo *MFI);
186 
187   private:
188     using ValueType = PointerUnion<const Value *, const PseudoSourceValue *>;
189 
190     bool hasHazard_(const MachineInstr &MI) override;
191 
192     /// Update Defs and Uses. Return true if there exist dependences that
193     /// disqualify the delay slot candidate between V and values in Uses and
194     /// Defs.
195     bool updateDefsUses(ValueType V, bool MayStore);
196 
197     /// Get the list of underlying objects of MI's memory operand.
198     bool getUnderlyingObjects(const MachineInstr &MI,
199                               SmallVectorImpl<ValueType> &Objects) const;
200 
201     const MachineFrameInfo *MFI;
202     SmallPtrSet<ValueType, 4> Uses, Defs;
203     const DataLayout &DL;
204 
205     /// Flags indicating whether loads or stores with no underlying objects have
206     /// been seen.
207     bool SeenNoObjLoad = false;
208     bool SeenNoObjStore = false;
209   };
210 
211   class MipsDelaySlotFiller : public MachineFunctionPass {
212   public:
213     MipsDelaySlotFiller() : MachineFunctionPass(ID) {
214       initializeMipsDelaySlotFillerPass(*PassRegistry::getPassRegistry());
215     }
216 
217     StringRef getPassName() const override { return "Mips Delay Slot Filler"; }
218 
219     bool runOnMachineFunction(MachineFunction &F) override {
220       TM = &F.getTarget();
221       bool Changed = false;
222       for (MachineFunction::iterator FI = F.begin(), FE = F.end();
223            FI != FE; ++FI)
224         Changed |= runOnMachineBasicBlock(*FI);
225 
226       // This pass invalidates liveness information when it reorders
227       // instructions to fill delay slot. Without this, -verify-machineinstrs
228       // will fail.
229       if (Changed)
230         F.getRegInfo().invalidateLiveness();
231 
232       return Changed;
233     }
234 
235     MachineFunctionProperties getRequiredProperties() const override {
236       return MachineFunctionProperties().set(
237           MachineFunctionProperties::Property::NoVRegs);
238     }
239 
240     void getAnalysisUsage(AnalysisUsage &AU) const override {
241       AU.addRequired<MachineBranchProbabilityInfo>();
242       MachineFunctionPass::getAnalysisUsage(AU);
243     }
244 
245     static char ID;
246 
247   private:
248     bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
249 
250     Iter replaceWithCompactBranch(MachineBasicBlock &MBB, Iter Branch,
251                                   const DebugLoc &DL);
252 
253     /// This function checks if it is valid to move Candidate to the delay slot
254     /// and returns true if it isn't. It also updates memory and register
255     /// dependence information.
256     bool delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
257                         InspectMemInstr &IM) const;
258 
259     /// This function searches range [Begin, End) for an instruction that can be
260     /// moved to the delay slot. Returns true on success.
261     template<typename IterTy>
262     bool searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
263                      RegDefsUses &RegDU, InspectMemInstr &IM, Iter Slot,
264                      IterTy &Filler) const;
265 
266     /// This function searches in the backward direction for an instruction that
267     /// can be moved to the delay slot. Returns true on success.
268     bool searchBackward(MachineBasicBlock &MBB, MachineInstr &Slot) const;
269 
270     /// This function searches MBB in the forward direction for an instruction
271     /// that can be moved to the delay slot. Returns true on success.
272     bool searchForward(MachineBasicBlock &MBB, Iter Slot) const;
273 
274     /// This function searches one of MBB's successor blocks for an instruction
275     /// that can be moved to the delay slot and inserts clones of the
276     /// instruction into the successor's predecessor blocks.
277     bool searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const;
278 
279     /// Pick a successor block of MBB. Return NULL if MBB doesn't have a
280     /// successor block that is not a landing pad.
281     MachineBasicBlock *selectSuccBB(MachineBasicBlock &B) const;
282 
283     /// This function analyzes MBB and returns an instruction with an unoccupied
284     /// slot that branches to Dst.
285     std::pair<MipsInstrInfo::BranchType, MachineInstr *>
286     getBranch(MachineBasicBlock &MBB, const MachineBasicBlock &Dst) const;
287 
288     /// Examine Pred and see if it is possible to insert an instruction into
289     /// one of its branches delay slot or its end.
290     bool examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ,
291                      RegDefsUses &RegDU, bool &HasMultipleSuccs,
292                      BB2BrMap &BrMap) const;
293 
294     bool terminateSearch(const MachineInstr &Candidate) const;
295 
296     const TargetMachine *TM = nullptr;
297   };
298 
299 } // end anonymous namespace
300 
301 char MipsDelaySlotFiller::ID = 0;
302 
303 static bool hasUnoccupiedSlot(const MachineInstr *MI) {
304   return MI->hasDelaySlot() && !MI->isBundledWithSucc();
305 }
306 
307 INITIALIZE_PASS(MipsDelaySlotFiller, DEBUG_TYPE,
308                 "Fill delay slot for MIPS", false, false)
309 
310 /// This function inserts clones of Filler into predecessor blocks.
311 static void insertDelayFiller(Iter Filler, const BB2BrMap &BrMap) {
312   MachineFunction *MF = Filler->getParent()->getParent();
313 
314   for (BB2BrMap::const_iterator I = BrMap.begin(); I != BrMap.end(); ++I) {
315     if (I->second) {
316       MIBundleBuilder(I->second).append(MF->CloneMachineInstr(&*Filler));
317       ++UsefulSlots;
318     } else {
319       I->first->insert(I->first->end(), MF->CloneMachineInstr(&*Filler));
320     }
321   }
322 }
323 
324 /// This function adds registers Filler defines to MBB's live-in register list.
325 static void addLiveInRegs(Iter Filler, MachineBasicBlock &MBB) {
326   for (unsigned I = 0, E = Filler->getNumOperands(); I != E; ++I) {
327     const MachineOperand &MO = Filler->getOperand(I);
328     unsigned R;
329 
330     if (!MO.isReg() || !MO.isDef() || !(R = MO.getReg()))
331       continue;
332 
333 #ifndef NDEBUG
334     const MachineFunction &MF = *MBB.getParent();
335     assert(MF.getSubtarget().getRegisterInfo()->getAllocatableSet(MF).test(R) &&
336            "Shouldn't move an instruction with unallocatable registers across "
337            "basic block boundaries.");
338 #endif
339 
340     if (!MBB.isLiveIn(R))
341       MBB.addLiveIn(R);
342   }
343 }
344 
345 RegDefsUses::RegDefsUses(const TargetRegisterInfo &TRI)
346     : TRI(TRI), Defs(TRI.getNumRegs(), false), Uses(TRI.getNumRegs(), false) {}
347 
348 void RegDefsUses::init(const MachineInstr &MI) {
349   // Add all register operands which are explicit and non-variadic.
350   update(MI, 0, MI.getDesc().getNumOperands());
351 
352   // If MI is a call, add RA to Defs to prevent users of RA from going into
353   // delay slot.
354   if (MI.isCall())
355     Defs.set(Mips::RA);
356 
357   // Add all implicit register operands of branch instructions except
358   // register AT.
359   if (MI.isBranch()) {
360     update(MI, MI.getDesc().getNumOperands(), MI.getNumOperands());
361     Defs.reset(Mips::AT);
362   }
363 }
364 
365 void RegDefsUses::setCallerSaved(const MachineInstr &MI) {
366   assert(MI.isCall());
367 
368   // Add RA/RA_64 to Defs to prevent users of RA/RA_64 from going into
369   // the delay slot. The reason is that RA/RA_64 must not be changed
370   // in the delay slot so that the callee can return to the caller.
371   if (MI.definesRegister(Mips::RA) || MI.definesRegister(Mips::RA_64)) {
372     Defs.set(Mips::RA);
373     Defs.set(Mips::RA_64);
374   }
375 
376   // If MI is a call, add all caller-saved registers to Defs.
377   BitVector CallerSavedRegs(TRI.getNumRegs(), true);
378 
379   CallerSavedRegs.reset(Mips::ZERO);
380   CallerSavedRegs.reset(Mips::ZERO_64);
381 
382   for (const MCPhysReg *R = TRI.getCalleeSavedRegs(MI.getParent()->getParent());
383        *R; ++R)
384     for (MCRegAliasIterator AI(*R, &TRI, true); AI.isValid(); ++AI)
385       CallerSavedRegs.reset(*AI);
386 
387   Defs |= CallerSavedRegs;
388 }
389 
390 void RegDefsUses::setUnallocatableRegs(const MachineFunction &MF) {
391   BitVector AllocSet = TRI.getAllocatableSet(MF);
392 
393   for (unsigned R : AllocSet.set_bits())
394     for (MCRegAliasIterator AI(R, &TRI, false); AI.isValid(); ++AI)
395       AllocSet.set(*AI);
396 
397   AllocSet.set(Mips::ZERO);
398   AllocSet.set(Mips::ZERO_64);
399 
400   Defs |= AllocSet.flip();
401 }
402 
403 void RegDefsUses::addLiveOut(const MachineBasicBlock &MBB,
404                              const MachineBasicBlock &SuccBB) {
405   for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(),
406        SE = MBB.succ_end(); SI != SE; ++SI)
407     if (*SI != &SuccBB)
408       for (const auto &LI : (*SI)->liveins())
409         Uses.set(LI.PhysReg);
410 }
411 
412 bool RegDefsUses::update(const MachineInstr &MI, unsigned Begin, unsigned End) {
413   BitVector NewDefs(TRI.getNumRegs()), NewUses(TRI.getNumRegs());
414   bool HasHazard = false;
415 
416   for (unsigned I = Begin; I != End; ++I) {
417     const MachineOperand &MO = MI.getOperand(I);
418 
419     if (MO.isReg() && MO.getReg()) {
420       if (checkRegDefsUses(NewDefs, NewUses, MO.getReg(), MO.isDef())) {
421         LLVM_DEBUG(dbgs() << DEBUG_TYPE ": found register hazard for operand "
422                           << I << ": ";
423                    MO.dump());
424         HasHazard = true;
425       }
426     }
427   }
428 
429   Defs |= NewDefs;
430   Uses |= NewUses;
431 
432   return HasHazard;
433 }
434 
435 bool RegDefsUses::checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses,
436                                    unsigned Reg, bool IsDef) const {
437   if (IsDef) {
438     NewDefs.set(Reg);
439     // check whether Reg has already been defined or used.
440     return (isRegInSet(Defs, Reg) || isRegInSet(Uses, Reg));
441   }
442 
443   NewUses.set(Reg);
444   // check whether Reg has already been defined.
445   return isRegInSet(Defs, Reg);
446 }
447 
448 bool RegDefsUses::isRegInSet(const BitVector &RegSet, unsigned Reg) const {
449   // Check Reg and all aliased Registers.
450   for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
451     if (RegSet.test(*AI))
452       return true;
453   return false;
454 }
455 
456 bool InspectMemInstr::hasHazard(const MachineInstr &MI) {
457   if (!MI.mayStore() && !MI.mayLoad())
458     return false;
459 
460   if (ForbidMemInstr)
461     return true;
462 
463   OrigSeenLoad = SeenLoad;
464   OrigSeenStore = SeenStore;
465   SeenLoad |= MI.mayLoad();
466   SeenStore |= MI.mayStore();
467 
468   // If MI is an ordered or volatile memory reference, disallow moving
469   // subsequent loads and stores to delay slot.
470   if (MI.hasOrderedMemoryRef() && (OrigSeenLoad || OrigSeenStore)) {
471     ForbidMemInstr = true;
472     return true;
473   }
474 
475   return hasHazard_(MI);
476 }
477 
478 bool LoadFromStackOrConst::hasHazard_(const MachineInstr &MI) {
479   if (MI.mayStore())
480     return true;
481 
482   if (!MI.hasOneMemOperand() || !(*MI.memoperands_begin())->getPseudoValue())
483     return true;
484 
485   if (const PseudoSourceValue *PSV =
486       (*MI.memoperands_begin())->getPseudoValue()) {
487     if (isa<FixedStackPseudoSourceValue>(PSV))
488       return false;
489     return !PSV->isConstant(nullptr) && !PSV->isStack();
490   }
491 
492   return true;
493 }
494 
495 MemDefsUses::MemDefsUses(const DataLayout &DL, const MachineFrameInfo *MFI_)
496     : InspectMemInstr(false), MFI(MFI_), DL(DL) {}
497 
498 bool MemDefsUses::hasHazard_(const MachineInstr &MI) {
499   bool HasHazard = false;
500 
501   // Check underlying object list.
502   SmallVector<ValueType, 4> Objs;
503   if (getUnderlyingObjects(MI, Objs)) {
504     for (ValueType VT : Objs)
505       HasHazard |= updateDefsUses(VT, MI.mayStore());
506     return HasHazard;
507   }
508 
509   // No underlying objects found.
510   HasHazard = MI.mayStore() && (OrigSeenLoad || OrigSeenStore);
511   HasHazard |= MI.mayLoad() || OrigSeenStore;
512 
513   SeenNoObjLoad |= MI.mayLoad();
514   SeenNoObjStore |= MI.mayStore();
515 
516   return HasHazard;
517 }
518 
519 bool MemDefsUses::updateDefsUses(ValueType V, bool MayStore) {
520   if (MayStore)
521     return !Defs.insert(V).second || Uses.count(V) || SeenNoObjStore ||
522            SeenNoObjLoad;
523 
524   Uses.insert(V);
525   return Defs.count(V) || SeenNoObjStore;
526 }
527 
528 bool MemDefsUses::
529 getUnderlyingObjects(const MachineInstr &MI,
530                      SmallVectorImpl<ValueType> &Objects) const {
531   if (!MI.hasOneMemOperand())
532     return false;
533 
534   auto & MMO = **MI.memoperands_begin();
535 
536   if (const PseudoSourceValue *PSV = MMO.getPseudoValue()) {
537     if (!PSV->isAliased(MFI))
538       return false;
539     Objects.push_back(PSV);
540     return true;
541   }
542 
543   if (const Value *V = MMO.getValue()) {
544     SmallVector<const Value *, 4> Objs;
545     GetUnderlyingObjects(V, Objs, DL);
546 
547     for (const Value *UValue : Objs) {
548       if (!isIdentifiedObject(V))
549         return false;
550 
551       Objects.push_back(UValue);
552     }
553     return true;
554   }
555 
556   return false;
557 }
558 
559 // Replace Branch with the compact branch instruction.
560 Iter MipsDelaySlotFiller::replaceWithCompactBranch(MachineBasicBlock &MBB,
561                                                    Iter Branch,
562                                                    const DebugLoc &DL) {
563   const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>();
564   const MipsInstrInfo *TII = STI.getInstrInfo();
565 
566   unsigned NewOpcode = TII->getEquivalentCompactForm(Branch);
567   Branch = TII->genInstrWithNewOpc(NewOpcode, Branch);
568 
569   std::next(Branch)->eraseFromParent();
570   return Branch;
571 }
572 
573 // For given opcode returns opcode of corresponding instruction with short
574 // delay slot.
575 // For the pseudo TAILCALL*_MM instructions return the short delay slot
576 // form. Unfortunately, TAILCALL<->b16 is denied as b16 has a limited range
577 // that is too short to make use of for tail calls.
578 static int getEquivalentCallShort(int Opcode) {
579   switch (Opcode) {
580   case Mips::BGEZAL:
581     return Mips::BGEZALS_MM;
582   case Mips::BLTZAL:
583     return Mips::BLTZALS_MM;
584   case Mips::JAL:
585   case Mips::JAL_MM:
586     return Mips::JALS_MM;
587   case Mips::JALR:
588     return Mips::JALRS_MM;
589   case Mips::JALR16_MM:
590     return Mips::JALRS16_MM;
591   case Mips::TAILCALL_MM:
592     llvm_unreachable("Attempting to shorten the TAILCALL_MM pseudo!");
593   case Mips::TAILCALLREG:
594     return Mips::JR16_MM;
595   default:
596     llvm_unreachable("Unexpected call instruction for microMIPS.");
597   }
598 }
599 
600 /// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
601 /// We assume there is only one delay slot per delayed instruction.
602 bool MipsDelaySlotFiller::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
603   bool Changed = false;
604   const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>();
605   bool InMicroMipsMode = STI.inMicroMipsMode();
606   const MipsInstrInfo *TII = STI.getInstrInfo();
607 
608   for (Iter I = MBB.begin(); I != MBB.end(); ++I) {
609     if (!hasUnoccupiedSlot(&*I))
610       continue;
611 
612     // Delay slot filling is disabled at -O0, or in microMIPS32R6.
613     if (!DisableDelaySlotFiller && (TM->getOptLevel() != CodeGenOpt::None) &&
614         !(InMicroMipsMode && STI.hasMips32r6())) {
615 
616       bool Filled = false;
617 
618       if (MipsCompactBranchPolicy.getValue() != CB_Always ||
619            !TII->getEquivalentCompactForm(I)) {
620         if (searchBackward(MBB, *I)) {
621           LLVM_DEBUG(dbgs() << DEBUG_TYPE ": found instruction for delay slot"
622                                           " in backwards search.\n");
623           Filled = true;
624         } else if (I->isTerminator()) {
625           if (searchSuccBBs(MBB, I)) {
626             Filled = true;
627             LLVM_DEBUG(dbgs() << DEBUG_TYPE ": found instruction for delay slot"
628                                             " in successor BB search.\n");
629           }
630         } else if (searchForward(MBB, I)) {
631           LLVM_DEBUG(dbgs() << DEBUG_TYPE ": found instruction for delay slot"
632                                           " in forwards search.\n");
633           Filled = true;
634         }
635       }
636 
637       if (Filled) {
638         // Get instruction with delay slot.
639         MachineBasicBlock::instr_iterator DSI = I.getInstrIterator();
640 
641         if (InMicroMipsMode && TII->getInstSizeInBytes(*std::next(DSI)) == 2 &&
642             DSI->isCall()) {
643           // If instruction in delay slot is 16b change opcode to
644           // corresponding instruction with short delay slot.
645 
646           // TODO: Implement an instruction mapping table of 16bit opcodes to
647           // 32bit opcodes so that an instruction can be expanded. This would
648           // save 16 bits as a TAILCALL_MM pseudo requires a fullsized nop.
649           // TODO: Permit b16 when branching backwards to the same function
650           // if it is in range.
651           DSI->setDesc(TII->get(getEquivalentCallShort(DSI->getOpcode())));
652         }
653         ++FilledSlots;
654         Changed = true;
655         continue;
656       }
657     }
658 
659     // For microMIPS if instruction is BEQ or BNE with one ZERO register, then
660     // instead of adding NOP replace this instruction with the corresponding
661     // compact branch instruction, i.e. BEQZC or BNEZC. Additionally
662     // PseudoReturn and PseudoIndirectBranch are expanded to JR_MM, so they can
663     // be replaced with JRC16_MM.
664 
665     // For MIPSR6 attempt to produce the corresponding compact (no delay slot)
666     // form of the CTI. For indirect jumps this will not require inserting a
667     // NOP and for branches will hopefully avoid requiring a NOP.
668     if ((InMicroMipsMode ||
669          (STI.hasMips32r6() && MipsCompactBranchPolicy != CB_Never)) &&
670         TII->getEquivalentCompactForm(I)) {
671       I = replaceWithCompactBranch(MBB, I, I->getDebugLoc());
672       Changed = true;
673       continue;
674     }
675 
676     // Bundle the NOP to the instruction with the delay slot.
677     LLVM_DEBUG(dbgs() << DEBUG_TYPE << ": could not fill delay slot for ";
678                I->dump());
679     BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
680     MIBundleBuilder(MBB, I, std::next(I, 2));
681     ++FilledSlots;
682     Changed = true;
683   }
684 
685   return Changed;
686 }
687 
688 template <typename IterTy>
689 bool MipsDelaySlotFiller::searchRange(MachineBasicBlock &MBB, IterTy Begin,
690                                       IterTy End, RegDefsUses &RegDU,
691                                       InspectMemInstr &IM, Iter Slot,
692                                       IterTy &Filler) const {
693   for (IterTy I = Begin; I != End;) {
694     IterTy CurrI = I;
695     ++I;
696     LLVM_DEBUG(dbgs() << DEBUG_TYPE ": checking instruction: "; CurrI->dump());
697     // skip debug value
698     if (CurrI->isDebugInstr()) {
699       LLVM_DEBUG(dbgs() << DEBUG_TYPE ": ignoring debug instruction: ";
700                  CurrI->dump());
701       continue;
702     }
703 
704     if (CurrI->isBundle()) {
705       LLVM_DEBUG(dbgs() << DEBUG_TYPE ": ignoring BUNDLE instruction: ";
706                  CurrI->dump());
707       // However, we still need to update the register def-use information.
708       RegDU.update(*CurrI, 0, CurrI->getNumOperands());
709       continue;
710     }
711 
712     if (terminateSearch(*CurrI)) {
713       LLVM_DEBUG(dbgs() << DEBUG_TYPE ": should terminate search: ";
714                  CurrI->dump());
715       break;
716     }
717 
718     assert((!CurrI->isCall() && !CurrI->isReturn() && !CurrI->isBranch()) &&
719            "Cannot put calls, returns or branches in delay slot.");
720 
721     if (CurrI->isKill()) {
722       CurrI->eraseFromParent();
723       continue;
724     }
725 
726     if (delayHasHazard(*CurrI, RegDU, IM))
727       continue;
728 
729     const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>();
730     if (STI.isTargetNaCl()) {
731       // In NaCl, instructions that must be masked are forbidden in delay slots.
732       // We only check for loads, stores and SP changes.  Calls, returns and
733       // branches are not checked because non-NaCl targets never put them in
734       // delay slots.
735       unsigned AddrIdx;
736       if ((isBasePlusOffsetMemoryAccess(CurrI->getOpcode(), &AddrIdx) &&
737            baseRegNeedsLoadStoreMask(CurrI->getOperand(AddrIdx).getReg())) ||
738           CurrI->modifiesRegister(Mips::SP, STI.getRegisterInfo()))
739         continue;
740     }
741 
742     bool InMicroMipsMode = STI.inMicroMipsMode();
743     const MipsInstrInfo *TII = STI.getInstrInfo();
744     unsigned Opcode = (*Slot).getOpcode();
745     // This is complicated by the tail call optimization. For non-PIC code
746     // there is only a 32bit sized unconditional branch which can be assumed
747     // to be able to reach the target. b16 only has a range of +/- 1 KB.
748     // It's entirely possible that the target function is reachable with b16
749     // but we don't have enough information to make that decision.
750      if (InMicroMipsMode && TII->getInstSizeInBytes(*CurrI) == 2 &&
751         (Opcode == Mips::JR || Opcode == Mips::PseudoIndirectBranch ||
752          Opcode == Mips::PseudoIndirectBranch_MM ||
753          Opcode == Mips::PseudoReturn || Opcode == Mips::TAILCALL))
754       continue;
755      // Instructions LWP/SWP and MOVEP should not be in a delay slot as that
756      // results in unpredictable behaviour
757      if (InMicroMipsMode && (Opcode == Mips::LWP_MM || Opcode == Mips::SWP_MM ||
758                              Opcode == Mips::MOVEP_MM))
759        continue;
760 
761     Filler = CurrI;
762     LLVM_DEBUG(dbgs() << DEBUG_TYPE ": found instruction for delay slot: ";
763                CurrI->dump());
764 
765     return true;
766   }
767 
768   return false;
769 }
770 
771 bool MipsDelaySlotFiller::searchBackward(MachineBasicBlock &MBB,
772                                          MachineInstr &Slot) const {
773   if (DisableBackwardSearch)
774     return false;
775 
776   auto *Fn = MBB.getParent();
777   RegDefsUses RegDU(*Fn->getSubtarget().getRegisterInfo());
778   MemDefsUses MemDU(Fn->getDataLayout(), &Fn->getFrameInfo());
779   ReverseIter Filler;
780 
781   RegDU.init(Slot);
782 
783   MachineBasicBlock::iterator SlotI = Slot;
784   if (!searchRange(MBB, ++SlotI.getReverse(), MBB.rend(), RegDU, MemDU, Slot,
785                    Filler)) {
786     LLVM_DEBUG(dbgs() << DEBUG_TYPE ": could not find instruction for delay "
787                                     "slot using backwards search.\n");
788     return false;
789   }
790 
791   MBB.splice(std::next(SlotI), &MBB, Filler.getReverse());
792   MIBundleBuilder(MBB, SlotI, std::next(SlotI, 2));
793   ++UsefulSlots;
794   return true;
795 }
796 
797 bool MipsDelaySlotFiller::searchForward(MachineBasicBlock &MBB,
798                                         Iter Slot) const {
799   // Can handle only calls.
800   if (DisableForwardSearch || !Slot->isCall())
801     return false;
802 
803   RegDefsUses RegDU(*MBB.getParent()->getSubtarget().getRegisterInfo());
804   NoMemInstr NM;
805   Iter Filler;
806 
807   RegDU.setCallerSaved(*Slot);
808 
809   if (!searchRange(MBB, std::next(Slot), MBB.end(), RegDU, NM, Slot, Filler)) {
810     LLVM_DEBUG(dbgs() << DEBUG_TYPE ": could not find instruction for delay "
811                                     "slot using forwards search.\n");
812     return false;
813   }
814 
815   MBB.splice(std::next(Slot), &MBB, Filler);
816   MIBundleBuilder(MBB, Slot, std::next(Slot, 2));
817   ++UsefulSlots;
818   return true;
819 }
820 
821 bool MipsDelaySlotFiller::searchSuccBBs(MachineBasicBlock &MBB,
822                                         Iter Slot) const {
823   if (DisableSuccBBSearch)
824     return false;
825 
826   MachineBasicBlock *SuccBB = selectSuccBB(MBB);
827 
828   if (!SuccBB)
829     return false;
830 
831   RegDefsUses RegDU(*MBB.getParent()->getSubtarget().getRegisterInfo());
832   bool HasMultipleSuccs = false;
833   BB2BrMap BrMap;
834   std::unique_ptr<InspectMemInstr> IM;
835   Iter Filler;
836   auto *Fn = MBB.getParent();
837 
838   // Iterate over SuccBB's predecessor list.
839   for (MachineBasicBlock::pred_iterator PI = SuccBB->pred_begin(),
840        PE = SuccBB->pred_end(); PI != PE; ++PI)
841     if (!examinePred(**PI, *SuccBB, RegDU, HasMultipleSuccs, BrMap))
842       return false;
843 
844   // Do not allow moving instructions which have unallocatable register operands
845   // across basic block boundaries.
846   RegDU.setUnallocatableRegs(*Fn);
847 
848   // Only allow moving loads from stack or constants if any of the SuccBB's
849   // predecessors have multiple successors.
850   if (HasMultipleSuccs) {
851     IM.reset(new LoadFromStackOrConst());
852   } else {
853     const MachineFrameInfo &MFI = Fn->getFrameInfo();
854     IM.reset(new MemDefsUses(Fn->getDataLayout(), &MFI));
855   }
856 
857   if (!searchRange(MBB, SuccBB->begin(), SuccBB->end(), RegDU, *IM, Slot,
858                    Filler))
859     return false;
860 
861   insertDelayFiller(Filler, BrMap);
862   addLiveInRegs(Filler, *SuccBB);
863   Filler->eraseFromParent();
864 
865   return true;
866 }
867 
868 MachineBasicBlock *
869 MipsDelaySlotFiller::selectSuccBB(MachineBasicBlock &B) const {
870   if (B.succ_empty())
871     return nullptr;
872 
873   // Select the successor with the larget edge weight.
874   auto &Prob = getAnalysis<MachineBranchProbabilityInfo>();
875   MachineBasicBlock *S = *std::max_element(
876       B.succ_begin(), B.succ_end(),
877       [&](const MachineBasicBlock *Dst0, const MachineBasicBlock *Dst1) {
878         return Prob.getEdgeProbability(&B, Dst0) <
879                Prob.getEdgeProbability(&B, Dst1);
880       });
881   return S->isEHPad() ? nullptr : S;
882 }
883 
884 std::pair<MipsInstrInfo::BranchType, MachineInstr *>
885 MipsDelaySlotFiller::getBranch(MachineBasicBlock &MBB,
886                                const MachineBasicBlock &Dst) const {
887   const MipsInstrInfo *TII =
888       MBB.getParent()->getSubtarget<MipsSubtarget>().getInstrInfo();
889   MachineBasicBlock *TrueBB = nullptr, *FalseBB = nullptr;
890   SmallVector<MachineInstr*, 2> BranchInstrs;
891   SmallVector<MachineOperand, 2> Cond;
892 
893   MipsInstrInfo::BranchType R =
894       TII->analyzeBranch(MBB, TrueBB, FalseBB, Cond, false, BranchInstrs);
895 
896   if ((R == MipsInstrInfo::BT_None) || (R == MipsInstrInfo::BT_NoBranch))
897     return std::make_pair(R, nullptr);
898 
899   if (R != MipsInstrInfo::BT_CondUncond) {
900     if (!hasUnoccupiedSlot(BranchInstrs[0]))
901       return std::make_pair(MipsInstrInfo::BT_None, nullptr);
902 
903     assert(((R != MipsInstrInfo::BT_Uncond) || (TrueBB == &Dst)));
904 
905     return std::make_pair(R, BranchInstrs[0]);
906   }
907 
908   assert((TrueBB == &Dst) || (FalseBB == &Dst));
909 
910   // Examine the conditional branch. See if its slot is occupied.
911   if (hasUnoccupiedSlot(BranchInstrs[0]))
912     return std::make_pair(MipsInstrInfo::BT_Cond, BranchInstrs[0]);
913 
914   // If that fails, try the unconditional branch.
915   if (hasUnoccupiedSlot(BranchInstrs[1]) && (FalseBB == &Dst))
916     return std::make_pair(MipsInstrInfo::BT_Uncond, BranchInstrs[1]);
917 
918   return std::make_pair(MipsInstrInfo::BT_None, nullptr);
919 }
920 
921 bool MipsDelaySlotFiller::examinePred(MachineBasicBlock &Pred,
922                                       const MachineBasicBlock &Succ,
923                                       RegDefsUses &RegDU,
924                                       bool &HasMultipleSuccs,
925                                       BB2BrMap &BrMap) const {
926   std::pair<MipsInstrInfo::BranchType, MachineInstr *> P =
927       getBranch(Pred, Succ);
928 
929   // Return if either getBranch wasn't able to analyze the branches or there
930   // were no branches with unoccupied slots.
931   if (P.first == MipsInstrInfo::BT_None)
932     return false;
933 
934   if ((P.first != MipsInstrInfo::BT_Uncond) &&
935       (P.first != MipsInstrInfo::BT_NoBranch)) {
936     HasMultipleSuccs = true;
937     RegDU.addLiveOut(Pred, Succ);
938   }
939 
940   BrMap[&Pred] = P.second;
941   return true;
942 }
943 
944 bool MipsDelaySlotFiller::delayHasHazard(const MachineInstr &Candidate,
945                                          RegDefsUses &RegDU,
946                                          InspectMemInstr &IM) const {
947   assert(!Candidate.isKill() &&
948          "KILL instructions should have been eliminated at this point.");
949 
950   bool HasHazard = Candidate.isImplicitDef();
951 
952   HasHazard |= IM.hasHazard(Candidate);
953   HasHazard |= RegDU.update(Candidate, 0, Candidate.getNumOperands());
954 
955   return HasHazard;
956 }
957 
958 bool MipsDelaySlotFiller::terminateSearch(const MachineInstr &Candidate) const {
959   return (Candidate.isTerminator() || Candidate.isCall() ||
960           Candidate.isPosition() || Candidate.isInlineAsm() ||
961           Candidate.hasUnmodeledSideEffects());
962 }
963 
964 /// createMipsDelaySlotFillerPass - Returns a pass that fills in delay
965 /// slots in Mips MachineFunctions
966 FunctionPass *llvm::createMipsDelaySlotFillerPass() {
967   return new MipsDelaySlotFiller();
968 }
969