1//===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// This describes the calling conventions for Mips architecture. 9//===----------------------------------------------------------------------===// 10 11/// CCIfSubtarget - Match if the current subtarget has a feature F. 12class CCIfSubtarget<string F, CCAction A, string Invert = ""> 13 : CCIf<!strconcat(Invert, 14 "static_cast<const MipsSubtarget&>" 15 "(State.getMachineFunction().getSubtarget()).", 16 F), 17 A>; 18 19// The inverse of CCIfSubtarget 20class CCIfSubtargetNot<string F, CCAction A> : CCIfSubtarget<F, A, "!">; 21 22/// Match if the original argument (before lowering) was a float. 23/// For example, this is true for i32's that were lowered from soft-float. 24class CCIfOrigArgWasNotFloat<CCAction A> 25 : CCIf<"!static_cast<MipsCCState *>(&State)->WasOriginalArgFloat(ValNo)", 26 A>; 27 28/// Match if the original argument (before lowering) was a 128-bit float (i.e. 29/// long double). 30class CCIfOrigArgWasF128<CCAction A> 31 : CCIf<"static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)", A>; 32 33/// Match if this specific argument is a vararg. 34/// This is slightly different fro CCIfIsVarArg which matches if any argument is 35/// a vararg. 36class CCIfArgIsVarArg<CCAction A> 37 : CCIf<"!static_cast<MipsCCState *>(&State)->IsCallOperandFixed(ValNo)", A>; 38 39/// Match if the return was a floating point vector. 40class CCIfOrigArgWasNotVectorFloat<CCAction A> 41 : CCIf<"!static_cast<MipsCCState *>(&State)" 42 "->WasOriginalRetVectorFloat(ValNo)", A>; 43 44/// Match if the special calling conv is the specified value. 45class CCIfSpecialCallingConv<string CC, CCAction A> 46 : CCIf<"static_cast<MipsCCState *>(&State)->getSpecialCallingConv() == " 47 "MipsCCState::" # CC, A>; 48 49// For soft-float, f128 values are returned in A0_64 rather than V1_64. 50def RetCC_F128SoftFloat : CallingConv<[ 51 CCAssignToReg<[V0_64, A0_64]> 52]>; 53 54// For hard-float, f128 values are returned as a pair of f64's rather than a 55// pair of i64's. 56def RetCC_F128HardFloat : CallingConv<[ 57 CCBitConvertToType<f64>, 58 59 // Contrary to the ABI documentation, a struct containing a long double is 60 // returned in $f0, and $f1 instead of the usual $f0, and $f2. This is to 61 // match the de facto ABI as implemented by GCC. 62 CCIfInReg<CCAssignToReg<[D0_64, D1_64]>>, 63 64 CCAssignToReg<[D0_64, D2_64]> 65]>; 66 67// Handle F128 specially since we can't identify the original type during the 68// tablegen-erated code. 69def RetCC_F128 : CallingConv<[ 70 CCIfSubtarget<"useSoftFloat()", 71 CCIfType<[i64], CCDelegateTo<RetCC_F128SoftFloat>>>, 72 CCIfSubtargetNot<"useSoftFloat()", 73 CCIfType<[i64], CCDelegateTo<RetCC_F128HardFloat>>> 74]>; 75 76//===----------------------------------------------------------------------===// 77// Mips O32 Calling Convention 78//===----------------------------------------------------------------------===// 79 80def CC_MipsO32 : CallingConv<[ 81 // Promote i8/i16 arguments to i32. 82 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 83 84 // Integer values get stored in stack slots that are 4 bytes in 85 // size and 4-byte aligned. 86 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 87 88 // Integer values get stored in stack slots that are 8 bytes in 89 // size and 8-byte aligned. 90 CCIfType<[f64], CCAssignToStack<8, 8>> 91]>; 92 93// Only the return rules are defined here for O32. The rules for argument 94// passing are defined in MipsISelLowering.cpp. 95def RetCC_MipsO32 : CallingConv<[ 96 // Promote i1/i8/i16 return values to i32. 97 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 98 99 // i32 are returned in registers V0, V1, A0, A1, unless the original return 100 // type was a vector of floats. 101 CCIfOrigArgWasNotVectorFloat<CCIfType<[i32], 102 CCAssignToReg<[V0, V1, A0, A1]>>>, 103 104 // f32 are returned in registers F0, F2 105 CCIfType<[f32], CCAssignToReg<[F0, F2]>>, 106 107 // f64 arguments are returned in D0_64 and D2_64 in FP64bit mode or 108 // in D0 and D1 in FP32bit mode. 109 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D2_64]>>>, 110 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()", CCAssignToReg<[D0, D1]>>> 111]>; 112 113def CC_MipsO32_FP32 : CustomCallingConv; 114def CC_MipsO32_FP64 : CustomCallingConv; 115 116def CC_MipsO32_FP : CallingConv<[ 117 CCIfSubtargetNot<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP32>>, 118 CCIfSubtarget<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP64>> 119]>; 120 121//===----------------------------------------------------------------------===// 122// Mips N32/64 Calling Convention 123//===----------------------------------------------------------------------===// 124 125def CC_MipsN_SoftFloat : CallingConv<[ 126 CCAssignToRegWithShadow<[A0, A1, A2, A3, 127 T0, T1, T2, T3], 128 [D12_64, D13_64, D14_64, D15_64, 129 D16_64, D17_64, D18_64, D19_64]>, 130 CCAssignToStack<4, 8> 131]>; 132 133def CC_MipsN : CallingConv<[ 134 CCIfType<[i8, i16, i32, i64], 135 CCIfSubtargetNot<"isLittle()", 136 CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>, 137 138 // All integers (except soft-float integers) are promoted to 64-bit. 139 CCIfType<[i8, i16, i32], CCIfOrigArgWasNotFloat<CCPromoteToType<i64>>>, 140 141 // The only i32's we have left are soft-float arguments. 142 CCIfSubtarget<"useSoftFloat()", CCIfType<[i32], CCDelegateTo<CC_MipsN_SoftFloat>>>, 143 144 // Integer arguments are passed in integer registers. 145 CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64, 146 T0_64, T1_64, T2_64, T3_64], 147 [D12_64, D13_64, D14_64, D15_64, 148 D16_64, D17_64, D18_64, D19_64]>>, 149 150 // f32 arguments are passed in single precision FP registers. 151 CCIfType<[f32], CCAssignToRegWithShadow<[F12, F13, F14, F15, 152 F16, F17, F18, F19], 153 [A0_64, A1_64, A2_64, A3_64, 154 T0_64, T1_64, T2_64, T3_64]>>, 155 156 // f64 arguments are passed in double precision FP registers. 157 CCIfType<[f64], CCAssignToRegWithShadow<[D12_64, D13_64, D14_64, D15_64, 158 D16_64, D17_64, D18_64, D19_64], 159 [A0_64, A1_64, A2_64, A3_64, 160 T0_64, T1_64, T2_64, T3_64]>>, 161 162 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned. 163 CCIfType<[f32], CCAssignToStack<4, 8>>, 164 CCIfType<[i64, f64], CCAssignToStack<8, 8>> 165]>; 166 167// N32/64 variable arguments. 168// All arguments are passed in integer registers. 169def CC_MipsN_VarArg : CallingConv<[ 170 CCIfType<[i8, i16, i32, i64], 171 CCIfSubtargetNot<"isLittle()", 172 CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>, 173 174 // All integers are promoted to 64-bit. 175 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 176 177 CCIfType<[f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>, 178 179 CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, 180 T0_64, T1_64, T2_64, T3_64]>>, 181 182 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned. 183 CCIfType<[f32], CCAssignToStack<4, 8>>, 184 CCIfType<[i64, f64], CCAssignToStack<8, 8>> 185]>; 186 187def RetCC_MipsN : CallingConv<[ 188 // f128 needs to be handled similarly to f32 and f64. However, f128 is not 189 // legal and is lowered to i128 which is further lowered to a pair of i64's. 190 // This presents us with a problem for the calling convention since hard-float 191 // still needs to pass them in FPU registers, and soft-float needs to use $v0, 192 // and $a0 instead of the usual $v0, and $v1. We therefore resort to a 193 // pre-analyze (see PreAnalyzeReturnForF128()) step to pass information on 194 // whether the result was originally an f128 into the tablegen-erated code. 195 // 196 // f128 should only occur for the N64 ABI where long double is 128-bit. On 197 // N32, long double is equivalent to double. 198 CCIfType<[i64], CCIfOrigArgWasF128<CCDelegateTo<RetCC_F128>>>, 199 200 // Aggregate returns are positioned at the lowest address in the slot for 201 // both little and big-endian targets. When passing in registers, this 202 // requires that big-endian targets shift the value into the upper bits. 203 CCIfSubtarget<"isLittle()", 204 CCIfType<[i8, i16, i32, i64], CCIfInReg<CCPromoteToType<i64>>>>, 205 CCIfSubtargetNot<"isLittle()", 206 CCIfType<[i8, i16, i32, i64], 207 CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>, 208 209 // i64 are returned in registers V0_64, V1_64 210 CCIfType<[i64], CCAssignToReg<[V0_64, V1_64]>>, 211 212 // f32 are returned in registers F0, F2 213 CCIfType<[f32], CCAssignToReg<[F0, F2]>>, 214 215 // f64 are returned in registers D0, D2 216 CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>> 217]>; 218 219//===----------------------------------------------------------------------===// 220// Mips FastCC Calling Convention 221//===----------------------------------------------------------------------===// 222def CC_MipsO32_FastCC : CallingConv<[ 223 // f64 arguments are passed in double-precision floating pointer registers. 224 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()", 225 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, 226 D7, D8, D9]>>>, 227 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"useOddSPReg()", 228 CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, 229 D4_64, D5_64, D6_64, D7_64, 230 D8_64, D9_64, D10_64, D11_64, 231 D12_64, D13_64, D14_64, D15_64, 232 D16_64, D17_64, D18_64, 233 D19_64]>>>>, 234 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"noOddSPReg()", 235 CCAssignToReg<[D0_64, D2_64, D4_64, D6_64, 236 D8_64, D10_64, D12_64, D14_64, 237 D16_64, D18_64]>>>>, 238 239 // Stack parameter slots for f64 are 64-bit doublewords and 8-byte aligned. 240 CCIfType<[f64], CCAssignToStack<8, 8>> 241]>; 242 243def CC_MipsN_FastCC : CallingConv<[ 244 // Integer arguments are passed in integer registers. 245 CCIfType<[i64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, T0_64, T1_64, 246 T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, 247 T8_64, V1_64]>>, 248 249 // f64 arguments are passed in double-precision floating pointer registers. 250 CCIfType<[f64], CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, D4_64, D5_64, 251 D6_64, D7_64, D8_64, D9_64, D10_64, D11_64, 252 D12_64, D13_64, D14_64, D15_64, D16_64, D17_64, 253 D18_64, D19_64]>>, 254 255 // Stack parameter slots for i64 and f64 are 64-bit doublewords and 256 // 8-byte aligned. 257 CCIfType<[i64, f64], CCAssignToStack<8, 8>> 258]>; 259 260def CC_Mips_FastCC : CallingConv<[ 261 // Handles byval parameters. 262 CCIfByVal<CCPassByVal<4, 4>>, 263 264 // Promote i8/i16 arguments to i32. 265 CCIfType<[i8, i16], CCPromoteToType<i32>>, 266 267 // Integer arguments are passed in integer registers. All scratch registers, 268 // except for AT, V0 and T9, are available to be used as argument registers. 269 CCIfType<[i32], CCIfSubtargetNot<"isTargetNaCl()", 270 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, V1]>>>, 271 272 // In NaCl, T6, T7 and T8 are reserved and not available as argument 273 // registers for fastcc. T6 contains the mask for sandboxing control flow 274 // (indirect jumps and calls). T7 contains the mask for sandboxing memory 275 // accesses (loads and stores). T8 contains the thread pointer. 276 CCIfType<[i32], CCIfSubtarget<"isTargetNaCl()", 277 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, V1]>>>, 278 279 // f32 arguments are passed in single-precision floating pointer registers. 280 CCIfType<[f32], CCIfSubtarget<"useOddSPReg()", 281 CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, 282 F14, F15, F16, F17, F18, F19]>>>, 283 284 // Don't use odd numbered single-precision registers for -mno-odd-spreg. 285 CCIfType<[f32], CCIfSubtarget<"noOddSPReg()", 286 CCAssignToReg<[F0, F2, F4, F6, F8, F10, F12, F14, F16, F18]>>>, 287 288 // Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned. 289 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 290 291 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FastCC>>, 292 CCDelegateTo<CC_MipsN_FastCC> 293]>; 294 295//===----------------------------------------------------------------------===// 296// Mips Calling Convention Dispatch 297//===----------------------------------------------------------------------===// 298 299def RetCC_Mips : CallingConv<[ 300 CCIfSubtarget<"isABI_N32()", CCDelegateTo<RetCC_MipsN>>, 301 CCIfSubtarget<"isABI_N64()", CCDelegateTo<RetCC_MipsN>>, 302 CCDelegateTo<RetCC_MipsO32> 303]>; 304 305def CC_Mips_ByVal : CallingConv<[ 306 CCIfSubtarget<"isABI_O32()", CCIfByVal<CCPassByVal<4, 4>>>, 307 CCIfByVal<CCPassByVal<8, 8>> 308]>; 309 310def CC_Mips16RetHelper : CallingConv<[ 311 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>, 312 313 // Integer arguments are passed in integer registers. 314 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>> 315]>; 316 317def CC_Mips_FixedArg : CallingConv<[ 318 // Mips16 needs special handling on some functions. 319 CCIf<"State.getCallingConv() != CallingConv::Fast", 320 CCIfSpecialCallingConv<"Mips16RetHelperConv", 321 CCDelegateTo<CC_Mips16RetHelper>>>, 322 323 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>, 324 325 // f128 needs to be handled similarly to f32 and f64 on hard-float. However, 326 // f128 is not legal and is lowered to i128 which is further lowered to a pair 327 // of i64's. 328 // This presents us with a problem for the calling convention since hard-float 329 // still needs to pass them in FPU registers. We therefore resort to a 330 // pre-analyze (see PreAnalyzeFormalArgsForF128()) step to pass information on 331 // whether the argument was originally an f128 into the tablegen-erated code. 332 // 333 // f128 should only occur for the N64 ABI where long double is 128-bit. On 334 // N32, long double is equivalent to double. 335 CCIfType<[i64], 336 CCIfSubtargetNot<"useSoftFloat()", 337 CCIfOrigArgWasF128<CCBitConvertToType<f64>>>>, 338 339 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_Mips_FastCC>>, 340 341 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>, 342 CCDelegateTo<CC_MipsN> 343]>; 344 345def CC_Mips_VarArg : CallingConv<[ 346 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>, 347 348 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>, 349 CCDelegateTo<CC_MipsN_VarArg> 350]>; 351 352def CC_Mips : CallingConv<[ 353 CCIfVarArg<CCIfArgIsVarArg<CCDelegateTo<CC_Mips_VarArg>>>, 354 CCDelegateTo<CC_Mips_FixedArg> 355]>; 356 357//===----------------------------------------------------------------------===// 358// Callee-saved register lists. 359//===----------------------------------------------------------------------===// 360 361def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP, 362 (sequence "S%u", 7, 0))>; 363 364def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP, 365 (sequence "S%u", 7, 0))> { 366 let OtherPreserved = (add (decimate (sequence "F%u", 30, 20), 2)); 367} 368 369def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP, 370 (sequence "S%u", 7, 0))>; 371 372def CSR_O32_FP64 : 373 CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP, 374 (sequence "S%u", 7, 0))>; 375 376def CSR_N32 : CalleeSavedRegs<(add D20_64, D22_64, D24_64, D26_64, D28_64, 377 D30_64, RA_64, FP_64, GP_64, 378 (sequence "S%u_64", 7, 0))>; 379 380def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64, 381 GP_64, (sequence "S%u_64", 7, 0))>; 382 383def CSR_Mips16RetHelper : 384 CalleeSavedRegs<(add V0, V1, FP, 385 (sequence "A%u", 3, 0), (sequence "S%u", 7, 0), 386 (sequence "D%u", 15, 10))>; 387 388def CSR_Interrupt_32R6 : CalleeSavedRegs<(add (sequence "A%u", 3, 0), 389 (sequence "S%u", 7, 0), 390 (sequence "V%u", 1, 0), 391 (sequence "T%u", 9, 0), 392 RA, FP, GP, AT)>; 393 394def CSR_Interrupt_32 : CalleeSavedRegs<(add (sequence "A%u", 3, 0), 395 (sequence "S%u", 7, 0), 396 (sequence "V%u", 1, 0), 397 (sequence "T%u", 9, 0), 398 RA, FP, GP, AT, LO0, HI0)>; 399 400def CSR_Interrupt_64R6 : CalleeSavedRegs<(add (sequence "A%u_64", 3, 0), 401 (sequence "V%u_64", 1, 0), 402 (sequence "S%u_64", 7, 0), 403 (sequence "T%u_64", 9, 0), 404 RA_64, FP_64, GP_64, AT_64)>; 405 406def CSR_Interrupt_64 : CalleeSavedRegs<(add (sequence "A%u_64", 3, 0), 407 (sequence "S%u_64", 7, 0), 408 (sequence "T%u_64", 9, 0), 409 (sequence "V%u_64", 1, 0), 410 RA_64, FP_64, GP_64, AT_64, 411 LO0_64, HI0_64)>; 412