xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MipsCallLowering.cpp (revision acb1f1269c6f4ff89a0d28ba742f6687e9ef779d) 
1 //===- MipsCallLowering.cpp -------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MipsCallLowering.h"
16 #include "MipsCCState.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/CodeGen/Analysis.h"
20 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
21 
22 using namespace llvm;
23 
24 MipsCallLowering::MipsCallLowering(const MipsTargetLowering &TLI)
25     : CallLowering(&TLI) {}
26 
27 bool MipsCallLowering::MipsHandler::assign(Register VReg, const CCValAssign &VA,
28                                            const EVT &VT) {
29   if (VA.isRegLoc()) {
30     assignValueToReg(VReg, VA, VT);
31   } else if (VA.isMemLoc()) {
32     assignValueToAddress(VReg, VA);
33   } else {
34     return false;
35   }
36   return true;
37 }
38 
39 bool MipsCallLowering::MipsHandler::assignVRegs(ArrayRef<Register> VRegs,
40                                                 ArrayRef<CCValAssign> ArgLocs,
41                                                 unsigned ArgLocsStartIndex,
42                                                 const EVT &VT) {
43   for (unsigned i = 0; i < VRegs.size(); ++i)
44     if (!assign(VRegs[i], ArgLocs[ArgLocsStartIndex + i], VT))
45       return false;
46   return true;
47 }
48 
49 void MipsCallLowering::MipsHandler::setLeastSignificantFirst(
50     SmallVectorImpl<Register> &VRegs) {
51   if (!MIRBuilder.getMF().getDataLayout().isLittleEndian())
52     std::reverse(VRegs.begin(), VRegs.end());
53 }
54 
55 bool MipsCallLowering::MipsHandler::handle(
56     ArrayRef<CCValAssign> ArgLocs, ArrayRef<CallLowering::ArgInfo> Args) {
57   SmallVector<Register, 4> VRegs;
58   unsigned SplitLength;
59   const Function &F = MIRBuilder.getMF().getFunction();
60   const DataLayout &DL = F.getParent()->getDataLayout();
61   const MipsTargetLowering &TLI = *static_cast<const MipsTargetLowering *>(
62       MIRBuilder.getMF().getSubtarget().getTargetLowering());
63 
64   for (unsigned ArgsIndex = 0, ArgLocsIndex = 0; ArgsIndex < Args.size();
65        ++ArgsIndex, ArgLocsIndex += SplitLength) {
66     EVT VT = TLI.getValueType(DL, Args[ArgsIndex].Ty);
67     SplitLength = TLI.getNumRegistersForCallingConv(F.getContext(),
68                                                     F.getCallingConv(), VT);
69     assert(Args[ArgsIndex].Regs.size() == 1 && "Can't handle multple regs yet");
70 
71     if (SplitLength > 1) {
72       VRegs.clear();
73       MVT RegisterVT = TLI.getRegisterTypeForCallingConv(
74           F.getContext(), F.getCallingConv(), VT);
75       for (unsigned i = 0; i < SplitLength; ++i)
76         VRegs.push_back(MRI.createGenericVirtualRegister(LLT{RegisterVT}));
77 
78       if (!handleSplit(VRegs, ArgLocs, ArgLocsIndex, Args[ArgsIndex].Regs[0],
79                        VT))
80         return false;
81     } else {
82       if (!assign(Args[ArgsIndex].Regs[0], ArgLocs[ArgLocsIndex], VT))
83         return false;
84     }
85   }
86   return true;
87 }
88 
89 namespace {
90 class MipsIncomingValueHandler : public MipsCallLowering::MipsHandler {
91 public:
92   MipsIncomingValueHandler(MachineIRBuilder &MIRBuilder,
93                            MachineRegisterInfo &MRI)
94       : MipsHandler(MIRBuilder, MRI) {}
95 
96 private:
97   void assignValueToReg(Register ValVReg, const CCValAssign &VA,
98                         const EVT &VT) override;
99 
100   Register getStackAddress(const CCValAssign &VA,
101                            MachineMemOperand *&MMO) override;
102 
103   void assignValueToAddress(Register ValVReg, const CCValAssign &VA) override;
104 
105   bool handleSplit(SmallVectorImpl<Register> &VRegs,
106                    ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex,
107                    Register ArgsReg, const EVT &VT) override;
108 
109   virtual void markPhysRegUsed(unsigned PhysReg) {
110     MIRBuilder.getMRI()->addLiveIn(PhysReg);
111     MIRBuilder.getMBB().addLiveIn(PhysReg);
112   }
113 
114   MachineInstrBuilder buildLoad(const DstOp &Res, const CCValAssign &VA) {
115     MachineMemOperand *MMO;
116     Register Addr = getStackAddress(VA, MMO);
117     return MIRBuilder.buildLoad(Res, Addr, *MMO);
118   }
119 };
120 
121 class CallReturnHandler : public MipsIncomingValueHandler {
122 public:
123   CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
124                     MachineInstrBuilder &MIB)
125       : MipsIncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
126 
127 private:
128   void markPhysRegUsed(unsigned PhysReg) override {
129     MIB.addDef(PhysReg, RegState::Implicit);
130   }
131 
132   MachineInstrBuilder &MIB;
133 };
134 
135 } // end anonymous namespace
136 
137 void MipsIncomingValueHandler::assignValueToReg(Register ValVReg,
138                                                 const CCValAssign &VA,
139                                                 const EVT &VT) {
140   Register PhysReg = VA.getLocReg();
141   if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
142     const MipsSubtarget &STI =
143         static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
144     bool IsEL = STI.isLittle();
145     LLT s32 = LLT::scalar(32);
146     auto Lo = MIRBuilder.buildCopy(s32, Register(PhysReg + (IsEL ? 0 : 1)));
147     auto Hi = MIRBuilder.buildCopy(s32, Register(PhysReg + (IsEL ? 1 : 0)));
148     MIRBuilder.buildMerge(ValVReg, {Lo, Hi});
149     markPhysRegUsed(PhysReg);
150     markPhysRegUsed(PhysReg + 1);
151   } else if (VT == MVT::f32 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
152     MIRBuilder.buildCopy(ValVReg, PhysReg);
153     markPhysRegUsed(PhysReg);
154   } else {
155     switch (VA.getLocInfo()) {
156     case CCValAssign::LocInfo::SExt:
157     case CCValAssign::LocInfo::ZExt:
158     case CCValAssign::LocInfo::AExt: {
159       auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
160       MIRBuilder.buildTrunc(ValVReg, Copy);
161       break;
162     }
163     default:
164       MIRBuilder.buildCopy(ValVReg, PhysReg);
165       break;
166     }
167     markPhysRegUsed(PhysReg);
168   }
169 }
170 
171 Register MipsIncomingValueHandler::getStackAddress(const CCValAssign &VA,
172                                                    MachineMemOperand *&MMO) {
173   MachineFunction &MF = MIRBuilder.getMF();
174   unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8;
175   unsigned Offset = VA.getLocMemOffset();
176   MachineFrameInfo &MFI = MF.getFrameInfo();
177 
178   int FI = MFI.CreateFixedObject(Size, Offset, true);
179   MachinePointerInfo MPO =
180       MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
181 
182   const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
183   Align Alignment = commonAlignment(TFL->getStackAlign(), Offset);
184   MMO =
185       MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, Size, Alignment);
186 
187   return MIRBuilder.buildFrameIndex(LLT::pointer(0, 32), FI).getReg(0);
188 }
189 
190 void MipsIncomingValueHandler::assignValueToAddress(Register ValVReg,
191                                                     const CCValAssign &VA) {
192   if (VA.getLocInfo() == CCValAssign::SExt ||
193       VA.getLocInfo() == CCValAssign::ZExt ||
194       VA.getLocInfo() == CCValAssign::AExt) {
195     auto Load = buildLoad(LLT::scalar(32), VA);
196     MIRBuilder.buildTrunc(ValVReg, Load);
197   } else
198     buildLoad(ValVReg, VA);
199 }
200 
201 bool MipsIncomingValueHandler::handleSplit(SmallVectorImpl<Register> &VRegs,
202                                            ArrayRef<CCValAssign> ArgLocs,
203                                            unsigned ArgLocsStartIndex,
204                                            Register ArgsReg, const EVT &VT) {
205   if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex, VT))
206     return false;
207   setLeastSignificantFirst(VRegs);
208   MIRBuilder.buildMerge(ArgsReg, VRegs);
209   return true;
210 }
211 
212 namespace {
213 class MipsOutgoingValueHandler : public MipsCallLowering::MipsHandler {
214 public:
215   MipsOutgoingValueHandler(MachineIRBuilder &MIRBuilder,
216                            MachineRegisterInfo &MRI, MachineInstrBuilder &MIB)
217       : MipsHandler(MIRBuilder, MRI), MIB(MIB) {}
218 
219 private:
220   void assignValueToReg(Register ValVReg, const CCValAssign &VA,
221                         const EVT &VT) override;
222 
223   Register getStackAddress(const CCValAssign &VA,
224                            MachineMemOperand *&MMO) override;
225 
226   void assignValueToAddress(Register ValVReg, const CCValAssign &VA) override;
227 
228   bool handleSplit(SmallVectorImpl<Register> &VRegs,
229                    ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex,
230                    Register ArgsReg, const EVT &VT) override;
231 
232   Register extendRegister(Register ValReg, const CCValAssign &VA);
233 
234   MachineInstrBuilder &MIB;
235 };
236 } // end anonymous namespace
237 
238 void MipsOutgoingValueHandler::assignValueToReg(Register ValVReg,
239                                                 const CCValAssign &VA,
240                                                 const EVT &VT) {
241   Register PhysReg = VA.getLocReg();
242   if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
243     const MipsSubtarget &STI =
244         static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
245     bool IsEL = STI.isLittle();
246     auto Unmerge = MIRBuilder.buildUnmerge(LLT::scalar(32), ValVReg);
247     MIRBuilder.buildCopy(Register(PhysReg + (IsEL ? 0 : 1)), Unmerge.getReg(0));
248     MIRBuilder.buildCopy(Register(PhysReg + (IsEL ? 1 : 0)), Unmerge.getReg(1));
249   } else if (VT == MVT::f32 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
250     MIRBuilder.buildCopy(PhysReg, ValVReg);
251   } else {
252     Register ExtReg = extendRegister(ValVReg, VA);
253     MIRBuilder.buildCopy(PhysReg, ExtReg);
254     MIB.addUse(PhysReg, RegState::Implicit);
255   }
256 }
257 
258 Register MipsOutgoingValueHandler::getStackAddress(const CCValAssign &VA,
259                                                    MachineMemOperand *&MMO) {
260   MachineFunction &MF = MIRBuilder.getMF();
261   const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
262 
263   LLT p0 = LLT::pointer(0, 32);
264   LLT s32 = LLT::scalar(32);
265   auto SPReg = MIRBuilder.buildCopy(p0, Register(Mips::SP));
266 
267   unsigned Offset = VA.getLocMemOffset();
268   auto OffsetReg = MIRBuilder.buildConstant(s32, Offset);
269 
270   auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
271 
272   MachinePointerInfo MPO =
273       MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
274   unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8;
275   Align Alignment = commonAlignment(TFL->getStackAlign(), Offset);
276   MMO =
277       MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, Size, Alignment);
278 
279   return AddrReg.getReg(0);
280 }
281 
282 void MipsOutgoingValueHandler::assignValueToAddress(Register ValVReg,
283                                                     const CCValAssign &VA) {
284   MachineMemOperand *MMO;
285   Register Addr = getStackAddress(VA, MMO);
286   Register ExtReg = extendRegister(ValVReg, VA);
287   MIRBuilder.buildStore(ExtReg, Addr, *MMO);
288 }
289 
290 Register MipsOutgoingValueHandler::extendRegister(Register ValReg,
291                                                   const CCValAssign &VA) {
292   LLT LocTy{VA.getLocVT()};
293   switch (VA.getLocInfo()) {
294   case CCValAssign::SExt: {
295     return MIRBuilder.buildSExt(LocTy, ValReg).getReg(0);
296   }
297   case CCValAssign::ZExt: {
298     return MIRBuilder.buildZExt(LocTy, ValReg).getReg(0);
299   }
300   case CCValAssign::AExt: {
301     return MIRBuilder.buildAnyExt(LocTy, ValReg).getReg(0);
302   }
303   // TODO : handle upper extends
304   case CCValAssign::Full:
305     return ValReg;
306   default:
307     break;
308   }
309   llvm_unreachable("unable to extend register");
310 }
311 
312 bool MipsOutgoingValueHandler::handleSplit(SmallVectorImpl<Register> &VRegs,
313                                            ArrayRef<CCValAssign> ArgLocs,
314                                            unsigned ArgLocsStartIndex,
315                                            Register ArgsReg, const EVT &VT) {
316   MIRBuilder.buildUnmerge(VRegs, ArgsReg);
317   setLeastSignificantFirst(VRegs);
318   if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex, VT))
319     return false;
320 
321   return true;
322 }
323 
324 static bool isSupportedArgumentType(Type *T) {
325   if (T->isIntegerTy())
326     return true;
327   if (T->isPointerTy())
328     return true;
329   if (T->isFloatingPointTy())
330     return true;
331   return false;
332 }
333 
334 static bool isSupportedReturnType(Type *T) {
335   if (T->isIntegerTy())
336     return true;
337   if (T->isPointerTy())
338     return true;
339   if (T->isFloatingPointTy())
340     return true;
341   if (T->isAggregateType())
342     return true;
343   return false;
344 }
345 
346 static CCValAssign::LocInfo determineLocInfo(const MVT RegisterVT, const EVT VT,
347                                              const ISD::ArgFlagsTy &Flags) {
348   // > does not mean loss of information as type RegisterVT can't hold type VT,
349   // it means that type VT is split into multiple registers of type RegisterVT
350   if (VT.getFixedSizeInBits() >= RegisterVT.getFixedSizeInBits())
351     return CCValAssign::LocInfo::Full;
352   if (Flags.isSExt())
353     return CCValAssign::LocInfo::SExt;
354   if (Flags.isZExt())
355     return CCValAssign::LocInfo::ZExt;
356   return CCValAssign::LocInfo::AExt;
357 }
358 
359 template <typename T>
360 static void setLocInfo(SmallVectorImpl<CCValAssign> &ArgLocs,
361                        const SmallVectorImpl<T> &Arguments) {
362   for (unsigned i = 0; i < ArgLocs.size(); ++i) {
363     const CCValAssign &VA = ArgLocs[i];
364     CCValAssign::LocInfo LocInfo = determineLocInfo(
365         Arguments[i].VT, Arguments[i].ArgVT, Arguments[i].Flags);
366     if (VA.isMemLoc())
367       ArgLocs[i] =
368           CCValAssign::getMem(VA.getValNo(), VA.getValVT(),
369                               VA.getLocMemOffset(), VA.getLocVT(), LocInfo);
370     else
371       ArgLocs[i] = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
372                                        VA.getLocReg(), VA.getLocVT(), LocInfo);
373   }
374 }
375 
376 bool MipsCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
377                                    const Value *Val, ArrayRef<Register> VRegs,
378                                    FunctionLoweringInfo &FLI) const {
379 
380   MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(Mips::RetRA);
381 
382   if (Val != nullptr && !isSupportedReturnType(Val->getType()))
383     return false;
384 
385   if (!VRegs.empty()) {
386     MachineFunction &MF = MIRBuilder.getMF();
387     const Function &F = MF.getFunction();
388     const DataLayout &DL = MF.getDataLayout();
389     const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
390 
391     SmallVector<ArgInfo, 8> RetInfos;
392     SmallVector<unsigned, 8> OrigArgIndices;
393 
394     ArgInfo ArgRetInfo(VRegs, Val->getType());
395     setArgFlags(ArgRetInfo, AttributeList::ReturnIndex, DL, F);
396     splitToValueTypes(DL, ArgRetInfo, 0, RetInfos, OrigArgIndices);
397 
398     SmallVector<ISD::OutputArg, 8> Outs;
399     subTargetRegTypeForCallingConv(F, RetInfos, OrigArgIndices, Outs);
400 
401     SmallVector<CCValAssign, 16> ArgLocs;
402     MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
403                        F.getContext());
404     CCInfo.AnalyzeReturn(Outs, TLI.CCAssignFnForReturn());
405     setLocInfo(ArgLocs, Outs);
406 
407     MipsOutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret);
408     if (!RetHandler.handle(ArgLocs, RetInfos)) {
409       return false;
410     }
411   }
412   MIRBuilder.insertInstr(Ret);
413   return true;
414 }
415 
416 bool MipsCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
417                                             const Function &F,
418                                             ArrayRef<ArrayRef<Register>> VRegs,
419                                             FunctionLoweringInfo &FLI) const {
420 
421   // Quick exit if there aren't any args.
422   if (F.arg_empty())
423     return true;
424 
425   for (auto &Arg : F.args()) {
426     if (!isSupportedArgumentType(Arg.getType()))
427       return false;
428   }
429 
430   MachineFunction &MF = MIRBuilder.getMF();
431   const DataLayout &DL = MF.getDataLayout();
432   const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
433 
434   SmallVector<ArgInfo, 8> ArgInfos;
435   SmallVector<unsigned, 8> OrigArgIndices;
436   unsigned i = 0;
437   for (auto &Arg : F.args()) {
438     ArgInfo AInfo(VRegs[i], Arg.getType());
439     setArgFlags(AInfo, i + AttributeList::FirstArgIndex, DL, F);
440     ArgInfos.push_back(AInfo);
441     OrigArgIndices.push_back(i);
442     ++i;
443   }
444 
445   SmallVector<ISD::InputArg, 8> Ins;
446   subTargetRegTypeForCallingConv(F, ArgInfos, OrigArgIndices, Ins);
447 
448   SmallVector<CCValAssign, 16> ArgLocs;
449   MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
450                      F.getContext());
451 
452   const MipsTargetMachine &TM =
453       static_cast<const MipsTargetMachine &>(MF.getTarget());
454   const MipsABIInfo &ABI = TM.getABI();
455   CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(F.getCallingConv()),
456                        Align(1));
457   CCInfo.AnalyzeFormalArguments(Ins, TLI.CCAssignFnForCall());
458   setLocInfo(ArgLocs, Ins);
459 
460   MipsIncomingValueHandler Handler(MIRBuilder, MF.getRegInfo());
461   if (!Handler.handle(ArgLocs, ArgInfos))
462     return false;
463 
464   if (F.isVarArg()) {
465     ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
466     unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
467 
468     int VaArgOffset;
469     unsigned RegSize = 4;
470     if (ArgRegs.size() == Idx)
471       VaArgOffset = alignTo(CCInfo.getNextStackOffset(), RegSize);
472     else {
473       VaArgOffset =
474           (int)ABI.GetCalleeAllocdArgSizeInBytes(CCInfo.getCallingConv()) -
475           (int)(RegSize * (ArgRegs.size() - Idx));
476     }
477 
478     MachineFrameInfo &MFI = MF.getFrameInfo();
479     int FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true);
480     MF.getInfo<MipsFunctionInfo>()->setVarArgsFrameIndex(FI);
481 
482     for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += RegSize) {
483       MIRBuilder.getMBB().addLiveIn(ArgRegs[I]);
484 
485       MachineInstrBuilder Copy =
486           MIRBuilder.buildCopy(LLT::scalar(RegSize * 8), Register(ArgRegs[I]));
487       FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true);
488       MachinePointerInfo MPO = MachinePointerInfo::getFixedStack(MF, FI);
489       MachineInstrBuilder FrameIndex =
490           MIRBuilder.buildFrameIndex(LLT::pointer(MPO.getAddrSpace(), 32), FI);
491       MachineMemOperand *MMO = MF.getMachineMemOperand(
492           MPO, MachineMemOperand::MOStore, RegSize, Align(RegSize));
493       MIRBuilder.buildStore(Copy, FrameIndex, *MMO);
494     }
495   }
496 
497   return true;
498 }
499 
500 bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
501                                  CallLoweringInfo &Info) const {
502 
503   if (Info.CallConv != CallingConv::C)
504     return false;
505 
506   for (auto &Arg : Info.OrigArgs) {
507     if (!isSupportedArgumentType(Arg.Ty))
508       return false;
509     if (Arg.Flags[0].isByVal())
510       return false;
511     if (Arg.Flags[0].isSRet() && !Arg.Ty->isPointerTy())
512       return false;
513   }
514 
515   if (!Info.OrigRet.Ty->isVoidTy() && !isSupportedReturnType(Info.OrigRet.Ty))
516     return false;
517 
518   MachineFunction &MF = MIRBuilder.getMF();
519   const Function &F = MF.getFunction();
520   const DataLayout &DL = MF.getDataLayout();
521   const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
522   const MipsTargetMachine &TM =
523       static_cast<const MipsTargetMachine &>(MF.getTarget());
524   const MipsABIInfo &ABI = TM.getABI();
525 
526   MachineInstrBuilder CallSeqStart =
527       MIRBuilder.buildInstr(Mips::ADJCALLSTACKDOWN);
528 
529   const bool IsCalleeGlobalPIC =
530       Info.Callee.isGlobal() && TM.isPositionIndependent();
531 
532   MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert(
533       Info.Callee.isReg() || IsCalleeGlobalPIC ? Mips::JALRPseudo : Mips::JAL);
534   MIB.addDef(Mips::SP, RegState::Implicit);
535   if (IsCalleeGlobalPIC) {
536     Register CalleeReg =
537         MF.getRegInfo().createGenericVirtualRegister(LLT::pointer(0, 32));
538     MachineInstr *CalleeGlobalValue =
539         MIRBuilder.buildGlobalValue(CalleeReg, Info.Callee.getGlobal());
540     if (!Info.Callee.getGlobal()->hasLocalLinkage())
541       CalleeGlobalValue->getOperand(1).setTargetFlags(MipsII::MO_GOT_CALL);
542     MIB.addUse(CalleeReg);
543   } else
544     MIB.add(Info.Callee);
545   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
546   MIB.addRegMask(TRI->getCallPreservedMask(MF, F.getCallingConv()));
547 
548   TargetLowering::ArgListTy FuncOrigArgs;
549   FuncOrigArgs.reserve(Info.OrigArgs.size());
550 
551   SmallVector<ArgInfo, 8> ArgInfos;
552   SmallVector<unsigned, 8> OrigArgIndices;
553   unsigned i = 0;
554   for (auto &Arg : Info.OrigArgs) {
555 
556     TargetLowering::ArgListEntry Entry;
557     Entry.Ty = Arg.Ty;
558     FuncOrigArgs.push_back(Entry);
559 
560     ArgInfos.push_back(Arg);
561     OrigArgIndices.push_back(i);
562     ++i;
563   }
564 
565   SmallVector<ISD::OutputArg, 8> Outs;
566   subTargetRegTypeForCallingConv(F, ArgInfos, OrigArgIndices, Outs);
567 
568   SmallVector<CCValAssign, 8> ArgLocs;
569   bool IsCalleeVarArg = false;
570   if (Info.Callee.isGlobal()) {
571     const Function *CF = static_cast<const Function *>(Info.Callee.getGlobal());
572     IsCalleeVarArg = CF->isVarArg();
573   }
574   MipsCCState CCInfo(F.getCallingConv(), IsCalleeVarArg, MF, ArgLocs,
575                      F.getContext());
576 
577   CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(Info.CallConv),
578                        Align(1));
579   const char *Call =
580       Info.Callee.isSymbol() ? Info.Callee.getSymbolName() : nullptr;
581   CCInfo.AnalyzeCallOperands(Outs, TLI.CCAssignFnForCall(), FuncOrigArgs, Call);
582   setLocInfo(ArgLocs, Outs);
583 
584   MipsOutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), MIB);
585   if (!RetHandler.handle(ArgLocs, ArgInfos)) {
586     return false;
587   }
588 
589   unsigned NextStackOffset = CCInfo.getNextStackOffset();
590   const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
591   unsigned StackAlignment = TFL->getStackAlignment();
592   NextStackOffset = alignTo(NextStackOffset, StackAlignment);
593   CallSeqStart.addImm(NextStackOffset).addImm(0);
594 
595   if (IsCalleeGlobalPIC) {
596     MIRBuilder.buildCopy(
597       Register(Mips::GP),
598       MF.getInfo<MipsFunctionInfo>()->getGlobalBaseRegForGlobalISel(MF));
599     MIB.addDef(Mips::GP, RegState::Implicit);
600   }
601   MIRBuilder.insertInstr(MIB);
602   if (MIB->getOpcode() == Mips::JALRPseudo) {
603     const MipsSubtarget &STI =
604         static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
605     MIB.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
606                          *STI.getRegBankInfo());
607   }
608 
609   if (!Info.OrigRet.Ty->isVoidTy()) {
610     ArgInfos.clear();
611     SmallVector<unsigned, 8> OrigRetIndices;
612 
613     splitToValueTypes(DL, Info.OrigRet, 0, ArgInfos, OrigRetIndices);
614 
615     SmallVector<ISD::InputArg, 8> Ins;
616     subTargetRegTypeForCallingConv(F, ArgInfos, OrigRetIndices, Ins);
617 
618     SmallVector<CCValAssign, 8> ArgLocs;
619     MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
620                        F.getContext());
621 
622     CCInfo.AnalyzeCallResult(Ins, TLI.CCAssignFnForReturn(), Info.OrigRet.Ty,
623                              Call);
624     setLocInfo(ArgLocs, Ins);
625 
626     CallReturnHandler Handler(MIRBuilder, MF.getRegInfo(), MIB);
627     if (!Handler.handle(ArgLocs, ArgInfos))
628       return false;
629   }
630 
631   MIRBuilder.buildInstr(Mips::ADJCALLSTACKUP).addImm(NextStackOffset).addImm(0);
632 
633   return true;
634 }
635 
636 template <typename T>
637 void MipsCallLowering::subTargetRegTypeForCallingConv(
638     const Function &F, ArrayRef<ArgInfo> Args,
639     ArrayRef<unsigned> OrigArgIndices, SmallVectorImpl<T> &ISDArgs) const {
640   const DataLayout &DL = F.getParent()->getDataLayout();
641   const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
642 
643   unsigned ArgNo = 0;
644   for (auto &Arg : Args) {
645 
646     EVT VT = TLI.getValueType(DL, Arg.Ty);
647     MVT RegisterVT = TLI.getRegisterTypeForCallingConv(F.getContext(),
648                                                        F.getCallingConv(), VT);
649     unsigned NumRegs = TLI.getNumRegistersForCallingConv(
650         F.getContext(), F.getCallingConv(), VT);
651 
652     for (unsigned i = 0; i < NumRegs; ++i) {
653       ISD::ArgFlagsTy Flags = Arg.Flags[0];
654 
655       if (i == 0)
656         Flags.setOrigAlign(TLI.getABIAlignmentForCallingConv(Arg.Ty, DL));
657       else
658         Flags.setOrigAlign(Align(1));
659 
660       ISDArgs.emplace_back(Flags, RegisterVT, VT, true, OrigArgIndices[ArgNo],
661                            0);
662     }
663     ++ArgNo;
664   }
665 }
666 
667 void MipsCallLowering::splitToValueTypes(
668     const DataLayout &DL, const ArgInfo &OrigArg, unsigned OriginalIndex,
669     SmallVectorImpl<ArgInfo> &SplitArgs,
670     SmallVectorImpl<unsigned> &SplitArgsOrigIndices) const {
671 
672   SmallVector<EVT, 4> SplitEVTs;
673   SmallVector<Register, 4> SplitVRegs;
674   const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
675   LLVMContext &Ctx = OrigArg.Ty->getContext();
676 
677   ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitEVTs);
678 
679   for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
680     ArgInfo Info = ArgInfo{OrigArg.Regs[i], SplitEVTs[i].getTypeForEVT(Ctx)};
681     Info.Flags = OrigArg.Flags;
682     SplitArgs.push_back(Info);
683     SplitArgsOrigIndices.push_back(OriginalIndex);
684   }
685 }
686