1//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes Mips64 instructions. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Mips Operand, Complex Patterns and Transformations Definitions. 15//===----------------------------------------------------------------------===// 16 17// shamt must fit in 6 bits. 18def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>; 19def timmZExt6 : TImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>; 20 21// Node immediate fits as 10-bit sign extended on target immediate. 22// e.g. seqi, snei 23def immSExt10_64 : PatLeaf<(i64 imm), 24 [{ return isInt<10>(N->getSExtValue()); }]>; 25 26def immZExt16_64 : PatLeaf<(i64 imm), 27 [{ return isUInt<16>(N->getZExtValue()); }]>; 28 29def immZExt5_64 : ImmLeaf<i64, [{ return Imm == (Imm & 0x1f); }]>; 30 31// Transformation function: get log2 of low 32 bits of immediate 32def Log2LO : SDNodeXForm<imm, [{ 33 return getImm(N, Log2_64((unsigned) N->getZExtValue())); 34}]>; 35 36// Transformation function: get log2 of high 32 bits of immediate 37def Log2HI : SDNodeXForm<imm, [{ 38 return getImm(N, Log2_64((unsigned) (N->getZExtValue() >> 32))); 39}]>; 40 41// Predicate: True if immediate is a power of 2 and fits 32 bits 42def PowerOf2LO : PatLeaf<(imm), [{ 43 if (N->getValueType(0) == MVT::i64) { 44 uint64_t Imm = N->getZExtValue(); 45 return isPowerOf2_64(Imm) && (Imm & 0xffffffff) == Imm; 46 } 47 else 48 return false; 49}]>; 50 51// Predicate: True if immediate is a power of 2 and exceeds 32 bits 52def PowerOf2HI : PatLeaf<(imm), [{ 53 if (N->getValueType(0) == MVT::i64) { 54 uint64_t Imm = N->getZExtValue(); 55 return isPowerOf2_64(Imm) && (Imm & 0xffffffff00000000) == Imm; 56 } 57 else 58 return false; 59}]>; 60 61def PowerOf2LO_i32 : PatLeaf<(imm), [{ 62 if (N->getValueType(0) == MVT::i32) { 63 uint64_t Imm = N->getZExtValue(); 64 return isPowerOf2_32(Imm) && isUInt<32>(Imm); 65 } 66 else 67 return false; 68}]>; 69 70def assertzext_lt_i32 : PatFrag<(ops node:$src), (assertzext node:$src), [{ 71 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLT(MVT::i32); 72}]>; 73 74//===----------------------------------------------------------------------===// 75// Instructions specific format 76//===----------------------------------------------------------------------===// 77let usesCustomInserter = 1 in { 78 def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>; 79 def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>; 80 def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>; 81 def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>; 82 def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>; 83 def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>; 84 def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>; 85 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>; 86 def ATOMIC_LOAD_MIN_I64 : Atomic2Ops<atomic_load_min_64, GPR64>; 87 def ATOMIC_LOAD_MAX_I64 : Atomic2Ops<atomic_load_max_64, GPR64>; 88 def ATOMIC_LOAD_UMIN_I64 : Atomic2Ops<atomic_load_umin_64, GPR64>; 89 def ATOMIC_LOAD_UMAX_I64 : Atomic2Ops<atomic_load_umax_64, GPR64>; 90} 91 92def ATOMIC_LOAD_ADD_I64_POSTRA : Atomic2OpsPostRA<GPR64>; 93def ATOMIC_LOAD_SUB_I64_POSTRA : Atomic2OpsPostRA<GPR64>; 94def ATOMIC_LOAD_AND_I64_POSTRA : Atomic2OpsPostRA<GPR64>; 95def ATOMIC_LOAD_OR_I64_POSTRA : Atomic2OpsPostRA<GPR64>; 96def ATOMIC_LOAD_XOR_I64_POSTRA : Atomic2OpsPostRA<GPR64>; 97def ATOMIC_LOAD_NAND_I64_POSTRA : Atomic2OpsPostRA<GPR64>; 98 99def ATOMIC_SWAP_I64_POSTRA : Atomic2OpsPostRA<GPR64>; 100 101def ATOMIC_CMP_SWAP_I64_POSTRA : AtomicCmpSwapPostRA<GPR64>; 102 103def ATOMIC_LOAD_MIN_I64_POSTRA : Atomic2OpsPostRA<GPR64>; 104def ATOMIC_LOAD_MAX_I64_POSTRA : Atomic2OpsPostRA<GPR64>; 105def ATOMIC_LOAD_UMIN_I64_POSTRA : Atomic2OpsPostRA<GPR64>; 106def ATOMIC_LOAD_UMAX_I64_POSTRA : Atomic2OpsPostRA<GPR64>; 107 108/// Pseudo instructions for loading and storing accumulator registers. 109let isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in { 110 def LOAD_ACC128 : Load<"", ACC128>; 111 def STORE_ACC128 : Store<"", ACC128>; 112} 113 114//===----------------------------------------------------------------------===// 115// Instruction definition 116//===----------------------------------------------------------------------===// 117let DecoderNamespace = "Mips64" in { 118/// Arithmetic Instructions (ALU Immediate) 119def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd, II_DADDI>, 120 ADDI_FM<0x18>, ISA_MIPS3_NOT_32R6_64R6; 121let AdditionalPredicates = [NotInMicroMips] in { 122 def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU, 123 immSExt16, add>, 124 ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3; 125} 126 127let isCodeGenOnly = 1 in { 128def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>, 129 SLTI_FM<0xa>, GPR_64; 130def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>, 131 SLTI_FM<0xb>, GPR_64; 132def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>, 133 ADDI_FM<0xc>, GPR_64; 134def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>, 135 ADDI_FM<0xd>, GPR_64; 136def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>, 137 ADDI_FM<0xe>, GPR_64; 138def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64_relaxed>, LUI_FM, GPR_64; 139} 140 141/// Arithmetic Instructions (3-Operand, R-Type) 142let AdditionalPredicates = [NotInMicroMips] in { 143 def DADD : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>, 144 ISA_MIPS3; 145 def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>, 146 ADD_FM<0, 0x2d>, ISA_MIPS3; 147 def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, 148 ADD_FM<0, 0x2f>, ISA_MIPS3; 149 def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>, 150 ISA_MIPS3; 151} 152 153let isCodeGenOnly = 1 in { 154def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>, GPR_64; 155def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>, GPR_64; 156def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>, 157 GPR_64; 158def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>, 159 GPR_64; 160def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>, 161 GPR_64; 162def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>, GPR_64; 163} 164 165/// Shift Instructions 166let AdditionalPredicates = [NotInMicroMips] in { 167 def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, mshl_64, 168 immZExt6>, 169 SRA_FM<0x38, 0>, ISA_MIPS3; 170 def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, msrl_64, 171 immZExt6>, 172 SRA_FM<0x3a, 0>, ISA_MIPS3; 173 def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, msra_64, 174 immZExt6>, 175 SRA_FM<0x3b, 0>, ISA_MIPS3; 176 def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, mshl_64>, 177 SRLV_FM<0x14, 0>, ISA_MIPS3; 178 def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, msra_64>, 179 SRLV_FM<0x17, 0>, ISA_MIPS3; 180 def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, msrl_64>, 181 SRLV_FM<0x16, 0>, ISA_MIPS3; 182 def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>, 183 SRA_FM<0x3c, 0>, ISA_MIPS3; 184 def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>, 185 SRA_FM<0x3e, 0>, ISA_MIPS3; 186 def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>, 187 SRA_FM<0x3f, 0>, ISA_MIPS3; 188 189// Rotate Instructions 190 def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr, 191 immZExt6>, 192 SRA_FM<0x3a, 1>, ISA_MIPS64R2; 193 def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>, 194 SRLV_FM<0x16, 1>, ISA_MIPS64R2; 195 def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>, 196 SRA_FM<0x3e, 1>, ISA_MIPS64R2; 197} 198 199/// Load and Store Instructions 200/// aligned 201let isCodeGenOnly = 1 in { 202def LB64 : Load<"lb", GPR64Opnd, sextloadi8, II_LB>, LW_FM<0x20>, GPR_64; 203def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>, GPR_64; 204def LH64 : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>, GPR_64; 205def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>, GPR_64; 206def LW64 : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>, GPR_64; 207def SB64 : Store<"sb", GPR64Opnd, truncstorei8, II_SB>, LW_FM<0x28>, GPR_64; 208def SH64 : Store<"sh", GPR64Opnd, truncstorei16, II_SH>, LW_FM<0x29>, 209 GPR_64; 210def SW64 : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>, 211 GPR_64; 212} 213 214let AdditionalPredicates = [NotInMicroMips] in { 215 def LWu : MMRel, Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, 216 LW_FM<0x27>, ISA_MIPS3; 217 def LD : LoadMemory<"ld", GPR64Opnd, mem_simmptr, load, II_LD>, 218 LW_FM<0x37>, ISA_MIPS3; 219 def SD : StoreMemory<"sd", GPR64Opnd, mem_simmptr, store, II_SD>, 220 LW_FM<0x3f>, ISA_MIPS3; 221} 222 223 224 225/// load/store left/right 226let isCodeGenOnly = 1 in { 227def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, II_LWL>, LW_FM<0x22>, 228 GPR_64; 229def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, II_LWR>, LW_FM<0x26>, 230 GPR_64; 231def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, II_SWL>, LW_FM<0x2a>, 232 GPR_64; 233def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, II_SWR>, LW_FM<0x2e>, 234 GPR_64; 235} 236 237def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>, 238 ISA_MIPS3_NOT_32R6_64R6; 239def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>, 240 ISA_MIPS3_NOT_32R6_64R6; 241def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, II_SDL>, LW_FM<0x2c>, 242 ISA_MIPS3_NOT_32R6_64R6; 243def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>, 244 ISA_MIPS3_NOT_32R6_64R6; 245 246/// Load-linked, Store-conditional 247let AdditionalPredicates = [NotInMicroMips] in { 248 def LLD : LLBase<"lld", GPR64Opnd, mem_simmptr>, LW_FM<0x34>, 249 ISA_MIPS3_NOT_32R6_64R6; 250} 251def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6; 252 253let AdditionalPredicates = [NotInMicroMips], 254 DecoderNamespace = "Mips32_64_PTR64" in { 255def LL64 : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, PTR_64, 256 ISA_MIPS2_NOT_32R6_64R6; 257def SC64 : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, PTR_64, 258 ISA_MIPS2_NOT_32R6_64R6; 259def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>, PTR_64; 260} 261 262def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM, PTR_64; 263 264/// Jump and Branch Instructions 265let isCodeGenOnly = 1 in { 266 def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>, 267 GPR_64; 268 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>, 269 GPR_64; 270 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>, 271 GPR_64; 272 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>, 273 GPR_64; 274 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>, 275 GPR_64; 276 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>, 277 GPR_64; 278 let AdditionalPredicates = [NoIndirectJumpGuards] in 279 def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>, 280 PTR_64; 281} 282let AdditionalPredicates = [NotInMicroMips], 283 DecoderNamespace = "Mips64" in { 284 def JR_HB64 : JR_HB_DESC<GPR64Opnd>, JR_HB_ENC, ISA_MIPS64_NOT_64R6; 285 def JALR_HB64 : JALR_HB_DESC<GPR64Opnd>, JALR_HB_ENC, ISA_MIPS64R2; 286} 287def PseudoReturn64 : PseudoReturnBase<GPR64Opnd>, GPR_64; 288 289let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, 290 NoIndirectJumpGuards] in { 291 def TAILCALLREG64 : TailCallReg<JR64, GPR64Opnd>, ISA_MIPS3_NOT_32R6_64R6, 292 PTR_64; 293 def PseudoIndirectBranch64 : PseudoIndirectBranchBase<JR64, GPR64Opnd>, 294 ISA_MIPS3_NOT_32R6_64R6; 295} 296 297let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, 298 UseIndirectJumpsHazard] in { 299 def TAILCALLREGHB64 : TailCallReg<JR_HB64, GPR64Opnd>, 300 ISA_MIPS32R2_NOT_32R6_64R6, PTR_64; 301 def PseudoIndirectHazardBranch64 : PseudoIndirectBranchBase<JR_HB64, 302 GPR64Opnd>, 303 ISA_MIPS32R2_NOT_32R6_64R6, PTR_64; 304} 305 306/// Multiply and Divide Instructions. 307let AdditionalPredicates = [NotInMicroMips] in { 308 def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>, 309 MULT_FM<0, 0x1c>, ISA_MIPS3_NOT_32R6_64R6; 310 def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>, 311 MULT_FM<0, 0x1d>, ISA_MIPS3_NOT_32R6_64R6; 312} 313def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult, 314 II_DMULT>, ISA_MIPS3_NOT_32R6_64R6; 315def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu, 316 II_DMULTU>, ISA_MIPS3_NOT_32R6_64R6; 317let AdditionalPredicates = [NotInMicroMips] in { 318 def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>, 319 MULT_FM<0, 0x1e>, ISA_MIPS3_NOT_32R6_64R6; 320 def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>, 321 MULT_FM<0, 0x1f>, ISA_MIPS3_NOT_32R6_64R6; 322} 323def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem, 324 II_DDIV, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6; 325def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU, 326 II_DDIVU, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6; 327 328let isCodeGenOnly = 1 in { 329def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>, 330 ISA_MIPS3_NOT_32R6_64R6; 331def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>, 332 ISA_MIPS3_NOT_32R6_64R6; 333def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, AC0_64>, MFLO_FM<0x10>, 334 ISA_MIPS3_NOT_32R6_64R6; 335def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, AC0_64>, MFLO_FM<0x12>, 336 ISA_MIPS3_NOT_32R6_64R6; 337def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>, 338 ISA_MIPS3_NOT_32R6_64R6; 339def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>, 340 ISA_MIPS3_NOT_32R6_64R6; 341def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>, ISA_MIPS3_NOT_32R6_64R6; 342 343/// Sign Ext In Register Instructions. 344def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>, 345 ISA_MIPS32R2, GPR_64; 346def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>, 347 ISA_MIPS32R2, GPR_64; 348} 349 350/// Count Leading 351let AdditionalPredicates = [NotInMicroMips] in { 352 def DCLZ : CountLeading0<"dclz", GPR64Opnd, II_DCLZ>, CLO_FM<0x24>, 353 ISA_MIPS64_NOT_64R6, GPR_64; 354 def DCLO : CountLeading1<"dclo", GPR64Opnd, II_DCLO>, CLO_FM<0x25>, 355 ISA_MIPS64_NOT_64R6, GPR_64; 356 357/// Double Word Swap Bytes/HalfWords 358 def DSBH : SubwordSwap<"dsbh", GPR64Opnd, II_DSBH>, SEB_FM<2, 0x24>, 359 ISA_MIPS64R2; 360 def DSHD : SubwordSwap<"dshd", GPR64Opnd, II_DSHD>, SEB_FM<5, 0x24>, 361 ISA_MIPS64R2; 362 363 def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>, 364 GPR_64; 365} 366 367let isCodeGenOnly = 1 in 368def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM, GPR_64; 369 370let AdditionalPredicates = [NotInMicroMips] in { 371 // The 'pos + size' constraints for code generation are enforced by the 372 // code that lowers into MipsISD::Ext. 373 // For assembly parsing, we alias dextu and dextm to dext, and match by 374 // operand were possible then check the 'pos + size' in MipsAsmParser. 375 // We override the generated decoder to enforce that dext always comes out 376 // for dextm and dextu like binutils. 377 let DecoderMethod = "DecodeDEXT" in { 378 def DEXT : ExtBase<"dext", GPR64Opnd, uimm5_report_uimm6, 379 uimm5_plus1_report_uimm6, immZExt5, immZExt5Plus1, 380 MipsExt>, EXT_FM<3>, ISA_MIPS64R2; 381 def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5, uimm5_plus33, immZExt5, 382 immZExt5Plus33, MipsExt>, EXT_FM<1>, ISA_MIPS64R2; 383 def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm5_plus32, uimm5_plus1, 384 immZExt5Plus32, immZExt5Plus1, MipsExt>, EXT_FM<2>, 385 ISA_MIPS64R2; 386 } 387 // The 'pos + size' constraints for code generation are enforced by the 388 // code that lowers into MipsISD::Ins. 389 // For assembly parsing, we alias dinsu and dinsm to dins, and match by 390 // operand were possible then check the 'pos + size' in MipsAsmParser. 391 // We override the generated decoder to enforce that dins always comes out 392 // for dinsm and dinsu like binutils. 393 let DecoderMethod = "DecodeDINS" in { 394 def DINS : InsBase<"dins", GPR64Opnd, uimm6, uimm5_inssize_plus1, 395 immZExt5, immZExt5Plus1>, EXT_FM<7>, 396 ISA_MIPS64R2; 397 def DINSU : InsBase<"dinsu", GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1, 398 immZExt5Plus32, immZExt5Plus1>, 399 EXT_FM<6>, ISA_MIPS64R2; 400 def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64, 401 immZExt5, immZExtRange2To64>, 402 EXT_FM<5>, ISA_MIPS64R2; 403 } 404} 405 406let isCodeGenOnly = 1, AdditionalPredicates = [NotInMicroMips] in { 407 def DEXT64_32 408 : InstSE<(outs GPR64Opnd:$rt), 409 (ins GPR32Opnd:$rs, uimm5_report_uimm6:$pos, uimm5_plus1:$size), 410 "dext $rt, $rs, $pos, $size", [], II_EXT, FrmR, "dext">, 411 EXT_FM<3>, ISA_MIPS64R2; 412} 413 414let isCodeGenOnly = 1, rs = 0, shamt = 0 in { 415 def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt), 416 "dsll\t$rd, $rt, 32", [], II_DSLL>, GPR_64; 417 let isMoveReg = 1 in { 418 def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt), 419 "sll\t$rd, $rt, 0", [], II_SLL>, GPR_64; 420 def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt), 421 "sll\t$rd, $rt, 0", [], II_SLL>, GPR_64; 422 } 423} 424 425// We need the following pseudo instruction to avoid offset calculation for 426// long branches. See the comment in file MipsLongBranch.cpp for detailed 427// explanation. 428 429// Expands to: lui $dst, %highest/%higher/%hi/%lo($tgt) 430def LONG_BRANCH_LUi2Op_64 : 431 PseudoSE<(outs GPR64Opnd:$dst), (ins brtarget:$tgt), []>, GPR_64 { 432 bit hasNoSchedulingInfo = 1; 433} 434// Expands to: addiu $dst, %highest/%higher/%hi/%lo($tgt) 435def LONG_BRANCH_DADDiu2Op : 436 PseudoSE<(outs GPR64Opnd:$dst), (ins GPR64Opnd:$src, brtarget:$tgt), []>, 437 GPR_64 { 438 bit hasNoSchedulingInfo = 1; 439} 440// Expands to: daddiu $dst, $src, %PART($tgt - $baltgt) 441// where %PART may be %hi or %lo, depending on the relocation kind 442// that $tgt is annotated with. 443def LONG_BRANCH_DADDiu : 444 PseudoSE<(outs GPR64Opnd:$dst), 445 (ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>, 446 GPR_64 { 447 bit hasNoSchedulingInfo = 1; 448} 449 450// Cavium Octeon cnMIPS instructions 451let DecoderNamespace = "CnMips", 452 // FIXME: The lack of HasStdEnc is probably a bug 453 EncodingPredicates = []<Predicate> in { 454 455class Count1s<string opstr, RegisterOperand RO>: 456 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 457 [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> { 458 let TwoOperandAliasConstraint = "$rd = $rs"; 459} 460 461class ExtsCins<string opstr, InstrItinClass itin, RegisterOperand RO, 462 PatFrag PosImm, SDPatternOperator Op = null_frag>: 463 InstSE<(outs RO:$rt), (ins RO:$rs, uimm5:$pos, uimm5:$lenm1), 464 !strconcat(opstr, "\t$rt, $rs, $pos, $lenm1"), 465 [(set RO:$rt, (Op RO:$rs, PosImm:$pos, imm:$lenm1))], 466 itin, FrmR, opstr> { 467 let TwoOperandAliasConstraint = "$rt = $rs"; 468} 469 470class SetCC64_R<string opstr, PatFrag cond_op> : 471 InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt), 472 !strconcat(opstr, "\t$rd, $rs, $rt"), 473 [(set GPR64Opnd:$rd, (zext (cond_op GPR64Opnd:$rs, 474 GPR64Opnd:$rt)))], 475 II_SEQ_SNE, FrmR, opstr> { 476 let TwoOperandAliasConstraint = "$rd = $rs"; 477} 478 479class SetCC64_I<string opstr, PatFrag cond_op>: 480 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10), 481 !strconcat(opstr, "\t$rt, $rs, $imm10"), 482 [(set GPR64Opnd:$rt, (zext (cond_op GPR64Opnd:$rs, 483 immSExt10_64:$imm10)))], 484 II_SEQI_SNEI, FrmI, opstr> { 485 let TwoOperandAliasConstraint = "$rt = $rs"; 486} 487 488class CBranchBitNum<string opstr, DAGOperand opnd, PatFrag cond_op, 489 RegisterOperand RO, Operand ImmOp, bits<64> shift = 1> : 490 InstSE<(outs), (ins RO:$rs, ImmOp:$p, opnd:$offset), 491 !strconcat(opstr, "\t$rs, $p, $offset"), 492 [(brcond (i32 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)), 493 bb:$offset)], II_BBIT, FrmI, opstr> { 494 let isBranch = 1; 495 let isTerminator = 1; 496 let hasDelaySlot = 1; 497 let Defs = [AT]; 498} 499 500class MFC2OP<string asmstr, RegisterOperand RO, InstrItinClass itin> : 501 InstSE<(outs RO:$rt, uimm16:$imm16), (ins), 502 !strconcat(asmstr, "\t$rt, $imm16"), [], itin, FrmFR>; 503 504// Unsigned Byte Add 505def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>, 506 ADD_FM<0x1c, 0x28>, ASE_CNMIPS { 507 let Pattern = [(set GPR64Opnd:$rd, 508 (and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))]; 509} 510 511// Branch on Bit Clear /+32 512def BBIT0 : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd, 513 uimm5_64_report_uimm6>, BBIT_FM<0x32>, ASE_CNMIPS; 514def BBIT032: CBranchBitNum<"bbit032", brtarget, seteq, GPR64Opnd, uimm5_64, 515 0x100000000>, BBIT_FM<0x36>, ASE_CNMIPS; 516 517// Branch on Bit Set /+32 518def BBIT1 : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd, 519 uimm5_64_report_uimm6>, BBIT_FM<0x3a>, ASE_CNMIPS; 520def BBIT132: CBranchBitNum<"bbit132", brtarget, setne, GPR64Opnd, uimm5_64, 521 0x100000000>, BBIT_FM<0x3e>, ASE_CNMIPS; 522 523// Multiply Doubleword to GPR 524def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>, 525 ADD_FM<0x1c, 0x03>, ASE_CNMIPS { 526 let Defs = [HI0, LO0, P0, P1, P2]; 527} 528 529let AdditionalPredicates = [NotInMicroMips] in { 530 // Extract a signed bit field /+32 531 def EXTS : ExtsCins<"exts", II_EXT, GPR64Opnd, immZExt5>, EXTS_FM<0x3a>, 532 ASE_MIPS64_CNMIPS; 533 def EXTS32: ExtsCins<"exts32", II_EXT, GPR64Opnd, immZExt5Plus32>, 534 EXTS_FM<0x3b>, ASE_MIPS64_CNMIPS; 535 536 // Clear and insert a bit field /+32 537 def CINS : ExtsCins<"cins", II_INS, GPR64Opnd, immZExt5, MipsCIns>, 538 EXTS_FM<0x32>, ASE_MIPS64_CNMIPS; 539 def CINS32: ExtsCins<"cins32", II_INS, GPR64Opnd, immZExt5Plus32, MipsCIns>, 540 EXTS_FM<0x33>, ASE_MIPS64_CNMIPS; 541 let isCodeGenOnly = 1 in { 542 def CINS_i32 : ExtsCins<"cins", II_INS, GPR32Opnd, immZExt5, MipsCIns>, 543 EXTS_FM<0x32>, ASE_MIPS64_CNMIPS; 544 def CINS64_32 :InstSE<(outs GPR64Opnd:$rt), 545 (ins GPR32Opnd:$rs, uimm5:$pos, uimm5:$lenm1), 546 "cins\t$rt, $rs, $pos, $lenm1", [], II_INS, FrmR, 547 "cins">, 548 EXTS_FM<0x32>, ASE_MIPS64_CNMIPS; 549 } 550} 551 552// Move to multiplier/product register 553def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>, 554 ASE_CNMIPS; 555def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>, 556 ASE_CNMIPS; 557def MTM2 : MoveToLOHI<"mtm2", GPR64Opnd, [MPL2, P0, P1, P2]>, MTMR_FM<0x0d>, 558 ASE_CNMIPS; 559def MTP0 : MoveToLOHI<"mtp0", GPR64Opnd, [P0]>, MTMR_FM<0x09>, ASE_CNMIPS; 560def MTP1 : MoveToLOHI<"mtp1", GPR64Opnd, [P1]>, MTMR_FM<0x0a>, ASE_CNMIPS; 561def MTP2 : MoveToLOHI<"mtp2", GPR64Opnd, [P2]>, MTMR_FM<0x0b>, ASE_CNMIPS; 562 563// Count Ones in a Word/Doubleword 564def POP : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>, ASE_CNMIPS; 565def DPOP : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>, ASE_CNMIPS; 566 567// Set on equal/not equal 568def SEQ : SetCC64_R<"seq", seteq>, SEQ_FM<0x2a>, ASE_CNMIPS; 569def SEQi : SetCC64_I<"seqi", seteq>, SEQI_FM<0x2e>, ASE_CNMIPS; 570def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>, ASE_CNMIPS; 571def SNEi : SetCC64_I<"snei", setne>, SEQI_FM<0x2f>, ASE_CNMIPS; 572 573// 192-bit x 64-bit Unsigned Multiply and Add 574def V3MULU: ArithLogicR<"v3mulu", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x11>, 575 ASE_CNMIPS { 576 let Defs = [P0, P1, P2]; 577} 578 579// 64-bit Unsigned Multiply and Add Move 580def VMM0 : ArithLogicR<"vmm0", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x10>, 581 ASE_CNMIPS { 582 let Defs = [MPL0, P0, P1, P2]; 583} 584 585// 64-bit Unsigned Multiply and Add 586def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x0f>, 587 ASE_CNMIPS { 588 let Defs = [MPL1, MPL2, P0, P1, P2]; 589} 590 591// Move between CPU and coprocessor registers 592def DMFC2_OCTEON : MFC2OP<"dmfc2", GPR64Opnd, II_DMFC2>, MFC2OP_FM<0x12, 1>, 593 ASE_CNMIPS; 594def DMTC2_OCTEON : MFC2OP<"dmtc2", GPR64Opnd, II_DMTC2>, MFC2OP_FM<0x12, 5>, 595 ASE_CNMIPS; 596} 597 598// Cavium Octeon+ cnMIPS instructions 599let DecoderNamespace = "CnMipsP", 600 // FIXME: The lack of HasStdEnc is probably a bug 601 EncodingPredicates = []<Predicate> in { 602 603class Saa<string opstr>: 604 InstSE<(outs), (ins GPR64Opnd:$rt, GPR64Opnd:$rs), 605 !strconcat(opstr, "\t$rt, (${rs})"), [], NoItinerary, FrmR, opstr>; 606 607def SAA : Saa<"saa">, SAA_FM<0x18>, ASE_CNMIPSP; 608def SAAD : Saa<"saad">, SAA_FM<0x19>, ASE_CNMIPSP; 609 610def SaaAddr : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rt, mem:$addr), 611 "saa\t$rt, $addr">, ASE_CNMIPSP; 612def SaadAddr : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rt, mem:$addr), 613 "saad\t$rt, $addr">, ASE_CNMIPSP; 614} 615 616} 617 618/// Move between CPU and coprocessor registers 619let DecoderNamespace = "Mips64" in { 620def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd, COP0Opnd, II_DMFC0>, 621 MFC3OP_FM<0x10, 1, 0>, ISA_MIPS3, GPR_64; 622def DMTC0 : MTC3OP<"dmtc0", COP0Opnd, GPR64Opnd, II_DMTC0>, 623 MFC3OP_FM<0x10, 5, 0>, ISA_MIPS3, GPR_64; 624def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd, COP2Opnd, II_DMFC2>, 625 MFC3OP_FM<0x12, 1, 0>, ISA_MIPS3, GPR_64; 626def DMTC2 : MTC3OP<"dmtc2", COP2Opnd, GPR64Opnd, II_DMTC2>, 627 MFC3OP_FM<0x12, 5, 0>, ISA_MIPS3, GPR_64; 628} 629 630/// Move between CPU and guest coprocessor registers (Virtualization ASE) 631let DecoderNamespace = "Mips64" in { 632 def DMFGC0 : MFC3OP<"dmfgc0", GPR64Opnd, COP0Opnd, II_DMFGC0>, 633 MFC3OP_FM<0x10, 3, 1>, ISA_MIPS64R5, ASE_VIRT; 634 def DMTGC0 : MTC3OP<"dmtgc0", COP0Opnd, GPR64Opnd, II_DMTGC0>, 635 MFC3OP_FM<0x10, 3, 3>, ISA_MIPS64R5, ASE_VIRT; 636} 637 638let AdditionalPredicates = [UseIndirectJumpsHazard] in 639 def JALRHB64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR_HB64, RA_64>, PTR_64; 640 641//===----------------------------------------------------------------------===// 642// Arbitrary patterns that map to one or more instructions 643//===----------------------------------------------------------------------===// 644 645// Materialize i64 constants. 646defm : MaterializeImms<i64, ZERO_64, DADDiu, LUi64, ORi64>, ISA_MIPS3, GPR_64; 647 648def : MipsPat<(i64 immZExt32Low16Zero:$imm), 649 (DSLL (ORi64 ZERO_64, (HI16 imm:$imm)), 16)>, ISA_MIPS3, GPR_64; 650 651def : MipsPat<(i64 immZExt32:$imm), 652 (ORi64 (DSLL (ORi64 ZERO_64, (HI16 imm:$imm)), 16), 653 (LO16 imm:$imm))>, ISA_MIPS3, GPR_64; 654 655// extended loads 656def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>, ISA_MIPS3, 657 GPR_64; 658def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>, ISA_MIPS3, 659 GPR_64; 660def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>, ISA_MIPS3, 661 GPR_64; 662def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>, ISA_MIPS3, 663 GPR_64; 664 665// hi/lo relocs 666let AdditionalPredicates = [NotInMicroMips] in 667defm : MipsHiLoRelocs<LUi64, DADDiu, ZERO_64, GPR64Opnd>, ISA_MIPS3, GPR_64, 668 SYM_32; 669 670def : MipsPat<(MipsGotHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>, ISA_MIPS3, 671 GPR_64; 672def : MipsPat<(MipsGotHi texternalsym:$in), (LUi64 texternalsym:$in)>, 673 ISA_MIPS3, GPR_64; 674 675def : MipsPat<(MipsTlsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>, 676 ISA_MIPS3, GPR_64; 677 678// highest/higher/hi/lo relocs 679let AdditionalPredicates = [NotInMicroMips] in { 680 def : MipsPat<(MipsJmpLink (i64 texternalsym:$dst)), 681 (JAL texternalsym:$dst)>, ISA_MIPS3, GPR_64, SYM_64; 682 683 def : MipsPat<(MipsHighest (i64 tglobaladdr:$in)), 684 (LUi64 tglobaladdr:$in)>, ISA_MIPS3, GPR_64, SYM_64; 685 def : MipsPat<(MipsHighest (i64 tblockaddress:$in)), 686 (LUi64 tblockaddress:$in)>, ISA_MIPS3, GPR_64, SYM_64; 687 def : MipsPat<(MipsHighest (i64 tjumptable:$in)), 688 (LUi64 tjumptable:$in)>, ISA_MIPS3, GPR_64, SYM_64; 689 def : MipsPat<(MipsHighest (i64 tconstpool:$in)), 690 (LUi64 tconstpool:$in)>, ISA_MIPS3, GPR_64, SYM_64; 691 def : MipsPat<(MipsHighest (i64 texternalsym:$in)), 692 (LUi64 texternalsym:$in)>, ISA_MIPS3, GPR_64, SYM_64; 693 694 def : MipsPat<(MipsHigher (i64 tglobaladdr:$in)), 695 (DADDiu ZERO_64, tglobaladdr:$in)>, ISA_MIPS3, GPR_64, SYM_64; 696 def : MipsPat<(MipsHigher (i64 tblockaddress:$in)), 697 (DADDiu ZERO_64, tblockaddress:$in)>, ISA_MIPS3, GPR_64, SYM_64; 698 def : MipsPat<(MipsHigher (i64 tjumptable:$in)), 699 (DADDiu ZERO_64, tjumptable:$in)>, ISA_MIPS3, GPR_64, SYM_64; 700 def : MipsPat<(MipsHigher (i64 tconstpool:$in)), 701 (DADDiu ZERO_64, tconstpool:$in)>, ISA_MIPS3, GPR_64, SYM_64; 702 def : MipsPat<(MipsHigher (i64 texternalsym:$in)), 703 (DADDiu ZERO_64, texternalsym:$in)>, ISA_MIPS3, GPR_64, SYM_64; 704 705 def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tglobaladdr:$lo))), 706 (DADDiu GPR64:$hi, tglobaladdr:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 707 def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tblockaddress:$lo))), 708 (DADDiu GPR64:$hi, tblockaddress:$lo)>, ISA_MIPS3, GPR_64, 709 SYM_64; 710 def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tjumptable:$lo))), 711 (DADDiu GPR64:$hi, tjumptable:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 712 def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tconstpool:$lo))), 713 (DADDiu GPR64:$hi, tconstpool:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 714 def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 texternalsym:$lo))), 715 (DADDiu GPR64:$hi, texternalsym:$lo)>, 716 ISA_MIPS3, GPR_64, SYM_64; 717 718 def : MipsPat<(MipsHi (i64 tglobaladdr:$in)), 719 (DADDiu ZERO_64, tglobaladdr:$in)>, ISA_MIPS3, GPR_64, SYM_64; 720 def : MipsPat<(MipsHi (i64 tblockaddress:$in)), 721 (DADDiu ZERO_64, tblockaddress:$in)>, ISA_MIPS3, GPR_64, SYM_64; 722 def : MipsPat<(MipsHi (i64 tjumptable:$in)), 723 (DADDiu ZERO_64, tjumptable:$in)>, ISA_MIPS3, GPR_64, SYM_64; 724 def : MipsPat<(MipsHi (i64 tconstpool:$in)), 725 (DADDiu ZERO_64, tconstpool:$in)>, ISA_MIPS3, GPR_64, SYM_64; 726 def : MipsPat<(MipsHi (i64 texternalsym:$in)), 727 (DADDiu ZERO_64, texternalsym:$in)>, ISA_MIPS3, GPR_64, SYM_64; 728 729 def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tglobaladdr:$lo))), 730 (DADDiu GPR64:$hi, tglobaladdr:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 731 def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tblockaddress:$lo))), 732 (DADDiu GPR64:$hi, tblockaddress:$lo)>, ISA_MIPS3, GPR_64, 733 SYM_64; 734 def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tjumptable:$lo))), 735 (DADDiu GPR64:$hi, tjumptable:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 736 def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tconstpool:$lo))), 737 (DADDiu GPR64:$hi, tconstpool:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 738 def : MipsPat<(add GPR64:$hi, (MipsHi (i64 texternalsym:$lo))), 739 (DADDiu GPR64:$hi, texternalsym:$lo)>, 740 ISA_MIPS3, GPR_64, SYM_64; 741 742 def : MipsPat<(MipsLo (i64 tglobaladdr:$in)), 743 (DADDiu ZERO_64, tglobaladdr:$in)>, ISA_MIPS3, GPR_64, SYM_64; 744 def : MipsPat<(MipsLo (i64 tblockaddress:$in)), 745 (DADDiu ZERO_64, tblockaddress:$in)>, ISA_MIPS3, GPR_64, SYM_64; 746 def : MipsPat<(MipsLo (i64 tjumptable:$in)), 747 (DADDiu ZERO_64, tjumptable:$in)>, ISA_MIPS3, GPR_64, SYM_64; 748 def : MipsPat<(MipsLo (i64 tconstpool:$in)), 749 (DADDiu ZERO_64, tconstpool:$in)>, ISA_MIPS3, GPR_64, SYM_64; 750 def : MipsPat<(MipsLo (i64 tglobaltlsaddr:$in)), 751 (DADDiu ZERO_64, tglobaltlsaddr:$in)>, 752 ISA_MIPS3, GPR_64, SYM_64; 753 def : MipsPat<(MipsLo (i64 texternalsym:$in)), 754 (DADDiu ZERO_64, texternalsym:$in)>, ISA_MIPS3, GPR_64, SYM_64; 755 756 def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tglobaladdr:$lo))), 757 (DADDiu GPR64:$hi, tglobaladdr:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 758 def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tblockaddress:$lo))), 759 (DADDiu GPR64:$hi, tblockaddress:$lo)>, ISA_MIPS3, GPR_64, 760 SYM_64; 761 def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tjumptable:$lo))), 762 (DADDiu GPR64:$hi, tjumptable:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 763 def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tconstpool:$lo))), 764 (DADDiu GPR64:$hi, tconstpool:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 765 def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tglobaltlsaddr:$lo))), 766 (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>, ISA_MIPS3, GPR_64, 767 SYM_64; 768 def : MipsPat<(add GPR64:$hi, (MipsLo (i64 texternalsym:$lo))), 769 (DADDiu GPR64:$hi, texternalsym:$lo)>, 770 ISA_MIPS3, GPR_64, SYM_64; 771} 772 773// gp_rel relocs 774def : MipsPat<(add GPR64:$gp, (MipsGPRel tglobaladdr:$in)), 775 (DADDiu GPR64:$gp, tglobaladdr:$in)>, ISA_MIPS3, ABI_N64; 776def : MipsPat<(add GPR64:$gp, (MipsGPRel tconstpool:$in)), 777 (DADDiu GPR64:$gp, tconstpool:$in)>, ISA_MIPS3, ABI_N64; 778 779def : WrapperPat<tglobaladdr, DADDiu, GPR64>, ISA_MIPS3, GPR_64; 780def : WrapperPat<tconstpool, DADDiu, GPR64>, ISA_MIPS3, GPR_64; 781def : WrapperPat<texternalsym, DADDiu, GPR64>, ISA_MIPS3, GPR_64; 782def : WrapperPat<tblockaddress, DADDiu, GPR64>, ISA_MIPS3, GPR_64; 783def : WrapperPat<tjumptable, DADDiu, GPR64>, ISA_MIPS3, GPR_64; 784def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>, ISA_MIPS3, GPR_64; 785 786 787defm : BrcondPats<GPR64, BEQ64, BEQ, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, 788 ZERO_64>, ISA_MIPS3, GPR_64; 789def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst), 790 (BLEZ64 i64:$lhs, bb:$dst)>, ISA_MIPS3, GPR_64; 791def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst), 792 (BGEZ64 i64:$lhs, bb:$dst)>, ISA_MIPS3, GPR_64; 793 794// setcc patterns 795let AdditionalPredicates = [NotInMicroMips] in { 796 defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>, ISA_MIPS3, GPR_64; 797 defm : SetlePats<GPR64, XORi, SLT64, SLTu64>, ISA_MIPS3, GPR_64; 798 defm : SetgtPats<GPR64, SLT64, SLTu64>, ISA_MIPS3, GPR_64; 799 defm : SetgePats<GPR64, XORi, SLT64, SLTu64>, ISA_MIPS3, GPR_64; 800 defm : SetgeImmPats<GPR64, XORi, SLTi64, SLTiu64>, ISA_MIPS3, GPR_64; 801} 802// truncate 803def : MipsPat<(trunc (assertsext GPR64:$src)), 804 (EXTRACT_SUBREG GPR64:$src, sub_32)>, ISA_MIPS3, GPR_64; 805// The forward compatibility strategy employed by MIPS requires us to treat 806// values as being sign extended to an infinite number of bits. This allows 807// existing software to run without modification on any future MIPS 808// implementation (e.g. 128-bit, or 1024-bit). Being compatible with this 809// strategy requires that truncation acts as a sign-extension for values being 810// fed into instructions operating on 32-bit values. Such instructions have 811// undefined results if this is not true. 812// For our case, this means that we can't issue an extract_subreg for nodes 813// such as (trunc:i32 (assertzext:i64 X, i32)), because the sign-bit of the 814// lower subreg would not be replicated into the upper half. 815def : MipsPat<(trunc (assertzext_lt_i32 GPR64:$src)), 816 (EXTRACT_SUBREG GPR64:$src, sub_32)>, ISA_MIPS3, GPR_64; 817def : MipsPat<(i32 (trunc GPR64:$src)), 818 (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>, ISA_MIPS3, GPR_64; 819 820// variable shift instructions patterns 821def : MipsPat<(shl GPR64:$rt, (i32 (trunc GPR64:$rs))), 822 (DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>, 823 ISA_MIPS3, GPR_64; 824def : MipsPat<(srl GPR64:$rt, (i32 (trunc GPR64:$rs))), 825 (DSRLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>, 826 ISA_MIPS3, GPR_64; 827def : MipsPat<(sra GPR64:$rt, (i32 (trunc GPR64:$rs))), 828 (DSRAV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>, 829 ISA_MIPS3, GPR_64; 830def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))), 831 (DROTRV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>, 832 ISA_MIPS3, GPR_64; 833 834// 32-to-64-bit extension 835def : MipsPat<(i64 (anyext GPR32:$src)), 836 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>, 837 ISA_MIPS3, GPR_64; 838def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>, 839 ISA_MIPS3, GPR_64; 840def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>, ISA_MIPS3, 841 GPR_64; 842 843let AdditionalPredicates = [NotInMicroMips] in { 844 def : MipsPat<(i64 (zext GPR32:$src)), (DEXT64_32 GPR32:$src, 0, 32)>, 845 ISA_MIPS64R2, GPR_64; 846 def : MipsPat<(i64 (zext (i32 (shl GPR32:$rt, immZExt5:$imm)))), 847 (CINS64_32 GPR32:$rt, imm:$imm, (immZExt5To31 imm:$imm))>, 848 ISA_MIPS64R2, GPR_64, ASE_MIPS64_CNMIPS; 849} 850 851// Sign extend in register 852def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)), 853 (SLL64_64 GPR64:$src)>, ISA_MIPS3, GPR_64; 854 855// bswap MipsPattern 856def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>, ISA_MIPS64R2; 857 858// Carry pattern 859let AdditionalPredicates = [NotInMicroMips] in { 860 def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs), 861 (DSUBu GPR64:$lhs, GPR64:$rhs)>, ISA_MIPS3, GPR_64; 862 def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs), 863 (DADDu GPR64:$lhs, GPR64:$rhs)>, ISA_MIPS3, ASE_NOT_DSP, GPR_64; 864 def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm), 865 (DADDiu GPR64:$lhs, imm:$imm)>, ISA_MIPS3, ASE_NOT_DSP, GPR_64; 866} 867 868// Octeon bbit0/bbit1 MipsPattern 869def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst), 870 (BBIT0 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, 871 ISA_MIPS64R2, ASE_MIPS64_CNMIPS; 872def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst), 873 (BBIT032 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, 874 ISA_MIPS64R2, ASE_MIPS64_CNMIPS; 875def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst), 876 (BBIT1 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, 877 ISA_MIPS64R2, ASE_MIPS64_CNMIPS; 878def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst), 879 (BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, 880 ISA_MIPS64R2, ASE_MIPS64_CNMIPS; 881def : MipsPat<(brcond (i32 (seteq (and i32:$lhs, PowerOf2LO_i32:$mask), 0)), bb:$dst), 882 (BBIT0 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$lhs, sub_32), 883 (Log2LO PowerOf2LO_i32:$mask), bb:$dst)>, ISA_MIPS64R2, 884 ASE_MIPS64_CNMIPS; 885def : MipsPat<(brcond (i32 (setne (and i32:$lhs, PowerOf2LO_i32:$mask), 0)), bb:$dst), 886 (BBIT1 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$lhs, sub_32), 887 (Log2LO PowerOf2LO_i32:$mask), bb:$dst)>, ISA_MIPS64R2, 888 ASE_MIPS64_CNMIPS; 889 890// Atomic load patterns. 891def : MipsPat<(atomic_load_8 addr:$a), (LB64 addr:$a)>, ISA_MIPS3, GPR_64; 892def : MipsPat<(atomic_load_16 addr:$a), (LH64 addr:$a)>, ISA_MIPS3, GPR_64; 893def : MipsPat<(atomic_load_32 addr:$a), (LW64 addr:$a)>, ISA_MIPS3, GPR_64; 894def : MipsPat<(atomic_load_64 addr:$a), (LD addr:$a)>, ISA_MIPS3, GPR_64; 895 896// Atomic store patterns. 897def : MipsPat<(atomic_store_8 GPR64:$v, addr:$a), (SB64 GPR64:$v, addr:$a)>, 898 ISA_MIPS3, GPR_64; 899def : MipsPat<(atomic_store_16 GPR64:$v, addr:$a), (SH64 GPR64:$v, addr:$a)>, 900 ISA_MIPS3, GPR_64; 901def : MipsPat<(atomic_store_32 GPR64:$v, addr:$a), (SW64 GPR64:$v, addr:$a)>, 902 ISA_MIPS3, GPR_64; 903def : MipsPat<(atomic_store_64 GPR64:$v, addr:$a), (SD GPR64:$v, addr:$a)>, 904 ISA_MIPS3, GPR_64; 905 906// Patterns used for matching away redundant sign extensions. 907// MIPS32 arithmetic instructions sign extend their result implicitly. 908def : MipsPat<(i64 (sext (i32 (add GPR32:$src, immSExt16:$imm16)))), 909 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 910 (ADDiu GPR32:$src, immSExt16:$imm16), sub_32)>; 911def : MipsPat<(i64 (sext (i32 (add GPR32:$src, GPR32:$src2)))), 912 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 913 (ADDu GPR32:$src, GPR32:$src2), sub_32)>; 914def : MipsPat<(i64 (sext (i32 (sub GPR32:$src, GPR32:$src2)))), 915 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 916 (SUBu GPR32:$src, GPR32:$src2), sub_32)>; 917def : MipsPat<(i64 (sext (i32 (mul GPR32:$src, GPR32:$src2)))), 918 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 919 (MUL GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS32_NOT_32R6_64R6; 920def : MipsPat<(i64 (sext (i32 (MipsMFHI ACC64:$src)))), 921 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 922 (PseudoMFHI ACC64:$src), sub_32)>; 923def : MipsPat<(i64 (sext (i32 (MipsMFLO ACC64:$src)))), 924 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 925 (PseudoMFLO ACC64:$src), sub_32)>; 926def : MipsPat<(i64 (sext (i32 (shl GPR32:$src, immZExt5:$imm5)))), 927 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 928 (SLL GPR32:$src, immZExt5:$imm5), sub_32)>; 929def : MipsPat<(i64 (sext (i32 (shl GPR32:$src, GPR32:$src2)))), 930 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 931 (SLLV GPR32:$src, GPR32:$src2), sub_32)>; 932def : MipsPat<(i64 (sext (i32 (srl GPR32:$src, immZExt5:$imm5)))), 933 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 934 (SRL GPR32:$src, immZExt5:$imm5), sub_32)>; 935def : MipsPat<(i64 (sext (i32 (srl GPR32:$src, GPR32:$src2)))), 936 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 937 (SRLV GPR32:$src, GPR32:$src2), sub_32)>; 938def : MipsPat<(i64 (sext (i32 (sra GPR32:$src, immZExt5:$imm5)))), 939 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 940 (SRA GPR32:$src, immZExt5:$imm5), sub_32)>; 941def : MipsPat<(i64 (sext (i32 (sra GPR32:$src, GPR32:$src2)))), 942 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 943 (SRAV GPR32:$src, GPR32:$src2), sub_32)>; 944 945//===----------------------------------------------------------------------===// 946// Instruction aliases 947//===----------------------------------------------------------------------===// 948let AdditionalPredicates = [NotInMicroMips] in { 949 def : MipsInstAlias<"move $dst, $src", 950 (OR64 GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>, 951 GPR_64; 952 def : MipsInstAlias<"move $dst, $src", 953 (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>, 954 GPR_64; 955 def : MipsInstAlias<"dadd $rs, $rt, $imm", 956 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm), 957 0>, ISA_MIPS3_NOT_32R6_64R6; 958 def : MipsInstAlias<"dadd $rs, $imm", 959 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm), 960 0>, ISA_MIPS3_NOT_32R6_64R6; 961 def : MipsInstAlias<"daddu $rs, $rt, $imm", 962 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm), 963 0>, ISA_MIPS3; 964 def : MipsInstAlias<"daddu $rs, $imm", 965 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm), 966 0>, ISA_MIPS3; 967 968 defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi64, GPR64Opnd, imm64>, 969 ISA_MIPS3, GPR_64; 970 971 defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi64, GPR64Opnd, imm64>, 972 ISA_MIPS3, GPR_64; 973 974 defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi64, GPR64Opnd, imm64>, 975 ISA_MIPS3, GPR_64; 976} 977let AdditionalPredicates = [NotInMicroMips] in { 978 def : MipsInstAlias<"dneg $rt, $rs", 979 (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>, 980 ISA_MIPS3; 981 def : MipsInstAlias<"dneg $rt", 982 (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>, 983 ISA_MIPS3; 984 def : MipsInstAlias<"dnegu $rt, $rs", 985 (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>, 986 ISA_MIPS3; 987 def : MipsInstAlias<"dnegu $rt", 988 (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>, 989 ISA_MIPS3; 990} 991def : MipsInstAlias<"dsubi $rs, $rt, $imm", 992 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, 993 InvertedImOperand64:$imm), 994 0>, ISA_MIPS3_NOT_32R6_64R6; 995def : MipsInstAlias<"dsubi $rs, $imm", 996 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, 997 InvertedImOperand64:$imm), 998 0>, ISA_MIPS3_NOT_32R6_64R6; 999def : MipsInstAlias<"dsub $rs, $rt, $imm", 1000 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, 1001 InvertedImOperand64:$imm), 1002 0>, ISA_MIPS3_NOT_32R6_64R6; 1003def : MipsInstAlias<"dsub $rs, $imm", 1004 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, 1005 InvertedImOperand64:$imm), 1006 0>, ISA_MIPS3_NOT_32R6_64R6; 1007let AdditionalPredicates = [NotInMicroMips] in { 1008 def : MipsInstAlias<"dsubu $rt, $rs, $imm", 1009 (DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs, 1010 InvertedImOperand64:$imm), 0>, ISA_MIPS3; 1011 def : MipsInstAlias<"dsubu $rs, $imm", 1012 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, 1013 InvertedImOperand64:$imm), 0>, ISA_MIPS3; 1014} 1015def : MipsInstAlias<"dsra $rd, $rt, $rs", 1016 (DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>, 1017 ISA_MIPS3; 1018let AdditionalPredicates = [NotInMicroMips] in { 1019 def : MipsInstAlias<"dsll $rd, $rt, $rs", 1020 (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>, 1021 ISA_MIPS3; 1022 def : MipsInstAlias<"dsrl $rd, $rt, $rs", 1023 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>, 1024 ISA_MIPS3; 1025 def : MipsInstAlias<"dsrl $rd, $rt", 1026 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rd, GPR32Opnd:$rt), 0>, 1027 ISA_MIPS3; 1028 def : MipsInstAlias<"dsll $rd, $rt", 1029 (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rd, GPR32Opnd:$rt), 0>, 1030 ISA_MIPS3; 1031 def : MipsInstAlias<"dins $rt, $rs, $pos, $size", 1032 (DINSM GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5:$pos, 1033 uimm_range_2_64:$size), 0>, ISA_MIPS64R2; 1034 def : MipsInstAlias<"dins $rt, $rs, $pos, $size", 1035 (DINSU GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5_plus32:$pos, 1036 uimm5_plus1:$size), 0>, ISA_MIPS64R2; 1037 def : MipsInstAlias<"dext $rt, $rs, $pos, $size", 1038 (DEXTM GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5:$pos, 1039 uimm5_plus33:$size), 0>, ISA_MIPS64R2; 1040 def : MipsInstAlias<"dext $rt, $rs, $pos, $size", 1041 (DEXTU GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5_plus32:$pos, 1042 uimm5_plus1:$size), 0>, ISA_MIPS64R2; 1043 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB64 RA_64, GPR64Opnd:$rs), 1>, 1044 ISA_MIPS64; 1045// Two operand (implicit 0 selector) versions: 1046 def : MipsInstAlias<"dmtc0 $rt, $rd", 1047 (DMTC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>; 1048 def : MipsInstAlias<"dmfc0 $rt, $rd", 1049 (DMFC0 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>; 1050 def : MipsInstAlias<"dmfgc0 $rt, $rd", 1051 (DMFGC0 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>, 1052 ISA_MIPS64R5, ASE_VIRT; 1053 def : MipsInstAlias<"dmtgc0 $rt, $rd", 1054 (DMTGC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>, 1055 ISA_MIPS64R5, ASE_VIRT; 1056} 1057def : MipsInstAlias<"dmfc2 $rt, $rd", 1058 (DMFC2 GPR64Opnd:$rt, COP2Opnd:$rd, 0), 0>; 1059def : MipsInstAlias<"dmtc2 $rt, $rd", 1060 (DMTC2 COP2Opnd:$rd, GPR64Opnd:$rt, 0), 0>; 1061 1062def : MipsInstAlias<"synciobdma", (SYNC 0x2), 0>, ASE_MIPS64_CNMIPS; 1063def : MipsInstAlias<"syncs", (SYNC 0x6), 0>, ASE_MIPS64_CNMIPS; 1064def : MipsInstAlias<"syncw", (SYNC 0x4), 0>, ASE_MIPS64_CNMIPS; 1065def : MipsInstAlias<"syncws", (SYNC 0x5), 0>, ASE_MIPS64_CNMIPS; 1066 1067// cnMIPS Aliases. 1068 1069// bbit* with $p 32-63 converted to bbit*32 with $p 0-31 1070def : MipsInstAlias<"bbit0 $rs, $p, $offset", 1071 (BBIT032 GPR64Opnd:$rs, uimm5_plus32_normalize_64:$p, 1072 brtarget:$offset), 0>, 1073 ASE_CNMIPS; 1074def : MipsInstAlias<"bbit1 $rs, $p, $offset", 1075 (BBIT132 GPR64Opnd:$rs, uimm5_plus32_normalize_64:$p, 1076 brtarget:$offset), 0>, 1077 ASE_CNMIPS; 1078 1079// exts with $pos 32-63 in converted to exts32 with $pos 0-31 1080def : MipsInstAlias<"exts $rt, $rs, $pos, $lenm1", 1081 (EXTS32 GPR64Opnd:$rt, GPR64Opnd:$rs, 1082 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, 1083 ASE_MIPS64_CNMIPS; 1084def : MipsInstAlias<"exts $rt, $pos, $lenm1", 1085 (EXTS32 GPR64Opnd:$rt, GPR64Opnd:$rt, 1086 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, 1087 ASE_MIPS64_CNMIPS; 1088 1089// cins with $pos 32-63 in converted to cins32 with $pos 0-31 1090def : MipsInstAlias<"cins $rt, $rs, $pos, $lenm1", 1091 (CINS32 GPR64Opnd:$rt, GPR64Opnd:$rs, 1092 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, 1093 ASE_MIPS64_CNMIPS; 1094def : MipsInstAlias<"cins $rt, $pos, $lenm1", 1095 (CINS32 GPR64Opnd:$rt, GPR64Opnd:$rt, 1096 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, 1097 ASE_MIPS64_CNMIPS; 1098 1099//===----------------------------------------------------------------------===// 1100// Assembler Pseudo Instructions 1101//===----------------------------------------------------------------------===// 1102 1103class LoadImmediate64<string instr_asm, Operand Od, RegisterOperand RO> : 1104 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm64), 1105 !strconcat(instr_asm, "\t$rt, $imm64")> ; 1106def LoadImm64 : LoadImmediate64<"dli", imm64, GPR64Opnd>; 1107 1108def LoadAddrReg64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rt), (ins mem:$addr), 1109 "dla\t$rt, $addr">; 1110def LoadAddrImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rt), (ins imm64:$imm64), 1111 "dla\t$rt, $imm64">; 1112 1113def DMULImmMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt, 1114 simm32_relaxed:$imm), 1115 "dmul\t$rs, $rt, $imm">, 1116 ISA_MIPS3_NOT_32R6_64R6; 1117def DMULOMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt, 1118 GPR64Opnd:$rd), 1119 "dmulo\t$rs, $rt, $rd">, 1120 ISA_MIPS3_NOT_32R6_64R6; 1121def DMULOUMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt, 1122 GPR64Opnd:$rd), 1123 "dmulou\t$rs, $rt, $rd">, 1124 ISA_MIPS3_NOT_32R6_64R6; 1125 1126def DMULMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt, 1127 GPR64Opnd:$rd), 1128 "dmul\t$rs, $rt, $rd"> { 1129 let InsnPredicates = [HasMips3, NotMips64r6, NotCnMips]; 1130} 1131 1132let AdditionalPredicates = [NotInMicroMips] in { 1133 def DSDivMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1134 (ins GPR64Opnd:$rs, GPR64Opnd:$rt), 1135 "ddiv\t$rd, $rs, $rt">, 1136 ISA_MIPS3_NOT_32R6_64R6; 1137 def DSDivIMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1138 (ins GPR64Opnd:$rs, imm64:$imm), 1139 "ddiv\t$rd, $rs, $imm">, 1140 ISA_MIPS3_NOT_32R6_64R6; 1141 def DUDivMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1142 (ins GPR64Opnd:$rs, GPR64Opnd:$rt), 1143 "ddivu\t$rd, $rs, $rt">, 1144 ISA_MIPS3_NOT_32R6_64R6; 1145 def DUDivIMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1146 (ins GPR64Opnd:$rs, imm64:$imm), 1147 "ddivu\t$rd, $rs, $imm">, 1148 ISA_MIPS3_NOT_32R6_64R6; 1149 1150 // GAS expands 'div' and 'ddiv' differently when the destination 1151 // register is $zero and the instruction is in the two operand 1152 // form. 'ddiv' gets expanded, while 'div' is not expanded. 1153 1154 def : MipsInstAlias<"ddiv $rs, $rt", (DSDivMacro GPR64Opnd:$rs, 1155 GPR64Opnd:$rs, 1156 GPR64Opnd:$rt), 0>, 1157 ISA_MIPS3_NOT_32R6_64R6; 1158 def : MipsInstAlias<"ddiv $rd, $imm", (DSDivIMacro GPR64Opnd:$rd, 1159 GPR64Opnd:$rd, 1160 imm64:$imm), 0>, 1161 ISA_MIPS3_NOT_32R6_64R6; 1162 1163 // GAS expands 'divu' and 'ddivu' differently when the destination 1164 // register is $zero and the instruction is in the two operand 1165 // form. 'ddivu' gets expanded, while 'divu' is not expanded. 1166 1167 def : MipsInstAlias<"ddivu $rt, $rs", (DUDivMacro GPR64Opnd:$rt, 1168 GPR64Opnd:$rt, 1169 GPR64Opnd:$rs), 0>, 1170 ISA_MIPS3_NOT_32R6_64R6; 1171 def : MipsInstAlias<"ddivu $rd, $imm", (DUDivIMacro GPR64Opnd:$rd, 1172 GPR64Opnd:$rd, 1173 imm64:$imm), 0>, 1174 ISA_MIPS3_NOT_32R6_64R6; 1175 def DSRemMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1176 (ins GPR64Opnd:$rs, GPR64Opnd:$rt), 1177 "drem\t$rd, $rs, $rt">, 1178 ISA_MIPS3_NOT_32R6_64R6; 1179 def DSRemIMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1180 (ins GPR64Opnd:$rs, simm32_relaxed:$imm), 1181 "drem\t$rd, $rs, $imm">, 1182 ISA_MIPS3_NOT_32R6_64R6; 1183 def DURemMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1184 (ins GPR64Opnd:$rs, GPR64Opnd:$rt), 1185 "dremu\t$rd, $rs, $rt">, 1186 ISA_MIPS3_NOT_32R6_64R6; 1187 def DURemIMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1188 (ins GPR64Opnd:$rs, simm32_relaxed:$imm), 1189 "dremu\t$rd, $rs, $imm">, 1190 ISA_MIPS3_NOT_32R6_64R6; 1191 def : MipsInstAlias<"drem $rt, $rs", (DSRemMacro GPR64Opnd:$rt, 1192 GPR64Opnd:$rt, 1193 GPR64Opnd:$rs), 0>, 1194 ISA_MIPS3_NOT_32R6_64R6; 1195 def : MipsInstAlias<"drem $rd, $imm", (DSRemIMacro GPR64Opnd:$rd, 1196 GPR64Opnd:$rd, 1197 simm32_relaxed:$imm), 0>, 1198 ISA_MIPS3_NOT_32R6_64R6; 1199 def : MipsInstAlias<"dremu $rt, $rs", (DURemMacro GPR64Opnd:$rt, 1200 GPR64Opnd:$rt, 1201 GPR64Opnd:$rs), 0>, 1202 ISA_MIPS3_NOT_32R6_64R6; 1203 def : MipsInstAlias<"dremu $rd, $imm", (DURemIMacro GPR64Opnd:$rd, 1204 GPR64Opnd:$rd, 1205 simm32_relaxed:$imm), 0>, 1206 ISA_MIPS3_NOT_32R6_64R6; 1207} 1208 1209def NORImm64 : NORIMM_DESC_BASE<GPR64Opnd, imm64>, GPR_64; 1210def : MipsInstAlias<"nor\t$rs, $imm", (NORImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, 1211 imm64:$imm)>, GPR_64; 1212def SLTImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rs), 1213 (ins GPR64Opnd:$rt, imm64:$imm), 1214 "slt\t$rs, $rt, $imm">, GPR_64; 1215def : MipsInstAlias<"slt\t$rs, $imm", (SLTImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, 1216 imm64:$imm)>, GPR_64; 1217def SLTUImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rs), 1218 (ins GPR64Opnd:$rt, imm64:$imm), 1219 "sltu\t$rs, $rt, $imm">, GPR_64; 1220def : MipsInstAlias<"sltu\t$rs, $imm", (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, 1221 imm64:$imm)>, GPR_64; 1222 1223def SGEImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1224 (ins GPR64Opnd:$rs, imm64:$imm), 1225 "sge\t$rd, $rs, $imm">, GPR_64; 1226def : MipsInstAlias<"sge $rs, $imm", (SGEImm64 GPR64Opnd:$rs, 1227 GPR64Opnd:$rs, 1228 imm64:$imm), 0>, GPR_64; 1229 1230def SGEUImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1231 (ins GPR64Opnd:$rs, imm64:$imm), 1232 "sgeu\t$rd, $rs, $imm">, GPR_64; 1233def : MipsInstAlias<"sgeu $rs, $imm", (SGEUImm64 GPR64Opnd:$rs, 1234 GPR64Opnd:$rs, 1235 imm64:$imm), 0>, GPR_64; 1236 1237def SGTImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1238 (ins GPR64Opnd:$rs, imm64:$imm), 1239 "sgt\t$rd, $rs, $imm">, GPR_64; 1240def : MipsInstAlias<"sgt $rs, $imm", (SGTImm64 GPR64Opnd:$rs, 1241 GPR64Opnd:$rs, 1242 imm64:$imm), 0>, GPR_64; 1243 1244def SGTUImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1245 (ins GPR64Opnd:$rs, imm64:$imm), 1246 "sgtu\t$rd, $rs, $imm">, GPR_64; 1247def : MipsInstAlias<"sgtu $rs, $imm", (SGTUImm64 GPR64Opnd:$rs, 1248 GPR64Opnd:$rs, 1249 imm64:$imm), 0>, GPR_64; 1250 1251def SLEImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1252 (ins GPR64Opnd:$rs, imm64:$imm), 1253 "sle\t$rd, $rs, $imm">, GPR_64; 1254def : MipsInstAlias<"sle $rs, $imm", (SLEImm64 GPR64Opnd:$rs, 1255 GPR64Opnd:$rs, 1256 imm64:$imm), 0>, GPR_64; 1257 1258def SLEUImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1259 (ins GPR64Opnd:$rs, imm64:$imm), 1260 "sleu\t$rd, $rs, $imm">, GPR_64; 1261def : MipsInstAlias<"sleu $rs, $imm", (SLEUImm64 GPR64Opnd:$rs, 1262 GPR64Opnd:$rs, 1263 imm64:$imm), 0>, GPR_64; 1264 1265def : MipsInstAlias<"rdhwr $rt, $rs", 1266 (RDHWR64 GPR64Opnd:$rt, HWRegsOpnd:$rs, 0), 1>, GPR_64; 1267