1//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes Mips64 instructions. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Mips Operand, Complex Patterns and Transformations Definitions. 15//===----------------------------------------------------------------------===// 16 17// shamt must fit in 6 bits. 18def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>; 19 20// Node immediate fits as 10-bit sign extended on target immediate. 21// e.g. seqi, snei 22def immSExt10_64 : PatLeaf<(i64 imm), 23 [{ return isInt<10>(N->getSExtValue()); }]>; 24 25def immZExt16_64 : PatLeaf<(i64 imm), 26 [{ return isUInt<16>(N->getZExtValue()); }]>; 27 28def immZExt5_64 : ImmLeaf<i64, [{ return Imm == (Imm & 0x1f); }]>; 29 30// Transformation function: get log2 of low 32 bits of immediate 31def Log2LO : SDNodeXForm<imm, [{ 32 return getImm(N, Log2_64((unsigned) N->getZExtValue())); 33}]>; 34 35// Transformation function: get log2 of high 32 bits of immediate 36def Log2HI : SDNodeXForm<imm, [{ 37 return getImm(N, Log2_64((unsigned) (N->getZExtValue() >> 32))); 38}]>; 39 40// Predicate: True if immediate is a power of 2 and fits 32 bits 41def PowerOf2LO : PatLeaf<(imm), [{ 42 if (N->getValueType(0) == MVT::i64) { 43 uint64_t Imm = N->getZExtValue(); 44 return isPowerOf2_64(Imm) && (Imm & 0xffffffff) == Imm; 45 } 46 else 47 return false; 48}]>; 49 50// Predicate: True if immediate is a power of 2 and exceeds 32 bits 51def PowerOf2HI : PatLeaf<(imm), [{ 52 if (N->getValueType(0) == MVT::i64) { 53 uint64_t Imm = N->getZExtValue(); 54 return isPowerOf2_64(Imm) && (Imm & 0xffffffff00000000) == Imm; 55 } 56 else 57 return false; 58}]>; 59 60def PowerOf2LO_i32 : PatLeaf<(imm), [{ 61 if (N->getValueType(0) == MVT::i32) { 62 uint64_t Imm = N->getZExtValue(); 63 return isPowerOf2_32(Imm) && isUInt<32>(Imm); 64 } 65 else 66 return false; 67}]>; 68 69def assertzext_lt_i32 : PatFrag<(ops node:$src), (assertzext node:$src), [{ 70 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLT(MVT::i32); 71}]>; 72 73//===----------------------------------------------------------------------===// 74// Instructions specific format 75//===----------------------------------------------------------------------===// 76let usesCustomInserter = 1 in { 77 def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>; 78 def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>; 79 def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>; 80 def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>; 81 def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>; 82 def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>; 83 def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>; 84 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>; 85} 86 87def ATOMIC_LOAD_ADD_I64_POSTRA : Atomic2OpsPostRA<GPR64>; 88def ATOMIC_LOAD_SUB_I64_POSTRA : Atomic2OpsPostRA<GPR64>; 89def ATOMIC_LOAD_AND_I64_POSTRA : Atomic2OpsPostRA<GPR64>; 90def ATOMIC_LOAD_OR_I64_POSTRA : Atomic2OpsPostRA<GPR64>; 91def ATOMIC_LOAD_XOR_I64_POSTRA : Atomic2OpsPostRA<GPR64>; 92def ATOMIC_LOAD_NAND_I64_POSTRA : Atomic2OpsPostRA<GPR64>; 93 94def ATOMIC_SWAP_I64_POSTRA : Atomic2OpsPostRA<GPR64>; 95 96def ATOMIC_CMP_SWAP_I64_POSTRA : AtomicCmpSwapPostRA<GPR64>; 97 98/// Pseudo instructions for loading and storing accumulator registers. 99let isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in { 100 def LOAD_ACC128 : Load<"", ACC128>; 101 def STORE_ACC128 : Store<"", ACC128>; 102} 103 104//===----------------------------------------------------------------------===// 105// Instruction definition 106//===----------------------------------------------------------------------===// 107let DecoderNamespace = "Mips64" in { 108/// Arithmetic Instructions (ALU Immediate) 109def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd, II_DADDI>, 110 ADDI_FM<0x18>, ISA_MIPS3_NOT_32R6_64R6; 111let AdditionalPredicates = [NotInMicroMips] in { 112 def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU, 113 immSExt16, add>, 114 ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3; 115} 116 117let isCodeGenOnly = 1 in { 118def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>, 119 SLTI_FM<0xa>, GPR_64; 120def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>, 121 SLTI_FM<0xb>, GPR_64; 122def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>, 123 ADDI_FM<0xc>, GPR_64; 124def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>, 125 ADDI_FM<0xd>, GPR_64; 126def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>, 127 ADDI_FM<0xe>, GPR_64; 128def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64_relaxed>, LUI_FM, GPR_64; 129} 130 131/// Arithmetic Instructions (3-Operand, R-Type) 132let AdditionalPredicates = [NotInMicroMips] in { 133 def DADD : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>, 134 ISA_MIPS3; 135 def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>, 136 ADD_FM<0, 0x2d>, ISA_MIPS3; 137 def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, 138 ADD_FM<0, 0x2f>, ISA_MIPS3; 139 def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>, 140 ISA_MIPS3; 141} 142 143let isCodeGenOnly = 1 in { 144def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>, GPR_64; 145def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>, GPR_64; 146def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>, 147 GPR_64; 148def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>, 149 GPR_64; 150def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>, 151 GPR_64; 152def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>, GPR_64; 153} 154 155/// Shift Instructions 156let AdditionalPredicates = [NotInMicroMips] in { 157 def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, 158 immZExt6>, 159 SRA_FM<0x38, 0>, ISA_MIPS3; 160 def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, 161 immZExt6>, 162 SRA_FM<0x3a, 0>, ISA_MIPS3; 163 def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, 164 immZExt6>, 165 SRA_FM<0x3b, 0>, ISA_MIPS3; 166 def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>, 167 SRLV_FM<0x14, 0>, ISA_MIPS3; 168 def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>, 169 SRLV_FM<0x17, 0>, ISA_MIPS3; 170 def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>, 171 SRLV_FM<0x16, 0>, ISA_MIPS3; 172 def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>, 173 SRA_FM<0x3c, 0>, ISA_MIPS3; 174 def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>, 175 SRA_FM<0x3e, 0>, ISA_MIPS3; 176 def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>, 177 SRA_FM<0x3f, 0>, ISA_MIPS3; 178 179// Rotate Instructions 180 def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr, 181 immZExt6>, 182 SRA_FM<0x3a, 1>, ISA_MIPS64R2; 183 def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>, 184 SRLV_FM<0x16, 1>, ISA_MIPS64R2; 185 def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>, 186 SRA_FM<0x3e, 1>, ISA_MIPS64R2; 187} 188 189/// Load and Store Instructions 190/// aligned 191let isCodeGenOnly = 1 in { 192def LB64 : Load<"lb", GPR64Opnd, sextloadi8, II_LB>, LW_FM<0x20>, GPR_64; 193def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>, GPR_64; 194def LH64 : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>, GPR_64; 195def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>, GPR_64; 196def LW64 : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>, GPR_64; 197def SB64 : Store<"sb", GPR64Opnd, truncstorei8, II_SB>, LW_FM<0x28>, GPR_64; 198def SH64 : Store<"sh", GPR64Opnd, truncstorei16, II_SH>, LW_FM<0x29>, 199 GPR_64; 200def SW64 : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>, 201 GPR_64; 202} 203 204let AdditionalPredicates = [NotInMicroMips] in { 205 def LWu : MMRel, Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, 206 LW_FM<0x27>, ISA_MIPS3; 207 def LD : LoadMemory<"ld", GPR64Opnd, mem_simmptr, load, II_LD>, 208 LW_FM<0x37>, ISA_MIPS3; 209 def SD : StoreMemory<"sd", GPR64Opnd, mem_simmptr, store, II_SD>, 210 LW_FM<0x3f>, ISA_MIPS3; 211} 212 213 214 215/// load/store left/right 216let isCodeGenOnly = 1 in { 217def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, II_LWL>, LW_FM<0x22>, 218 GPR_64; 219def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, II_LWR>, LW_FM<0x26>, 220 GPR_64; 221def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, II_SWL>, LW_FM<0x2a>, 222 GPR_64; 223def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, II_SWR>, LW_FM<0x2e>, 224 GPR_64; 225} 226 227def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>, 228 ISA_MIPS3_NOT_32R6_64R6; 229def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>, 230 ISA_MIPS3_NOT_32R6_64R6; 231def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, II_SDL>, LW_FM<0x2c>, 232 ISA_MIPS3_NOT_32R6_64R6; 233def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>, 234 ISA_MIPS3_NOT_32R6_64R6; 235 236/// Load-linked, Store-conditional 237let AdditionalPredicates = [NotInMicroMips] in { 238 def LLD : LLBase<"lld", GPR64Opnd, mem_simmptr>, LW_FM<0x34>, 239 ISA_MIPS3_NOT_32R6_64R6; 240} 241def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6; 242 243let AdditionalPredicates = [NotInMicroMips], 244 DecoderNamespace = "Mips32_64_PTR64" in { 245def LL64 : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, PTR_64, 246 ISA_MIPS2_NOT_32R6_64R6; 247def SC64 : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, PTR_64, 248 ISA_MIPS2_NOT_32R6_64R6; 249def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>, PTR_64; 250} 251 252def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM, PTR_64; 253 254/// Jump and Branch Instructions 255let isCodeGenOnly = 1 in { 256 def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>, 257 GPR_64; 258 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>, 259 GPR_64; 260 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>, 261 GPR_64; 262 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>, 263 GPR_64; 264 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>, 265 GPR_64; 266 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>, 267 GPR_64; 268 let AdditionalPredicates = [NoIndirectJumpGuards] in 269 def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>, 270 PTR_64; 271} 272let AdditionalPredicates = [NotInMicroMips], 273 DecoderNamespace = "Mips64" in { 274 def JR_HB64 : JR_HB_DESC<GPR64Opnd>, JR_HB_ENC, ISA_MIPS64_NOT_64R6; 275 def JALR_HB64 : JALR_HB_DESC<GPR64Opnd>, JALR_HB_ENC, ISA_MIPS64R2; 276} 277def PseudoReturn64 : PseudoReturnBase<GPR64Opnd>, GPR_64; 278 279let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, 280 NoIndirectJumpGuards] in { 281 def TAILCALLREG64 : TailCallReg<JR64, GPR64Opnd>, ISA_MIPS3_NOT_32R6_64R6, 282 PTR_64; 283 def PseudoIndirectBranch64 : PseudoIndirectBranchBase<JR64, GPR64Opnd>, 284 ISA_MIPS3_NOT_32R6_64R6; 285} 286 287let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, 288 UseIndirectJumpsHazard] in { 289 def TAILCALLREGHB64 : TailCallReg<JR_HB64, GPR64Opnd>, 290 ISA_MIPS32R2_NOT_32R6_64R6, PTR_64; 291 def PseudoIndirectHazardBranch64 : PseudoIndirectBranchBase<JR_HB64, 292 GPR64Opnd>, 293 ISA_MIPS32R2_NOT_32R6_64R6, PTR_64; 294} 295 296/// Multiply and Divide Instructions. 297let AdditionalPredicates = [NotInMicroMips] in { 298 def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>, 299 MULT_FM<0, 0x1c>, ISA_MIPS3_NOT_32R6_64R6; 300 def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>, 301 MULT_FM<0, 0x1d>, ISA_MIPS3_NOT_32R6_64R6; 302} 303def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult, 304 II_DMULT>, ISA_MIPS3_NOT_32R6_64R6; 305def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu, 306 II_DMULTU>, ISA_MIPS3_NOT_32R6_64R6; 307let AdditionalPredicates = [NotInMicroMips] in { 308 def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>, 309 MULT_FM<0, 0x1e>, ISA_MIPS3_NOT_32R6_64R6; 310 def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>, 311 MULT_FM<0, 0x1f>, ISA_MIPS3_NOT_32R6_64R6; 312} 313def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem, 314 II_DDIV, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6; 315def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU, 316 II_DDIVU, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6; 317 318let isCodeGenOnly = 1 in { 319def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>, 320 ISA_MIPS3_NOT_32R6_64R6; 321def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>, 322 ISA_MIPS3_NOT_32R6_64R6; 323def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, AC0_64>, MFLO_FM<0x10>, 324 ISA_MIPS3_NOT_32R6_64R6; 325def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, AC0_64>, MFLO_FM<0x12>, 326 ISA_MIPS3_NOT_32R6_64R6; 327def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>, 328 ISA_MIPS3_NOT_32R6_64R6; 329def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>, 330 ISA_MIPS3_NOT_32R6_64R6; 331def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>, ISA_MIPS3_NOT_32R6_64R6; 332 333/// Sign Ext In Register Instructions. 334def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>, 335 ISA_MIPS32R2, GPR_64; 336def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>, 337 ISA_MIPS32R2, GPR_64; 338} 339 340/// Count Leading 341let AdditionalPredicates = [NotInMicroMips] in { 342 def DCLZ : CountLeading0<"dclz", GPR64Opnd, II_DCLZ>, CLO_FM<0x24>, 343 ISA_MIPS64_NOT_64R6, GPR_64; 344 def DCLO : CountLeading1<"dclo", GPR64Opnd, II_DCLO>, CLO_FM<0x25>, 345 ISA_MIPS64_NOT_64R6, GPR_64; 346 347/// Double Word Swap Bytes/HalfWords 348 def DSBH : SubwordSwap<"dsbh", GPR64Opnd, II_DSBH>, SEB_FM<2, 0x24>, 349 ISA_MIPS64R2; 350 def DSHD : SubwordSwap<"dshd", GPR64Opnd, II_DSHD>, SEB_FM<5, 0x24>, 351 ISA_MIPS64R2; 352 353 def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>, 354 GPR_64; 355} 356 357let isCodeGenOnly = 1 in 358def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM, GPR_64; 359 360let AdditionalPredicates = [NotInMicroMips] in { 361 // The 'pos + size' constraints for code generation are enforced by the 362 // code that lowers into MipsISD::Ext. 363 // For assembly parsing, we alias dextu and dextm to dext, and match by 364 // operand were possible then check the 'pos + size' in MipsAsmParser. 365 // We override the generated decoder to enforce that dext always comes out 366 // for dextm and dextu like binutils. 367 let DecoderMethod = "DecodeDEXT" in { 368 def DEXT : ExtBase<"dext", GPR64Opnd, uimm5_report_uimm6, 369 uimm5_plus1_report_uimm6, immZExt5, immZExt5Plus1, 370 MipsExt>, EXT_FM<3>, ISA_MIPS64R2; 371 def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5, uimm5_plus33, immZExt5, 372 immZExt5Plus33, MipsExt>, EXT_FM<1>, ISA_MIPS64R2; 373 def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm5_plus32, uimm5_plus1, 374 immZExt5Plus32, immZExt5Plus1, MipsExt>, EXT_FM<2>, 375 ISA_MIPS64R2; 376 } 377 // The 'pos + size' constraints for code generation are enforced by the 378 // code that lowers into MipsISD::Ins. 379 // For assembly parsing, we alias dinsu and dinsm to dins, and match by 380 // operand were possible then check the 'pos + size' in MipsAsmParser. 381 // We override the generated decoder to enforce that dins always comes out 382 // for dinsm and dinsu like binutils. 383 let DecoderMethod = "DecodeDINS" in { 384 def DINS : InsBase<"dins", GPR64Opnd, uimm6, uimm5_inssize_plus1, 385 immZExt5, immZExt5Plus1>, EXT_FM<7>, 386 ISA_MIPS64R2; 387 def DINSU : InsBase<"dinsu", GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1, 388 immZExt5Plus32, immZExt5Plus1>, 389 EXT_FM<6>, ISA_MIPS64R2; 390 def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64, 391 immZExt5, immZExtRange2To64>, 392 EXT_FM<5>, ISA_MIPS64R2; 393 } 394} 395 396let isCodeGenOnly = 1, AdditionalPredicates = [NotInMicroMips] in { 397 def DEXT64_32 : InstSE<(outs GPR64Opnd:$rt), 398 (ins GPR32Opnd:$rs, uimm5_report_uimm6:$pos, 399 uimm5_plus1:$size), 400 "dext $rt, $rs, $pos, $size", [], II_EXT, FrmR, "dext">, 401 EXT_FM<3>, ISA_MIPS64R2; 402} 403 404let isCodeGenOnly = 1, rs = 0, shamt = 0 in { 405 def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt), 406 "dsll\t$rd, $rt, 32", [], II_DSLL>, GPR_64; 407 let isMoveReg = 1 in { 408 def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt), 409 "sll\t$rd, $rt, 0", [], II_SLL>, GPR_64; 410 def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt), 411 "sll\t$rd, $rt, 0", [], II_SLL>, GPR_64; 412 } 413} 414 415// We need the following pseudo instruction to avoid offset calculation for 416// long branches. See the comment in file MipsLongBranch.cpp for detailed 417// explanation. 418 419// Expands to: lui $dst, %highest/%higher/%hi/%lo($tgt) 420def LONG_BRANCH_LUi2Op_64 : 421 PseudoSE<(outs GPR64Opnd:$dst), (ins brtarget:$tgt), []>, GPR_64 { 422 bit hasNoSchedulingInfo = 1; 423} 424// Expands to: addiu $dst, %highest/%higher/%hi/%lo($tgt) 425def LONG_BRANCH_DADDiu2Op : 426 PseudoSE<(outs GPR64Opnd:$dst), (ins GPR64Opnd:$src, brtarget:$tgt), []>, 427 GPR_64 { 428 bit hasNoSchedulingInfo = 1; 429} 430// Expands to: daddiu $dst, $src, %PART($tgt - $baltgt) 431// where %PART may be %hi or %lo, depending on the relocation kind 432// that $tgt is annotated with. 433def LONG_BRANCH_DADDiu : 434 PseudoSE<(outs GPR64Opnd:$dst), 435 (ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>, 436 GPR_64 { 437 bit hasNoSchedulingInfo = 1; 438} 439 440// Cavium Octeon cnMIPS instructions 441let DecoderNamespace = "CnMips", 442 // FIXME: The lack of HasStdEnc is probably a bug 443 EncodingPredicates = []<Predicate> in { 444 445class Count1s<string opstr, RegisterOperand RO>: 446 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 447 [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> { 448 let TwoOperandAliasConstraint = "$rd = $rs"; 449} 450 451class ExtsCins<string opstr, InstrItinClass itin, RegisterOperand RO, 452 PatFrag PosImm, SDPatternOperator Op = null_frag>: 453 InstSE<(outs RO:$rt), (ins RO:$rs, uimm5:$pos, uimm5:$lenm1), 454 !strconcat(opstr, "\t$rt, $rs, $pos, $lenm1"), 455 [(set RO:$rt, (Op RO:$rs, PosImm:$pos, imm:$lenm1))], 456 itin, FrmR, opstr> { 457 let TwoOperandAliasConstraint = "$rt = $rs"; 458} 459 460class SetCC64_R<string opstr, PatFrag cond_op> : 461 InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt), 462 !strconcat(opstr, "\t$rd, $rs, $rt"), 463 [(set GPR64Opnd:$rd, (zext (cond_op GPR64Opnd:$rs, 464 GPR64Opnd:$rt)))], 465 II_SEQ_SNE, FrmR, opstr> { 466 let TwoOperandAliasConstraint = "$rd = $rs"; 467} 468 469class SetCC64_I<string opstr, PatFrag cond_op>: 470 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10), 471 !strconcat(opstr, "\t$rt, $rs, $imm10"), 472 [(set GPR64Opnd:$rt, (zext (cond_op GPR64Opnd:$rs, 473 immSExt10_64:$imm10)))], 474 II_SEQI_SNEI, FrmI, opstr> { 475 let TwoOperandAliasConstraint = "$rt = $rs"; 476} 477 478class CBranchBitNum<string opstr, DAGOperand opnd, PatFrag cond_op, 479 RegisterOperand RO, Operand ImmOp, bits<64> shift = 1> : 480 InstSE<(outs), (ins RO:$rs, ImmOp:$p, opnd:$offset), 481 !strconcat(opstr, "\t$rs, $p, $offset"), 482 [(brcond (i32 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)), 483 bb:$offset)], II_BBIT, FrmI, opstr> { 484 let isBranch = 1; 485 let isTerminator = 1; 486 let hasDelaySlot = 1; 487 let Defs = [AT]; 488} 489 490class MFC2OP<string asmstr, RegisterOperand RO, InstrItinClass itin> : 491 InstSE<(outs RO:$rt, uimm16:$imm16), (ins), 492 !strconcat(asmstr, "\t$rt, $imm16"), [], itin, FrmFR>; 493 494// Unsigned Byte Add 495def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>, 496 ADD_FM<0x1c, 0x28>, ASE_CNMIPS { 497 let Pattern = [(set GPR64Opnd:$rd, 498 (and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))]; 499} 500 501// Branch on Bit Clear /+32 502def BBIT0 : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd, 503 uimm5_64_report_uimm6>, BBIT_FM<0x32>, ASE_CNMIPS; 504def BBIT032: CBranchBitNum<"bbit032", brtarget, seteq, GPR64Opnd, uimm5_64, 505 0x100000000>, BBIT_FM<0x36>, ASE_CNMIPS; 506 507// Branch on Bit Set /+32 508def BBIT1 : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd, 509 uimm5_64_report_uimm6>, BBIT_FM<0x3a>, ASE_CNMIPS; 510def BBIT132: CBranchBitNum<"bbit132", brtarget, setne, GPR64Opnd, uimm5_64, 511 0x100000000>, BBIT_FM<0x3e>, ASE_CNMIPS; 512 513// Multiply Doubleword to GPR 514def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>, 515 ADD_FM<0x1c, 0x03>, ASE_CNMIPS { 516 let Defs = [HI0, LO0, P0, P1, P2]; 517} 518 519let AdditionalPredicates = [NotInMicroMips] in { 520 // Extract a signed bit field /+32 521 def EXTS : ExtsCins<"exts", II_EXT, GPR64Opnd, immZExt5>, EXTS_FM<0x3a>, 522 ASE_MIPS64_CNMIPS; 523 def EXTS32: ExtsCins<"exts32", II_EXT, GPR64Opnd, immZExt5Plus32>, 524 EXTS_FM<0x3b>, ASE_MIPS64_CNMIPS; 525 526 // Clear and insert a bit field /+32 527 def CINS : ExtsCins<"cins", II_INS, GPR64Opnd, immZExt5, MipsCIns>, 528 EXTS_FM<0x32>, ASE_MIPS64_CNMIPS; 529 def CINS32: ExtsCins<"cins32", II_INS, GPR64Opnd, immZExt5Plus32, MipsCIns>, 530 EXTS_FM<0x33>, ASE_MIPS64_CNMIPS; 531 let isCodeGenOnly = 1 in { 532 def CINS_i32 : ExtsCins<"cins", II_INS, GPR32Opnd, immZExt5, MipsCIns>, 533 EXTS_FM<0x32>, ASE_MIPS64_CNMIPS; 534 def CINS64_32 :InstSE<(outs GPR64Opnd:$rt), 535 (ins GPR32Opnd:$rs, uimm5:$pos, uimm5:$lenm1), 536 "cins\t$rt, $rs, $pos, $lenm1", [], II_INS, FrmR, 537 "cins">, 538 EXTS_FM<0x32>, ASE_MIPS64_CNMIPS; 539 } 540} 541 542// Move to multiplier/product register 543def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>, 544 ASE_CNMIPS; 545def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>, 546 ASE_CNMIPS; 547def MTM2 : MoveToLOHI<"mtm2", GPR64Opnd, [MPL2, P0, P1, P2]>, MTMR_FM<0x0d>, 548 ASE_CNMIPS; 549def MTP0 : MoveToLOHI<"mtp0", GPR64Opnd, [P0]>, MTMR_FM<0x09>, ASE_CNMIPS; 550def MTP1 : MoveToLOHI<"mtp1", GPR64Opnd, [P1]>, MTMR_FM<0x0a>, ASE_CNMIPS; 551def MTP2 : MoveToLOHI<"mtp2", GPR64Opnd, [P2]>, MTMR_FM<0x0b>, ASE_CNMIPS; 552 553// Count Ones in a Word/Doubleword 554def POP : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>, ASE_CNMIPS; 555def DPOP : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>, ASE_CNMIPS; 556 557// Set on equal/not equal 558def SEQ : SetCC64_R<"seq", seteq>, SEQ_FM<0x2a>, ASE_CNMIPS; 559def SEQi : SetCC64_I<"seqi", seteq>, SEQI_FM<0x2e>, ASE_CNMIPS; 560def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>, ASE_CNMIPS; 561def SNEi : SetCC64_I<"snei", setne>, SEQI_FM<0x2f>, ASE_CNMIPS; 562 563// 192-bit x 64-bit Unsigned Multiply and Add 564def V3MULU: ArithLogicR<"v3mulu", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x11>, 565 ASE_CNMIPS { 566 let Defs = [P0, P1, P2]; 567} 568 569// 64-bit Unsigned Multiply and Add Move 570def VMM0 : ArithLogicR<"vmm0", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x10>, 571 ASE_CNMIPS { 572 let Defs = [MPL0, P0, P1, P2]; 573} 574 575// 64-bit Unsigned Multiply and Add 576def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x0f>, 577 ASE_CNMIPS { 578 let Defs = [MPL1, MPL2, P0, P1, P2]; 579} 580 581// Move between CPU and coprocessor registers 582def DMFC2_OCTEON : MFC2OP<"dmfc2", GPR64Opnd, II_DMFC2>, MFC2OP_FM<0x12, 1>, 583 ASE_CNMIPS; 584def DMTC2_OCTEON : MFC2OP<"dmtc2", GPR64Opnd, II_DMTC2>, MFC2OP_FM<0x12, 5>, 585 ASE_CNMIPS; 586} 587 588// Cavium Octeon+ cnMIPS instructions 589let DecoderNamespace = "CnMipsP", 590 // FIXME: The lack of HasStdEnc is probably a bug 591 EncodingPredicates = []<Predicate> in { 592 593class Saa<string opstr>: 594 InstSE<(outs), (ins GPR64Opnd:$rt, GPR64Opnd:$rs), 595 !strconcat(opstr, "\t$rt, (${rs})"), [], NoItinerary, FrmR, opstr>; 596 597def SAA : Saa<"saa">, SAA_FM<0x18>, ASE_CNMIPSP; 598def SAAD : Saa<"saad">, SAA_FM<0x19>, ASE_CNMIPSP; 599 600def SaaAddr : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rt, mem:$addr), 601 "saa\t$rt, $addr">, ASE_CNMIPSP; 602def SaadAddr : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rt, mem:$addr), 603 "saad\t$rt, $addr">, ASE_CNMIPSP; 604} 605 606} 607 608/// Move between CPU and coprocessor registers 609let DecoderNamespace = "Mips64" in { 610def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd, COP0Opnd, II_DMFC0>, 611 MFC3OP_FM<0x10, 1, 0>, ISA_MIPS3, GPR_64; 612def DMTC0 : MTC3OP<"dmtc0", COP0Opnd, GPR64Opnd, II_DMTC0>, 613 MFC3OP_FM<0x10, 5, 0>, ISA_MIPS3, GPR_64; 614def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd, COP2Opnd, II_DMFC2>, 615 MFC3OP_FM<0x12, 1, 0>, ISA_MIPS3, GPR_64; 616def DMTC2 : MTC3OP<"dmtc2", COP2Opnd, GPR64Opnd, II_DMTC2>, 617 MFC3OP_FM<0x12, 5, 0>, ISA_MIPS3, GPR_64; 618} 619 620/// Move between CPU and guest coprocessor registers (Virtualization ASE) 621let DecoderNamespace = "Mips64" in { 622 def DMFGC0 : MFC3OP<"dmfgc0", GPR64Opnd, COP0Opnd, II_DMFGC0>, 623 MFC3OP_FM<0x10, 3, 1>, ISA_MIPS64R5, ASE_VIRT; 624 def DMTGC0 : MTC3OP<"dmtgc0", COP0Opnd, GPR64Opnd, II_DMTGC0>, 625 MFC3OP_FM<0x10, 3, 3>, ISA_MIPS64R5, ASE_VIRT; 626} 627 628let AdditionalPredicates = [UseIndirectJumpsHazard] in 629 def JALRHB64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR_HB64, RA_64>, PTR_64; 630 631//===----------------------------------------------------------------------===// 632// Arbitrary patterns that map to one or more instructions 633//===----------------------------------------------------------------------===// 634 635// Materialize i64 constants. 636defm : MaterializeImms<i64, ZERO_64, DADDiu, LUi64, ORi64>, ISA_MIPS3, GPR_64; 637 638def : MipsPat<(i64 immZExt32Low16Zero:$imm), 639 (DSLL (ORi64 ZERO_64, (HI16 imm:$imm)), 16)>, ISA_MIPS3, GPR_64; 640 641def : MipsPat<(i64 immZExt32:$imm), 642 (ORi64 (DSLL (ORi64 ZERO_64, (HI16 imm:$imm)), 16), 643 (LO16 imm:$imm))>, ISA_MIPS3, GPR_64; 644 645// extended loads 646def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>, ISA_MIPS3, 647 GPR_64; 648def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>, ISA_MIPS3, 649 GPR_64; 650def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>, ISA_MIPS3, 651 GPR_64; 652def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>, ISA_MIPS3, 653 GPR_64; 654 655// hi/lo relocs 656let AdditionalPredicates = [NotInMicroMips] in 657defm : MipsHiLoRelocs<LUi64, DADDiu, ZERO_64, GPR64Opnd>, ISA_MIPS3, GPR_64, 658 SYM_32; 659 660def : MipsPat<(MipsGotHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>, ISA_MIPS3, 661 GPR_64; 662def : MipsPat<(MipsGotHi texternalsym:$in), (LUi64 texternalsym:$in)>, 663 ISA_MIPS3, GPR_64; 664 665def : MipsPat<(MipsTlsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>, 666 ISA_MIPS3, GPR_64; 667 668// highest/higher/hi/lo relocs 669let AdditionalPredicates = [NotInMicroMips] in { 670 def : MipsPat<(MipsJmpLink (i64 texternalsym:$dst)), 671 (JAL texternalsym:$dst)>, ISA_MIPS3, GPR_64, SYM_64; 672 def : MipsPat<(MipsHighest (i64 tglobaladdr:$in)), 673 (LUi64 tglobaladdr:$in)>, ISA_MIPS3, GPR_64, SYM_64; 674 def : MipsPat<(MipsHighest (i64 tblockaddress:$in)), 675 (LUi64 tblockaddress:$in)>, ISA_MIPS3, GPR_64, SYM_64; 676 def : MipsPat<(MipsHighest (i64 tjumptable:$in)), 677 (LUi64 tjumptable:$in)>, ISA_MIPS3, GPR_64, SYM_64; 678 def : MipsPat<(MipsHighest (i64 tconstpool:$in)), 679 (LUi64 tconstpool:$in)>, ISA_MIPS3, GPR_64, SYM_64; 680 def : MipsPat<(MipsHighest (i64 texternalsym:$in)), 681 (LUi64 texternalsym:$in)>, ISA_MIPS3, GPR_64, SYM_64; 682 683 def : MipsPat<(MipsHigher (i64 tglobaladdr:$in)), 684 (DADDiu ZERO_64, tglobaladdr:$in)>, ISA_MIPS3, GPR_64, SYM_64; 685 def : MipsPat<(MipsHigher (i64 tblockaddress:$in)), 686 (DADDiu ZERO_64, tblockaddress:$in)>, ISA_MIPS3, GPR_64, SYM_64; 687 def : MipsPat<(MipsHigher (i64 tjumptable:$in)), 688 (DADDiu ZERO_64, tjumptable:$in)>, ISA_MIPS3, GPR_64, SYM_64; 689 def : MipsPat<(MipsHigher (i64 tconstpool:$in)), 690 (DADDiu ZERO_64, tconstpool:$in)>, ISA_MIPS3, GPR_64, SYM_64; 691 def : MipsPat<(MipsHigher (i64 texternalsym:$in)), 692 (DADDiu ZERO_64, texternalsym:$in)>, ISA_MIPS3, GPR_64, SYM_64; 693 694 def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tglobaladdr:$lo))), 695 (DADDiu GPR64:$hi, tglobaladdr:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 696 def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tblockaddress:$lo))), 697 (DADDiu GPR64:$hi, tblockaddress:$lo)>, ISA_MIPS3, GPR_64, 698 SYM_64; 699 def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tjumptable:$lo))), 700 (DADDiu GPR64:$hi, tjumptable:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 701 def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tconstpool:$lo))), 702 (DADDiu GPR64:$hi, tconstpool:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 703 def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 texternalsym:$lo))), 704 (DADDiu GPR64:$hi, texternalsym:$lo)>, 705 ISA_MIPS3, GPR_64, SYM_64; 706 707 def : MipsPat<(MipsHi (i64 tglobaladdr:$in)), 708 (DADDiu ZERO_64, tglobaladdr:$in)>, ISA_MIPS3, GPR_64, SYM_64; 709 def : MipsPat<(MipsHi (i64 tblockaddress:$in)), 710 (DADDiu ZERO_64, tblockaddress:$in)>, ISA_MIPS3, GPR_64, SYM_64; 711 def : MipsPat<(MipsHi (i64 tjumptable:$in)), 712 (DADDiu ZERO_64, tjumptable:$in)>, ISA_MIPS3, GPR_64, SYM_64; 713 def : MipsPat<(MipsHi (i64 tconstpool:$in)), 714 (DADDiu ZERO_64, tconstpool:$in)>, ISA_MIPS3, GPR_64, SYM_64; 715 def : MipsPat<(MipsHi (i64 texternalsym:$in)), 716 (DADDiu ZERO_64, texternalsym:$in)>, ISA_MIPS3, GPR_64, SYM_64; 717 718 def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tglobaladdr:$lo))), 719 (DADDiu GPR64:$hi, tglobaladdr:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 720 def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tblockaddress:$lo))), 721 (DADDiu GPR64:$hi, tblockaddress:$lo)>, ISA_MIPS3, GPR_64, 722 SYM_64; 723 def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tjumptable:$lo))), 724 (DADDiu GPR64:$hi, tjumptable:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 725 def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tconstpool:$lo))), 726 (DADDiu GPR64:$hi, tconstpool:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 727 def : MipsPat<(add GPR64:$hi, (MipsHi (i64 texternalsym:$lo))), 728 (DADDiu GPR64:$hi, texternalsym:$lo)>, 729 ISA_MIPS3, GPR_64, SYM_64; 730 731 def : MipsPat<(MipsLo (i64 tglobaladdr:$in)), 732 (DADDiu ZERO_64, tglobaladdr:$in)>, ISA_MIPS3, GPR_64, SYM_64; 733 def : MipsPat<(MipsLo (i64 tblockaddress:$in)), 734 (DADDiu ZERO_64, tblockaddress:$in)>, ISA_MIPS3, GPR_64, SYM_64; 735 def : MipsPat<(MipsLo (i64 tjumptable:$in)), 736 (DADDiu ZERO_64, tjumptable:$in)>, ISA_MIPS3, GPR_64, SYM_64; 737 def : MipsPat<(MipsLo (i64 tconstpool:$in)), 738 (DADDiu ZERO_64, tconstpool:$in)>, ISA_MIPS3, GPR_64, SYM_64; 739 def : MipsPat<(MipsLo (i64 tglobaltlsaddr:$in)), 740 (DADDiu ZERO_64, tglobaltlsaddr:$in)>, 741 ISA_MIPS3, GPR_64, SYM_64; 742 def : MipsPat<(MipsLo (i64 texternalsym:$in)), 743 (DADDiu ZERO_64, texternalsym:$in)>, ISA_MIPS3, GPR_64, SYM_64; 744 745 def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tglobaladdr:$lo))), 746 (DADDiu GPR64:$hi, tglobaladdr:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 747 def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tblockaddress:$lo))), 748 (DADDiu GPR64:$hi, tblockaddress:$lo)>, ISA_MIPS3, GPR_64, 749 SYM_64; 750 def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tjumptable:$lo))), 751 (DADDiu GPR64:$hi, tjumptable:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 752 def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tconstpool:$lo))), 753 (DADDiu GPR64:$hi, tconstpool:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 754 def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tglobaltlsaddr:$lo))), 755 (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>, ISA_MIPS3, GPR_64, 756 SYM_64; 757 def : MipsPat<(add GPR64:$hi, (MipsLo (i64 texternalsym:$lo))), 758 (DADDiu GPR64:$hi, texternalsym:$lo)>, 759 ISA_MIPS3, GPR_64, SYM_64; 760} 761 762// gp_rel relocs 763def : MipsPat<(add GPR64:$gp, (MipsGPRel tglobaladdr:$in)), 764 (DADDiu GPR64:$gp, tglobaladdr:$in)>, ISA_MIPS3, ABI_N64; 765def : MipsPat<(add GPR64:$gp, (MipsGPRel tconstpool:$in)), 766 (DADDiu GPR64:$gp, tconstpool:$in)>, ISA_MIPS3, ABI_N64; 767 768def : WrapperPat<tglobaladdr, DADDiu, GPR64>, ISA_MIPS3, GPR_64; 769def : WrapperPat<tconstpool, DADDiu, GPR64>, ISA_MIPS3, GPR_64; 770def : WrapperPat<texternalsym, DADDiu, GPR64>, ISA_MIPS3, GPR_64; 771def : WrapperPat<tblockaddress, DADDiu, GPR64>, ISA_MIPS3, GPR_64; 772def : WrapperPat<tjumptable, DADDiu, GPR64>, ISA_MIPS3, GPR_64; 773def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>, ISA_MIPS3, GPR_64; 774 775 776defm : BrcondPats<GPR64, BEQ64, BEQ, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, 777 ZERO_64>, ISA_MIPS3, GPR_64; 778def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst), 779 (BLEZ64 i64:$lhs, bb:$dst)>, ISA_MIPS3, GPR_64; 780def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst), 781 (BGEZ64 i64:$lhs, bb:$dst)>, ISA_MIPS3, GPR_64; 782 783// setcc patterns 784let AdditionalPredicates = [NotInMicroMips] in { 785 defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>, ISA_MIPS3, GPR_64; 786 defm : SetlePats<GPR64, XORi, SLT64, SLTu64>, ISA_MIPS3, GPR_64; 787 defm : SetgtPats<GPR64, SLT64, SLTu64>, ISA_MIPS3, GPR_64; 788 defm : SetgePats<GPR64, XORi, SLT64, SLTu64>, ISA_MIPS3, GPR_64; 789 defm : SetgeImmPats<GPR64, XORi, SLTi64, SLTiu64>, ISA_MIPS3, GPR_64; 790} 791// truncate 792def : MipsPat<(trunc (assertsext GPR64:$src)), 793 (EXTRACT_SUBREG GPR64:$src, sub_32)>, ISA_MIPS3, GPR_64; 794// The forward compatibility strategy employed by MIPS requires us to treat 795// values as being sign extended to an infinite number of bits. This allows 796// existing software to run without modification on any future MIPS 797// implementation (e.g. 128-bit, or 1024-bit). Being compatible with this 798// strategy requires that truncation acts as a sign-extension for values being 799// fed into instructions operating on 32-bit values. Such instructions have 800// undefined results if this is not true. 801// For our case, this means that we can't issue an extract_subreg for nodes 802// such as (trunc:i32 (assertzext:i64 X, i32)), because the sign-bit of the 803// lower subreg would not be replicated into the upper half. 804def : MipsPat<(trunc (assertzext_lt_i32 GPR64:$src)), 805 (EXTRACT_SUBREG GPR64:$src, sub_32)>, ISA_MIPS3, GPR_64; 806def : MipsPat<(i32 (trunc GPR64:$src)), 807 (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>, ISA_MIPS3, GPR_64; 808 809// variable shift instructions patterns 810def : MipsPat<(shl GPR64:$rt, (i32 (trunc GPR64:$rs))), 811 (DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>, 812 ISA_MIPS3, GPR_64; 813def : MipsPat<(srl GPR64:$rt, (i32 (trunc GPR64:$rs))), 814 (DSRLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>, 815 ISA_MIPS3, GPR_64; 816def : MipsPat<(sra GPR64:$rt, (i32 (trunc GPR64:$rs))), 817 (DSRAV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>, 818 ISA_MIPS3, GPR_64; 819def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))), 820 (DROTRV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>, 821 ISA_MIPS3, GPR_64; 822 823// 32-to-64-bit extension 824def : MipsPat<(i64 (anyext GPR32:$src)), 825 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>, 826 ISA_MIPS3, GPR_64; 827def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>, 828 ISA_MIPS3, GPR_64; 829def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>, ISA_MIPS3, 830 GPR_64; 831 832let AdditionalPredicates = [NotInMicroMips] in { 833 def : MipsPat<(i64 (zext GPR32:$src)), (DEXT64_32 GPR32:$src, 0, 32)>, 834 ISA_MIPS64R2, GPR_64; 835 def : MipsPat<(i64 (zext (i32 (shl GPR32:$rt, immZExt5:$imm)))), 836 (CINS64_32 GPR32:$rt, imm:$imm, (immZExt5To31 imm:$imm))>, 837 ISA_MIPS64R2, GPR_64, ASE_MIPS64_CNMIPS; 838} 839 840// Sign extend in register 841def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)), 842 (SLL64_64 GPR64:$src)>, ISA_MIPS3, GPR_64; 843 844// bswap MipsPattern 845def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>, ISA_MIPS64R2; 846 847// Carry pattern 848let AdditionalPredicates = [NotInMicroMips] in { 849 def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs), 850 (DSUBu GPR64:$lhs, GPR64:$rhs)>, ISA_MIPS3, GPR_64; 851 def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs), 852 (DADDu GPR64:$lhs, GPR64:$rhs)>, ISA_MIPS3, ASE_NOT_DSP, GPR_64; 853 def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm), 854 (DADDiu GPR64:$lhs, imm:$imm)>, ISA_MIPS3, ASE_NOT_DSP, GPR_64; 855} 856 857// Octeon bbit0/bbit1 MipsPattern 858def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst), 859 (BBIT0 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, 860 ISA_MIPS64R2, ASE_MIPS64_CNMIPS; 861def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst), 862 (BBIT032 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, 863 ISA_MIPS64R2, ASE_MIPS64_CNMIPS; 864def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst), 865 (BBIT1 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, 866 ISA_MIPS64R2, ASE_MIPS64_CNMIPS; 867def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst), 868 (BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, 869 ISA_MIPS64R2, ASE_MIPS64_CNMIPS; 870def : MipsPat<(brcond (i32 (seteq (and i32:$lhs, PowerOf2LO_i32:$mask), 0)), bb:$dst), 871 (BBIT0 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$lhs, sub_32), 872 (Log2LO PowerOf2LO_i32:$mask), bb:$dst)>, ISA_MIPS64R2, 873 ASE_MIPS64_CNMIPS; 874def : MipsPat<(brcond (i32 (setne (and i32:$lhs, PowerOf2LO_i32:$mask), 0)), bb:$dst), 875 (BBIT1 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$lhs, sub_32), 876 (Log2LO PowerOf2LO_i32:$mask), bb:$dst)>, ISA_MIPS64R2, 877 ASE_MIPS64_CNMIPS; 878 879// Atomic load patterns. 880def : MipsPat<(atomic_load_8 addr:$a), (LB64 addr:$a)>, ISA_MIPS3, GPR_64; 881def : MipsPat<(atomic_load_16 addr:$a), (LH64 addr:$a)>, ISA_MIPS3, GPR_64; 882def : MipsPat<(atomic_load_32 addr:$a), (LW64 addr:$a)>, ISA_MIPS3, GPR_64; 883def : MipsPat<(atomic_load_64 addr:$a), (LD addr:$a)>, ISA_MIPS3, GPR_64; 884 885// Atomic store patterns. 886def : MipsPat<(atomic_store_8 addr:$a, GPR64:$v), (SB64 GPR64:$v, addr:$a)>, 887 ISA_MIPS3, GPR_64; 888def : MipsPat<(atomic_store_16 addr:$a, GPR64:$v), (SH64 GPR64:$v, addr:$a)>, 889 ISA_MIPS3, GPR_64; 890def : MipsPat<(atomic_store_32 addr:$a, GPR64:$v), (SW64 GPR64:$v, addr:$a)>, 891 ISA_MIPS3, GPR_64; 892def : MipsPat<(atomic_store_64 addr:$a, GPR64:$v), (SD GPR64:$v, addr:$a)>, 893 ISA_MIPS3, GPR_64; 894 895// Patterns used for matching away redundant sign extensions. 896// MIPS32 arithmetic instructions sign extend their result implicitly. 897def : MipsPat<(i64 (sext (i32 (add GPR32:$src, immSExt16:$imm16)))), 898 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 899 (ADDiu GPR32:$src, immSExt16:$imm16), sub_32)>; 900def : MipsPat<(i64 (sext (i32 (add GPR32:$src, GPR32:$src2)))), 901 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 902 (ADDu GPR32:$src, GPR32:$src2), sub_32)>; 903def : MipsPat<(i64 (sext (i32 (sub GPR32:$src, GPR32:$src2)))), 904 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 905 (SUBu GPR32:$src, GPR32:$src2), sub_32)>; 906def : MipsPat<(i64 (sext (i32 (mul GPR32:$src, GPR32:$src2)))), 907 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 908 (MUL GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS32_NOT_32R6_64R6; 909def : MipsPat<(i64 (sext (i32 (MipsMFHI ACC64:$src)))), 910 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 911 (PseudoMFHI ACC64:$src), sub_32)>; 912def : MipsPat<(i64 (sext (i32 (MipsMFLO ACC64:$src)))), 913 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 914 (PseudoMFLO ACC64:$src), sub_32)>; 915def : MipsPat<(i64 (sext (i32 (shl GPR32:$src, immZExt5:$imm5)))), 916 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 917 (SLL GPR32:$src, immZExt5:$imm5), sub_32)>; 918def : MipsPat<(i64 (sext (i32 (shl GPR32:$src, GPR32:$src2)))), 919 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 920 (SLLV GPR32:$src, GPR32:$src2), sub_32)>; 921def : MipsPat<(i64 (sext (i32 (srl GPR32:$src, immZExt5:$imm5)))), 922 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 923 (SRL GPR32:$src, immZExt5:$imm5), sub_32)>; 924def : MipsPat<(i64 (sext (i32 (srl GPR32:$src, GPR32:$src2)))), 925 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 926 (SRLV GPR32:$src, GPR32:$src2), sub_32)>; 927def : MipsPat<(i64 (sext (i32 (sra GPR32:$src, immZExt5:$imm5)))), 928 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 929 (SRA GPR32:$src, immZExt5:$imm5), sub_32)>; 930def : MipsPat<(i64 (sext (i32 (sra GPR32:$src, GPR32:$src2)))), 931 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 932 (SRAV GPR32:$src, GPR32:$src2), sub_32)>; 933 934//===----------------------------------------------------------------------===// 935// Instruction aliases 936//===----------------------------------------------------------------------===// 937let AdditionalPredicates = [NotInMicroMips] in { 938 def : MipsInstAlias<"move $dst, $src", 939 (OR64 GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>, 940 GPR_64; 941 def : MipsInstAlias<"move $dst, $src", 942 (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>, 943 GPR_64; 944 def : MipsInstAlias<"dadd $rs, $rt, $imm", 945 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm), 946 0>, ISA_MIPS3_NOT_32R6_64R6; 947 def : MipsInstAlias<"dadd $rs, $imm", 948 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm), 949 0>, ISA_MIPS3_NOT_32R6_64R6; 950 def : MipsInstAlias<"daddu $rs, $rt, $imm", 951 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm), 952 0>, ISA_MIPS3; 953 def : MipsInstAlias<"daddu $rs, $imm", 954 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm), 955 0>, ISA_MIPS3; 956 957 defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi64, GPR64Opnd, imm64>, 958 ISA_MIPS3, GPR_64; 959 960 defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi64, GPR64Opnd, imm64>, 961 ISA_MIPS3, GPR_64; 962 963 defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi64, GPR64Opnd, imm64>, 964 ISA_MIPS3, GPR_64; 965} 966let AdditionalPredicates = [NotInMicroMips] in { 967 def : MipsInstAlias<"dneg $rt, $rs", 968 (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>, 969 ISA_MIPS3; 970 def : MipsInstAlias<"dneg $rt", 971 (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>, 972 ISA_MIPS3; 973 def : MipsInstAlias<"dnegu $rt, $rs", 974 (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>, 975 ISA_MIPS3; 976 def : MipsInstAlias<"dnegu $rt", 977 (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>, 978 ISA_MIPS3; 979} 980def : MipsInstAlias<"dsubi $rs, $rt, $imm", 981 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, 982 InvertedImOperand64:$imm), 983 0>, ISA_MIPS3_NOT_32R6_64R6; 984def : MipsInstAlias<"dsubi $rs, $imm", 985 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, 986 InvertedImOperand64:$imm), 987 0>, ISA_MIPS3_NOT_32R6_64R6; 988def : MipsInstAlias<"dsub $rs, $rt, $imm", 989 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, 990 InvertedImOperand64:$imm), 991 0>, ISA_MIPS3_NOT_32R6_64R6; 992def : MipsInstAlias<"dsub $rs, $imm", 993 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, 994 InvertedImOperand64:$imm), 995 0>, ISA_MIPS3_NOT_32R6_64R6; 996let AdditionalPredicates = [NotInMicroMips] in { 997 def : MipsInstAlias<"dsubu $rt, $rs, $imm", 998 (DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs, 999 InvertedImOperand64:$imm), 0>, ISA_MIPS3; 1000 def : MipsInstAlias<"dsubu $rs, $imm", 1001 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, 1002 InvertedImOperand64:$imm), 0>, ISA_MIPS3; 1003} 1004def : MipsInstAlias<"dsra $rd, $rt, $rs", 1005 (DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>, 1006 ISA_MIPS3; 1007let AdditionalPredicates = [NotInMicroMips] in { 1008 def : MipsInstAlias<"dsll $rd, $rt, $rs", 1009 (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>, 1010 ISA_MIPS3; 1011 def : MipsInstAlias<"dsrl $rd, $rt, $rs", 1012 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>, 1013 ISA_MIPS3; 1014 def : MipsInstAlias<"dsrl $rd, $rt", 1015 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rd, GPR32Opnd:$rt), 0>, 1016 ISA_MIPS3; 1017 def : MipsInstAlias<"dsll $rd, $rt", 1018 (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rd, GPR32Opnd:$rt), 0>, 1019 ISA_MIPS3; 1020 def : MipsInstAlias<"dins $rt, $rs, $pos, $size", 1021 (DINSM GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5:$pos, 1022 uimm_range_2_64:$size), 0>, ISA_MIPS64R2; 1023 def : MipsInstAlias<"dins $rt, $rs, $pos, $size", 1024 (DINSU GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5_plus32:$pos, 1025 uimm5_plus1:$size), 0>, ISA_MIPS64R2; 1026 def : MipsInstAlias<"dext $rt, $rs, $pos, $size", 1027 (DEXTM GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5:$pos, 1028 uimm5_plus33:$size), 0>, ISA_MIPS64R2; 1029 def : MipsInstAlias<"dext $rt, $rs, $pos, $size", 1030 (DEXTU GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5_plus32:$pos, 1031 uimm5_plus1:$size), 0>, ISA_MIPS64R2; 1032 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB64 RA_64, GPR64Opnd:$rs), 1>, 1033 ISA_MIPS64; 1034// Two operand (implicit 0 selector) versions: 1035 def : MipsInstAlias<"dmtc0 $rt, $rd", 1036 (DMTC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>; 1037 def : MipsInstAlias<"dmfc0 $rt, $rd", 1038 (DMFC0 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>; 1039 def : MipsInstAlias<"dmfgc0 $rt, $rd", 1040 (DMFGC0 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>, 1041 ISA_MIPS64R5, ASE_VIRT; 1042 def : MipsInstAlias<"dmtgc0 $rt, $rd", 1043 (DMTGC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>, 1044 ISA_MIPS64R5, ASE_VIRT; 1045} 1046def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, COP2Opnd:$rd, 0), 0>; 1047def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 COP2Opnd:$rd, GPR64Opnd:$rt, 0), 0>; 1048 1049def : MipsInstAlias<"synciobdma", (SYNC 0x2), 0>, ASE_MIPS64_CNMIPS; 1050def : MipsInstAlias<"syncs", (SYNC 0x6), 0>, ASE_MIPS64_CNMIPS; 1051def : MipsInstAlias<"syncw", (SYNC 0x4), 0>, ASE_MIPS64_CNMIPS; 1052def : MipsInstAlias<"syncws", (SYNC 0x5), 0>, ASE_MIPS64_CNMIPS; 1053 1054// cnMIPS Aliases. 1055 1056// bbit* with $p 32-63 converted to bbit*32 with $p 0-31 1057def : MipsInstAlias<"bbit0 $rs, $p, $offset", 1058 (BBIT032 GPR64Opnd:$rs, uimm5_plus32_normalize_64:$p, 1059 brtarget:$offset), 0>, 1060 ASE_CNMIPS; 1061def : MipsInstAlias<"bbit1 $rs, $p, $offset", 1062 (BBIT132 GPR64Opnd:$rs, uimm5_plus32_normalize_64:$p, 1063 brtarget:$offset), 0>, 1064 ASE_CNMIPS; 1065 1066// exts with $pos 32-63 in converted to exts32 with $pos 0-31 1067def : MipsInstAlias<"exts $rt, $rs, $pos, $lenm1", 1068 (EXTS32 GPR64Opnd:$rt, GPR64Opnd:$rs, 1069 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, 1070 ASE_MIPS64_CNMIPS; 1071def : MipsInstAlias<"exts $rt, $pos, $lenm1", 1072 (EXTS32 GPR64Opnd:$rt, GPR64Opnd:$rt, 1073 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, 1074 ASE_MIPS64_CNMIPS; 1075 1076// cins with $pos 32-63 in converted to cins32 with $pos 0-31 1077def : MipsInstAlias<"cins $rt, $rs, $pos, $lenm1", 1078 (CINS32 GPR64Opnd:$rt, GPR64Opnd:$rs, 1079 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, 1080 ASE_MIPS64_CNMIPS; 1081def : MipsInstAlias<"cins $rt, $pos, $lenm1", 1082 (CINS32 GPR64Opnd:$rt, GPR64Opnd:$rt, 1083 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, 1084 ASE_MIPS64_CNMIPS; 1085 1086//===----------------------------------------------------------------------===// 1087// Assembler Pseudo Instructions 1088//===----------------------------------------------------------------------===// 1089 1090class LoadImmediate64<string instr_asm, Operand Od, RegisterOperand RO> : 1091 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm64), 1092 !strconcat(instr_asm, "\t$rt, $imm64")> ; 1093def LoadImm64 : LoadImmediate64<"dli", imm64, GPR64Opnd>; 1094 1095def LoadAddrReg64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rt), (ins mem:$addr), 1096 "dla\t$rt, $addr">; 1097def LoadAddrImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rt), (ins imm64:$imm64), 1098 "dla\t$rt, $imm64">; 1099 1100def DMULImmMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt, 1101 simm32_relaxed:$imm), 1102 "dmul\t$rs, $rt, $imm">, 1103 ISA_MIPS3_NOT_32R6_64R6; 1104def DMULOMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt, 1105 GPR64Opnd:$rd), 1106 "dmulo\t$rs, $rt, $rd">, 1107 ISA_MIPS3_NOT_32R6_64R6; 1108def DMULOUMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt, 1109 GPR64Opnd:$rd), 1110 "dmulou\t$rs, $rt, $rd">, 1111 ISA_MIPS3_NOT_32R6_64R6; 1112 1113def DMULMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt, 1114 GPR64Opnd:$rd), 1115 "dmul\t$rs, $rt, $rd"> { 1116 let InsnPredicates = [HasMips3, NotMips64r6, NotCnMips]; 1117} 1118 1119let AdditionalPredicates = [NotInMicroMips] in { 1120 def DSDivMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1121 (ins GPR64Opnd:$rs, GPR64Opnd:$rt), 1122 "ddiv\t$rd, $rs, $rt">, 1123 ISA_MIPS3_NOT_32R6_64R6; 1124 def DSDivIMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1125 (ins GPR64Opnd:$rs, imm64:$imm), 1126 "ddiv\t$rd, $rs, $imm">, 1127 ISA_MIPS3_NOT_32R6_64R6; 1128 def DUDivMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1129 (ins GPR64Opnd:$rs, GPR64Opnd:$rt), 1130 "ddivu\t$rd, $rs, $rt">, 1131 ISA_MIPS3_NOT_32R6_64R6; 1132 def DUDivIMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1133 (ins GPR64Opnd:$rs, imm64:$imm), 1134 "ddivu\t$rd, $rs, $imm">, 1135 ISA_MIPS3_NOT_32R6_64R6; 1136 1137 // GAS expands 'div' and 'ddiv' differently when the destination 1138 // register is $zero and the instruction is in the two operand 1139 // form. 'ddiv' gets expanded, while 'div' is not expanded. 1140 1141 def : MipsInstAlias<"ddiv $rs, $rt", (DSDivMacro GPR64Opnd:$rs, 1142 GPR64Opnd:$rs, 1143 GPR64Opnd:$rt), 0>, 1144 ISA_MIPS3_NOT_32R6_64R6; 1145 def : MipsInstAlias<"ddiv $rd, $imm", (DSDivIMacro GPR64Opnd:$rd, 1146 GPR64Opnd:$rd, 1147 imm64:$imm), 0>, 1148 ISA_MIPS3_NOT_32R6_64R6; 1149 1150 // GAS expands 'divu' and 'ddivu' differently when the destination 1151 // register is $zero and the instruction is in the two operand 1152 // form. 'ddivu' gets expanded, while 'divu' is not expanded. 1153 1154 def : MipsInstAlias<"ddivu $rt, $rs", (DUDivMacro GPR64Opnd:$rt, 1155 GPR64Opnd:$rt, 1156 GPR64Opnd:$rs), 0>, 1157 ISA_MIPS3_NOT_32R6_64R6; 1158 def : MipsInstAlias<"ddivu $rd, $imm", (DUDivIMacro GPR64Opnd:$rd, 1159 GPR64Opnd:$rd, 1160 imm64:$imm), 0>, 1161 ISA_MIPS3_NOT_32R6_64R6; 1162 def DSRemMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1163 (ins GPR64Opnd:$rs, GPR64Opnd:$rt), 1164 "drem\t$rd, $rs, $rt">, 1165 ISA_MIPS3_NOT_32R6_64R6; 1166 def DSRemIMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1167 (ins GPR64Opnd:$rs, simm32_relaxed:$imm), 1168 "drem\t$rd, $rs, $imm">, 1169 ISA_MIPS3_NOT_32R6_64R6; 1170 def DURemMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1171 (ins GPR64Opnd:$rs, GPR64Opnd:$rt), 1172 "dremu\t$rd, $rs, $rt">, 1173 ISA_MIPS3_NOT_32R6_64R6; 1174 def DURemIMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1175 (ins GPR64Opnd:$rs, simm32_relaxed:$imm), 1176 "dremu\t$rd, $rs, $imm">, 1177 ISA_MIPS3_NOT_32R6_64R6; 1178 def : MipsInstAlias<"drem $rt, $rs", (DSRemMacro GPR64Opnd:$rt, 1179 GPR64Opnd:$rt, 1180 GPR64Opnd:$rs), 0>, 1181 ISA_MIPS3_NOT_32R6_64R6; 1182 def : MipsInstAlias<"drem $rd, $imm", (DSRemIMacro GPR64Opnd:$rd, 1183 GPR64Opnd:$rd, 1184 simm32_relaxed:$imm), 0>, 1185 ISA_MIPS3_NOT_32R6_64R6; 1186 def : MipsInstAlias<"dremu $rt, $rs", (DURemMacro GPR64Opnd:$rt, 1187 GPR64Opnd:$rt, 1188 GPR64Opnd:$rs), 0>, 1189 ISA_MIPS3_NOT_32R6_64R6; 1190 def : MipsInstAlias<"dremu $rd, $imm", (DURemIMacro GPR64Opnd:$rd, 1191 GPR64Opnd:$rd, 1192 simm32_relaxed:$imm), 0>, 1193 ISA_MIPS3_NOT_32R6_64R6; 1194} 1195 1196def NORImm64 : NORIMM_DESC_BASE<GPR64Opnd, imm64>, GPR_64; 1197def : MipsInstAlias<"nor\t$rs, $imm", (NORImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, 1198 imm64:$imm)>, GPR_64; 1199def SLTImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rs), 1200 (ins GPR64Opnd:$rt, imm64:$imm), 1201 "slt\t$rs, $rt, $imm">, GPR_64; 1202def : MipsInstAlias<"slt\t$rs, $imm", (SLTImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, 1203 imm64:$imm)>, GPR_64; 1204def SLTUImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rs), 1205 (ins GPR64Opnd:$rt, imm64:$imm), 1206 "sltu\t$rs, $rt, $imm">, GPR_64; 1207def : MipsInstAlias<"sltu\t$rs, $imm", (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, 1208 imm64:$imm)>, GPR_64; 1209 1210def SGEImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1211 (ins GPR64Opnd:$rs, imm64:$imm), 1212 "sge\t$rd, $rs, $imm">, GPR_64; 1213def : MipsInstAlias<"sge $rs, $imm", (SGEImm64 GPR64Opnd:$rs, 1214 GPR64Opnd:$rs, 1215 imm64:$imm), 0>, GPR_64; 1216 1217def SGEUImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1218 (ins GPR64Opnd:$rs, imm64:$imm), 1219 "sgeu\t$rd, $rs, $imm">, GPR_64; 1220def : MipsInstAlias<"sgeu $rs, $imm", (SGEUImm64 GPR64Opnd:$rs, 1221 GPR64Opnd:$rs, 1222 imm64:$imm), 0>, GPR_64; 1223 1224def SGTImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1225 (ins GPR64Opnd:$rs, imm64:$imm), 1226 "sgt\t$rd, $rs, $imm">, GPR_64; 1227def : MipsInstAlias<"sgt $rs, $imm", (SGTImm64 GPR64Opnd:$rs, 1228 GPR64Opnd:$rs, 1229 imm64:$imm), 0>, GPR_64; 1230 1231def SGTUImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1232 (ins GPR64Opnd:$rs, imm64:$imm), 1233 "sgtu\t$rd, $rs, $imm">, GPR_64; 1234def : MipsInstAlias<"sgtu $rs, $imm", (SGTUImm64 GPR64Opnd:$rs, 1235 GPR64Opnd:$rs, 1236 imm64:$imm), 0>, GPR_64; 1237 1238def : MipsInstAlias<"rdhwr $rt, $rs", 1239 (RDHWR64 GPR64Opnd:$rt, HWRegsOpnd:$rs, 0), 1>, GPR_64; 1240