xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/Mips32r6InstrInfo.td (revision f976241773df2260e6170317080761d1c5814fe5)
1//=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes Mips32r6 instructions.
10//
11//===----------------------------------------------------------------------===//
12
13include "Mips32r6InstrFormats.td"
14
15//===----------------------------------------------------------------------===//
16//
17// Mips profiles and nodes
18//
19//===----------------------------------------------------------------------===//
20
21def SDT_MipsFSelect : SDTypeProfile<1, 3, [SDTCisFP<1>,
22                                           SDTCisSameAs<0,2>,
23                                           SDTCisSameAs<2,3>]>;
24
25def MipsFSelect : SDNode<"MipsISD::FSELECT", SDT_MipsFSelect>;
26
27//===----------------------------------------------------------------------===//
28//
29// Mips Operands
30//
31//===----------------------------------------------------------------------===//
32
33// Notes about removals/changes from MIPS32r6:
34// Reencoded: jr -> jalr
35// Reencoded: jr.hb -> jalr.hb
36
37def brtarget21 : Operand<OtherVT> {
38  let EncoderMethod = "getBranchTarget21OpValue";
39  let OperandType = "OPERAND_PCREL";
40  let DecoderMethod = "DecodeBranchTarget21";
41  let ParserMatchClass = MipsJumpTargetAsmOperand;
42}
43
44def brtarget26 : Operand<OtherVT> {
45  let EncoderMethod = "getBranchTarget26OpValue";
46  let OperandType = "OPERAND_PCREL";
47  let DecoderMethod = "DecodeBranchTarget26";
48  let ParserMatchClass = MipsJumpTargetAsmOperand;
49}
50
51def jmpoffset16 : Operand<OtherVT> {
52  let EncoderMethod = "getJumpOffset16OpValue";
53  let ParserMatchClass = MipsJumpTargetAsmOperand;
54}
55
56def calloffset16 : Operand<iPTR> {
57  let EncoderMethod = "getJumpOffset16OpValue";
58  let ParserMatchClass = MipsJumpTargetAsmOperand;
59}
60
61//===----------------------------------------------------------------------===//
62//
63// Instruction Encodings
64//
65//===----------------------------------------------------------------------===//
66
67class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
68class ALIGN_ENC  : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
69class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
70class AUI_ENC    : AUI_FM;
71class AUIPC_ENC  : PCREL16_FM<OPCODE5_AUIPC>;
72
73class BAL_ENC   : BAL_FM;
74class BALC_ENC  : BRANCH_OFF26_FM<0b111010>;
75class BC_ENC    : BRANCH_OFF26_FM<0b110010>;
76class BEQC_ENC  : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
77                  DecodeDisambiguates<"AddiGroupBranch">;
78class BEQZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_ADDI>,
79                    DecodeDisambiguatedBy<"DaddiGroupBranch">;
80class BNEC_ENC  : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
81                  DecodeDisambiguates<"DaddiGroupBranch">;
82class BNEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_DADDI>,
83                    DecodeDisambiguatedBy<"DaddiGroupBranch">;
84
85class BLTZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZL>,
86                  DecodeDisambiguates<"BgtzlGroupBranch">;
87class BGEC_ENC  : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZL>,
88                  DecodeDisambiguatedBy<"BlezlGroupBranch">;
89class BGEUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZ>,
90                  DecodeDisambiguatedBy<"BlezGroupBranch">;
91class BGEZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZL>,
92                  DecodeDisambiguates<"BlezlGroupBranch">;
93class BGTZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZ>,
94                    DecodeDisambiguatedBy<"BgtzGroupBranch">;
95
96class BLTC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BGTZL>,
97                 DecodeDisambiguatedBy<"BgtzlGroupBranch">;
98class BLTUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BGTZ>,
99                  DecodeDisambiguatedBy<"BgtzGroupBranch">;
100
101class BLEZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZL>,
102                  DecodeDisambiguatedBy<"BlezlGroupBranch">;
103class BLTZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZ>,
104                    DecodeDisambiguates<"BgtzGroupBranch">;
105class BGTZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZL>,
106                  DecodeDisambiguatedBy<"BgtzlGroupBranch">;
107
108class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>;
109class BGEZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZ>,
110                    DecodeDisambiguates<"BlezGroupBranch">;
111class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;
112
113class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>;
114class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>;
115class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>;
116class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>;
117
118class DVP_ENC : COP0_EVP_DVP_FM<0b1>;
119class EVP_ENC : COP0_EVP_DVP_FM<0b0>;
120
121class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>;
122class JIC_ENC   : JMP_IDX_COMPACT_FM<0b110110>;
123class JR_HB_R6_ENC : JR_HB_R6_FM<OPCODE6_JALR>;
124class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
125class BLEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZ>,
126                    DecodeDisambiguatedBy<"BlezGroupBranch">;
127class BNVC_ENC   : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
128                   DecodeDisambiguatedBy<"DaddiGroupBranch">;
129class BOVC_ENC   : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
130                   DecodeDisambiguatedBy<"AddiGroupBranch">;
131class DIV_ENC    : SPECIAL_3R_FM<0b00010, 0b011010>;
132class DIVU_ENC   : SPECIAL_3R_FM<0b00010, 0b011011>;
133class MOD_ENC    : SPECIAL_3R_FM<0b00011, 0b011010>;
134class MODU_ENC   : SPECIAL_3R_FM<0b00011, 0b011011>;
135class MUH_ENC    : SPECIAL_3R_FM<0b00011, 0b011000>;
136class MUHU_ENC   : SPECIAL_3R_FM<0b00011, 0b011001>;
137class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
138class MULU_ENC   : SPECIAL_3R_FM<0b00010, 0b011001>;
139
140class MADDF_S_ENC  : COP1_3R_FM<0b011000, FIELD_FMT_S>;
141class MADDF_D_ENC  : COP1_3R_FM<0b011000, FIELD_FMT_D>;
142class MSUBF_S_ENC  : COP1_3R_FM<0b011001, FIELD_FMT_S>;
143class MSUBF_D_ENC  : COP1_3R_FM<0b011001, FIELD_FMT_D>;
144
145class SEL_D_ENC  : COP1_3R_FM<0b010000, FIELD_FMT_D>;
146class SEL_S_ENC  : COP1_3R_FM<0b010000, FIELD_FMT_S>;
147
148class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>;
149class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>;
150
151class LWPC_ENC   : PCREL19_FM<OPCODE2_LWPC>;
152
153class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
154class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
155class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
156class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
157
158class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
159class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
160class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
161class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
162
163class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
164class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
165class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
166class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
167
168class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
169class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
170class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
171class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
172
173class CACHE_ENC : SPECIAL3_MEM_FM<OPCODE6_CACHE>;
174class PREF_ENC : SPECIAL3_MEM_FM<OPCODE6_PREF>;
175
176class LDC2_R6_ENC : COP2LDST_FM<OPCODE5_LDC2>;
177class LWC2_R6_ENC : COP2LDST_FM<OPCODE5_LWC2>;
178class SDC2_R6_ENC : COP2LDST_FM<OPCODE5_SDC2>;
179class SWC2_R6_ENC : COP2LDST_FM<OPCODE5_SWC2>;
180
181class LSA_R6_ENC : SPECIAL_LSA_FM<OPCODE6_LSA>;
182
183class LL_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LL>;
184class SC_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SC>;
185
186class CLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLO>;
187class CLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLZ>;
188
189class SDBBP_R6_ENC : SPECIAL_SDBBP_FM;
190
191class CRC32B_ENC  : SPECIAL3_2R_SZ_CRC<0,0>;
192class CRC32H_ENC  : SPECIAL3_2R_SZ_CRC<1,0>;
193class CRC32W_ENC  : SPECIAL3_2R_SZ_CRC<2,0>;
194class CRC32CB_ENC : SPECIAL3_2R_SZ_CRC<0,1>;
195class CRC32CH_ENC : SPECIAL3_2R_SZ_CRC<1,1>;
196class CRC32CW_ENC : SPECIAL3_2R_SZ_CRC<2,1>;
197
198class GINVI_ENC : SPECIAL3_GINV<0>;
199class GINVT_ENC : SPECIAL3_GINV<2>;
200
201class SIGRIE_ENC : SIGRIE_FM;
202
203//===----------------------------------------------------------------------===//
204//
205// Instruction Multiclasses
206//
207//===----------------------------------------------------------------------===//
208
209class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,
210                          RegisterOperand FGROpnd,
211                          InstrItinClass Itin,
212                          SDPatternOperator Op = null_frag> {
213  dag OutOperandList = (outs FGRCCOpnd:$fd);
214  dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
215  string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
216  list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))];
217  bit isCTI = 1;
218  InstrItinClass Itinerary = Itin;
219}
220
221multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
222                     RegisterOperand FGROpnd, InstrItinClass Itin>{
223  let AdditionalPredicates = [NotInMicroMips] in {
224    def CMP_F_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_AF>,
225                      CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd, Itin>,
226                      MipsR6Arch<!strconcat("cmp.af.", Typestr)>,
227                      ISA_MIPS32R6, HARDFLOAT;
228    def CMP_UN_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
229                       CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, Itin, setuo>,
230                       MipsR6Arch<!strconcat("cmp.un.", Typestr)>,
231                       ISA_MIPS32R6, HARDFLOAT;
232    def CMP_EQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
233                       CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, Itin,
234                                           setoeq>,
235                       MipsR6Arch<!strconcat("cmp.eq.", Typestr)>,
236                       ISA_MIPS32R6, HARDFLOAT;
237    def CMP_UEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
238                                                     FIELD_CMP_COND_UEQ>,
239                        CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, Itin,
240                                            setueq>,
241                        MipsR6Arch<!strconcat("cmp.ueq.", Typestr)>,
242                        ISA_MIPS32R6, HARDFLOAT;
243    def CMP_LT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
244                       CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, Itin,
245                                           setolt>,
246                       MipsR6Arch<!strconcat("cmp.lt.", Typestr)>,
247                       ISA_MIPS32R6, HARDFLOAT;
248    def CMP_ULT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
249                                                     FIELD_CMP_COND_ULT>,
250                        CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, Itin,
251                                            setult>,
252                        MipsR6Arch<!strconcat("cmp.ult.", Typestr)>,
253                        ISA_MIPS32R6, HARDFLOAT;
254    def CMP_LE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
255                       CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, Itin,
256                                           setole>,
257                       MipsR6Arch<!strconcat("cmp.le.", Typestr)>,
258                       ISA_MIPS32R6, HARDFLOAT;
259    def CMP_ULE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
260                                                     FIELD_CMP_COND_ULE>,
261                        CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, Itin,
262                                            setule>,
263                        MipsR6Arch<!strconcat("cmp.ule.", Typestr)>,
264                        ISA_MIPS32R6, HARDFLOAT;
265    def CMP_SAF_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
266                                                     FIELD_CMP_COND_SAF>,
267                        CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd, Itin>,
268                        MipsR6Arch<!strconcat("cmp.saf.", Typestr)>,
269                        ISA_MIPS32R6, HARDFLOAT;
270    def CMP_SUN_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
271                                                     FIELD_CMP_COND_SUN>,
272                        CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd, Itin>,
273                        MipsR6Arch<!strconcat("cmp.sun.", Typestr)>,
274                        ISA_MIPS32R6, HARDFLOAT;
275    def CMP_SEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
276                                                     FIELD_CMP_COND_SEQ>,
277                        CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd, Itin>,
278                        MipsR6Arch<!strconcat("cmp.seq.", Typestr)>,
279                        ISA_MIPS32R6, HARDFLOAT;
280    def CMP_SUEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
281                                                      FIELD_CMP_COND_SUEQ>,
282                         CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd, Itin>,
283                         MipsR6Arch<!strconcat("cmp.sueq.", Typestr)>,
284                         ISA_MIPS32R6, HARDFLOAT;
285    def CMP_SLT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
286                                                     FIELD_CMP_COND_SLT>,
287                        CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd, Itin>,
288                        MipsR6Arch<!strconcat("cmp.slt.", Typestr)>,
289                        ISA_MIPS32R6, HARDFLOAT;
290    def CMP_SULT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
291                                                      FIELD_CMP_COND_SULT>,
292                         CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd, Itin>,
293                         MipsR6Arch<!strconcat("cmp.sult.", Typestr)>,
294                         ISA_MIPS32R6, HARDFLOAT;
295    def CMP_SLE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
296                                                     FIELD_CMP_COND_SLE>,
297                        CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd, Itin>,
298                        MipsR6Arch<!strconcat("cmp.sle.", Typestr)>,
299                        ISA_MIPS32R6, HARDFLOAT;
300    def CMP_SULE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
301                                                      FIELD_CMP_COND_SULE>,
302                         CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd, Itin>,
303                         MipsR6Arch<!strconcat("cmp.sule.", Typestr)>,
304                         ISA_MIPS32R6, HARDFLOAT;
305  }
306}
307
308//===----------------------------------------------------------------------===//
309//
310// Instruction Descriptions
311//
312//===----------------------------------------------------------------------===//
313
314class PCREL_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
315                      Operand ImmOpnd, InstrItinClass itin>
316      : MipsR6Arch<instr_asm> {
317  dag OutOperandList = (outs GPROpnd:$rs);
318  dag InOperandList = (ins ImmOpnd:$imm);
319  string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
320  list<dag> Pattern = [];
321  InstrItinClass Itinerary = itin;
322}
323
324class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2,
325                                     II_ADDIUPC>;
326class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2, II_LWPC>;
327
328class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
329                      Operand ImmOpnd, InstrItinClass itin>
330      : MipsR6Arch<instr_asm> {
331  dag OutOperandList = (outs GPROpnd:$rd);
332  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
333  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
334  list<dag> Pattern = [];
335  InstrItinClass Itinerary = itin;
336}
337
338class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2, II_ALIGN>;
339
340class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
341                       InstrItinClass itin = NoItinerary>
342      : MipsR6Arch<instr_asm> {
343  dag OutOperandList = (outs GPROpnd:$rs);
344  dag InOperandList = (ins simm16:$imm);
345  string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
346  list<dag> Pattern = [];
347  InstrItinClass Itinerary = itin;
348}
349
350class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd, II_ALUIPC>;
351class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd, II_AUIPC>;
352
353class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
354                    InstrItinClass itin = NoItinerary>
355      : MipsR6Arch<instr_asm> {
356  dag OutOperandList = (outs GPROpnd:$rt);
357  dag InOperandList = (ins GPROpnd:$rs, uimm16:$imm);
358  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
359  list<dag> Pattern = [];
360  InstrItinClass Itinerary = itin;
361}
362
363class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd, II_AUI>;
364
365class BRANCH_DESC_BASE {
366  bit isBranch = 1;
367  bit isTerminator = 1;
368  bit hasDelaySlot = 0;
369  bit isCTI = 1;
370}
371
372class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE,
373    MipsR6Arch<instr_asm> {
374  dag InOperandList = (ins opnd:$offset);
375  dag OutOperandList = (outs);
376  string AsmString = !strconcat(instr_asm, "\t$offset");
377  bit isBarrier = 1;
378  InstrItinClass Itinerary = II_BC;
379  bit isCTI = 1;
380}
381
382class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
383                       RegisterOperand GPROpnd> : BRANCH_DESC_BASE,
384                                                  MipsR6Arch<instr_asm> {
385  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
386  dag OutOperandList = (outs);
387  string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
388  list<Register> Defs = [AT];
389  InstrItinClass Itinerary = II_BCCC;
390  bit hasForbiddenSlot = 1;
391  bit isCTI = 1;
392}
393
394class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
395                               RegisterOperand GPROpnd>
396    : BRANCH_DESC_BASE, MipsR6Arch<instr_asm> {
397  dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);
398  dag OutOperandList = (outs);
399  string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
400  list<Register> Defs = [AT];
401  InstrItinClass Itinerary = II_BCCZC;
402  bit hasForbiddenSlot = 1;
403  bit isCTI = 1;
404}
405
406class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
407                             RegisterOperand GPROpnd>
408    : BRANCH_DESC_BASE, MipsR6Arch<instr_asm> {
409  dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
410  dag OutOperandList = (outs);
411  string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
412  list<Register> Defs = [AT];
413  InstrItinClass Itinerary = II_BCCZC;
414  bit hasForbiddenSlot = 1;
415  bit isCTI = 1;
416}
417
418class BAL_DESC : BC_DESC_BASE<"bal", brtarget> {
419  bit isCall = 1;
420  bit hasDelaySlot = 1;
421  list<Register> Defs = [RA];
422  bit isCTI = 1;
423}
424
425class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
426  bit isCall = 1;
427  list<Register> Defs = [RA];
428  InstrItinClass Itinerary = II_BALC;
429  bit isCTI = 1;
430}
431
432class BC_DESC : BC_DESC_BASE<"bc", brtarget26>;
433class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>;
434class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
435class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
436class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
437
438class BLTC_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR32Opnd>;
439class BLTUC_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR32Opnd>;
440
441class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
442class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
443
444class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
445class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
446
447class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
448class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
449
450class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
451  dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset);
452  dag OutOperandList = (outs);
453  string AsmString = instr_asm;
454  bit hasDelaySlot = 1;
455  InstrItinClass Itinerary = II_BC1CCZ;
456}
457
458class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">;
459class BC1NEZ_DESC : COP1_BCCZ_DESC_BASE<"bc1nez $ft, $offset">;
460
461class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
462  dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset);
463  dag OutOperandList = (outs);
464  string AsmString = instr_asm;
465  bit hasDelaySlot = 1;
466  bit isCTI = 1;
467  InstrItinClass Itinerary = II_BC2CCZ;
468}
469
470class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">;
471class BC2NEZ_DESC : COP2_BCCZ_DESC_BASE<"bc2nez $ct, $offset">;
472
473class BOVC_DESC   : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>;
474class BNVC_DESC   : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>;
475
476class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
477                                RegisterOperand GPROpnd,
478                                InstrItinClass itin = NoItinerary>
479    : MipsR6Arch<opstr> {
480  dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
481  string AsmString = !strconcat(opstr, "\t$rt, $offset");
482  list<dag> Pattern = [];
483  bit hasDelaySlot = 0;
484  InstrItinClass Itinerary = itin;
485  bit isCTI = 1;
486  bit isBranch = 1;
487  bit isIndirectBranch = 1;
488}
489
490class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
491                                             GPR32Opnd, II_JIALC> {
492  bit isCall = 1;
493  list<Register> Defs = [RA];
494}
495
496class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
497                                           GPR32Opnd, II_JIALC> {
498  bit isBarrier = 1;
499  bit isTerminator = 1;
500  list<Register> Defs = [AT];
501}
502
503class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
504  bit isBranch = 1;
505  bit isIndirectBranch = 1;
506  bit hasDelaySlot = 1;
507  bit isTerminator=1;
508  bit isBarrier=1;
509  bit isCTI = 1;
510  InstrItinClass Itinerary = II_JR_HB;
511}
512
513class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
514                        InstrItinClass itin>
515    : MipsR6Arch<instr_asm> {
516  dag OutOperandList = (outs GPROpnd:$rd);
517  dag InOperandList = (ins GPROpnd:$rt);
518  string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
519  list<dag> Pattern = [];
520  InstrItinClass Itinerary = itin;
521}
522
523class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd, II_BITSWAP>;
524
525class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
526                       InstrItinClass itin,
527                       SDPatternOperator Op=null_frag>
528    : MipsR6Arch<instr_asm> {
529  dag OutOperandList = (outs GPROpnd:$rd);
530  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
531  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
532  list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
533  InstrItinClass Itinerary = itin;
534  // This instruction doesn't trap division by zero itself. We must insert
535  // teq instructions as well.
536  bit usesCustomInserter = 1;
537}
538
539class DVPEVP_DESC_BASE<string instr_asm, InstrItinClass Itin>
540    : MipsR6Arch<instr_asm> {
541  dag OutOperandList = (outs GPR32Opnd:$rt);
542  dag InOperandList = (ins);
543  string AsmString = !strconcat(instr_asm, "\t$rt");
544  list<dag> Pattern = [];
545  InstrItinClass Itinerary = Itin;
546  bit hasUnModeledSideEffects = 1;
547}
548
549class DVP_DESC : DVPEVP_DESC_BASE<"dvp", II_DVP>;
550class EVP_DESC : DVPEVP_DESC_BASE<"evp", II_EVP>;
551
552class DIV_DESC  : DIVMOD_DESC_BASE<"div", GPR32Opnd, II_DIV, sdiv>;
553class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, II_DIVU, udiv>;
554class MOD_DESC  : DIVMOD_DESC_BASE<"mod", GPR32Opnd, II_MOD, srem>;
555class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, II_MODU, urem>;
556
557class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
558  list<Register> Defs = [RA];
559}
560
561class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> {
562  list<Register> Defs = [RA];
563}
564
565class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> {
566  list<Register> Defs = [RA];
567}
568
569class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> {
570  list<Register> Defs = [RA];
571}
572
573class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> {
574  list<Register> Defs = [RA];
575}
576
577class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> {
578  list<Register> Defs = [RA];
579}
580
581class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
582                       InstrItinClass itin,
583                       SDPatternOperator Op=null_frag> : MipsR6Arch<instr_asm> {
584  dag OutOperandList = (outs GPROpnd:$rd);
585  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
586  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
587  list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
588  InstrItinClass Itinerary = itin;
589}
590
591class MUH_DESC    : MUL_R6_DESC_BASE<"muh", GPR32Opnd, II_MUH, mulhs>;
592class MUHU_DESC   : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, II_MUHU, mulhu>;
593class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, II_MUL, mul>;
594class MULU_DESC   : MUL_R6_DESC_BASE<"mulu", GPR32Opnd, II_MULU>;
595
596class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
597                         InstrItinClass itin> {
598  dag OutOperandList = (outs FGROpnd:$fd);
599  dag InOperandList = (ins FGRCCOpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
600  string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
601  list<dag> Pattern = [(set FGROpnd:$fd, (select FGRCCOpnd:$fd_in,
602                                                 FGROpnd:$ft,
603                                                 FGROpnd:$fs))];
604  string Constraints = "$fd_in = $fd";
605  InstrItinClass Itinerary = itin;
606}
607
608class COP1_SEL_D_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
609                           InstrItinClass itin> {
610  dag OutOperandList = (outs FGROpnd:$fd);
611  dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
612  string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
613  list<dag> Pattern = [(set FGROpnd:$fd, (MipsFSelect FGROpnd:$fd_in,
614                                                      FGROpnd:$ft,
615                                                      FGROpnd:$fs))];
616  string Constraints = "$fd_in = $fd";
617  InstrItinClass Itinerary = itin;
618}
619
620class SEL_D_DESC : COP1_SEL_D_DESC_BASE<"sel.d", FGR64Opnd, II_SEL_D>,
621                   MipsR6Arch<"sel.d">;
622class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd, II_SEL_S>,
623                   MipsR6Arch<"sel.s">;
624
625class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
626    : MipsR6Arch<instr_asm> {
627  dag OutOperandList = (outs GPROpnd:$rd);
628  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
629  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
630  list<dag> Pattern = [];
631  InstrItinClass Itinerary = II_SELCCZ;
632}
633
634class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>;
635class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>;
636
637class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
638                        InstrItinClass itin = NoItinerary> {
639  dag OutOperandList = (outs FGROpnd:$fd);
640  dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
641  string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
642  list<dag> Pattern = [];
643  string Constraints = "$fd_in = $fd";
644  InstrItinClass Itinerary = itin;
645}
646
647class MADDF_S_DESC  : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd, II_MADDF_S>;
648class MADDF_D_DESC  : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd, II_MADDF_D>;
649class MSUBF_S_DESC  : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd, II_MSUBF_S>;
650class MSUBF_D_DESC  : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd, II_MSUBF_D>;
651
652class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
653                        InstrItinClass itin> {
654  dag OutOperandList = (outs FGROpnd:$fd);
655  dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
656  string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
657  list<dag> Pattern = [];
658  InstrItinClass Itinerary = itin;
659}
660
661class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd, II_MAX_S>;
662class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd, II_MAX_D>;
663class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd, II_MIN_S>;
664class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd, II_MIN_D>;
665
666class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd, II_MAX_S>;
667class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd, II_MAX_D>;
668class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd, II_MIN_D>;
669class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd, II_MIN_S>;
670
671class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
672                         InstrItinClass itin> {
673  dag OutOperandList = (outs FGROpnd:$fd);
674  dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
675  string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
676  list<dag> Pattern = [];
677  InstrItinClass Itinerary = itin;
678}
679
680class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd, II_SELCCZ_S>,
681                      MipsR6Arch<"seleqz.s">;
682class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd, II_SELCCZ_D>,
683                      MipsR6Arch<"seleqz.d">;
684class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd, II_SELCCZ_S>,
685                      MipsR6Arch<"selnez.s">;
686class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd, II_SELCCZ_D>,
687                      MipsR6Arch<"selnez.d">;
688
689class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
690                           InstrItinClass itin> {
691  dag OutOperandList = (outs FGROpnd:$fd);
692  dag InOperandList = (ins FGROpnd:$fs);
693  string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
694  list<dag> Pattern = [];
695  InstrItinClass Itinerary = itin;
696}
697
698class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd, II_RINT_S>;
699class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd, II_RINT_D>;
700class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd, II_CLASS_S>;
701class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd, II_CLASS_D>;
702
703class CACHE_HINT_DESC<string instr_asm, Operand MemOpnd,
704                      RegisterOperand GPROpnd, InstrItinClass itin>
705                     : MipsR6Arch<instr_asm> {
706  dag OutOperandList = (outs);
707  dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
708  string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
709  list<dag> Pattern = [];
710  string DecoderMethod = "DecodeCacheeOp_CacheOpR6";
711  InstrItinClass Itinerary = itin;
712}
713
714class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, GPR32Opnd, II_CACHE>;
715class PREF_DESC : CACHE_HINT_DESC<"pref", mem_simm9, GPR32Opnd, II_PREF>;
716
717class COP2LD_DESC_BASE<string instr_asm, RegisterOperand COPOpnd,
718                       InstrItinClass itin> {
719  dag OutOperandList = (outs COPOpnd:$rt);
720  dag InOperandList = (ins mem_simm11:$addr);
721  string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
722  list<dag> Pattern = [];
723  bit mayLoad = 1;
724  string DecoderMethod = "DecodeFMemCop2R6";
725  InstrItinClass Itinerary = itin;
726}
727
728class LDC2_R6_DESC : COP2LD_DESC_BASE<"ldc2", COP2Opnd, II_LDC2>;
729class LWC2_R6_DESC : COP2LD_DESC_BASE<"lwc2", COP2Opnd, II_LWC2>;
730
731class COP2ST_DESC_BASE<string instr_asm, RegisterOperand COPOpnd,
732                       InstrItinClass itin> {
733  dag OutOperandList = (outs);
734  dag InOperandList = (ins COPOpnd:$rt, mem_simm11:$addr);
735  string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
736  list<dag> Pattern = [];
737  bit mayStore = 1;
738  string DecoderMethod = "DecodeFMemCop2R6";
739  InstrItinClass Itinerary = itin;
740}
741
742class SDC2_R6_DESC : COP2ST_DESC_BASE<"sdc2", COP2Opnd, II_SDC2>;
743class SWC2_R6_DESC : COP2ST_DESC_BASE<"swc2", COP2Opnd, II_SWC2>;
744
745class LSA_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
746                       Operand ImmOpnd, InstrItinClass itin>
747      : MipsR6Arch<instr_asm> {
748  dag OutOperandList = (outs GPROpnd:$rd);
749  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
750  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $imm2");
751  list<dag> Pattern = [];
752  InstrItinClass Itinerary = itin;
753}
754
755class LSA_R6_DESC : LSA_R6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1, II_LSA>;
756
757class LL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
758                      Operand MemOpnd, InstrItinClass itin>
759      : MipsR6Arch<instr_asm> {
760  dag OutOperandList = (outs GPROpnd:$rt);
761  dag InOperandList = (ins MemOpnd:$addr);
762  string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
763  list<dag> Pattern = [];
764  bit mayLoad = 1;
765  InstrItinClass Itinerary = itin;
766}
767
768class LL_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, mem_simm9, II_LL>;
769
770class SC_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
771                      InstrItinClass itin> {
772  dag OutOperandList = (outs GPROpnd:$dst);
773  dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr);
774  string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
775  list<dag> Pattern = [];
776  bit mayStore = 1;
777  string Constraints = "$rt = $dst";
778  InstrItinClass Itinerary = itin;
779}
780
781class SC_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd, II_SC>;
782
783class CLO_CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
784                           InstrItinClass itin>
785    : MipsR6Arch<instr_asm> {
786  dag OutOperandList = (outs GPROpnd:$rd);
787  dag InOperandList = (ins GPROpnd:$rs);
788  string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
789  InstrItinClass Itinerary = itin;
790}
791
792class CLO_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
793                       InstrItinClass itin> :
794    CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd, itin> {
795  list<dag> Pattern = [(set GPROpnd:$rd, (ctlz (not GPROpnd:$rs)))];
796}
797
798class CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
799                       InstrItinClass itin> :
800    CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd, itin> {
801  list<dag> Pattern = [(set GPROpnd:$rd, (ctlz GPROpnd:$rs))];
802}
803
804class CLO_R6_DESC : CLO_R6_DESC_BASE<"clo", GPR32Opnd, II_CLO>;
805class CLZ_R6_DESC : CLZ_R6_DESC_BASE<"clz", GPR32Opnd, II_CLZ>;
806
807class SDBBP_R6_DESC {
808  dag OutOperandList = (outs);
809  dag InOperandList = (ins uimm20:$code_);
810  string AsmString = "sdbbp\t$code_";
811  list<dag> Pattern = [];
812  bit isCTI = 1;
813  InstrItinClass Itinerary = II_SDBBP;
814}
815
816class CRC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
817                    InstrItinClass itin> : MipsR6Arch<instr_asm> {
818  dag OutOperandList = (outs GPROpnd:$rd);
819  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
820  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
821  list<dag> Pattern = [];
822  InstrItinClass Itinerary = itin;
823}
824
825class CRC32B_DESC : CRC_DESC_BASE<"crc32b", GPR32Opnd, II_CRC32B>;
826class CRC32H_DESC : CRC_DESC_BASE<"crc32h", GPR32Opnd, II_CRC32H>;
827class CRC32W_DESC : CRC_DESC_BASE<"crc32w", GPR32Opnd, II_CRC32W>;
828class CRC32CB_DESC : CRC_DESC_BASE<"crc32cb", GPR32Opnd, II_CRC32CB>;
829class CRC32CH_DESC : CRC_DESC_BASE<"crc32ch", GPR32Opnd, II_CRC32CH>;
830class CRC32CW_DESC : CRC_DESC_BASE<"crc32cw", GPR32Opnd, II_CRC32CW>;
831
832class GINV_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
833                     InstrItinClass itin> : MipsR6Arch<instr_asm> {
834  dag OutOperandList = (outs);
835  dag InOperandList = (ins GPROpnd:$rs, uimm2:$type_);
836  string AsmString = !strconcat(instr_asm, "\t$rs, $type_");
837  list<dag> Pattern = [];
838  InstrItinClass Itinerary = itin;
839  bit hasSideEffects = 1;
840}
841
842class GINVI_DESC : GINV_DESC_BASE<"ginvi", GPR32Opnd, II_GINVI> {
843  dag InOperandList = (ins GPR32Opnd:$rs);
844  string AsmString = "ginvi\t$rs";
845}
846class GINVT_DESC : GINV_DESC_BASE<"ginvt", GPR32Opnd, II_GINVT>;
847
848class SIGRIE_DESC {
849  dag OutOperandList = (outs);
850  dag InOperandList = (ins uimm16:$code_);
851  string AsmString = "sigrie\t$code_";
852  list<dag> Pattern = [];
853  InstrItinClass Itinerary = II_SIGRIE;
854}
855
856//===----------------------------------------------------------------------===//
857//
858// Instruction Definitions
859//
860//===----------------------------------------------------------------------===//
861
862def ADDIUPC : R6MMR6Rel, ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
863def ALIGN : R6MMR6Rel, ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
864def ALUIPC : R6MMR6Rel, ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
865def AUI : R6MMR6Rel, AUI_ENC, AUI_DESC, ISA_MIPS32R6;
866def AUIPC : R6MMR6Rel, AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
867def BAL : BAL_ENC, BAL_DESC, ISA_MIPS32R6;
868def BALC : R6MMR6Rel, BALC_ENC, BALC_DESC, ISA_MIPS32R6;
869let AdditionalPredicates = [NotInMicroMips] in {
870  def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6, HARDFLOAT;
871  def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6, HARDFLOAT;
872  def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6;
873  def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;
874  def BC : R6MMR6Rel, BC_ENC, BC_DESC, ISA_MIPS32R6;
875  def BEQC : R6MMR6Rel, BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
876  def BEQZALC : R6MMR6Rel, BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
877  def BEQZC : R6MMR6Rel, BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
878  def BGEC : R6MMR6Rel, BGEC_ENC, BGEC_DESC, ISA_MIPS32R6;
879  def BGEUC : R6MMR6Rel, BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6;
880  def BGEZALC : R6MMR6Rel, BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
881  def BGEZC : R6MMR6Rel, BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
882  def BGTZALC : R6MMR6Rel, BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6;
883  def BGTZC : R6MMR6Rel, BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
884}
885def BITSWAP : R6MMR6Rel, BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
886let AdditionalPredicates = [NotInMicroMips] in {
887  def BLEZALC : R6MMR6Rel, BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;
888  def BLEZC : R6MMR6Rel, BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
889  def BLTC : R6MMR6Rel, BLTC_ENC, BLTC_DESC, ISA_MIPS32R6;
890  def BLTUC : R6MMR6Rel, BLTUC_ENC, BLTUC_DESC, ISA_MIPS32R6;
891  def BLTZALC : R6MMR6Rel, BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
892  def BLTZC : R6MMR6Rel, BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
893  def BNEC : R6MMR6Rel, BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
894  def BNEZALC : R6MMR6Rel, BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
895  def BNEZC : R6MMR6Rel, BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
896  def BNVC : R6MMR6Rel, BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
897  def BOVC : R6MMR6Rel, BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
898  def CACHE_R6 : R6MMR6Rel, CACHE_ENC, CACHE_DESC, ISA_MIPS32R6;
899  def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6, HARDFLOAT;
900  def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6, HARDFLOAT;
901}
902def CLO_R6 : R6MMR6Rel, CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6;
903def CLZ_R6 : R6MMR6Rel, CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6;
904defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd, II_CMP_CC_S>;
905defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd, II_CMP_CC_D>;
906let AdditionalPredicates = [NotInMicroMips] in {
907  def DIV : R6MMR6Rel, DIV_ENC, DIV_DESC, ISA_MIPS32R6;
908  def DIVU : R6MMR6Rel, DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
909}
910
911def DVP : R6MMR6Rel, DVP_ENC, DVP_DESC, ISA_MIPS32R6;
912def EVP : R6MMR6Rel, EVP_ENC, EVP_DESC, ISA_MIPS32R6;
913
914def JIALC : R6MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
915def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6;
916def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
917let AdditionalPredicates = [NotInMicroMips] in {
918  def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6;
919  def LL_R6 : LL_R6_ENC, LL_R6_DESC, PTR_32, ISA_MIPS32R6;
920}
921def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6;
922let AdditionalPredicates = [NotInMicroMips] in {
923  def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6;
924}
925def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
926let AdditionalPredicates = [NotInMicroMips] in {
927  def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
928  def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
929  def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
930  def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
931  def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6, HARDFLOAT;
932  def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6, HARDFLOAT;
933  def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
934  def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
935  def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6, HARDFLOAT;
936  def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6, HARDFLOAT;
937
938  def MOD : R6MMR6Rel, MOD_ENC, MOD_DESC, ISA_MIPS32R6;
939  def MODU : R6MMR6Rel, MODU_ENC, MODU_DESC, ISA_MIPS32R6;
940
941  def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
942  def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
943
944  def MUH    : R6MMR6Rel, MUH_ENC, MUH_DESC, ISA_MIPS32R6;
945  def MUHU   : R6MMR6Rel, MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
946  def MUL_R6 : R6MMR6Rel, MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
947  def MULU   : R6MMR6Rel, MULU_ENC, MULU_DESC, ISA_MIPS32R6;
948}
949def NAL; // BAL with rd=0
950let AdditionalPredicates = [NotInMicroMips] in {
951  def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6;
952  def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT;
953  def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT;
954  def SC_R6 : SC_R6_ENC, SC_R6_DESC, PTR_32, ISA_MIPS32R6;
955  def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6;
956  def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
957  def SELNEZ : R6MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
958  def SELEQZ_D : R6MMR6Rel, SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6,
959                 HARDFLOAT;
960  def SELEQZ_S : R6MMR6Rel, SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6,
961                 HARDFLOAT;
962  def SELNEZ_D : R6MMR6Rel, SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6,
963                 HARDFLOAT;
964  def SELNEZ_S : R6MMR6Rel, SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6,
965                 HARDFLOAT;
966  def SEL_D : R6MMR6Rel, SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6, HARDFLOAT;
967  def SEL_S : R6MMR6Rel, SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT;
968  def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
969  def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
970  def SIGRIE : SIGRIE_ENC, SIGRIE_DESC, ISA_MIPS32R6;
971}
972
973let AdditionalPredicates = [NotInMicroMips] in {
974  def CRC32B : R6MMR6Rel, CRC32B_ENC, CRC32B_DESC, ISA_MIPS32R6, ASE_CRC;
975  def CRC32H : R6MMR6Rel, CRC32H_ENC, CRC32H_DESC, ISA_MIPS32R6, ASE_CRC;
976  def CRC32W : R6MMR6Rel, CRC32W_ENC, CRC32W_DESC, ISA_MIPS32R6, ASE_CRC;
977  def CRC32CB : R6MMR6Rel, CRC32CB_ENC, CRC32CB_DESC, ISA_MIPS32R6, ASE_CRC;
978  def CRC32CH : R6MMR6Rel, CRC32CH_ENC, CRC32CH_DESC, ISA_MIPS32R6, ASE_CRC;
979  def CRC32CW : R6MMR6Rel, CRC32CW_ENC, CRC32CW_DESC, ISA_MIPS32R6, ASE_CRC;
980}
981
982let AdditionalPredicates = [NotInMicroMips] in {
983  def GINVI : R6MMR6Rel, GINVI_ENC, GINVI_DESC, ISA_MIPS32R6, ASE_GINV;
984  def GINVT : R6MMR6Rel, GINVT_ENC, GINVT_DESC, ISA_MIPS32R6, ASE_GINV;
985}
986
987//===----------------------------------------------------------------------===//
988//
989// Instruction Aliases
990//
991//===----------------------------------------------------------------------===//
992
993def : MipsInstAlias<"dvp", (DVP ZERO), 0>, ISA_MIPS32R6;
994def : MipsInstAlias<"evp", (EVP ZERO), 0>, ISA_MIPS32R6;
995
996let AdditionalPredicates = [NotInMicroMips] in {
997def : MipsInstAlias<"sdbbp", (SDBBP_R6 0)>, ISA_MIPS32R6;
998def : MipsInstAlias<"sigrie", (SIGRIE 0)>, ISA_MIPS32R6;
999def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6, GPR_32;
1000}
1001
1002def : MipsInstAlias<"jrc $rs", (JIC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
1003
1004let AdditionalPredicates = [NotInMicroMips] in {
1005def : MipsInstAlias<"jalrc $rs", (JIALC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
1006}
1007
1008def : MipsInstAlias<"div $rs, $rt", (DIV GPR32Opnd:$rs, GPR32Opnd:$rs,
1009                                         GPR32Opnd:$rt)>, ISA_MIPS32R6;
1010def : MipsInstAlias<"divu $rs, $rt", (DIVU GPR32Opnd:$rs, GPR32Opnd:$rs,
1011                                           GPR32Opnd:$rt)>, ISA_MIPS32R6;
1012
1013def : MipsInstAlias<"lapc $rd, $imm",
1014                    (ADDIUPC GPR32Opnd:$rd, simm19_lsl2:$imm)>, ISA_MIPS32R6;
1015
1016//===----------------------------------------------------------------------===//
1017//
1018// Patterns and Pseudo Instructions
1019//
1020//===----------------------------------------------------------------------===//
1021
1022// comparisons supported via another comparison
1023multiclass Cmp_Pats<ValueType VT, Instruction NOROp, Register ZEROReg> {
1024def : MipsPat<(setone VT:$lhs, VT:$rhs),
1025      (NOROp (!cast<Instruction>("CMP_UEQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
1026def : MipsPat<(seto VT:$lhs, VT:$rhs),
1027      (NOROp (!cast<Instruction>("CMP_UN_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
1028def : MipsPat<(setune VT:$lhs, VT:$rhs),
1029      (NOROp (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
1030def : MipsPat<(seteq VT:$lhs, VT:$rhs),
1031      (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs)>;
1032def : MipsPat<(setgt VT:$lhs, VT:$rhs),
1033      (!cast<Instruction>("CMP_LE_"#NAME) VT:$rhs, VT:$lhs)>;
1034def : MipsPat<(setge VT:$lhs, VT:$rhs),
1035      (!cast<Instruction>("CMP_LT_"#NAME) VT:$rhs, VT:$lhs)>;
1036def : MipsPat<(setlt VT:$lhs, VT:$rhs),
1037      (!cast<Instruction>("CMP_LT_"#NAME) VT:$lhs, VT:$rhs)>;
1038def : MipsPat<(setle VT:$lhs, VT:$rhs),
1039      (!cast<Instruction>("CMP_LE_"#NAME) VT:$lhs, VT:$rhs)>;
1040def : MipsPat<(setne VT:$lhs, VT:$rhs),
1041      (NOROp (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
1042}
1043
1044let AdditionalPredicates = [NotInMicroMips] in {
1045  defm S : Cmp_Pats<f32, NOR, ZERO>, ISA_MIPS32R6;
1046  defm D : Cmp_Pats<f64, NOR, ZERO>, ISA_MIPS32R6;
1047}
1048
1049// i32 selects
1050multiclass SelectInt_Pats<ValueType RC, Instruction OROp, Instruction XORiOp,
1051                          Instruction SLTiOp, Instruction SLTiuOp,
1052                          Instruction SELEQZOp, Instruction SELNEZOp,
1053                          SDPatternOperator imm_type, ValueType Opg> {
1054// reg, immz
1055def : MipsPat<(select (Opg (seteq RC:$cond, immz)), RC:$t, RC:$f),
1056              (OROp (SELEQZOp RC:$t, RC:$cond), (SELNEZOp RC:$f, RC:$cond))>;
1057def : MipsPat<(select (Opg (setne RC:$cond, immz)), RC:$t, RC:$f),
1058              (OROp (SELNEZOp RC:$t, RC:$cond), (SELEQZOp RC:$f, RC:$cond))>;
1059
1060// reg, immZExt16[_64]
1061def : MipsPat<(select (Opg (seteq RC:$cond, imm_type:$imm)), RC:$t, RC:$f),
1062              (OROp (SELEQZOp RC:$t, (XORiOp RC:$cond, imm_type:$imm)),
1063                    (SELNEZOp RC:$f, (XORiOp RC:$cond, imm_type:$imm)))>;
1064def : MipsPat<(select (Opg (setne RC:$cond, imm_type:$imm)), RC:$t, RC:$f),
1065              (OROp (SELNEZOp RC:$t, (XORiOp RC:$cond, imm_type:$imm)),
1066                    (SELEQZOp RC:$f, (XORiOp RC:$cond, imm_type:$imm)))>;
1067
1068// reg, immSExt16Plus1
1069def : MipsPat<(select (Opg (setgt RC:$cond, immSExt16Plus1:$imm)), RC:$t, RC:$f),
1070              (OROp (SELEQZOp RC:$t, (SLTiOp RC:$cond, (Plus1 imm:$imm))),
1071                    (SELNEZOp RC:$f, (SLTiOp RC:$cond, (Plus1 imm:$imm))))>;
1072def : MipsPat<(select (Opg (setugt RC:$cond, immSExt16Plus1:$imm)), RC:$t, RC:$f),
1073              (OROp (SELEQZOp RC:$t, (SLTiuOp RC:$cond, (Plus1 imm:$imm))),
1074                    (SELNEZOp RC:$f, (SLTiuOp RC:$cond, (Plus1 imm:$imm))))>;
1075
1076def : MipsPat<(select (Opg (seteq RC:$cond, immz)), RC:$t, immz),
1077              (SELEQZOp RC:$t, RC:$cond)>;
1078def : MipsPat<(select (Opg (setne RC:$cond, immz)), RC:$t, immz),
1079              (SELNEZOp RC:$t, RC:$cond)>;
1080def : MipsPat<(select (Opg (seteq RC:$cond, immz)), immz, RC:$f),
1081              (SELNEZOp RC:$f, RC:$cond)>;
1082def : MipsPat<(select (Opg (setne RC:$cond, immz)), immz, RC:$f),
1083              (SELEQZOp RC:$f, RC:$cond)>;
1084}
1085
1086let AdditionalPredicates = [NotInMicroMips] in {
1087defm : SelectInt_Pats<i32, OR, XORi, SLTi, SLTiu, SELEQZ, SELNEZ,
1088                      immZExt16, i32>, ISA_MIPS32R6;
1089
1090def : MipsPat<(select i32:$cond, i32:$t, i32:$f),
1091              (OR (SELNEZ i32:$t, i32:$cond),
1092                  (SELEQZ i32:$f, i32:$cond))>,
1093              ISA_MIPS32R6;
1094def : MipsPat<(select i32:$cond, i32:$t, immz),
1095              (SELNEZ i32:$t, i32:$cond)>,
1096              ISA_MIPS32R6;
1097def : MipsPat<(select i32:$cond, immz, i32:$f),
1098              (SELEQZ i32:$f, i32:$cond)>,
1099              ISA_MIPS32R6;
1100}
1101
1102// Pseudo instructions
1103let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
1104    hasExtraSrcRegAllocReq = 1, isCTI = 1, Defs = [AT], hasPostISelHook = 1 in {
1105  class TailCallRegR6<Instruction JumpInst, Register RT, RegisterOperand RO> :
1106    PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>,
1107    PseudoInstExpansion<(JumpInst RT:$rt, RO:$rs)>;
1108}
1109
1110class PseudoIndirectBranchBaseR6<Instruction JumpInst, Register RT,
1111                                 RegisterOperand RO> :
1112    MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)],
1113               II_IndirectBranchPseudo>,
1114    PseudoInstExpansion<(JumpInst RT:$rt, RO:$rs)> {
1115  let isTerminator=1;
1116  let isBarrier=1;
1117  let hasDelaySlot = 1;
1118  let isBranch = 1;
1119  let isIndirectBranch = 1;
1120  bit isCTI = 1;
1121}
1122
1123
1124let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
1125                            NoIndirectJumpGuards] in {
1126  def TAILCALLR6REG : TailCallRegR6<JALR, ZERO, GPR32Opnd>, ISA_MIPS32R6;
1127  def PseudoIndirectBranchR6 : PseudoIndirectBranchBaseR6<JALR, ZERO,
1128                                                          GPR32Opnd>,
1129                               ISA_MIPS32R6;
1130}
1131
1132let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
1133                            UseIndirectJumpsHazard] in {
1134  def TAILCALLHBR6REG : TailCallReg<JR_HB_R6, GPR32Opnd>, ISA_MIPS32R6;
1135  def PseudoIndrectHazardBranchR6 : PseudoIndirectBranchBase<JR_HB_R6,
1136                                                             GPR32Opnd>,
1137                                    ISA_MIPS32R6;
1138}
1139
1140