xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/Mips32r6InstrInfo.td (revision 4d3fc8b0570b29fb0d6ee9525f104d52176ff0d4)
1//=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes Mips32r6 instructions.
10//
11//===----------------------------------------------------------------------===//
12
13include "Mips32r6InstrFormats.td"
14
15//===----------------------------------------------------------------------===//
16//
17// Mips profiles and nodes
18//
19//===----------------------------------------------------------------------===//
20
21def SDT_MipsFSelect : SDTypeProfile<1, 3, [SDTCisFP<1>,
22                                           SDTCisSameAs<0,2>,
23                                           SDTCisSameAs<2,3>]>;
24
25def MipsFSelect : SDNode<"MipsISD::FSELECT", SDT_MipsFSelect>;
26
27//===----------------------------------------------------------------------===//
28//
29// Mips Operands
30//
31//===----------------------------------------------------------------------===//
32
33// Notes about removals/changes from MIPS32r6:
34// Reencoded: jr -> jalr
35// Reencoded: jr.hb -> jalr.hb
36
37def brtarget21 : Operand<OtherVT> {
38  let EncoderMethod = "getBranchTarget21OpValue";
39  let OperandType = "OPERAND_PCREL";
40  let DecoderMethod = "DecodeBranchTarget21";
41  let ParserMatchClass = MipsJumpTargetAsmOperand;
42  let PrintMethod = "printBranchOperand";
43}
44
45def brtarget26 : Operand<OtherVT> {
46  let EncoderMethod = "getBranchTarget26OpValue";
47  let OperandType = "OPERAND_PCREL";
48  let DecoderMethod = "DecodeBranchTarget26";
49  let ParserMatchClass = MipsJumpTargetAsmOperand;
50  let PrintMethod = "printBranchOperand";
51}
52
53def jmpoffset16 : Operand<OtherVT> {
54  let EncoderMethod = "getJumpOffset16OpValue";
55  let ParserMatchClass = MipsJumpTargetAsmOperand;
56}
57
58def calloffset16 : Operand<iPTR> {
59  let EncoderMethod = "getJumpOffset16OpValue";
60  let ParserMatchClass = MipsJumpTargetAsmOperand;
61}
62
63//===----------------------------------------------------------------------===//
64//
65// Instruction Encodings
66//
67//===----------------------------------------------------------------------===//
68
69class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
70class ALIGN_ENC  : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
71class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
72class AUI_ENC    : AUI_FM;
73class AUIPC_ENC  : PCREL16_FM<OPCODE5_AUIPC>;
74
75class BAL_ENC   : BAL_FM;
76class BALC_ENC  : BRANCH_OFF26_FM<0b111010>;
77class BC_ENC    : BRANCH_OFF26_FM<0b110010>;
78class BEQC_ENC  : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
79                  DecodeDisambiguates<"AddiGroupBranch">;
80class BEQZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_ADDI>,
81                    DecodeDisambiguatedBy<"DaddiGroupBranch">;
82class BNEC_ENC  : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
83                  DecodeDisambiguates<"DaddiGroupBranch">;
84class BNEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_DADDI>,
85                    DecodeDisambiguatedBy<"DaddiGroupBranch">;
86
87class BLTZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZL>,
88                  DecodeDisambiguates<"BgtzlGroupBranch">;
89class BGEC_ENC  : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZL>,
90                  DecodeDisambiguatedBy<"BlezlGroupBranch">;
91class BGEUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZ>,
92                  DecodeDisambiguatedBy<"BlezGroupBranch">;
93class BGEZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZL>,
94                  DecodeDisambiguates<"BlezlGroupBranch">;
95class BGTZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZ>,
96                    DecodeDisambiguatedBy<"BgtzGroupBranch">;
97
98class BLTC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BGTZL>,
99                 DecodeDisambiguatedBy<"BgtzlGroupBranch">;
100class BLTUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BGTZ>,
101                  DecodeDisambiguatedBy<"BgtzGroupBranch">;
102
103class BLEZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZL>,
104                  DecodeDisambiguatedBy<"BlezlGroupBranch">;
105class BLTZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZ>,
106                    DecodeDisambiguates<"BgtzGroupBranch">;
107class BGTZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZL>,
108                  DecodeDisambiguatedBy<"BgtzlGroupBranch">;
109
110class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>;
111class BGEZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZ>,
112                    DecodeDisambiguates<"BlezGroupBranch">;
113class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;
114
115class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>;
116class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>;
117class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>;
118class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>;
119
120class DVP_ENC : COP0_EVP_DVP_FM<0b1>;
121class EVP_ENC : COP0_EVP_DVP_FM<0b0>;
122
123class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>;
124class JIC_ENC   : JMP_IDX_COMPACT_FM<0b110110>;
125class JR_HB_R6_ENC : JR_HB_R6_FM<OPCODE6_JALR>;
126class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
127class BLEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZ>,
128                    DecodeDisambiguatedBy<"BlezGroupBranch">;
129class BNVC_ENC   : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
130                   DecodeDisambiguatedBy<"DaddiGroupBranch">;
131class BOVC_ENC   : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
132                   DecodeDisambiguatedBy<"AddiGroupBranch">;
133class DIV_ENC    : SPECIAL_3R_FM<0b00010, 0b011010>;
134class DIVU_ENC   : SPECIAL_3R_FM<0b00010, 0b011011>;
135class MOD_ENC    : SPECIAL_3R_FM<0b00011, 0b011010>;
136class MODU_ENC   : SPECIAL_3R_FM<0b00011, 0b011011>;
137class MUH_ENC    : SPECIAL_3R_FM<0b00011, 0b011000>;
138class MUHU_ENC   : SPECIAL_3R_FM<0b00011, 0b011001>;
139class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
140class MULU_ENC   : SPECIAL_3R_FM<0b00010, 0b011001>;
141
142class MADDF_S_ENC  : COP1_3R_FM<0b011000, FIELD_FMT_S>;
143class MADDF_D_ENC  : COP1_3R_FM<0b011000, FIELD_FMT_D>;
144class MSUBF_S_ENC  : COP1_3R_FM<0b011001, FIELD_FMT_S>;
145class MSUBF_D_ENC  : COP1_3R_FM<0b011001, FIELD_FMT_D>;
146
147class SEL_D_ENC  : COP1_3R_FM<0b010000, FIELD_FMT_D>;
148class SEL_S_ENC  : COP1_3R_FM<0b010000, FIELD_FMT_S>;
149
150class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>;
151class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>;
152
153class LWPC_ENC   : PCREL19_FM<OPCODE2_LWPC>;
154
155class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
156class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
157class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
158class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
159
160class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
161class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
162class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
163class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
164
165class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
166class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
167class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
168class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
169
170class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
171class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
172class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
173class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
174
175class CACHE_ENC : SPECIAL3_MEM_FM<OPCODE6_CACHE>;
176class PREF_ENC : SPECIAL3_MEM_FM<OPCODE6_PREF>;
177
178class LDC2_R6_ENC : COP2LDST_FM<OPCODE5_LDC2>;
179class LWC2_R6_ENC : COP2LDST_FM<OPCODE5_LWC2>;
180class SDC2_R6_ENC : COP2LDST_FM<OPCODE5_SDC2>;
181class SWC2_R6_ENC : COP2LDST_FM<OPCODE5_SWC2>;
182
183class LSA_R6_ENC : SPECIAL_LSA_FM<OPCODE6_LSA>;
184
185class LL_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LL>;
186class SC_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SC>;
187
188class CLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLO>;
189class CLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLZ>;
190
191class SDBBP_R6_ENC : SPECIAL_SDBBP_FM;
192
193class CRC32B_ENC  : SPECIAL3_2R_SZ_CRC<0,0>;
194class CRC32H_ENC  : SPECIAL3_2R_SZ_CRC<1,0>;
195class CRC32W_ENC  : SPECIAL3_2R_SZ_CRC<2,0>;
196class CRC32CB_ENC : SPECIAL3_2R_SZ_CRC<0,1>;
197class CRC32CH_ENC : SPECIAL3_2R_SZ_CRC<1,1>;
198class CRC32CW_ENC : SPECIAL3_2R_SZ_CRC<2,1>;
199
200class GINVI_ENC : SPECIAL3_GINV<0>;
201class GINVT_ENC : SPECIAL3_GINV<2>;
202
203class SIGRIE_ENC : SIGRIE_FM;
204
205//===----------------------------------------------------------------------===//
206//
207// Instruction Multiclasses
208//
209//===----------------------------------------------------------------------===//
210
211class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,
212                          RegisterOperand FGROpnd,
213                          InstrItinClass Itin,
214                          SDPatternOperator Op = null_frag> {
215  dag OutOperandList = (outs FGRCCOpnd:$fd);
216  dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
217  string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
218  list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))];
219  bit isCTI = 1;
220  InstrItinClass Itinerary = Itin;
221}
222
223multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
224                     RegisterOperand FGROpnd, InstrItinClass Itin>{
225  let AdditionalPredicates = [NotInMicroMips] in {
226    def CMP_F_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_AF>,
227                      CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd, Itin>,
228                      MipsR6Arch<!strconcat("cmp.af.", Typestr)>,
229                      ISA_MIPS32R6, HARDFLOAT;
230    def CMP_UN_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
231                       CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, Itin, setuo>,
232                       MipsR6Arch<!strconcat("cmp.un.", Typestr)>,
233                       ISA_MIPS32R6, HARDFLOAT;
234    def CMP_EQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
235                       CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, Itin,
236                                           setoeq>,
237                       MipsR6Arch<!strconcat("cmp.eq.", Typestr)>,
238                       ISA_MIPS32R6, HARDFLOAT;
239    def CMP_UEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
240                                                     FIELD_CMP_COND_UEQ>,
241                        CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, Itin,
242                                            setueq>,
243                        MipsR6Arch<!strconcat("cmp.ueq.", Typestr)>,
244                        ISA_MIPS32R6, HARDFLOAT;
245    def CMP_LT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
246                       CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, Itin,
247                                           setolt>,
248                       MipsR6Arch<!strconcat("cmp.lt.", Typestr)>,
249                       ISA_MIPS32R6, HARDFLOAT;
250    def CMP_ULT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
251                                                     FIELD_CMP_COND_ULT>,
252                        CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, Itin,
253                                            setult>,
254                        MipsR6Arch<!strconcat("cmp.ult.", Typestr)>,
255                        ISA_MIPS32R6, HARDFLOAT;
256    def CMP_LE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
257                       CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, Itin,
258                                           setole>,
259                       MipsR6Arch<!strconcat("cmp.le.", Typestr)>,
260                       ISA_MIPS32R6, HARDFLOAT;
261    def CMP_ULE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
262                                                     FIELD_CMP_COND_ULE>,
263                        CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, Itin,
264                                            setule>,
265                        MipsR6Arch<!strconcat("cmp.ule.", Typestr)>,
266                        ISA_MIPS32R6, HARDFLOAT;
267    def CMP_SAF_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
268                                                     FIELD_CMP_COND_SAF>,
269                        CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd, Itin>,
270                        MipsR6Arch<!strconcat("cmp.saf.", Typestr)>,
271                        ISA_MIPS32R6, HARDFLOAT;
272    def CMP_SUN_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
273                                                     FIELD_CMP_COND_SUN>,
274                        CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd, Itin>,
275                        MipsR6Arch<!strconcat("cmp.sun.", Typestr)>,
276                        ISA_MIPS32R6, HARDFLOAT;
277    def CMP_SEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
278                                                     FIELD_CMP_COND_SEQ>,
279                        CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd, Itin>,
280                        MipsR6Arch<!strconcat("cmp.seq.", Typestr)>,
281                        ISA_MIPS32R6, HARDFLOAT;
282    def CMP_SUEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
283                                                      FIELD_CMP_COND_SUEQ>,
284                         CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd, Itin>,
285                         MipsR6Arch<!strconcat("cmp.sueq.", Typestr)>,
286                         ISA_MIPS32R6, HARDFLOAT;
287    def CMP_SLT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
288                                                     FIELD_CMP_COND_SLT>,
289                        CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd, Itin>,
290                        MipsR6Arch<!strconcat("cmp.slt.", Typestr)>,
291                        ISA_MIPS32R6, HARDFLOAT;
292    def CMP_SULT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
293                                                      FIELD_CMP_COND_SULT>,
294                         CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd, Itin>,
295                         MipsR6Arch<!strconcat("cmp.sult.", Typestr)>,
296                         ISA_MIPS32R6, HARDFLOAT;
297    def CMP_SLE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
298                                                     FIELD_CMP_COND_SLE>,
299                        CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd, Itin>,
300                        MipsR6Arch<!strconcat("cmp.sle.", Typestr)>,
301                        ISA_MIPS32R6, HARDFLOAT;
302    def CMP_SULE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
303                                                      FIELD_CMP_COND_SULE>,
304                         CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd, Itin>,
305                         MipsR6Arch<!strconcat("cmp.sule.", Typestr)>,
306                         ISA_MIPS32R6, HARDFLOAT;
307  }
308}
309
310//===----------------------------------------------------------------------===//
311//
312// Instruction Descriptions
313//
314//===----------------------------------------------------------------------===//
315
316class PCREL_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
317                      Operand ImmOpnd, InstrItinClass itin>
318      : MipsR6Arch<instr_asm> {
319  dag OutOperandList = (outs GPROpnd:$rs);
320  dag InOperandList = (ins ImmOpnd:$imm);
321  string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
322  list<dag> Pattern = [];
323  InstrItinClass Itinerary = itin;
324}
325
326class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2,
327                                     II_ADDIUPC>;
328class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2, II_LWPC>;
329
330class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
331                      Operand ImmOpnd, InstrItinClass itin>
332      : MipsR6Arch<instr_asm> {
333  dag OutOperandList = (outs GPROpnd:$rd);
334  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
335  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
336  list<dag> Pattern = [];
337  InstrItinClass Itinerary = itin;
338}
339
340class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2, II_ALIGN>;
341
342class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
343                       InstrItinClass itin = NoItinerary>
344      : MipsR6Arch<instr_asm> {
345  dag OutOperandList = (outs GPROpnd:$rs);
346  dag InOperandList = (ins simm16:$imm);
347  string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
348  list<dag> Pattern = [];
349  InstrItinClass Itinerary = itin;
350}
351
352class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd, II_ALUIPC>;
353class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd, II_AUIPC>;
354
355class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
356                    InstrItinClass itin = NoItinerary>
357      : MipsR6Arch<instr_asm> {
358  dag OutOperandList = (outs GPROpnd:$rt);
359  dag InOperandList = (ins GPROpnd:$rs, uimm16:$imm);
360  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
361  list<dag> Pattern = [];
362  InstrItinClass Itinerary = itin;
363}
364
365class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd, II_AUI>;
366
367class BRANCH_DESC_BASE {
368  bit isBranch = 1;
369  bit isTerminator = 1;
370  bit hasDelaySlot = 0;
371  bit isCTI = 1;
372}
373
374class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE,
375    MipsR6Arch<instr_asm> {
376  dag InOperandList = (ins opnd:$offset);
377  dag OutOperandList = (outs);
378  string AsmString = !strconcat(instr_asm, "\t$offset");
379  bit isBarrier = 1;
380  InstrItinClass Itinerary = II_BC;
381  bit isCTI = 1;
382}
383
384class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
385                       RegisterOperand GPROpnd> : BRANCH_DESC_BASE,
386                                                  MipsR6Arch<instr_asm> {
387  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
388  dag OutOperandList = (outs);
389  string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
390  list<Register> Defs = [AT];
391  InstrItinClass Itinerary = II_BCCC;
392  bit hasForbiddenSlot = 1;
393  bit isCTI = 1;
394}
395
396class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
397                               RegisterOperand GPROpnd>
398    : BRANCH_DESC_BASE, MipsR6Arch<instr_asm> {
399  dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);
400  dag OutOperandList = (outs);
401  string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
402  list<Register> Defs = [AT];
403  InstrItinClass Itinerary = II_BCCZC;
404  bit hasForbiddenSlot = 1;
405  bit isCTI = 1;
406}
407
408class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
409                             RegisterOperand GPROpnd>
410    : BRANCH_DESC_BASE, MipsR6Arch<instr_asm> {
411  dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
412  dag OutOperandList = (outs);
413  string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
414  list<Register> Defs = [AT];
415  InstrItinClass Itinerary = II_BCCZC;
416  bit hasForbiddenSlot = 1;
417  bit isCTI = 1;
418}
419
420class BAL_DESC : BC_DESC_BASE<"bal", brtarget> {
421  bit isCall = 1;
422  bit hasDelaySlot = 1;
423  list<Register> Defs = [RA];
424  bit isCTI = 1;
425}
426
427class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
428  bit isCall = 1;
429  list<Register> Defs = [RA];
430  InstrItinClass Itinerary = II_BALC;
431  bit isCTI = 1;
432}
433
434class BC_DESC : BC_DESC_BASE<"bc", brtarget26>;
435class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>;
436class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
437class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
438class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
439
440class BLTC_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR32Opnd>;
441class BLTUC_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR32Opnd>;
442
443class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
444class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
445
446class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
447class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
448
449class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
450class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
451
452class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
453  dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset);
454  dag OutOperandList = (outs);
455  string AsmString = instr_asm;
456  bit hasDelaySlot = 1;
457  InstrItinClass Itinerary = II_BC1CCZ;
458}
459
460class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">;
461class BC1NEZ_DESC : COP1_BCCZ_DESC_BASE<"bc1nez $ft, $offset">;
462
463class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
464  dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset);
465  dag OutOperandList = (outs);
466  string AsmString = instr_asm;
467  bit hasDelaySlot = 1;
468  bit isCTI = 1;
469  InstrItinClass Itinerary = II_BC2CCZ;
470}
471
472class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">;
473class BC2NEZ_DESC : COP2_BCCZ_DESC_BASE<"bc2nez $ct, $offset">;
474
475class BOVC_DESC   : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>;
476class BNVC_DESC   : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>;
477
478class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
479                                RegisterOperand GPROpnd,
480                                InstrItinClass itin = NoItinerary>
481    : MipsR6Arch<opstr> {
482  dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
483  string AsmString = !strconcat(opstr, "\t$rt, $offset");
484  list<dag> Pattern = [];
485  bit hasDelaySlot = 0;
486  InstrItinClass Itinerary = itin;
487  bit isCTI = 1;
488  bit isBranch = 1;
489  bit isIndirectBranch = 1;
490}
491
492class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
493                                             GPR32Opnd, II_JIALC> {
494  bit isCall = 1;
495  list<Register> Defs = [RA];
496}
497
498class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
499                                           GPR32Opnd, II_JIALC> {
500  bit isBarrier = 1;
501  bit isTerminator = 1;
502  list<Register> Defs = [AT];
503}
504
505class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
506  bit isBranch = 1;
507  bit isIndirectBranch = 1;
508  bit hasDelaySlot = 1;
509  bit isTerminator=1;
510  bit isBarrier=1;
511  bit isCTI = 1;
512  InstrItinClass Itinerary = II_JR_HB;
513}
514
515class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
516                        InstrItinClass itin>
517    : MipsR6Arch<instr_asm> {
518  dag OutOperandList = (outs GPROpnd:$rd);
519  dag InOperandList = (ins GPROpnd:$rt);
520  string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
521  list<dag> Pattern = [];
522  InstrItinClass Itinerary = itin;
523}
524
525class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd, II_BITSWAP>;
526
527class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
528                       InstrItinClass itin,
529                       SDPatternOperator Op=null_frag>
530    : MipsR6Arch<instr_asm> {
531  dag OutOperandList = (outs GPROpnd:$rd);
532  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
533  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
534  list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
535  InstrItinClass Itinerary = itin;
536  // This instruction doesn't trap division by zero itself. We must insert
537  // teq instructions as well.
538  bit usesCustomInserter = 1;
539}
540
541class DVPEVP_DESC_BASE<string instr_asm, InstrItinClass Itin>
542    : MipsR6Arch<instr_asm> {
543  dag OutOperandList = (outs GPR32Opnd:$rt);
544  dag InOperandList = (ins);
545  string AsmString = !strconcat(instr_asm, "\t$rt");
546  list<dag> Pattern = [];
547  InstrItinClass Itinerary = Itin;
548  bit hasUnModeledSideEffects = 1;
549}
550
551class DVP_DESC : DVPEVP_DESC_BASE<"dvp", II_DVP>;
552class EVP_DESC : DVPEVP_DESC_BASE<"evp", II_EVP>;
553
554class DIV_DESC  : DIVMOD_DESC_BASE<"div", GPR32Opnd, II_DIV, sdiv>;
555class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, II_DIVU, udiv>;
556class MOD_DESC  : DIVMOD_DESC_BASE<"mod", GPR32Opnd, II_MOD, srem>;
557class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, II_MODU, urem>;
558
559class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
560  list<Register> Defs = [RA];
561}
562
563class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> {
564  list<Register> Defs = [RA];
565}
566
567class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> {
568  list<Register> Defs = [RA];
569}
570
571class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> {
572  list<Register> Defs = [RA];
573}
574
575class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> {
576  list<Register> Defs = [RA];
577}
578
579class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> {
580  list<Register> Defs = [RA];
581}
582
583class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
584                       InstrItinClass itin,
585                       SDPatternOperator Op=null_frag> : MipsR6Arch<instr_asm> {
586  dag OutOperandList = (outs GPROpnd:$rd);
587  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
588  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
589  list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
590  InstrItinClass Itinerary = itin;
591}
592
593class MUH_DESC    : MUL_R6_DESC_BASE<"muh", GPR32Opnd, II_MUH, mulhs>;
594class MUHU_DESC   : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, II_MUHU, mulhu>;
595class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, II_MUL, mul>;
596class MULU_DESC   : MUL_R6_DESC_BASE<"mulu", GPR32Opnd, II_MULU>;
597
598class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
599                         InstrItinClass itin> {
600  dag OutOperandList = (outs FGROpnd:$fd);
601  dag InOperandList = (ins FGRCCOpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
602  string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
603  list<dag> Pattern = [(set FGROpnd:$fd, (select FGRCCOpnd:$fd_in,
604                                                 FGROpnd:$ft,
605                                                 FGROpnd:$fs))];
606  string Constraints = "$fd_in = $fd";
607  InstrItinClass Itinerary = itin;
608}
609
610class COP1_SEL_D_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
611                           InstrItinClass itin> {
612  dag OutOperandList = (outs FGROpnd:$fd);
613  dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
614  string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
615  list<dag> Pattern = [(set FGROpnd:$fd, (MipsFSelect FGROpnd:$fd_in,
616                                                      FGROpnd:$ft,
617                                                      FGROpnd:$fs))];
618  string Constraints = "$fd_in = $fd";
619  InstrItinClass Itinerary = itin;
620}
621
622class SEL_D_DESC : COP1_SEL_D_DESC_BASE<"sel.d", FGR64Opnd, II_SEL_D>,
623                   MipsR6Arch<"sel.d">;
624class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd, II_SEL_S>,
625                   MipsR6Arch<"sel.s">;
626
627class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
628    : MipsR6Arch<instr_asm> {
629  dag OutOperandList = (outs GPROpnd:$rd);
630  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
631  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
632  list<dag> Pattern = [];
633  InstrItinClass Itinerary = II_SELCCZ;
634}
635
636class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>;
637class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>;
638
639class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
640                        InstrItinClass itin = NoItinerary> {
641  dag OutOperandList = (outs FGROpnd:$fd);
642  dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
643  string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
644  list<dag> Pattern = [];
645  string Constraints = "$fd_in = $fd";
646  InstrItinClass Itinerary = itin;
647}
648
649class MADDF_S_DESC  : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd, II_MADDF_S>;
650class MADDF_D_DESC  : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd, II_MADDF_D>;
651class MSUBF_S_DESC  : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd, II_MSUBF_S>;
652class MSUBF_D_DESC  : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd, II_MSUBF_D>;
653
654class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
655                        InstrItinClass itin> {
656  dag OutOperandList = (outs FGROpnd:$fd);
657  dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
658  string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
659  list<dag> Pattern = [];
660  InstrItinClass Itinerary = itin;
661}
662
663class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd, II_MAX_S>;
664class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd, II_MAX_D>;
665class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd, II_MIN_S>;
666class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd, II_MIN_D>;
667
668class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd, II_MAX_S>;
669class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd, II_MAX_D>;
670class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd, II_MIN_D>;
671class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd, II_MIN_S>;
672
673class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
674                         InstrItinClass itin> {
675  dag OutOperandList = (outs FGROpnd:$fd);
676  dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
677  string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
678  list<dag> Pattern = [];
679  InstrItinClass Itinerary = itin;
680}
681
682class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd, II_SELCCZ_S>,
683                      MipsR6Arch<"seleqz.s">;
684class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd, II_SELCCZ_D>,
685                      MipsR6Arch<"seleqz.d">;
686class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd, II_SELCCZ_S>,
687                      MipsR6Arch<"selnez.s">;
688class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd, II_SELCCZ_D>,
689                      MipsR6Arch<"selnez.d">;
690
691class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
692                           InstrItinClass itin> {
693  dag OutOperandList = (outs FGROpnd:$fd);
694  dag InOperandList = (ins FGROpnd:$fs);
695  string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
696  list<dag> Pattern = [];
697  InstrItinClass Itinerary = itin;
698}
699
700class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd, II_RINT_S>;
701class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd, II_RINT_D>;
702class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd, II_CLASS_S>;
703class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd, II_CLASS_D>;
704
705class CACHE_HINT_DESC<string instr_asm, Operand MemOpnd, InstrItinClass itin>
706                     : MipsR6Arch<instr_asm> {
707  dag OutOperandList = (outs);
708  dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
709  string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
710  list<dag> Pattern = [];
711  string DecoderMethod = "DecodeCacheeOp_CacheOpR6";
712  InstrItinClass Itinerary = itin;
713}
714
715class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, II_CACHE>;
716class PREF_DESC : CACHE_HINT_DESC<"pref", mem_simm9, II_PREF>;
717
718class COP2LD_DESC_BASE<string instr_asm, RegisterOperand COPOpnd,
719                       InstrItinClass itin> {
720  dag OutOperandList = (outs COPOpnd:$rt);
721  dag InOperandList = (ins mem_simm11:$addr);
722  string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
723  list<dag> Pattern = [];
724  bit mayLoad = 1;
725  string DecoderMethod = "DecodeFMemCop2R6";
726  InstrItinClass Itinerary = itin;
727}
728
729class LDC2_R6_DESC : COP2LD_DESC_BASE<"ldc2", COP2Opnd, II_LDC2>;
730class LWC2_R6_DESC : COP2LD_DESC_BASE<"lwc2", COP2Opnd, II_LWC2>;
731
732class COP2ST_DESC_BASE<string instr_asm, RegisterOperand COPOpnd,
733                       InstrItinClass itin> {
734  dag OutOperandList = (outs);
735  dag InOperandList = (ins COPOpnd:$rt, mem_simm11:$addr);
736  string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
737  list<dag> Pattern = [];
738  bit mayStore = 1;
739  string DecoderMethod = "DecodeFMemCop2R6";
740  InstrItinClass Itinerary = itin;
741}
742
743class SDC2_R6_DESC : COP2ST_DESC_BASE<"sdc2", COP2Opnd, II_SDC2>;
744class SWC2_R6_DESC : COP2ST_DESC_BASE<"swc2", COP2Opnd, II_SWC2>;
745
746class LSA_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
747                       Operand ImmOpnd, InstrItinClass itin>
748      : MipsR6Arch<instr_asm> {
749  dag OutOperandList = (outs GPROpnd:$rd);
750  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
751  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $imm2");
752  list<dag> Pattern = [];
753  InstrItinClass Itinerary = itin;
754}
755
756class LSA_R6_DESC : LSA_R6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1, II_LSA>;
757
758class LL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
759                      Operand MemOpnd, InstrItinClass itin>
760      : MipsR6Arch<instr_asm> {
761  dag OutOperandList = (outs GPROpnd:$rt);
762  dag InOperandList = (ins MemOpnd:$addr);
763  string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
764  list<dag> Pattern = [];
765  bit mayLoad = 1;
766  InstrItinClass Itinerary = itin;
767}
768
769class LL_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, mem_simm9_exp, II_LL>;
770
771class SC_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
772                      InstrItinClass itin> {
773  dag OutOperandList = (outs GPROpnd:$dst);
774  dag InOperandList = (ins GPROpnd:$rt, mem_simm9_exp:$addr);
775  string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
776  list<dag> Pattern = [];
777  bit mayStore = 1;
778  string Constraints = "$rt = $dst";
779  InstrItinClass Itinerary = itin;
780}
781
782class SC_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd, II_SC>;
783
784class CLO_CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
785                           InstrItinClass itin>
786    : MipsR6Arch<instr_asm> {
787  dag OutOperandList = (outs GPROpnd:$rd);
788  dag InOperandList = (ins GPROpnd:$rs);
789  string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
790  InstrItinClass Itinerary = itin;
791}
792
793class CLO_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
794                       InstrItinClass itin> :
795    CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd, itin> {
796  list<dag> Pattern = [(set GPROpnd:$rd, (ctlz (not GPROpnd:$rs)))];
797}
798
799class CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
800                       InstrItinClass itin> :
801    CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd, itin> {
802  list<dag> Pattern = [(set GPROpnd:$rd, (ctlz GPROpnd:$rs))];
803}
804
805class CLO_R6_DESC : CLO_R6_DESC_BASE<"clo", GPR32Opnd, II_CLO>;
806class CLZ_R6_DESC : CLZ_R6_DESC_BASE<"clz", GPR32Opnd, II_CLZ>;
807
808class SDBBP_R6_DESC {
809  dag OutOperandList = (outs);
810  dag InOperandList = (ins uimm20:$code_);
811  string AsmString = "sdbbp\t$code_";
812  list<dag> Pattern = [];
813  bit isCTI = 1;
814  InstrItinClass Itinerary = II_SDBBP;
815}
816
817class CRC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
818                    InstrItinClass itin> : MipsR6Arch<instr_asm> {
819  dag OutOperandList = (outs GPROpnd:$rd);
820  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
821  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
822  list<dag> Pattern = [];
823  InstrItinClass Itinerary = itin;
824}
825
826class CRC32B_DESC : CRC_DESC_BASE<"crc32b", GPR32Opnd, II_CRC32B>;
827class CRC32H_DESC : CRC_DESC_BASE<"crc32h", GPR32Opnd, II_CRC32H>;
828class CRC32W_DESC : CRC_DESC_BASE<"crc32w", GPR32Opnd, II_CRC32W>;
829class CRC32CB_DESC : CRC_DESC_BASE<"crc32cb", GPR32Opnd, II_CRC32CB>;
830class CRC32CH_DESC : CRC_DESC_BASE<"crc32ch", GPR32Opnd, II_CRC32CH>;
831class CRC32CW_DESC : CRC_DESC_BASE<"crc32cw", GPR32Opnd, II_CRC32CW>;
832
833class GINV_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
834                     InstrItinClass itin> : MipsR6Arch<instr_asm> {
835  dag OutOperandList = (outs);
836  dag InOperandList = (ins GPROpnd:$rs, uimm2:$type_);
837  string AsmString = !strconcat(instr_asm, "\t$rs, $type_");
838  list<dag> Pattern = [];
839  InstrItinClass Itinerary = itin;
840  bit hasSideEffects = 1;
841}
842
843class GINVI_DESC : GINV_DESC_BASE<"ginvi", GPR32Opnd, II_GINVI> {
844  dag InOperandList = (ins GPR32Opnd:$rs);
845  string AsmString = "ginvi\t$rs";
846}
847class GINVT_DESC : GINV_DESC_BASE<"ginvt", GPR32Opnd, II_GINVT>;
848
849class SIGRIE_DESC {
850  dag OutOperandList = (outs);
851  dag InOperandList = (ins uimm16:$code_);
852  string AsmString = "sigrie\t$code_";
853  list<dag> Pattern = [];
854  InstrItinClass Itinerary = II_SIGRIE;
855}
856
857//===----------------------------------------------------------------------===//
858//
859// Instruction Definitions
860//
861//===----------------------------------------------------------------------===//
862
863def ADDIUPC : R6MMR6Rel, ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
864def ALIGN : R6MMR6Rel, ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
865def ALUIPC : R6MMR6Rel, ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
866def AUI : R6MMR6Rel, AUI_ENC, AUI_DESC, ISA_MIPS32R6;
867def AUIPC : R6MMR6Rel, AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
868def BAL : BAL_ENC, BAL_DESC, ISA_MIPS32R6;
869def BALC : R6MMR6Rel, BALC_ENC, BALC_DESC, ISA_MIPS32R6;
870let AdditionalPredicates = [NotInMicroMips] in {
871  def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6, HARDFLOAT;
872  def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6, HARDFLOAT;
873  def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6;
874  def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;
875  def BC : R6MMR6Rel, BC_ENC, BC_DESC, ISA_MIPS32R6;
876  def BEQC : R6MMR6Rel, BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
877  def BEQZALC : R6MMR6Rel, BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
878  def BEQZC : R6MMR6Rel, BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
879  def BGEC : R6MMR6Rel, BGEC_ENC, BGEC_DESC, ISA_MIPS32R6;
880  def BGEUC : R6MMR6Rel, BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6;
881  def BGEZALC : R6MMR6Rel, BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
882  def BGEZC : R6MMR6Rel, BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
883  def BGTZALC : R6MMR6Rel, BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6;
884  def BGTZC : R6MMR6Rel, BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
885}
886def BITSWAP : R6MMR6Rel, BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
887let AdditionalPredicates = [NotInMicroMips] in {
888  def BLEZALC : R6MMR6Rel, BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;
889  def BLEZC : R6MMR6Rel, BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
890  def BLTC : R6MMR6Rel, BLTC_ENC, BLTC_DESC, ISA_MIPS32R6;
891  def BLTUC : R6MMR6Rel, BLTUC_ENC, BLTUC_DESC, ISA_MIPS32R6;
892  def BLTZALC : R6MMR6Rel, BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
893  def BLTZC : R6MMR6Rel, BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
894  def BNEC : R6MMR6Rel, BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
895  def BNEZALC : R6MMR6Rel, BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
896  def BNEZC : R6MMR6Rel, BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
897  def BNVC : R6MMR6Rel, BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
898  def BOVC : R6MMR6Rel, BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
899  def CACHE_R6 : R6MMR6Rel, CACHE_ENC, CACHE_DESC, ISA_MIPS32R6;
900  def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6, HARDFLOAT;
901  def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6, HARDFLOAT;
902}
903def CLO_R6 : R6MMR6Rel, CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6;
904def CLZ_R6 : R6MMR6Rel, CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6;
905defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd, II_CMP_CC_S>;
906defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd, II_CMP_CC_D>;
907let AdditionalPredicates = [NotInMicroMips] in {
908  def DIV : R6MMR6Rel, DIV_ENC, DIV_DESC, ISA_MIPS32R6;
909  def DIVU : R6MMR6Rel, DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
910}
911
912def DVP : R6MMR6Rel, DVP_ENC, DVP_DESC, ISA_MIPS32R6;
913def EVP : R6MMR6Rel, EVP_ENC, EVP_DESC, ISA_MIPS32R6;
914
915def JIALC : R6MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
916def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6;
917def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
918let AdditionalPredicates = [NotInMicroMips] in {
919  def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6;
920  def LL_R6 : LL_R6_ENC, LL_R6_DESC, PTR_32, ISA_MIPS32R6;
921}
922def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6;
923let AdditionalPredicates = [NotInMicroMips] in {
924  def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6;
925}
926def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
927let AdditionalPredicates = [NotInMicroMips] in {
928  def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
929  def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
930  def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
931  def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
932  def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6, HARDFLOAT;
933  def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6, HARDFLOAT;
934  def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
935  def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
936  def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6, HARDFLOAT;
937  def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6, HARDFLOAT;
938
939  def MOD : R6MMR6Rel, MOD_ENC, MOD_DESC, ISA_MIPS32R6;
940  def MODU : R6MMR6Rel, MODU_ENC, MODU_DESC, ISA_MIPS32R6;
941
942  def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
943  def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
944
945  def MUH    : R6MMR6Rel, MUH_ENC, MUH_DESC, ISA_MIPS32R6;
946  def MUHU   : R6MMR6Rel, MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
947  def MUL_R6 : R6MMR6Rel, MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
948  def MULU   : R6MMR6Rel, MULU_ENC, MULU_DESC, ISA_MIPS32R6;
949}
950def NAL; // BAL with rd=0
951let AdditionalPredicates = [NotInMicroMips] in {
952  def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6;
953  def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT;
954  def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT;
955  def SC_R6 : SC_R6_ENC, SC_R6_DESC, PTR_32, ISA_MIPS32R6;
956  def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6;
957  def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
958  def SELNEZ : R6MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
959  def SELEQZ_D : R6MMR6Rel, SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6,
960                 HARDFLOAT;
961  def SELEQZ_S : R6MMR6Rel, SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6,
962                 HARDFLOAT;
963  def SELNEZ_D : R6MMR6Rel, SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6,
964                 HARDFLOAT;
965  def SELNEZ_S : R6MMR6Rel, SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6,
966                 HARDFLOAT;
967  def SEL_D : R6MMR6Rel, SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6, HARDFLOAT;
968  def SEL_S : R6MMR6Rel, SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT;
969  def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
970  def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
971  def SIGRIE : SIGRIE_ENC, SIGRIE_DESC, ISA_MIPS32R6;
972}
973
974let AdditionalPredicates = [NotInMicroMips] in {
975  def CRC32B : R6MMR6Rel, CRC32B_ENC, CRC32B_DESC, ISA_MIPS32R6, ASE_CRC;
976  def CRC32H : R6MMR6Rel, CRC32H_ENC, CRC32H_DESC, ISA_MIPS32R6, ASE_CRC;
977  def CRC32W : R6MMR6Rel, CRC32W_ENC, CRC32W_DESC, ISA_MIPS32R6, ASE_CRC;
978  def CRC32CB : R6MMR6Rel, CRC32CB_ENC, CRC32CB_DESC, ISA_MIPS32R6, ASE_CRC;
979  def CRC32CH : R6MMR6Rel, CRC32CH_ENC, CRC32CH_DESC, ISA_MIPS32R6, ASE_CRC;
980  def CRC32CW : R6MMR6Rel, CRC32CW_ENC, CRC32CW_DESC, ISA_MIPS32R6, ASE_CRC;
981}
982
983let AdditionalPredicates = [NotInMicroMips] in {
984  def GINVI : R6MMR6Rel, GINVI_ENC, GINVI_DESC, ISA_MIPS32R6, ASE_GINV;
985  def GINVT : R6MMR6Rel, GINVT_ENC, GINVT_DESC, ISA_MIPS32R6, ASE_GINV;
986}
987
988//===----------------------------------------------------------------------===//
989//
990// Instruction Aliases
991//
992//===----------------------------------------------------------------------===//
993
994def : MipsInstAlias<"dvp", (DVP ZERO), 0>, ISA_MIPS32R6;
995def : MipsInstAlias<"evp", (EVP ZERO), 0>, ISA_MIPS32R6;
996
997let AdditionalPredicates = [NotInMicroMips] in {
998def : MipsInstAlias<"sdbbp", (SDBBP_R6 0)>, ISA_MIPS32R6;
999def : MipsInstAlias<"sigrie", (SIGRIE 0)>, ISA_MIPS32R6;
1000def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>,
1001      ISA_MIPS32R6, GPR_32;
1002}
1003
1004def : MipsInstAlias<"jrc $rs", (JIC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
1005
1006let AdditionalPredicates = [NotInMicroMips] in {
1007def : MipsInstAlias<"jalrc $rs", (JIALC GPR32Opnd:$rs, 0), 1>,
1008      ISA_MIPS32R6, GPR_32;
1009}
1010
1011def : MipsInstAlias<"div $rs, $rt", (DIV GPR32Opnd:$rs, GPR32Opnd:$rs,
1012                                         GPR32Opnd:$rt)>, ISA_MIPS32R6;
1013def : MipsInstAlias<"divu $rs, $rt", (DIVU GPR32Opnd:$rs, GPR32Opnd:$rs,
1014                                           GPR32Opnd:$rt)>, ISA_MIPS32R6;
1015
1016def : MipsInstAlias<"lapc $rd, $imm",
1017                    (ADDIUPC GPR32Opnd:$rd, simm19_lsl2:$imm)>, ISA_MIPS32R6;
1018
1019//===----------------------------------------------------------------------===//
1020//
1021// Patterns and Pseudo Instructions
1022//
1023//===----------------------------------------------------------------------===//
1024
1025// comparisons supported via another comparison
1026multiclass Cmp_Pats<ValueType VT, Instruction NOROp, Register ZEROReg> {
1027def : MipsPat<(setone VT:$lhs, VT:$rhs),
1028      (NOROp (!cast<Instruction>("CMP_UEQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
1029def : MipsPat<(seto VT:$lhs, VT:$rhs),
1030      (NOROp (!cast<Instruction>("CMP_UN_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
1031def : MipsPat<(setune VT:$lhs, VT:$rhs),
1032      (NOROp (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
1033def : MipsPat<(seteq VT:$lhs, VT:$rhs),
1034      (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs)>;
1035def : MipsPat<(setgt VT:$lhs, VT:$rhs),
1036      (!cast<Instruction>("CMP_LE_"#NAME) VT:$rhs, VT:$lhs)>;
1037def : MipsPat<(setge VT:$lhs, VT:$rhs),
1038      (!cast<Instruction>("CMP_LT_"#NAME) VT:$rhs, VT:$lhs)>;
1039def : MipsPat<(setlt VT:$lhs, VT:$rhs),
1040      (!cast<Instruction>("CMP_LT_"#NAME) VT:$lhs, VT:$rhs)>;
1041def : MipsPat<(setle VT:$lhs, VT:$rhs),
1042      (!cast<Instruction>("CMP_LE_"#NAME) VT:$lhs, VT:$rhs)>;
1043def : MipsPat<(setne VT:$lhs, VT:$rhs),
1044      (NOROp (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
1045}
1046
1047let AdditionalPredicates = [NotInMicroMips] in {
1048  defm S : Cmp_Pats<f32, NOR, ZERO>, ISA_MIPS32R6;
1049  defm D : Cmp_Pats<f64, NOR, ZERO>, ISA_MIPS32R6;
1050}
1051
1052// i32 selects
1053multiclass SelectInt_Pats<ValueType RC, Instruction OROp, Instruction XORiOp,
1054                          Instruction SLTiOp, Instruction SLTiuOp,
1055                          Instruction SELEQZOp, Instruction SELNEZOp,
1056                          SDPatternOperator imm_type, ValueType Opg> {
1057// reg, immz
1058def : MipsPat<(select (Opg (seteq RC:$cond, immz)), RC:$t, RC:$f),
1059              (OROp (SELEQZOp RC:$t, RC:$cond), (SELNEZOp RC:$f, RC:$cond))>;
1060def : MipsPat<(select (Opg (setne RC:$cond, immz)), RC:$t, RC:$f),
1061              (OROp (SELNEZOp RC:$t, RC:$cond), (SELEQZOp RC:$f, RC:$cond))>;
1062
1063// reg, immZExt16[_64]
1064def : MipsPat<(select (Opg (seteq RC:$cond, imm_type:$imm)), RC:$t, RC:$f),
1065              (OROp (SELEQZOp RC:$t, (XORiOp RC:$cond, imm_type:$imm)),
1066                    (SELNEZOp RC:$f, (XORiOp RC:$cond, imm_type:$imm)))>;
1067def : MipsPat<(select (Opg (setne RC:$cond, imm_type:$imm)), RC:$t, RC:$f),
1068              (OROp (SELNEZOp RC:$t, (XORiOp RC:$cond, imm_type:$imm)),
1069                    (SELEQZOp RC:$f, (XORiOp RC:$cond, imm_type:$imm)))>;
1070
1071// reg, immSExt16Plus1
1072def : MipsPat<(select (Opg (setgt RC:$cond, immSExt16Plus1:$imm)), RC:$t, RC:$f),
1073              (OROp (SELEQZOp RC:$t, (SLTiOp RC:$cond, (Plus1 imm:$imm))),
1074                    (SELNEZOp RC:$f, (SLTiOp RC:$cond, (Plus1 imm:$imm))))>;
1075def : MipsPat<(select (Opg (setugt RC:$cond, immSExt16Plus1:$imm)), RC:$t, RC:$f),
1076              (OROp (SELEQZOp RC:$t, (SLTiuOp RC:$cond, (Plus1 imm:$imm))),
1077                    (SELNEZOp RC:$f, (SLTiuOp RC:$cond, (Plus1 imm:$imm))))>;
1078
1079def : MipsPat<(select (Opg (seteq RC:$cond, immz)), RC:$t, immz),
1080              (SELEQZOp RC:$t, RC:$cond)>;
1081def : MipsPat<(select (Opg (setne RC:$cond, immz)), RC:$t, immz),
1082              (SELNEZOp RC:$t, RC:$cond)>;
1083def : MipsPat<(select (Opg (seteq RC:$cond, immz)), immz, RC:$f),
1084              (SELNEZOp RC:$f, RC:$cond)>;
1085def : MipsPat<(select (Opg (setne RC:$cond, immz)), immz, RC:$f),
1086              (SELEQZOp RC:$f, RC:$cond)>;
1087}
1088
1089let AdditionalPredicates = [NotInMicroMips] in {
1090defm : SelectInt_Pats<i32, OR, XORi, SLTi, SLTiu, SELEQZ, SELNEZ,
1091                      immZExt16, i32>, ISA_MIPS32R6;
1092
1093def : MipsPat<(select i32:$cond, i32:$t, i32:$f),
1094              (OR (SELNEZ i32:$t, i32:$cond),
1095                  (SELEQZ i32:$f, i32:$cond))>,
1096              ISA_MIPS32R6;
1097def : MipsPat<(select i32:$cond, i32:$t, immz),
1098              (SELNEZ i32:$t, i32:$cond)>,
1099              ISA_MIPS32R6;
1100def : MipsPat<(select i32:$cond, immz, i32:$f),
1101              (SELEQZ i32:$f, i32:$cond)>,
1102              ISA_MIPS32R6;
1103}
1104
1105// Pseudo instructions
1106let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
1107    hasExtraSrcRegAllocReq = 1, isCTI = 1, Defs = [AT], hasPostISelHook = 1 in {
1108  class TailCallRegR6<Instruction JumpInst, Register RT, RegisterOperand RO> :
1109    PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>,
1110    PseudoInstExpansion<(JumpInst RT:$rt, RO:$rs)>;
1111}
1112
1113class PseudoIndirectBranchBaseR6<Instruction JumpInst, Register RT,
1114                                 RegisterOperand RO> :
1115    MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)],
1116               II_IndirectBranchPseudo>,
1117    PseudoInstExpansion<(JumpInst RT:$rt, RO:$rs)> {
1118  let isTerminator=1;
1119  let isBarrier=1;
1120  let hasDelaySlot = 1;
1121  let isBranch = 1;
1122  let isIndirectBranch = 1;
1123  bit isCTI = 1;
1124}
1125
1126
1127let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
1128                            NoIndirectJumpGuards] in {
1129  def TAILCALLR6REG : TailCallRegR6<JALR, ZERO, GPR32Opnd>, ISA_MIPS32R6;
1130  def PseudoIndirectBranchR6 : PseudoIndirectBranchBaseR6<JALR, ZERO,
1131                                                          GPR32Opnd>,
1132                               ISA_MIPS32R6;
1133}
1134
1135let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
1136                            UseIndirectJumpsHazard] in {
1137  def TAILCALLHBR6REG : TailCallReg<JR_HB_R6, GPR32Opnd>, ISA_MIPS32R6;
1138  def PseudoIndrectHazardBranchR6 : PseudoIndirectBranchBase<JR_HB_R6,
1139                                                             GPR32Opnd>,
1140                                    ISA_MIPS32R6;
1141}
1142
1143