xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/Mips16InstrInfo.td (revision 9f23cbd6cae82fd77edfad7173432fa8dccd0a95)
1//===- Mips16InstrInfo.td - Target Description for Mips16  -*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes Mips16 instructions.
10//
11//===----------------------------------------------------------------------===//
12//
13//
14// Mips Address
15//
16def addr16 : ComplexPattern<iPTR, 2, "selectAddr16", [frameindex]>;
17def addr16sp : ComplexPattern<iPTR, 2, "selectAddr16SP", [frameindex]>;
18
19//
20// Address operand
21def mem16 : Operand<i32> {
22  let PrintMethod = "printMemOperand";
23  let MIOperandInfo = (ops CPU16Regs, simm16);
24  let EncoderMethod = "getMemEncoding";
25}
26
27def mem16sp : Operand<i32> {
28  let PrintMethod = "printMemOperand";
29  // This should be CPUSPReg but the MIPS16 subtarget isn't good enough at
30  // keeping the sp-relative load and the other varieties separate at the
31  // moment. This lie fixes the problem sufficiently well to fix the errors
32  // emitted by -verify-machineinstrs and the output ends up correct as long
33  // as we use an external assembler (which is already a requirement for MIPS16
34  // for several other reasons).
35  let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
36  let EncoderMethod = "getMemEncoding";
37}
38
39def mem16_ea : Operand<i32> {
40  let PrintMethod = "printMemOperandEA";
41  let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
42  let EncoderMethod = "getMemEncoding";
43}
44
45def pcrel16 : Operand<i32>;
46
47//
48// I-type instruction format
49//
50// this is only used by bimm. the actual assembly value is a 12 bit signed
51// number
52//
53class FI16_ins<bits<5> op, string asmstr, InstrItinClass itin>:
54  FI16<op, (outs), (ins brtarget:$imm11),
55            !strconcat(asmstr, "\t$imm11 # 16 bit inst"), [], itin>;
56
57//
58//
59// I8 instruction format
60//
61
62class FI816_ins_base<bits<3> _func, string asmstr,
63                     string asmstr2, InstrItinClass itin>:
64  FI816<_func, (outs), (ins simm16:$imm8), !strconcat(asmstr, asmstr2),
65        [], itin>;
66
67class FI816_ins<bits<3> _func, string asmstr,
68                InstrItinClass itin>:
69  FI816_ins_base<_func, asmstr, "\t$imm8  # 16 bit inst", itin>;
70
71class FI816_SP_ins<bits<3> _func, string asmstr,
72                   InstrItinClass itin>:
73  FI816_ins_base<_func, asmstr, "\t$$sp, $imm8 # 16 bit inst", itin>;
74
75//
76// RI instruction format
77//
78
79
80class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2,
81                     InstrItinClass itin>:
82  FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm8),
83        !strconcat(asmstr, asmstr2), [], itin>;
84
85class FRI16_ins<bits<5> op, string asmstr,
86                InstrItinClass itin>:
87  FRI16_ins_base<op, asmstr, "\t$rx, $imm8 \t# 16 bit inst", itin>;
88
89class FRI16_TCP_ins<bits<5> _op, string asmstr,
90                    InstrItinClass itin>:
91  FRI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm8, i32imm:$size),
92            !strconcat(asmstr, "\t$rx, $imm8\t# 16 bit inst"), [], itin>;
93
94class FRI16R_ins_base<bits<5> op, string asmstr, string asmstr2,
95                     InstrItinClass itin>:
96  FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm8),
97        !strconcat(asmstr, asmstr2), [], itin>;
98
99class FRI16R_ins<bits<5> op, string asmstr,
100                InstrItinClass itin>:
101  FRI16R_ins_base<op, asmstr, "\t$rx, $imm8 \t# 16 bit inst", itin>;
102
103class F2RI16_ins<bits<5> _op, string asmstr,
104                     InstrItinClass itin>:
105  FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm8),
106        !strconcat(asmstr, "\t$rx, $imm8\t# 16 bit inst"), [], itin> {
107  let Constraints = "$rx_ = $rx";
108}
109
110class FRI16_B_ins<bits<5> _op, string asmstr,
111                  InstrItinClass itin>:
112  FRI16<_op, (outs), (ins  CPU16Regs:$rx, brtarget:$imm8),
113        !strconcat(asmstr, "\t$rx, $imm8  # 16 bit inst"), [], itin>;
114//
115// Compare a register and immediate and place result in CC
116// Implicit use of T8
117//
118// EXT-CCRR Instruction format
119//
120class FEXT_CCRXI16_ins<string asmstr>:
121  MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
122               !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> {
123  let isCodeGenOnly=1;
124  let usesCustomInserter = 1;
125}
126
127// JAL and JALX instruction format
128//
129class FJAL16_ins<bits<1> _X, string asmstr,
130                 InstrItinClass itin>:
131  FJAL16<_X, (outs), (ins uimm26:$imm26),
132         !strconcat(asmstr, "\t$imm26\n\tnop"),[],
133         itin>  {
134  let isCodeGenOnly=1;
135  let Size=6;
136}
137
138class FJALB16_ins<bits<1> _X, string asmstr,
139                 InstrItinClass itin>:
140  FJAL16<_X, (outs), (ins uimm26:$imm26),
141         !strconcat(asmstr, "\t$imm26\t# branch\n\tnop"),[],
142         itin>  {
143  let isCodeGenOnly=1;
144  let Size=6;
145}
146
147//
148// EXT-I instruction format
149//
150class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> :
151  FEXT_I16<eop, (outs), (ins brtarget:$imm16),
152           !strconcat(asmstr, "\t$imm16"),[], itin>;
153
154//
155// EXT-I8 instruction format
156//
157
158class FEXT_I816_ins_base<bits<3> _func, string asmstr,
159                         string asmstr2, InstrItinClass itin>:
160  FEXT_I816<_func, (outs), (ins simm16:$imm16), !strconcat(asmstr, asmstr2),
161            [], itin>;
162
163class FEXT_I816_ins<bits<3> _func, string asmstr,
164                    InstrItinClass itin>:
165  FEXT_I816_ins_base<_func, asmstr, "\t$imm16", itin>;
166
167class FEXT_I816_SP_ins<bits<3> _func, string asmstr,
168                       InstrItinClass itin>:
169      FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm16", itin>;
170
171//
172// Assembler formats in alphabetical order.
173// Natural and pseudos are mixed together.
174//
175// Compare two registers and place result in CC
176// Implicit use of T8
177//
178// CC-RR Instruction format
179//
180class FCCRR16_ins<string asmstr> :
181  MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
182               !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> {
183  let isCodeGenOnly=1;
184  let usesCustomInserter = 1;
185}
186
187//
188// EXT-RI instruction format
189//
190
191class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2,
192                         InstrItinClass itin>:
193  FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm16),
194                  !strconcat(asmstr, asmstr2), [], itin>;
195
196class FEXT_RI16_ins<bits<5> _op, string asmstr,
197                    InstrItinClass itin>:
198  FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm16", itin>;
199
200class FEXT_RI16R_ins_base<bits<5> _op, string asmstr, string asmstr2,
201                         InstrItinClass itin>:
202  FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm16),
203                  !strconcat(asmstr, asmstr2), [], itin>;
204
205class FEXT_RI16R_ins<bits<5> _op, string asmstr,
206                    InstrItinClass itin>:
207  FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm16", itin>;
208
209class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
210  FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm16", itin>;
211
212class FEXT_RI16_B_ins<bits<5> _op, string asmstr,
213                      InstrItinClass itin>:
214  FEXT_RI16<_op, (outs), (ins  CPU16Regs:$rx, brtarget:$imm16),
215            !strconcat(asmstr, "\t$rx, $imm16"), [], itin>;
216
217class FEXT_RI16_TCP_ins<bits<5> _op, string asmstr,
218                        InstrItinClass itin>:
219  FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm16, i32imm:$size),
220            !strconcat(asmstr, "\t$rx, $imm16"), [], itin>;
221
222class FEXT_2RI16_ins<bits<5> _op, string asmstr,
223                     InstrItinClass itin>:
224  FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm16),
225            !strconcat(asmstr, "\t$rx, $imm16"), [], itin> {
226  let Constraints = "$rx_ = $rx";
227}
228
229//
230// EXT-RRI instruction format
231//
232
233class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd,
234                         InstrItinClass itin>:
235  FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins  (MemOpnd $rx, $imm16):$addr),
236             !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
237
238class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd,
239                          InstrItinClass itin>:
240  FEXT_RRI16<op, (outs ), (ins  CPU16Regs:$ry, (MemOpnd $rx, $imm16):$addr),
241             !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
242
243//
244//
245// EXT-RRI-A instruction format
246//
247
248class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd,
249                           InstrItinClass itin>:
250  FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins  (MemOpnd $rx, $imm15):$addr),
251               !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
252
253//
254// EXT-SHIFT instruction format
255//
256class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
257  FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, uimm5:$sa6),
258               !strconcat(asmstr, "\t$rx, $ry, $sa6"), [], itin>;
259
260//
261// EXT-T8I8
262//
263class FEXT_T8I816_ins<string asmstr, string asmstr2>:
264  MipsPseudo16<(outs),
265               (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
266               !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
267               !strconcat(asmstr, "\t$imm"))),[]> {
268  let isCodeGenOnly=1;
269  let usesCustomInserter = 1;
270}
271
272//
273// EXT-T8I8I
274//
275class FEXT_T8I8I16_ins<string asmstr, string asmstr2>:
276  MipsPseudo16<(outs),
277               (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
278               !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t",
279               !strconcat(asmstr, "\t$targ"))), []> {
280  let isCodeGenOnly=1;
281  let usesCustomInserter = 1;
282}
283//
284
285
286//
287// I8_MOVR32 instruction format (used only by the MOVR32 instructio
288//
289class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
290       FI8_MOVR3216<(outs CPU16Regs:$ry), (ins GPR32:$r32),
291       !strconcat(asmstr,  "\t$ry, $r32"), [], itin>;
292
293//
294// I8_MOV32R instruction format (used only by MOV32R instruction)
295//
296
297class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
298  FI8_MOV32R16<(outs GPR32:$r32), (ins CPU16Regs:$rz),
299               !strconcat(asmstr,  "\t$r32, $rz"), [], itin>;
300
301//
302// This are pseudo formats for multiply
303// This first one can be changed to non-pseudo now.
304//
305// MULT
306//
307class FMULT16_ins<string asmstr> :
308  MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
309               !strconcat(asmstr, "\t$rx, $ry"), []>;
310
311//
312// MULT-LO
313//
314class FMULT16_LO_ins<string asmstr> :
315  MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
316               !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
317  let isCodeGenOnly=1;
318}
319
320//
321// RR-type instruction format
322//
323
324class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
325  FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
326        !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
327}
328
329class FRRBreakNull16_ins<string asmstr, InstrItinClass itin> :
330  FRRBreak16<(outs), (ins), asmstr, [], itin> {
331  let Code=0;
332}
333
334class FRR16R_ins<bits<5> f, string asmstr, InstrItinClass itin> :
335  FRR16<f, (outs), (ins  CPU16Regs:$rx, CPU16Regs:$ry),
336        !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
337}
338
339class FRRTR16_ins<string asmstr> :
340  MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
341               !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ;
342
343//
344// maybe refactor but need a $zero as a dummy first parameter
345//
346class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> :
347  FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
348        !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
349
350class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
351  FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
352        !strconcat(asmstr, "\t$rx, $ry"), [], itin> ;
353
354
355class FRR16_M_ins<bits<5> f, string asmstr,
356                  InstrItinClass itin> :
357  FRR16<f, (outs CPU16Regs:$rx), (ins),
358        !strconcat(asmstr, "\t$rx"), [], itin>;
359
360class FRxRxRy16_ins<bits<5> f, string asmstr,
361                    InstrItinClass itin> :
362  FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
363            !strconcat(asmstr, "\t$rz, $ry"),
364            [], itin> {
365  let Constraints = "$rx = $rz";
366}
367
368let rx=0 in
369class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
370                              string asmstr, InstrItinClass itin>:
371  FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t$$ra"),
372              [], itin> ;
373
374
375class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra,
376                      string asmstr, InstrItinClass itin>:
377  FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rs),
378              !strconcat(asmstr, "\t$rs"), [], itin> ;
379
380class FRR_SF16_ins
381  <bits<5> _funct, bits<3> _subfunc,
382    string asmstr, InstrItinClass itin>:
383  FRR_SF16<_funct, _subfunc, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_),
384           !strconcat(asmstr, "\t $rx"),
385           [], itin> {
386  let Constraints = "$rx_ = $rx";
387  }
388//
389// RRR-type instruction format
390//
391
392class FRRR16_ins<bits<2> _f, string asmstr,  InstrItinClass itin> :
393  FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
394         !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
395
396//
397// These Sel patterns support the generation of conditional move
398// pseudo instructions.
399//
400// The nomenclature uses the components making up the pseudo and may
401// be a bit counter intuitive when compared with the end result we seek.
402// For example using a bqez in the example directly below results in the
403// conditional move being done if the tested register is not zero.
404// I considered in easier to check by keeping the pseudo consistent with
405// it's components but it could have been done differently.
406//
407// The simplest case is when can test and operand directly and do the
408// conditional move based on a simple mips16 conditional
409//  branch instruction.
410// for example:
411// if $op == beqz or bnez:
412//
413// $op1 $rt, .+4
414// move $rd, $rs
415//
416// if $op == beqz, then if $rt != 0, then the conditional assignment
417// $rd = $rs is done.
418
419// if $op == bnez, then if $rt == 0, then the conditional assignment
420// $rd = $rs is done.
421//
422// So this pseudo class only has one operand, i.e. op
423//
424class Sel<string op>:
425  MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
426               CPU16Regs:$rt),
427               !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), []> {
428  //let isCodeGenOnly=1;
429  let Constraints = "$rd = $rd_";
430  let usesCustomInserter = 1;
431}
432
433//
434// The next two instruction classes allow for an operand which tests
435// two operands and returns a value in register T8 and
436//then does a conditional branch based on the value of T8
437//
438
439// op2 can be cmpi or slti/sltiu
440// op1 can bteqz or btnez
441// the operands for op2 are a register and a signed constant
442//
443// $op2 $t, $imm  ;test register t and branch conditionally
444// $op1 .+4       ;op1 is a conditional branch
445// move $rd, $rs
446//
447//
448class SeliT<string op1, string op2>:
449  MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
450                                       CPU16Regs:$rl, simm16:$imm),
451               !strconcat(op2,
452               !strconcat("\t$rl, $imm\n\t",
453               !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
454  let isCodeGenOnly=1;
455  let Constraints = "$rd = $rd_";
456  let usesCustomInserter = 1;
457}
458
459//
460// op2 can be cmp or slt/sltu
461// op1 can be bteqz or btnez
462// the operands for op2 are two registers
463// op1 is a conditional branch
464//
465//
466// $op2 $rl, $rr  ;test registers rl,rr
467// $op1 .+4       ;op2 is a conditional branch
468// move $rd, $rs
469//
470//
471class SelT<string op1, string op2>:
472  MipsPseudo16<(outs CPU16Regs:$rd_),
473               (ins CPU16Regs:$rd, CPU16Regs:$rs,
474                CPU16Regs:$rl, CPU16Regs:$rr),
475               !strconcat(op2,
476               !strconcat("\t$rl, $rr\n\t",
477               !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
478  let isCodeGenOnly=1;
479  let Constraints = "$rd = $rd_";
480  let usesCustomInserter = 1;
481}
482
483//
484// 32 bit constant
485//
486def Constant32 : MipsPseudo16<(outs), (ins simm32:$imm), "\t.word $imm", []>;
487
488def LwConstant32 :
489  MipsPseudo16<(outs CPU16Regs:$rx), (ins simm32:$imm, simm32:$constid),
490               "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>;
491
492//
493// Some general instruction class info
494//
495//
496
497class ArithLogic16Defs<bit isCom=0> {
498  bits<5> shamt = 0;
499  bit isCommutable = isCom;
500  bit isReMaterializable = 1;
501  bit hasSideEffects = 0;
502}
503
504class branch16 {
505  bit isBranch = 1;
506  bit isTerminator = 1;
507  bit isBarrier = 1;
508}
509
510class cbranch16 {
511  bit isBranch = 1;
512  bit isTerminator = 1;
513}
514
515class MayLoad {
516  bit mayLoad = 1;
517}
518
519class MayStore {
520  bit mayStore = 1;
521}
522//
523
524
525// Format: ADDIU rx, immediate MIPS16e
526// Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
527// To add a constant to a 32-bit integer.
528//
529def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIM16Alu>;
530
531def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIM16Alu>,
532  ArithLogic16Defs<0> {
533  let AddedComplexity = 5;
534}
535def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIM16Alu>,
536  ArithLogic16Defs<0> {
537  let isCodeGenOnly = 1;
538}
539
540let DecoderMethod = "DecodeFIXMEInstruction" in
541def AddiuRxRyOffMemX16:
542  FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIM16Alu>;
543
544//
545
546// Format: ADDIU rx, pc, immediate MIPS16e
547// Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)
548// To add a constant to the program counter.
549//
550def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIM16Alu>;
551
552//
553// Format: ADDIU sp, immediate MIPS16e
554// Purpose: Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended)
555// To add a constant to the stack pointer.
556//
557def AddiuSpImm16
558  : FI816_SP_ins<0b011, "addiu", IIM16Alu> {
559  let Defs = [SP];
560  let Uses = [SP];
561  let AddedComplexity = 5;
562}
563
564def AddiuSpImmX16
565  : FEXT_I816_SP_ins<0b011, "addiu", IIM16Alu> {
566  let Defs = [SP];
567  let Uses = [SP];
568}
569
570//
571// Format: ADDU rz, rx, ry MIPS16e
572// Purpose: Add Unsigned Word (3-Operand)
573// To add 32-bit integers.
574//
575
576def AdduRxRyRz16: FRRR16_ins<01, "addu", IIM16Alu>, ArithLogic16Defs<1>;
577
578//
579// Format: AND rx, ry MIPS16e
580// Purpose: AND
581// To do a bitwise logical AND.
582
583def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIM16Alu>, ArithLogic16Defs<1>;
584
585
586//
587// Format: BEQZ rx, offset MIPS16e
588// Purpose: Branch on Equal to Zero
589// To test a GPR then do a PC-relative conditional branch.
590//
591def BeqzRxImm16: FRI16_B_ins<0b00100, "beqz", IIM16Alu>, cbranch16;
592
593
594//
595// Format: BEQZ rx, offset MIPS16e
596// Purpose: Branch on Equal to Zero (Extended)
597// To test a GPR then do a PC-relative conditional branch.
598//
599def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIM16Alu>, cbranch16;
600
601//
602// Format: B offset MIPS16e
603// Purpose: Unconditional Branch (Extended)
604// To do an unconditional PC-relative branch.
605//
606
607def Bimm16: FI16_ins<0b00010, "b", IIM16Alu>, branch16;
608
609// Format: B offset MIPS16e
610// Purpose: Unconditional Branch
611// To do an unconditional PC-relative branch.
612//
613def BimmX16: FEXT_I16_ins<0b00010, "b", IIM16Alu>, branch16;
614
615//
616// Format: BNEZ rx, offset MIPS16e
617// Purpose: Branch on Not Equal to Zero
618// To test a GPR then do a PC-relative conditional branch.
619//
620def BnezRxImm16: FRI16_B_ins<0b00101, "bnez", IIM16Alu>, cbranch16;
621
622//
623// Format: BNEZ rx, offset MIPS16e
624// Purpose: Branch on Not Equal to Zero (Extended)
625// To test a GPR then do a PC-relative conditional branch.
626//
627def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIM16Alu>, cbranch16;
628
629
630//
631//Format: BREAK immediate
632// Purpose: Breakpoint
633// To cause a Breakpoint exception.
634
635def Break16: FRRBreakNull16_ins<"break 0", IIM16Alu>;
636//
637// Format: BTEQZ offset MIPS16e
638// Purpose: Branch on T Equal to Zero (Extended)
639// To test special register T then do a PC-relative conditional branch.
640//
641def Bteqz16: FI816_ins<0b000, "bteqz", IIM16Alu>, cbranch16 {
642  let Uses = [T8];
643}
644
645def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIM16Alu>, cbranch16 {
646  let Uses = [T8];
647}
648
649def BteqzT8CmpX16: FEXT_T8I816_ins<"bteqz", "cmp">, cbranch16;
650
651def BteqzT8CmpiX16: FEXT_T8I8I16_ins<"bteqz", "cmpi">,
652  cbranch16;
653
654def BteqzT8SltX16: FEXT_T8I816_ins<"bteqz", "slt">, cbranch16;
655
656def BteqzT8SltuX16: FEXT_T8I816_ins<"bteqz", "sltu">, cbranch16;
657
658def BteqzT8SltiX16: FEXT_T8I8I16_ins<"bteqz", "slti">, cbranch16;
659
660def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">,
661  cbranch16;
662
663//
664// Format: BTNEZ offset MIPS16e
665// Purpose: Branch on T Not Equal to Zero (Extended)
666// To test special register T then do a PC-relative conditional branch.
667//
668
669def Btnez16: FI816_ins<0b001, "btnez", IIM16Alu>, cbranch16 {
670  let Uses = [T8];
671}
672
673def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIM16Alu> ,cbranch16 {
674  let Uses = [T8];
675}
676
677def BtnezT8CmpX16: FEXT_T8I816_ins<"btnez", "cmp">, cbranch16;
678
679def BtnezT8CmpiX16: FEXT_T8I8I16_ins<"btnez", "cmpi">, cbranch16;
680
681def BtnezT8SltX16: FEXT_T8I816_ins<"btnez", "slt">, cbranch16;
682
683def BtnezT8SltuX16: FEXT_T8I816_ins<"btnez", "sltu">, cbranch16;
684
685def BtnezT8SltiX16: FEXT_T8I8I16_ins<"btnez", "slti">, cbranch16;
686
687def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">,
688  cbranch16;
689
690//
691// Format: CMP rx, ry MIPS16e
692// Purpose: Compare
693// To compare the contents of two GPRs.
694//
695def CmpRxRy16: FRR16R_ins<0b01010, "cmp", IIM16Alu> {
696  let Defs = [T8];
697}
698
699//
700// Format: CMPI rx, immediate MIPS16e
701// Purpose: Compare Immediate
702// To compare a constant with the contents of a GPR.
703//
704def CmpiRxImm16: FRI16R_ins<0b01110, "cmpi", IIM16Alu> {
705  let Defs = [T8];
706}
707
708//
709// Format: CMPI rx, immediate MIPS16e
710// Purpose: Compare Immediate (Extended)
711// To compare a constant with the contents of a GPR.
712//
713def CmpiRxImmX16: FEXT_RI16R_ins<0b01110, "cmpi", IIM16Alu> {
714  let Defs = [T8];
715}
716
717
718//
719// Format: DIV rx, ry MIPS16e
720// Purpose: Divide Word
721// To divide 32-bit signed integers.
722//
723def DivRxRy16: FRR16_div_ins<0b11010, "div", IIM16Alu> {
724  let Defs = [HI0, LO0];
725}
726
727//
728// Format: DIVU rx, ry MIPS16e
729// Purpose: Divide Unsigned Word
730// To divide 32-bit unsigned integers.
731//
732def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIM16Alu> {
733  let Defs = [HI0, LO0];
734}
735//
736// Format: JAL target MIPS16e
737// Purpose: Jump and Link
738// To execute a procedure call within the current 256 MB-aligned
739// region and preserve the current ISA.
740//
741
742def Jal16 : FJAL16_ins<0b0, "jal", IIM16Alu> {
743  let hasDelaySlot = 0;  // not true, but we add the nop for now
744  let isCall=1;
745  let Defs = [RA];
746}
747
748def JalB16 : FJALB16_ins<0b0, "jal", IIM16Alu>, branch16 {
749  let hasDelaySlot = 0;  // not true, but we add the nop for now
750  let isBranch=1;
751  let Defs = [RA];
752}
753
754//
755// Format: JR ra MIPS16e
756// Purpose: Jump Register Through Register ra
757// To execute a branch to the instruction address in the return
758// address register.
759//
760
761def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIM16Alu> {
762  let isBranch = 1;
763  let isIndirectBranch = 1;
764  let hasDelaySlot = 1;
765  let isTerminator=1;
766  let isBarrier=1;
767  let isReturn=1;
768}
769
770def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIM16Alu> {
771  let isBranch = 1;
772  let isIndirectBranch = 1;
773  let isTerminator=1;
774  let isBarrier=1;
775  let isReturn=1;
776}
777
778def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIM16Alu> {
779  let rx = 0b000;
780  let isBranch = 1;
781  let isIndirectBranch = 1;
782  let isTerminator=1;
783  let isBarrier=1;
784}
785//
786// Format: LB ry, offset(rx) MIPS16e
787// Purpose: Load Byte (Extended)
788// To load a byte from memory as a signed value.
789//
790def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, II_LB>, MayLoad{
791  let isCodeGenOnly = 1;
792}
793
794//
795// Format: LBU ry, offset(rx) MIPS16e
796// Purpose: Load Byte Unsigned (Extended)
797// To load a byte from memory as a unsigned value.
798//
799def LbuRxRyOffMemX16:
800  FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, II_LBU>, MayLoad {
801  let isCodeGenOnly = 1;
802}
803
804//
805// Format: LH ry, offset(rx) MIPS16e
806// Purpose: Load Halfword signed (Extended)
807// To load a halfword from memory as a signed value.
808//
809def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, II_LH>, MayLoad{
810  let isCodeGenOnly = 1;
811}
812
813//
814// Format: LHU ry, offset(rx) MIPS16e
815// Purpose: Load Halfword unsigned (Extended)
816// To load a halfword from memory as an unsigned value.
817//
818def LhuRxRyOffMemX16:
819  FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, II_LHU>, MayLoad {
820  let isCodeGenOnly = 1;
821}
822
823//
824// Format: LI rx, immediate MIPS16e
825// Purpose: Load Immediate
826// To load a constant into a GPR.
827//
828def LiRxImm16: FRI16_ins<0b01101, "li", IIM16Alu>;
829
830//
831// Format: LI rx, immediate MIPS16e
832// Purpose: Load Immediate (Extended)
833// To load a constant into a GPR.
834//
835def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIM16Alu>;
836
837def LiRxImmAlignX16: FEXT_RI16_ins<0b01101, ".align 2\n\tli", IIM16Alu> {
838  let isCodeGenOnly = 1;
839}
840
841//
842// Format: LW ry, offset(rx) MIPS16e
843// Purpose: Load Word (Extended)
844// To load a word from memory as a signed value.
845//
846def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, II_LW>, MayLoad{
847  let isCodeGenOnly = 1;
848}
849
850// Format: LW rx, offset(sp) MIPS16e
851// Purpose: Load Word (SP-Relative, Extended)
852// To load an SP-relative word from memory as a signed value.
853//
854let DecoderMethod = "DecodeFIXMEInstruction" in
855def LwRxSpImmX16: FEXT_RRI16_mem_ins<0b10010, "lw", mem16sp, II_LW>, MayLoad;
856
857def LwRxPcTcp16: FRI16_TCP_ins<0b10110, "lw", II_LW>, MayLoad;
858
859def LwRxPcTcpX16: FEXT_RI16_TCP_ins<0b10110, "lw", II_LW>, MayLoad;
860//
861// Format: MOVE r32, rz MIPS16e
862// Purpose: Move
863// To move the contents of a GPR to a GPR.
864//
865def Move32R16: FI8_MOV32R16_ins<"move", IIM16Alu>;
866
867//
868// Format: MOVE ry, r32 MIPS16e
869//Purpose: Move
870// To move the contents of a GPR to a GPR.
871//
872def MoveR3216: FI8_MOVR3216_ins<"move", IIM16Alu> {
873  let isMoveReg = 1;
874}
875
876//
877// Format: MFHI rx MIPS16e
878// Purpose: Move From HI Register
879// To copy the special purpose HI register to a GPR.
880//
881def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIM16Alu> {
882  let ry = 0b000; // no 'ry' field
883  let Uses = [HI0];
884  let hasSideEffects = 0;
885  let isMoveReg = 1;
886}
887
888//
889// Format: MFLO rx MIPS16e
890// Purpose: Move From LO Register
891// To copy the special purpose LO register to a GPR.
892//
893def Mflo16: FRR16_M_ins<0b10010, "mflo", IIM16Alu> {
894  let ry = 0b000; // no 'ry' field
895  let Uses = [LO0];
896  let hasSideEffects = 0;
897  let isMoveReg = 0;
898}
899
900//
901// Pseudo Instruction for mult
902//
903def MultRxRy16:  FMULT16_ins<"mult"> {
904  let isCommutable = 1;
905  let hasSideEffects = 0;
906  let Defs = [HI0, LO0];
907}
908
909def MultuRxRy16: FMULT16_ins<"multu"> {
910  let isCommutable = 1;
911  let hasSideEffects = 0;
912  let Defs = [HI0, LO0];
913}
914
915//
916// Format: MULT rx, ry MIPS16e
917// Purpose: Multiply Word
918// To multiply 32-bit signed integers.
919//
920def MultRxRyRz16: FMULT16_LO_ins<"mult"> {
921  let isCommutable = 1;
922  let hasSideEffects = 0;
923  let Defs = [HI0, LO0];
924}
925
926//
927// Format: MULTU rx, ry MIPS16e
928// Purpose: Multiply Unsigned Word
929// To multiply 32-bit unsigned integers.
930//
931def MultuRxRyRz16: FMULT16_LO_ins<"multu"> {
932  let isCommutable = 1;
933  let hasSideEffects = 0;
934  let Defs = [HI0, LO0];
935}
936
937//
938// Format: NEG rx, ry MIPS16e
939// Purpose: Negate
940// To negate an integer value.
941//
942def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIM16Alu>;
943
944//
945// Format: NOT rx, ry MIPS16e
946// Purpose: Not
947// To complement an integer value
948//
949def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIM16Alu>;
950
951//
952// Format: OR rx, ry MIPS16e
953// Purpose: Or
954// To do a bitwise logical OR.
955//
956def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIM16Alu>, ArithLogic16Defs<1>;
957
958//
959// Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize}
960// (All args are optional) MIPS16e
961// Purpose: Restore Registers and Deallocate Stack Frame
962// To deallocate a stack frame before exit from a subroutine,
963// restoring return address and static registers, and adjusting
964// stack
965//
966
967def Restore16:
968  FI8_SVRS16<0b1, (outs), (ins variable_ops),
969             "", [], II_RESTORE >, MayLoad {
970  let isCodeGenOnly = 1;
971  let Defs = [SP];
972  let Uses = [SP];
973}
974
975
976def RestoreX16:
977  FI8_SVRS16<0b1, (outs), (ins variable_ops),
978             "", [], II_RESTORE >, MayLoad {
979  let isCodeGenOnly = 1;
980  let Defs = [SP];
981  let Uses = [SP];
982}
983
984//
985// Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional)
986// MIPS16e
987// Purpose: Save Registers and Set Up Stack Frame
988// To set up a stack frame on entry to a subroutine,
989// saving return address and static registers, and adjusting stack
990//
991def Save16:
992  FI8_SVRS16<0b1, (outs), (ins variable_ops),
993             "", [], II_SAVE >, MayStore {
994  let isCodeGenOnly = 1;
995  let Uses = [SP];
996  let Defs = [SP];
997}
998
999def SaveX16:
1000  FI8_SVRS16<0b1, (outs), (ins variable_ops),
1001             "", [], II_SAVE >, MayStore {
1002  let isCodeGenOnly = 1;
1003  let Uses = [SP];
1004  let Defs = [SP];
1005}
1006//
1007// Format: SB ry, offset(rx) MIPS16e
1008// Purpose: Store Byte (Extended)
1009// To store a byte to memory.
1010//
1011let DecoderMethod = "DecodeFIXMEInstruction" in
1012def SbRxRyOffMemX16:
1013  FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, II_SB>, MayStore;
1014
1015//
1016// Format: SEB rx MIPS16e
1017// Purpose: Sign-Extend Byte
1018// Sign-extend least significant byte in register rx.
1019//
1020def SebRx16
1021  : FRR_SF16_ins<0b10001, 0b100, "seb", IIM16Alu>;
1022
1023//
1024// Format: SEH rx MIPS16e
1025// Purpose: Sign-Extend Halfword
1026// Sign-extend least significant word in register rx.
1027//
1028def SehRx16
1029  : FRR_SF16_ins<0b10001, 0b101, "seh", IIM16Alu>;
1030
1031//
1032// The Sel(T) instructions are pseudos
1033// T means that they use T8 implicitly.
1034//
1035//
1036// Format: SelBeqZ rd, rs, rt
1037// Purpose: if rt==0, do nothing
1038//          else rs = rt
1039//
1040def SelBeqZ: Sel<"beqz">;
1041
1042//
1043// Format:  SelTBteqZCmp rd, rs, rl, rr
1044// Purpose: b = Cmp rl, rr.
1045//          If b==0 then do nothing.
1046//          if b!=0 then rd = rs
1047//
1048def SelTBteqZCmp: SelT<"bteqz", "cmp">;
1049
1050//
1051// Format:  SelTBteqZCmpi rd, rs, rl, rr
1052// Purpose: b = Cmpi rl, imm.
1053//          If b==0 then do nothing.
1054//          if b!=0 then rd = rs
1055//
1056def SelTBteqZCmpi: SeliT<"bteqz", "cmpi">;
1057
1058//
1059// Format:  SelTBteqZSlt rd, rs, rl, rr
1060// Purpose: b = Slt rl, rr.
1061//          If b==0 then do nothing.
1062//          if b!=0 then rd = rs
1063//
1064def SelTBteqZSlt: SelT<"bteqz", "slt">;
1065
1066//
1067// Format:  SelTBteqZSlti rd, rs, rl, rr
1068// Purpose: b = Slti rl, imm.
1069//          If b==0 then do nothing.
1070//          if b!=0 then rd = rs
1071//
1072def SelTBteqZSlti: SeliT<"bteqz", "slti">;
1073
1074//
1075// Format:  SelTBteqZSltu rd, rs, rl, rr
1076// Purpose: b = Sltu rl, rr.
1077//          If b==0 then do nothing.
1078//          if b!=0 then rd = rs
1079//
1080def SelTBteqZSltu: SelT<"bteqz", "sltu">;
1081
1082//
1083// Format:  SelTBteqZSltiu rd, rs, rl, rr
1084// Purpose: b = Sltiu rl, imm.
1085//          If b==0 then do nothing.
1086//          if b!=0 then rd = rs
1087//
1088def SelTBteqZSltiu: SeliT<"bteqz", "sltiu">;
1089
1090//
1091// Format: SelBnez rd, rs, rt
1092// Purpose: if rt!=0, do nothing
1093//          else rs = rt
1094//
1095def SelBneZ: Sel<"bnez">;
1096
1097//
1098// Format:  SelTBtneZCmp rd, rs, rl, rr
1099// Purpose: b = Cmp rl, rr.
1100//          If b!=0 then do nothing.
1101//          if b0=0 then rd = rs
1102//
1103def SelTBtneZCmp: SelT<"btnez", "cmp">;
1104
1105//
1106// Format:  SelTBtnezCmpi rd, rs, rl, rr
1107// Purpose: b = Cmpi rl, imm.
1108//          If b!=0 then do nothing.
1109//          if b==0 then rd = rs
1110//
1111def SelTBtneZCmpi: SeliT<"btnez", "cmpi">;
1112
1113//
1114// Format:  SelTBtneZSlt rd, rs, rl, rr
1115// Purpose: b = Slt rl, rr.
1116//          If b!=0 then do nothing.
1117//          if b==0 then rd = rs
1118//
1119def SelTBtneZSlt: SelT<"btnez", "slt">;
1120
1121//
1122// Format:  SelTBtneZSlti rd, rs, rl, rr
1123// Purpose: b = Slti rl, imm.
1124//          If b!=0 then do nothing.
1125//          if b==0 then rd = rs
1126//
1127def SelTBtneZSlti: SeliT<"btnez", "slti">;
1128
1129//
1130// Format:  SelTBtneZSltu rd, rs, rl, rr
1131// Purpose: b = Sltu rl, rr.
1132//          If b!=0 then do nothing.
1133//          if b==0 then rd = rs
1134//
1135def SelTBtneZSltu: SelT<"btnez", "sltu">;
1136
1137//
1138// Format:  SelTBtneZSltiu rd, rs, rl, rr
1139// Purpose: b = Slti rl, imm.
1140//          If b!=0 then do nothing.
1141//          if b==0 then rd = rs
1142//
1143def SelTBtneZSltiu: SeliT<"btnez", "sltiu">;
1144//
1145//
1146// Format: SH ry, offset(rx) MIPS16e
1147// Purpose: Store Halfword (Extended)
1148// To store a halfword to memory.
1149//
1150let DecoderMethod = "DecodeFIXMEInstruction" in
1151def ShRxRyOffMemX16:
1152  FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, II_SH>, MayStore;
1153
1154//
1155// Format: SLL rx, ry, sa MIPS16e
1156// Purpose: Shift Word Left Logical (Extended)
1157// To execute a left-shift of a word by a fixed number of bits-0 to 31 bits.
1158//
1159def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIM16Alu>;
1160
1161//
1162// Format: SLLV ry, rx MIPS16e
1163// Purpose: Shift Word Left Logical Variable
1164// To execute a left-shift of a word by a variable number of bits.
1165//
1166def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIM16Alu>;
1167
1168// Format: SLTI rx, immediate MIPS16e
1169// Purpose: Set on Less Than Immediate
1170// To record the result of a less-than comparison with a constant.
1171//
1172//
1173def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIM16Alu> {
1174  let Defs = [T8];
1175}
1176
1177//
1178// Format: SLTI rx, immediate MIPS16e
1179// Purpose: Set on Less Than Immediate (Extended)
1180// To record the result of a less-than comparison with a constant.
1181//
1182//
1183def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti", IIM16Alu> {
1184  let Defs = [T8];
1185}
1186
1187def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">;
1188
1189// Format: SLTIU rx, immediate MIPS16e
1190// Purpose: Set on Less Than Immediate Unsigned
1191// To record the result of a less-than comparison with a constant.
1192//
1193//
1194def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIM16Alu> {
1195  let Defs = [T8];
1196}
1197
1198//
1199// Format: SLTI rx, immediate MIPS16e
1200// Purpose: Set on Less Than Immediate Unsigned (Extended)
1201// To record the result of a less-than comparison with a constant.
1202//
1203//
1204def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu", IIM16Alu> {
1205  let Defs = [T8];
1206}
1207//
1208// Format: SLTIU rx, immediate MIPS16e
1209// Purpose: Set on Less Than Immediate Unsigned (Extended)
1210// To record the result of a less-than comparison with a constant.
1211//
1212def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">;
1213
1214//
1215// Format: SLT rx, ry MIPS16e
1216// Purpose: Set on Less Than
1217// To record the result of a less-than comparison.
1218//
1219def SltRxRy16: FRR16R_ins<0b00010, "slt", IIM16Alu>{
1220  let Defs = [T8];
1221}
1222
1223def SltCCRxRy16: FCCRR16_ins<"slt">;
1224
1225// Format: SLTU rx, ry MIPS16e
1226// Purpose: Set on Less Than Unsigned
1227// To record the result of an unsigned less-than comparison.
1228//
1229def SltuRxRy16: FRR16R_ins<0b00011, "sltu", IIM16Alu>{
1230  let Defs = [T8];
1231}
1232
1233def SltuRxRyRz16: FRRTR16_ins<"sltu"> {
1234  let isCodeGenOnly=1;
1235  let Defs = [T8];
1236}
1237
1238
1239def SltuCCRxRy16: FCCRR16_ins<"sltu">;
1240//
1241// Format: SRAV ry, rx MIPS16e
1242// Purpose: Shift Word Right Arithmetic Variable
1243// To execute an arithmetic right-shift of a word by a variable
1244// number of bits.
1245//
1246def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIM16Alu>;
1247
1248
1249//
1250// Format: SRA rx, ry, sa MIPS16e
1251// Purpose: Shift Word Right Arithmetic (Extended)
1252// To execute an arithmetic right-shift of a word by a fixed
1253// number of bits-1 to 8 bits.
1254//
1255def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIM16Alu>;
1256
1257
1258//
1259// Format: SRLV ry, rx MIPS16e
1260// Purpose: Shift Word Right Logical Variable
1261// To execute a logical right-shift of a word by a variable
1262// number of bits.
1263//
1264def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIM16Alu>;
1265
1266
1267//
1268// Format: SRL rx, ry, sa MIPS16e
1269// Purpose: Shift Word Right Logical (Extended)
1270// To execute a logical right-shift of a word by a fixed
1271// number of bits-1 to 31 bits.
1272//
1273def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIM16Alu>;
1274
1275//
1276// Format: SUBU rz, rx, ry MIPS16e
1277// Purpose: Subtract Unsigned Word
1278// To subtract 32-bit integers
1279//
1280def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIM16Alu>, ArithLogic16Defs<0>;
1281
1282//
1283// Format: SW ry, offset(rx) MIPS16e
1284// Purpose: Store Word (Extended)
1285// To store a word to memory.
1286//
1287let DecoderMethod = "DecodeFIXMEInstruction" in
1288def SwRxRyOffMemX16: FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, II_SW>, MayStore;
1289
1290//
1291// Format: SW rx, offset(sp) MIPS16e
1292// Purpose: Store Word rx (SP-Relative)
1293// To store an SP-relative word to memory.
1294//
1295let DecoderMethod = "DecodeFIXMEInstruction" in
1296def SwRxSpImmX16: FEXT_RRI16_mem2_ins<0b11010, "sw", mem16sp, II_SW>, MayStore;
1297
1298//
1299//
1300// Format: XOR rx, ry MIPS16e
1301// Purpose: Xor
1302// To do a bitwise logical XOR.
1303//
1304def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIM16Alu>, ArithLogic16Defs<1>;
1305
1306class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
1307  let Predicates = [InMips16Mode];
1308}
1309
1310// Unary Arith/Logic
1311//
1312class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
1313  Mips16Pat<(OpNode CPU16Regs:$r),
1314            (I CPU16Regs:$r)>;
1315
1316def: ArithLogicU_pat<not, NotRxRy16>;
1317def: ArithLogicU_pat<ineg, NegRxRy16>;
1318
1319class ArithLogic16_pat<SDNode OpNode, Instruction I> :
1320  Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
1321            (I CPU16Regs:$l, CPU16Regs:$r)>;
1322
1323def: ArithLogic16_pat<add, AdduRxRyRz16>;
1324def: ArithLogic16_pat<and, AndRxRxRy16>;
1325def: ArithLogic16_pat<mul, MultRxRyRz16>;
1326def: ArithLogic16_pat<or, OrRxRxRy16>;
1327def: ArithLogic16_pat<sub, SubuRxRyRz16>;
1328def: ArithLogic16_pat<xor, XorRxRxRy16>;
1329
1330// Arithmetic and logical instructions with 2 register operands.
1331
1332class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
1333  Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1334            (I CPU16Regs:$in, imm_type:$imm)>;
1335
1336def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>;
1337def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>;
1338def: ArithLogicI16_pat<shl, immZExt5, SllX16>;
1339def: ArithLogicI16_pat<srl, immZExt5, SrlX16>;
1340def: ArithLogicI16_pat<sra, immZExt5, SraX16>;
1341
1342class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
1343  Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
1344            (I CPU16Regs:$r, CPU16Regs:$ra)>;
1345
1346def: shift_rotate_reg16_pat<shl, SllvRxRy16>;
1347def: shift_rotate_reg16_pat<sra, SravRxRy16>;
1348def: shift_rotate_reg16_pat<srl, SrlvRxRy16>;
1349
1350class LoadM16_pat<PatFrag OpNode, Instruction I, ComplexPattern Addr> :
1351  Mips16Pat<(OpNode Addr:$addr), (I Addr:$addr)>;
1352
1353def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16, addr16>;
1354def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16, addr16>;
1355def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16, addr16>;
1356def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16, addr16>;
1357def: LoadM16_pat<load, LwRxSpImmX16, addr16sp>;
1358
1359class StoreM16_pat<PatFrag OpNode, Instruction I, ComplexPattern Addr> :
1360  Mips16Pat<(OpNode CPU16Regs:$r, Addr:$addr), (I CPU16Regs:$r, Addr:$addr)>;
1361
1362def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16, addr16>;
1363def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16, addr16>;
1364def: StoreM16_pat<store, SwRxSpImmX16, addr16sp>;
1365
1366// Unconditional branch
1367class UncondBranch16_pat<SDNode OpNode, Instruction I>:
1368  Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> {
1369    let Predicates = [InMips16Mode];
1370  }
1371
1372def : Mips16Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1373                (Jal16 tglobaladdr:$dst)>;
1374
1375def : Mips16Pat<(MipsJmpLink (i32 texternalsym:$dst)),
1376                (Jal16 texternalsym:$dst)>;
1377
1378// Indirect branch
1379def: Mips16Pat<(brind CPU16Regs:$rs), (JrcRx16 CPU16Regs:$rs)> {
1380  // Ensure that the addition of MIPS32r6/MIPS64r6 support does not change
1381  // MIPS16's behaviour.
1382  let AddedComplexity = 1;
1383}
1384
1385// Jump and Link (Call)
1386let isCall=1, hasDelaySlot=0 in
1387def JumpLinkReg16:
1388  FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rx),
1389              "jalrc\t$rx", [(MipsJmpLink CPU16Regs:$rx)], II_JALRC> {
1390  let Defs = [RA];
1391}
1392
1393// Mips16 pseudos
1394let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
1395  hasExtraSrcRegAllocReq = 1 in
1396def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
1397
1398
1399// setcc patterns
1400
1401class SetCC_R16<PatFrag cond_op, Instruction I>:
1402  Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
1403            (I CPU16Regs:$rx, CPU16Regs:$ry)>;
1404
1405class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
1406  Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1407            (I CPU16Regs:$rx, imm_type:$imm16)>;
1408
1409
1410def: Mips16Pat<(i32 addr16sp:$addr), (AddiuRxRyOffMemX16 addr16sp:$addr)>;
1411
1412
1413// Large (>16 bit) immediate loads
1414def : Mips16Pat<(i32 imm:$imm), (LwConstant32 imm:$imm, -1)>;
1415
1416//
1417// Some branch conditional patterns are not generated by llvm at this time.
1418// Some are for seemingly arbitrary reasons not used: i.e. with signed number
1419// comparison they are used and for unsigned a different pattern is used.
1420// I am pushing upstream from the full mips16 port and it seemed that I needed
1421// these earlier and the mips32 port has these but now I cannot create test
1422// cases that use these patterns. While I sort this all out I will leave these
1423// extra patterns commented out and if I can be sure they are really not used,
1424// I will delete the code. I don't want to check the code in uncommented without
1425// a valid test case. In some cases, the compiler is generating patterns with
1426// setcc instead and earlier I had implemented setcc first so may have masked
1427// the problem. The setcc variants are suboptimal for mips16 so I may wantto
1428// figure out how to enable the brcond patterns or else possibly new
1429// combinations of brcond and setcc.
1430//
1431//
1432// bcond-seteq
1433//
1434def: Mips16Pat
1435  <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1436   (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry,  bb:$imm16)
1437  >;
1438
1439
1440def: Mips16Pat
1441  <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1442   (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm,  bb:$targ16)
1443  >;
1444
1445def: Mips16Pat
1446  <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16),
1447   (BeqzRxImm16 CPU16Regs:$rx, bb:$targ16)
1448  >;
1449
1450//
1451// bcond-setgt (do we need to have this pair of setlt, setgt??)
1452//
1453def: Mips16Pat
1454  <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1455   (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx,  bb:$imm16)
1456  >;
1457
1458//
1459// bcond-setge
1460//
1461def: Mips16Pat
1462  <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1463   (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry,  bb:$imm16)
1464  >;
1465
1466//
1467// never called because compiler transforms a >= k to a > (k-1)
1468def: Mips16Pat
1469  <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1470   (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm,  bb:$imm16)
1471  >;
1472
1473//
1474// bcond-setlt
1475//
1476def: Mips16Pat
1477  <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1478   (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry,  bb:$imm16)
1479  >;
1480
1481def: Mips16Pat
1482  <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1483   (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm,  bb:$imm16)
1484  >;
1485
1486//
1487// bcond-setle
1488//
1489def: Mips16Pat
1490  <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1491   (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx,  bb:$imm16)
1492  >;
1493
1494//
1495// bcond-setne
1496//
1497def: Mips16Pat
1498  <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1499   (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry,  bb:$imm16)
1500  >;
1501
1502def: Mips16Pat
1503  <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1504   (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm,  bb:$targ16)
1505  >;
1506
1507def: Mips16Pat
1508  <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16),
1509   (BnezRxImm16 CPU16Regs:$rx, bb:$targ16)
1510  >;
1511
1512//
1513// This needs to be there but I forget which code will generate it
1514//
1515def: Mips16Pat
1516  <(brcond CPU16Regs:$rx, bb:$targ16),
1517   (BnezRxImm16 CPU16Regs:$rx, bb:$targ16)
1518  >;
1519
1520//
1521
1522//
1523// bcond-setugt
1524//
1525//def: Mips16Pat
1526//  <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1527//   (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx,  bb:$imm16)
1528//  >;
1529
1530//
1531// bcond-setuge
1532//
1533//def: Mips16Pat
1534//  <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1535//   (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry,  bb:$imm16)
1536//  >;
1537
1538
1539//
1540// bcond-setult
1541//
1542//def: Mips16Pat
1543//  <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1544//   (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry,  bb:$imm16)
1545//  >;
1546
1547def: UncondBranch16_pat<br, Bimm16>;
1548
1549// Small immediates
1550def: Mips16Pat<(i32 immSExt16:$in),
1551               (AddiuRxRxImmX16 (MoveR3216 ZERO), immSExt16:$in)>;
1552
1553def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
1554
1555//
1556// MipsDivRem
1557//
1558def: Mips16Pat
1559  <(MipsDivRem16 CPU16Regs:$rx, CPU16Regs:$ry),
1560   (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1561
1562//
1563// MipsDivRemU
1564//
1565def: Mips16Pat
1566  <(MipsDivRemU16 CPU16Regs:$rx, CPU16Regs:$ry),
1567   (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1568
1569//  signed a,b
1570//  x = (a>=b)?x:y
1571//
1572//  if !(a < b) x = y
1573//
1574def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)),
1575                 CPU16Regs:$x, CPU16Regs:$y),
1576                (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1577                 CPU16Regs:$a, CPU16Regs:$b)>;
1578
1579//  signed a,b
1580//  x = (a>b)?x:y
1581//
1582//  if  (b < a) x = y
1583//
1584def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)),
1585                 CPU16Regs:$x, CPU16Regs:$y),
1586                (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y,
1587                 CPU16Regs:$b, CPU16Regs:$a)>;
1588
1589// unsigned a,b
1590// x = (a>=b)?x:y
1591//
1592// if !(a < b) x = y;
1593//
1594def : Mips16Pat<
1595  (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)),
1596   CPU16Regs:$x, CPU16Regs:$y),
1597  (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1598   CPU16Regs:$a, CPU16Regs:$b)>;
1599
1600//  unsigned a,b
1601//  x = (a>b)?x:y
1602//
1603//  if (b < a) x = y
1604//
1605def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)),
1606                 CPU16Regs:$x, CPU16Regs:$y),
1607                (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y,
1608                 CPU16Regs:$b, CPU16Regs:$a)>;
1609
1610// signed
1611// x = (a >= k)?x:y
1612// due to an llvm optimization, i don't think that this will ever
1613// be used. This is transformed into x = (a > k-1)?x:y
1614//
1615//
1616
1617//def : Mips16Pat<
1618//  (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)),
1619//   CPU16Regs:$T, CPU16Regs:$F),
1620//  (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F,
1621//   CPU16Regs:$lhs, immSExt16:$rhs)>;
1622
1623//def : Mips16Pat<
1624//  (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)),
1625//   CPU16Regs:$T, CPU16Regs:$F),
1626//  (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F,
1627//   CPU16Regs:$lhs, immSExt16:$rhs)>;
1628
1629// signed
1630// x = (a < k)?x:y
1631//
1632// if !(a < k) x = y;
1633//
1634def : Mips16Pat<
1635  (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)),
1636   CPU16Regs:$x, CPU16Regs:$y),
1637  (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y,
1638   CPU16Regs:$a, immSExt16:$b)>;
1639
1640
1641//
1642//
1643// signed
1644// x = (a <= b)? x : y
1645//
1646// if  (b < a) x = y
1647//
1648def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)),
1649                 CPU16Regs:$x, CPU16Regs:$y),
1650                (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1651                 CPU16Regs:$b, CPU16Regs:$a)>;
1652
1653//
1654// unsigned
1655// x = (a <= b)? x : y
1656//
1657// if  (b < a) x = y
1658//
1659def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)),
1660                 CPU16Regs:$x, CPU16Regs:$y),
1661                (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1662                 CPU16Regs:$b, CPU16Regs:$a)>;
1663
1664//
1665// signed/unsigned
1666// x = (a == b)? x : y
1667//
1668// if (a != b) x = y
1669//
1670def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)),
1671                 CPU16Regs:$x, CPU16Regs:$y),
1672                (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y,
1673                 CPU16Regs:$b, CPU16Regs:$a)>;
1674
1675//
1676// signed/unsigned
1677// x = (a == 0)? x : y
1678//
1679// if (a != 0) x = y
1680//
1681def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)),
1682                 CPU16Regs:$x, CPU16Regs:$y),
1683                (SelBeqZ CPU16Regs:$x, CPU16Regs:$y,
1684                 CPU16Regs:$a)>;
1685
1686
1687//
1688// signed/unsigned
1689// x = (a == k)? x : y
1690//
1691// if (a != k) x = y
1692//
1693def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)),
1694                 CPU16Regs:$x, CPU16Regs:$y),
1695                (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y,
1696                 CPU16Regs:$a, immZExt16:$k)>;
1697
1698
1699//
1700// signed/unsigned
1701// x = (a != b)? x : y
1702//
1703// if (a == b) x = y
1704//
1705//
1706def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)),
1707                 CPU16Regs:$x, CPU16Regs:$y),
1708                (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y,
1709                 CPU16Regs:$b, CPU16Regs:$a)>;
1710
1711//
1712// signed/unsigned
1713// x = (a != 0)? x : y
1714//
1715// if (a == 0) x = y
1716//
1717def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)),
1718                 CPU16Regs:$x, CPU16Regs:$y),
1719                (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1720                 CPU16Regs:$a)>;
1721
1722// signed/unsigned
1723// x = (a)? x : y
1724//
1725// if (!a) x = y
1726//
1727def : Mips16Pat<(select  CPU16Regs:$a,
1728                 CPU16Regs:$x, CPU16Regs:$y),
1729      (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1730       CPU16Regs:$a)>;
1731
1732
1733//
1734// signed/unsigned
1735// x = (a != k)? x : y
1736//
1737// if (a == k) x = y
1738//
1739def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)),
1740                 CPU16Regs:$x, CPU16Regs:$y),
1741                (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y,
1742                 CPU16Regs:$a, immZExt16:$k)>;
1743
1744//
1745// When writing C code to test setxx these patterns,
1746// some will be transformed into
1747// other things. So we test using C code but using -O3 and -O0
1748//
1749// seteq
1750//
1751def : Mips16Pat
1752  <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs),
1753   (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>;
1754
1755def : Mips16Pat
1756  <(seteq CPU16Regs:$lhs, 0),
1757   (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>;
1758
1759
1760//
1761// setge
1762//
1763
1764def: Mips16Pat
1765  <(setge CPU16Regs:$lhs, CPU16Regs:$rhs),
1766   (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1767   (LiRxImmX16 1))>;
1768
1769//
1770// For constants, llvm transforms this to:
1771// x > (k - 1) and then reverses the operands to use setlt. So this pattern
1772// is not used now by the compiler. (Presumably checking that k-1 does not
1773// overflow). The compiler never uses this at the current time, due to
1774// other optimizations.
1775//
1776//def: Mips16Pat
1777//  <(setge CPU16Regs:$lhs, immSExt16:$rhs),
1778//   (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs),
1779//   (LiRxImmX16 1))>;
1780
1781// This catches the x >= -32768 case by transforming it to  x > -32769
1782//
1783def: Mips16Pat
1784  <(setgt CPU16Regs:$lhs, -32769),
1785   (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768),
1786   (LiRxImmX16 1))>;
1787
1788//
1789// setgt
1790//
1791//
1792
1793def: Mips16Pat
1794  <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
1795   (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1796
1797//
1798// setle
1799//
1800def: Mips16Pat
1801  <(setle CPU16Regs:$lhs, CPU16Regs:$rhs),
1802   (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImm16 1))>;
1803
1804//
1805// setlt
1806//
1807def: SetCC_R16<setlt, SltCCRxRy16>;
1808
1809def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
1810
1811//
1812// setne
1813//
1814def : Mips16Pat
1815  <(setne CPU16Regs:$lhs,CPU16Regs:$rhs),
1816   (SltuCCRxRy16 (LiRxImmX16 0),
1817   (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>;
1818
1819
1820//
1821// setuge
1822//
1823def: Mips16Pat
1824  <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs),
1825   (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1826   (LiRxImmX16 1))>;
1827
1828// this pattern will never be used because the compiler will transform
1829// x >= k to x > (k - 1) and then use SLT
1830//
1831//def: Mips16Pat
1832//  <(setuge CPU16Regs:$lhs, immZExt16:$rhs),
1833//   (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs),
1834//   (LiRxImmX16 1))>;
1835
1836//
1837// setugt
1838//
1839def: Mips16Pat
1840  <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs),
1841   (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1842
1843//
1844// setule
1845//
1846def: Mips16Pat
1847  <(setule CPU16Regs:$lhs, CPU16Regs:$rhs),
1848   (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
1849
1850//
1851// setult
1852//
1853def: SetCC_R16<setult, SltuCCRxRy16>;
1854
1855def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>;
1856
1857def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
1858               (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;
1859
1860// hi/lo relocs
1861def : Mips16Pat<(MipsHi tblockaddress:$in),
1862                (SllX16 (LiRxImmX16 tblockaddress:$in), 16)>;
1863def : Mips16Pat<(MipsHi tglobaladdr:$in),
1864                (SllX16 (LiRxImmX16 tglobaladdr:$in), 16)>;
1865def : Mips16Pat<(MipsHi tjumptable:$in),
1866                (SllX16 (LiRxImmX16 tjumptable:$in), 16)>;
1867
1868def : Mips16Pat<(MipsLo tblockaddress:$in), (LiRxImmX16 tblockaddress:$in)>;
1869
1870def : Mips16Pat<(MipsTlsHi tglobaltlsaddr:$in),
1871                (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>;
1872
1873// wrapper_pic
1874class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1875  Mips16Pat<(MipsWrapper RC:$gp, node:$in),
1876            (ADDiuOp RC:$gp, node:$in)>;
1877
1878
1879def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>;
1880def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>;
1881
1882def : Mips16Pat<(i32 (extloadi8   addr16:$src)),
1883                (LbuRxRyOffMemX16  addr16:$src)>;
1884def : Mips16Pat<(i32 (extloadi16  addr16:$src)),
1885                (LhuRxRyOffMemX16  addr16:$src)>;
1886
1887def: Mips16Pat<(trap), (Break16)>;
1888
1889def : Mips16Pat<(sext_inreg CPU16Regs:$val, i8),
1890                (SebRx16 CPU16Regs:$val)>;
1891
1892def : Mips16Pat<(sext_inreg CPU16Regs:$val, i16),
1893                (SehRx16 CPU16Regs:$val)>;
1894
1895def GotPrologue16:
1896  MipsPseudo16<
1897    (outs CPU16Regs:$rh, CPU16Regs:$rl),
1898    (ins simm16:$immHi, simm16:$immLo),
1899    "li\t$rh, $immHi\n\taddiu\t$rl, $$pc, $immLo\n ",[]> ;
1900
1901// An operand for the CONSTPOOL_ENTRY pseudo-instruction.
1902def cpinst_operand : Operand<i32> {
1903  // let PrintMethod = "printCPInstOperand";
1904}
1905
1906// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1907// the function.  The first operand is the ID# for this instruction, the second
1908// is the index into the MachineConstantPool that this is, the third is the
1909// size in bytes of this constant pool entry.
1910//
1911let hasSideEffects = 0, isNotDuplicable = 1 in
1912def CONSTPOOL_ENTRY :
1913MipsPseudo16<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1914                      i32imm:$size), "foo", []>;
1915
1916// Instruction Aliases
1917
1918let EncodingPredicates = [InMips16Mode] in
1919def : MipsInstAlias<"nop", (Move32R16 ZERO, S0)>;
1920