1*0b57cec5SDimitry Andric //===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===// 2*0b57cec5SDimitry Andric // 3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric // 7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric // 9*0b57cec5SDimitry Andric // Subclass of MipsTargetLowering specialized for mips16. 10*0b57cec5SDimitry Andric // 11*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 12*0b57cec5SDimitry Andric 13*0b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_MIPS_MIPS16ISELLOWERING_H 14*0b57cec5SDimitry Andric #define LLVM_LIB_TARGET_MIPS_MIPS16ISELLOWERING_H 15*0b57cec5SDimitry Andric 16*0b57cec5SDimitry Andric #include "MipsISelLowering.h" 17*0b57cec5SDimitry Andric 18*0b57cec5SDimitry Andric namespace llvm { 19*0b57cec5SDimitry Andric class Mips16TargetLowering : public MipsTargetLowering { 20*0b57cec5SDimitry Andric public: 21*0b57cec5SDimitry Andric explicit Mips16TargetLowering(const MipsTargetMachine &TM, 22*0b57cec5SDimitry Andric const MipsSubtarget &STI); 23*0b57cec5SDimitry Andric 24*0b57cec5SDimitry Andric bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, 25*0b57cec5SDimitry Andric unsigned Align, 26*0b57cec5SDimitry Andric MachineMemOperand::Flags Flags, 27*0b57cec5SDimitry Andric bool *Fast) const override; 28*0b57cec5SDimitry Andric 29*0b57cec5SDimitry Andric MachineBasicBlock * 30*0b57cec5SDimitry Andric EmitInstrWithCustomInserter(MachineInstr &MI, 31*0b57cec5SDimitry Andric MachineBasicBlock *MBB) const override; 32*0b57cec5SDimitry Andric 33*0b57cec5SDimitry Andric private: 34*0b57cec5SDimitry Andric bool isEligibleForTailCallOptimization( 35*0b57cec5SDimitry Andric const CCState &CCInfo, unsigned NextStackOffset, 36*0b57cec5SDimitry Andric const MipsFunctionInfo &FI) const override; 37*0b57cec5SDimitry Andric 38*0b57cec5SDimitry Andric void setMips16HardFloatLibCalls(); 39*0b57cec5SDimitry Andric 40*0b57cec5SDimitry Andric unsigned int 41*0b57cec5SDimitry Andric getMips16HelperFunctionStubNumber(ArgListTy &Args) const; 42*0b57cec5SDimitry Andric 43*0b57cec5SDimitry Andric const char *getMips16HelperFunction 44*0b57cec5SDimitry Andric (Type* RetTy, ArgListTy &Args, bool &needHelper) const; 45*0b57cec5SDimitry Andric 46*0b57cec5SDimitry Andric void 47*0b57cec5SDimitry Andric getOpndList(SmallVectorImpl<SDValue> &Ops, 48*0b57cec5SDimitry Andric std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 49*0b57cec5SDimitry Andric bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 50*0b57cec5SDimitry Andric bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 51*0b57cec5SDimitry Andric SDValue Chain) const override; 52*0b57cec5SDimitry Andric 53*0b57cec5SDimitry Andric MachineBasicBlock *emitSel16(unsigned Opc, MachineInstr &MI, 54*0b57cec5SDimitry Andric MachineBasicBlock *BB) const; 55*0b57cec5SDimitry Andric 56*0b57cec5SDimitry Andric MachineBasicBlock *emitSeliT16(unsigned Opc1, unsigned Opc2, 57*0b57cec5SDimitry Andric MachineInstr &MI, 58*0b57cec5SDimitry Andric MachineBasicBlock *BB) const; 59*0b57cec5SDimitry Andric 60*0b57cec5SDimitry Andric MachineBasicBlock *emitSelT16(unsigned Opc1, unsigned Opc2, 61*0b57cec5SDimitry Andric MachineInstr &MI, 62*0b57cec5SDimitry Andric MachineBasicBlock *BB) const; 63*0b57cec5SDimitry Andric 64*0b57cec5SDimitry Andric MachineBasicBlock *emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc, 65*0b57cec5SDimitry Andric MachineInstr &MI, 66*0b57cec5SDimitry Andric MachineBasicBlock *BB) const; 67*0b57cec5SDimitry Andric 68*0b57cec5SDimitry Andric MachineBasicBlock *emitFEXT_T8I8I16_ins(unsigned BtOpc, unsigned CmpiOpc, 69*0b57cec5SDimitry Andric unsigned CmpiXOpc, bool ImmSigned, 70*0b57cec5SDimitry Andric MachineInstr &MI, 71*0b57cec5SDimitry Andric MachineBasicBlock *BB) const; 72*0b57cec5SDimitry Andric 73*0b57cec5SDimitry Andric MachineBasicBlock *emitFEXT_CCRX16_ins(unsigned SltOpc, MachineInstr &MI, 74*0b57cec5SDimitry Andric MachineBasicBlock *BB) const; 75*0b57cec5SDimitry Andric 76*0b57cec5SDimitry Andric MachineBasicBlock *emitFEXT_CCRXI16_ins(unsigned SltiOpc, unsigned SltiXOpc, 77*0b57cec5SDimitry Andric MachineInstr &MI, 78*0b57cec5SDimitry Andric MachineBasicBlock *BB) const; 79*0b57cec5SDimitry Andric }; 80*0b57cec5SDimitry Andric } 81*0b57cec5SDimitry Andric 82*0b57cec5SDimitry Andric #endif 83