1//===- MicroMipsDSPInstrInfo.td - Micromips DSP instructions -*- tablegen *-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes MicroMips DSP instructions. 10// 11//===----------------------------------------------------------------------===// 12 13// Instruction encoding. 14class ADDQ_PH_MM_ENC : POOL32A_3R_FMT<"addq.ph", 0b00000001101>; 15class ADDQ_S_PH_MM_ENC : POOL32A_3R_FMT<"addq_s.ph", 0b10000001101>; 16class ADDQ_S_W_MM_ENC : POOL32A_3RB0_FMT<"addq_s.w", 0b1100000101>; 17class ADDQH_PH_MMR2_ENC : POOL32A_3R_FMT<"addqh.ph", 0b00001001101>; 18class ADDQH_R_PH_MMR2_ENC : POOL32A_3R_FMT<"addqh_r.ph", 0b10001001101>; 19class ADDQH_W_MMR2_ENC: POOL32A_3R_FMT<"addqh.w", 0b00010001101>; 20class ADDQH_R_W_MMR2_ENC : POOL32A_3R_FMT<"addqh_r.w", 0b10010001101>; 21class ADDU_PH_MMR2_ENC : POOL32A_3R_FMT<"addu.ph", 0b00100001101>; 22class ADDU_S_PH_MMR2_ENC : POOL32A_3R_FMT<"addu_s.ph", 0b10100001101>; 23class ADDU_QB_MM_ENC : POOL32A_3R_FMT<"addu.qb", 0b00011001101>; 24class ADDU_S_QB_MM_ENC : POOL32A_3R_FMT<"addu_s.qb", 0b10011001101>; 25class ADDUH_QB_MMR2_ENC : POOL32A_3R_FMT<"adduh.qb", 0b00101001101>; 26class ADDUH_R_QB_MMR2_ENC : POOL32A_3R_FMT<"adduh_r.qb", 0b10101001101>; 27class ADDSC_MM_ENC : POOL32A_3RB0_FMT<"addsc", 0b1110000101>; 28class ADDWC_MM_ENC : POOL32A_3RB0_FMT<"addwc", 0b1111000101>; 29class DPA_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpa.w.ph", 0b00000010>; 30class DPAQ_S_W_PH_MM_ENC : POOL32A_2RAC_FMT<"dpaq_s.w.ph", 0b00001010>; 31class DPAQ_SA_L_W_MM_ENC : POOL32A_2RAC_FMT<"dpaq_sa.l.w", 0b01001010>; 32class DPAQX_S_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpaqx_s.w.ph", 0b10001010>; 33class DPAQX_SA_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpaqx_sa.w.ph", 0b11001010>; 34class DPAU_H_QBL_MM_ENC : POOL32A_2RAC_FMT<"dpau.h.qbl", 0b10000010>; 35class DPAU_H_QBR_MM_ENC : POOL32A_2RAC_FMT<"dpau.h.qbr", 0b11000010>; 36class DPAX_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpax.w.ph", 0b01000010>; 37class ABSQ_S_PH_MM_ENC : POOL32A_2R_FMT<"absq_s.ph", 0b0001000100>; 38class ABSQ_S_W_MM_ENC : POOL32A_2R_FMT<"absq_s.w", 0b0010000100>; 39class ABSQ_S_QB_MMR2_ENC : POOL32A_2R_FMT<"absq_s.qb", 0b0000000100>; 40class INSV_MM_ENC : POOL32A_2R_FMT<"insv", 0b0100000100>; 41class MADD_DSP_MM_ENC : POOL32A_2RAC_FMT<"madd", 0b00101010>; 42class MADDU_DSP_MM_ENC : POOL32A_2RAC_FMT<"maddu", 0b01101010>; 43class MSUB_DSP_MM_ENC : POOL32A_2RAC_FMT<"msub", 0b10101010>; 44class MSUBU_DSP_MM_ENC : POOL32A_2RAC_FMT<"msubu", 0b11101010>; 45class MULT_DSP_MM_ENC : POOL32A_2RAC_FMT<"mult", 0b00110010>; 46class MULTU_DSP_MM_ENC : POOL32A_2RAC_FMT<"multu", 0b01110010>; 47class SHLL_PH_MM_ENC : POOL32A_2RSA4_FMT<"shll.ph", 0b001110110101>; 48class SHLL_S_PH_MM_ENC : POOL32A_2RSA4_FMT<"shll_s.ph", 0b101110110101>; 49class SHLL_QB_MM_ENC : POOL32A_2RSA3_FMT<"shll.qb", 0b0100001>; 50class SHLLV_PH_MM_ENC : POOL32A_3R_FMT<"shllv.ph", 0b00000001110>; 51class SHLLV_S_PH_MM_ENC : POOL32A_3R_FMT<"shllv_s.ph", 0b10000001110>; 52class SHLLV_QB_MM_ENC : POOL32A_3RB0_FMT<"shllv.qb", 0b1110010101>; 53class SHLLV_S_W_MM_ENC : POOL32A_3RB0_FMT<"shllv_s.w", 0b1111010101>; 54class SHLL_S_W_MM_ENC : POOL32A_2RSA5B0_FMT<"shll_s.w", 0b1111110101>; 55class SHRA_QB_MMR2_ENC : POOL32A_2RSA3_FMT<"shra.qb", 0b0000111>; 56class SHRA_R_QB_MMR2_ENC : POOL32A_2RSA3_FMT<"shra_r.qb", 0b1000111>; 57class SHRA_PH_MM_ENC : POOL32A_2RSA4B0_FMT<"shra.ph", 0b01100110101>; 58class SHRA_R_PH_MM_ENC : POOL32A_2RSA4B0_FMT<"shra_r.ph", 0b11100110101>; 59class SHRAV_PH_MM_ENC : POOL32A_3R_FMT<"shrav.ph", 0b00110001101>; 60class SHRAV_R_PH_MM_ENC : POOL32A_3R_FMT<"shrav_r.ph", 0b10110001101>; 61class SHRAV_QB_MMR2_ENC : POOL32A_3R_FMT<"shrav.qb", 0b00111001101>; 62class SHRAV_R_QB_MMR2_ENC : POOL32A_3R_FMT<"shrav_r.qb", 0b10111001101>; 63class SHRAV_R_W_MM_ENC : POOL32A_3RB0_FMT<"shrav_r.w", 0b1011010101>; 64class SHRA_R_W_MM_ENC : POOL32A_2RSA5B0_FMT<"shra_r.w", 0b1011110101>; 65class SHRL_PH_MMR2_ENC : POOL32A_2RSA4OP6_FMT<"shrl.ph", 0b001111>; 66class SHRL_QB_MM_ENC : POOL32A_2RSA3_FMT<"shrl.qb", 0b1100001>; 67class SHRLV_PH_MMR2_ENC : POOL32A_3RB0_FMT<"shrlv.ph", 0b1100010101>; 68class SHRLV_QB_MM_ENC : POOL32A_3RB0_FMT<"shrlv.qb", 0b1101010101>; 69class PRECEQ_W_PHL_MM_ENC : POOL32A_2R_FMT<"preceq.w.phl", 0b0101000100>; 70class PRECEQ_W_PHR_MM_ENC : POOL32A_2R_FMT<"preceq.w.phr", 0b0110000100>; 71class PRECEQU_PH_QBL_MM_ENC : POOL32A_2R_FMT<"precequ.ph.qbl", 0b0111000100>; 72class PRECEQU_PH_QBLA_MM_ENC : POOL32A_2R_FMT<"precequ.ph.qbla", 0b0111001100>; 73class PRECEQU_PH_QBR_MM_ENC : POOL32A_2R_FMT<"precequ.ph.qbr", 0b1001000100>; 74class PRECEQU_PH_QBRA_MM_ENC : POOL32A_2R_FMT<"precequ.ph.qbra", 0b1001001100>; 75class PRECEU_PH_QBL_MM_ENC : POOL32A_2R_FMT<"preceu.ph.qbl", 0b1011000100>; 76class PRECEU_PH_QBLA_MM_ENC : POOL32A_2R_FMT<"preceu.ph.qbla", 0b1011001100>; 77class PRECEU_PH_QBR_MM_ENC : POOL32A_2R_FMT<"preceu.ph.qbr", 0b1101000100>; 78class PRECEU_PH_QBRA_MM_ENC : POOL32A_2R_FMT<"preceu.ph.qbra", 0b1101001100>; 79class SUBQ_PH_MM_ENC : POOL32A_3R_FMT<"subq.ph", 0b01000001101>; 80class SUBQ_S_PH_MM_ENC : POOL32A_3R_FMT<"subq_s.ph", 0b11000001101>; 81class SUBQ_S_W_MM_ENC : POOL32A_3RB0_FMT<"subq_s.w", 0b1101000101>; 82class SUBQH_PH_MMR2_ENC : POOL32A_3R_FMT<"subqh.ph", 0b01001001101>; 83class SUBQH_R_PH_MMR2_ENC : POOL32A_3R_FMT<"subqh_r.ph", 0b11001001101>; 84class SUBQH_W_MMR2_ENC : POOL32A_3R_FMT<"subqh.w", 0b01010001101>; 85class SUBQH_R_W_MMR2_ENC : POOL32A_3R_FMT<"subqh_r.w", 0b11010001101>; 86class SUBU_PH_MMR2_ENC : POOL32A_3R_FMT<"subu.ph", 0b01100001101>; 87class SUBU_S_PH_MMR2_ENC : POOL32A_3R_FMT<"subu_s.ph", 0b11100001101>; 88class SUBU_QB_MM_ENC : POOL32A_3R_FMT<"subu.qb", 0b01011001101>; 89class SUBU_S_QB_MM_ENC : POOL32A_3R_FMT<"subu_s.qb", 0b11011001101>; 90class SUBUH_QB_MMR2_ENC : POOL32A_3R_FMT<"subuh.qb", 0b01101001101>; 91class SUBUH_R_QB_MMR2_ENC : POOL32A_3R_FMT<"subuh_r.qb", 0b11101001101>; 92class EXTP_MM_ENC : POOL32A_1RIMM5AC_FMT<"extp", 0b10011001>; 93class EXTPDP_MM_ENC : POOL32A_1RIMM5AC_FMT<"extpdp", 0b11011001>; 94class EXTPDPV_MM_ENC : POOL32A_2RAC_FMT<"extpdpv", 0b11100010>; 95class EXTPV_MM_ENC : POOL32A_2RAC_FMT<"extpv", 0b10100010>; 96class EXTR_W_MM_ENC : POOL32A_1RIMM5AC_FMT<"extr.w", 0b00111001>; 97class EXTR_R_W_MM_ENC : POOL32A_1RIMM5AC_FMT<"extr_r.w", 0b01111001>; 98class EXTR_RS_W_MM_ENC : POOL32A_1RIMM5AC_FMT<"extr_rs.w", 0b10111001>; 99class EXTR_S_H_MM_ENC : POOL32A_1RIMM5AC_FMT<"extr_s.h", 0b11111001>; 100class EXTRV_W_MM_ENC : POOL32A_2RAC_FMT<"extrv.w", 0b00111010>; 101class EXTRV_R_W_MM_ENC : POOL32A_2RAC_FMT<"extrv_r.w", 0b01111010>; 102class EXTRV_RS_W_MM_ENC : POOL32A_2RAC_FMT<"extrv_rs.w", 0b10111010>; 103class EXTRV_S_H_MM_ENC : POOL32A_2RAC_FMT<"extrv_s.h", 0b11111010>; 104class DPS_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dps.w.ph", 0b00010010>; 105class DPSQ_S_W_PH_MM_ENC : POOL32A_2RAC_FMT<"dpsq_s.w.ph", 0b00011010>; 106class DPSQ_SA_L_W_MM_ENC : POOL32A_2RAC_FMT<"dpsq_sa.l.w", 0b01011010>; 107class DPSQX_S_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpsqx_s.w.ph", 0b10011010>; 108class DPSQX_SA_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpsqx_sa.w.ph", 0b11011010>; 109class DPSU_H_QBL_MM_ENC : POOL32A_2RAC_FMT<"dpsu.h.qbl", 0b10010010>; 110class DPSU_H_QBR_MM_ENC : POOL32A_2RAC_FMT<"dpsu.h.qbr", 0b11010010>; 111class DPSX_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpsx.w.ph", 0b01010010>; 112class MUL_PH_MMR2_ENC : POOL32A_3R_FMT<"mul.ph", 0b00000101101>; 113class MUL_S_PH_MMR2_ENC : POOL32A_3R_FMT<"mul_s.ph", 0b10000101101>; 114class MULEQ_S_W_PHL_MM_ENC : POOL32A_3RB0_FMT<"muleq_s.w.phl", 0b0000100101>; 115class MULEQ_S_W_PHR_MM_ENC : POOL32A_3RB0_FMT<"muleq_s.w.phr", 0b0001100101>; 116class MULEU_S_PH_QBL_MM_ENC : POOL32A_3RB0_FMT<"muleu_s.ph.qbl", 0b0010010101>; 117class MULEU_S_PH_QBR_MM_ENC : POOL32A_3RB0_FMT<"muleu_s.ph.qbr", 0b0011010101>; 118class MULQ_RS_PH_MM_ENC : POOL32A_3RB0_FMT<"mulq_rs.ph", 0b0100010101>; 119class MULQ_RS_W_MMR2_ENC : POOL32A_3RB0_FMT<"mulq_rs.w", 0b0110010101>; 120class MULQ_S_PH_MMR2_ENC : POOL32A_3RB0_FMT<"mulq_s.ph", 0b0101010101>; 121class MULQ_S_W_MMR2_ENC : POOL32A_3RB0_FMT<"mulq_s.w", 0b0111010101>; 122class PRECR_QB_PH_MMR2_ENC : POOL32A_3RB0_FMT<"precr.qb.ph", 0b0001101101>; 123class PRECR_SRA_PH_W_MMR2_ENC 124 : POOL32A_2RSA5_FMT<"precr_sra.ph.w", 0b01111001101>; 125class PRECR_SRA_R_PH_W_MMR2_ENC 126 : POOL32A_2RSA5_FMT<"precr_sra_r.ph.w", 0b11111001101>; 127class PRECRQ_PH_W_MM_ENC : POOL32A_3RB0_FMT<"precrq.ph.w", 0b0011101101>; 128class PRECRQ_QB_PH_MM_ENC : POOL32A_3RB0_FMT<"precrq.qb.ph", 0b0010101101>; 129class PRECRQU_S_QB_PH_MM_ENC 130 : POOL32A_3RB0_FMT<"precrqu_s.qb.ph", 0b0101101101>; 131class PRECRQ_RS_PH_W_MM_ENC : POOL32A_3RB0_FMT<"precrq_rs.ph.w", 0b0100101101>; 132class LBUX_MM_ENC : POOL32A_1RMEMB0_FMT<"lbux", 0b1000100101>; 133class LHX_MM_ENC : POOL32A_1RMEMB0_FMT<"lhx", 0b0101100101>; 134class LWX_MM_ENC : POOL32A_1RMEMB0_FMT<"lwx", 0b0110100101>; 135class MAQ_S_W_PHL_MM_ENC : POOL32A_2RAC_FMT<"maq_s.w.phl", 0b01101001>; 136class MAQ_SA_W_PHL_MM_ENC : POOL32A_2RAC_FMT<"maq_sa.w.phl", 0b11101001>; 137class MAQ_S_W_PHR_MM_ENC : POOL32A_2RAC_FMT<"maq_s.w.phr", 0b00101001>; 138class MAQ_SA_W_PHR_MM_ENC : POOL32A_2RAC_FMT<"maq_sa.w.phr", 0b10101001>; 139class MFHI_MM_ENC : POOL32A_1RAC_FMT<"mfhi", 0b00000001>; 140class MFLO_MM_ENC : POOL32A_1RAC_FMT<"mflo", 0b01000001>; 141class MTHI_MM_ENC : POOL32A_1RAC_FMT<"mthi", 0b10000001>; 142class MTLO_MM_ENC : POOL32A_1RAC_FMT<"mthi", 0b11000001>; 143class PREPEND_MMR2_ENC : POOL32A_2RSA5B0_FMT<"prepend", 0b1001010101>; 144class RADDU_W_QB_MM_ENC : POOL32A_2R_FMT<"raddu.w.qb", 0b1111000100>; 145class RDDSP_MM_ENC : POOL32A_1RMASK7_FMT<"rddsp", 0b00011001>; 146class REPL_PH_MM_ENC : POOL32A_1RIMM10_FMT<"repl.ph", 0b0000111101>; 147class REPL_QB_MM_ENC : POOL32A_1RIMM8_FMT<"repl.qb", 0b010111>; 148class REPLV_PH_MM_ENC : POOL32A_2R_FMT<"replv.ph", 0b0000001100>; 149class REPLV_QB_MM_ENC : POOL32A_2R_FMT<"replv.qb", 0b0001001100>; 150class MTHLIP_MM_ENC : POOL32A_1RAC_FMT<"mthlip", 0b00001001>; 151class PACKRL_PH_MM_ENC : POOL32A_3RB0_FMT<"packrl.ph", 0b0110101101>; 152class PICK_PH_MM_ENC : POOL32A_3RB0_FMT<"pick.ph", 0b1000101101>; 153class PICK_QB_MM_ENC : POOL32A_3RB0_FMT<"pick.qb", 0b0111101101>; 154class SHILO_MM_ENC : POOL32A_4B0SHIFT6AC4B0_FMT<"shilo", 0b0000011101>; 155class SHILOV_MM_ENC : POOL32A_5B01RAC_FMT<"shilov", 0b01001001>; 156class WRDSP_MM_ENC : POOL32A_1RMASK7_FMT<"wrdsp", 0b01011001>; 157class APPEND_MMR2_ENC : POOL32A_2RSA5B0_FMT<"append", 0b1000010101>; 158class MODSUB_MM_ENC : POOL32A_3RB0_FMT<"modsub", 0b1010010101>; 159class MULSA_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"mulsa.w.ph", 0b10110010>; 160class MULSAQ_S_W_PH_MM_ENC : POOL32A_2RAC_FMT<"mulsaq_s.w.ph", 0b11110010>; 161class BPOSGE32C_MMR3_ENC : POOL32I_IMMB0_FMT<"bposge32c", 0b11001>; 162class BITREV_MM_ENC : POOL32A_2R_FMT<"bitrev", 0b0011000100>; 163class BALIGN_MMR2_ENC : POOL32A_2RBP_FMT<"balign">; 164class BPOSGE32_MM_ENC : POOL32I_IMMB0_FMT<"bposge32", 0b11011>; 165class CMP_EQ_PH_MM_ENC : POOL32A_2RB0_FMT<"cmp.eq.ph", 0b0000000101>; 166class CMP_LE_PH_MM_ENC : POOL32A_2RB0_FMT<"cmp.le.ph", 0b0010000101>; 167class CMP_LT_PH_MM_ENC : POOL32A_2RB0_FMT<"cmp.lt.ph", 0b0001000101>; 168class CMPGDU_EQ_QB_MMR2_ENC : POOL32A_3RB0_FMT<"cmpgdu.eq.qb", 0b0110000101>; 169class CMPGDU_LT_QB_MMR2_ENC : POOL32A_3RB0_FMT<"cmpgdu.lt.qb", 0b0111000101>; 170class CMPGDU_LE_QB_MMR2_ENC : POOL32A_3RB0_FMT<"cmpgdu.le.qb", 0b1000000101>; 171class CMPGU_EQ_QB_MM_ENC : POOL32S_3RB0_FMT<"cmpgu.eq.qb", 0b0011000101>; 172class CMPGU_LT_QB_MM_ENC : POOL32S_3RB0_FMT<"cmpgu.lt.qb", 0b0100000101>; 173class CMPGU_LE_QB_MM_ENC : POOL32S_3RB0_FMT<"cmpgu.le.qb", 0b0101000101>; 174class CMPU_EQ_QB_MM_ENC : POOL32A_2R2B0_FMT<"cmpu.eq.qb", 0b1001000101>; 175class CMPU_LT_QB_MM_ENC : POOL32A_2R2B0_FMT<"cmpu.lt.qb", 0b1010000101>; 176class CMPU_LE_QB_MM_ENC : POOL32A_2R2B0_FMT<"cmpu.le.qb", 0b1011000101>; 177 178// Instruction desc. 179class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode, 180 InstrItinClass itin, RegisterOperand ROD, 181 RegisterOperand ROS = ROD> { 182 dag OutOperandList = (outs ROD:$rt); 183 dag InOperandList = (ins ROS:$rs); 184 string AsmString = !strconcat(opstr, "\t$rt, $rs"); 185 list<dag> Pattern = [(set ROD:$rt, (OpNode ROS:$rs))]; 186 InstrItinClass Itinerary = itin; 187} 188class ABSQ_S_PH_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< 189 "absq_s.ph", int_mips_absq_s_ph, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>; 190class ABSQ_S_W_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< 191 "absq_s.w", int_mips_absq_s_w, NoItinerary, GPR32Opnd>, Defs<[DSPOutFlag20]>; 192class ABSQ_S_QB_MMR2_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< 193 "absq_s.qb", int_mips_absq_s_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>; 194class PRECEQ_W_PHL_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< 195 "preceq.w.phl", int_mips_preceq_w_phl, NoItinerary, GPR32Opnd, DSPROpnd>; 196class PRECEQ_W_PHR_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< 197 "preceq.w.phr", int_mips_preceq_w_phr, NoItinerary, GPR32Opnd, DSPROpnd>; 198class PRECEQU_PH_QBL_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< 199 "precequ.ph.qbl", int_mips_precequ_ph_qbl, NoItinerary, DSPROpnd>; 200class PRECEQU_PH_QBLA_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< 201 "precequ.ph.qbla", int_mips_precequ_ph_qbla, NoItinerary, DSPROpnd>; 202class PRECEQU_PH_QBR_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< 203 "precequ.ph.qbr", int_mips_precequ_ph_qbr, NoItinerary, DSPROpnd>; 204class PRECEQU_PH_QBRA_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< 205 "precequ.ph.qbra", int_mips_precequ_ph_qbra, NoItinerary, DSPROpnd>; 206class PRECEU_PH_QBL_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< 207 "preceu.ph.qbl", int_mips_preceu_ph_qbl, NoItinerary, DSPROpnd>; 208class PRECEU_PH_QBLA_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< 209 "preceu.ph.qbla", int_mips_preceu_ph_qbla, NoItinerary, DSPROpnd>; 210class PRECEU_PH_QBR_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< 211 "preceu.ph.qbr", int_mips_preceu_ph_qbr, NoItinerary, DSPROpnd>; 212class PRECEU_PH_QBRA_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< 213 "preceu.ph.qbra", int_mips_preceu_ph_qbra, NoItinerary, DSPROpnd>; 214 215class SHLL_R2_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 216 SDPatternOperator ImmPat, InstrItinClass itin, 217 RegisterOperand RO, Operand ImmOpnd> { 218 dag OutOperandList = (outs RO:$rt); 219 dag InOperandList = (ins RO:$rs, ImmOpnd:$sa); 220 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa"); 221 list<dag> Pattern = [(set RO:$rt, (OpNode RO:$rs, ImmPat:$sa))]; 222 InstrItinClass Itinerary = itin; 223 bit hasSideEffects = 1; 224} 225class SHLL_PH_MM_DESC : SHLL_R2_MM_DESC_BASE< 226 "shll.ph", null_frag, immZExt4, NoItinerary, DSPROpnd, uimm4>, 227 Defs<[DSPOutFlag22]>; 228class SHLL_S_PH_MM_DESC : SHLL_R2_MM_DESC_BASE< 229 "shll_s.ph", int_mips_shll_s_ph, immZExt4, NoItinerary, DSPROpnd, uimm4>, 230 Defs<[DSPOutFlag22]>; 231class SHLL_QB_MM_DESC : SHLL_R2_MM_DESC_BASE< 232 "shll.qb", null_frag, immZExt3, NoItinerary, DSPROpnd, uimm3>, 233 Defs<[DSPOutFlag22]>; 234class SHLL_S_W_MM_DESC : SHLL_R2_MM_DESC_BASE< 235 "shll_s.w", int_mips_shll_s_w, immZExt5, NoItinerary, GPR32Opnd, uimm5>, 236 Defs<[DSPOutFlag22]>; 237class SHRA_QB_MMR2_DESC : SHLL_R2_MM_DESC_BASE< 238 "shra.qb", null_frag, immZExt3, NoItinerary, DSPROpnd, uimm3>; 239class SHRA_R_QB_MMR2_DESC : SHLL_R2_MM_DESC_BASE< 240 "shra_r.qb", int_mips_shra_r_qb, immZExt3, NoItinerary, DSPROpnd, uimm3>; 241class SHRA_PH_MM_DESC : SHLL_R2_MM_DESC_BASE< 242 "shra.ph", null_frag, immZExt4, NoItinerary, DSPROpnd, uimm4>; 243class SHRA_R_PH_MM_DESC : SHLL_R2_MM_DESC_BASE< 244 "shra_r.ph", int_mips_shra_r_ph, immZExt4, NoItinerary, DSPROpnd, uimm4>; 245class SHRA_R_W_MM_DESC : SHLL_R2_MM_DESC_BASE< 246 "shra_r.w", int_mips_shra_r_w, immZExt5, NoItinerary, GPR32Opnd, uimm5>; 247class SHRL_QB_MM_DESC : SHLL_R2_MM_DESC_BASE< 248 "shrl.qb", null_frag, immZExt3, NoItinerary, DSPROpnd, uimm3>; 249class SHRL_PH_MMR2_DESC : SHLL_R2_MM_DESC_BASE< 250 "shrl.ph", null_frag, immZExt4, NoItinerary, DSPROpnd, uimm4>; 251 252class SHLLV_R3_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 253 InstrItinClass itin, RegisterOperand RO> { 254 dag OutOperandList = (outs RO:$rd); 255 dag InOperandList = (ins RO:$rt, GPR32Opnd:$rs); 256 string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs"); 257 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))]; 258 InstrItinClass Itinerary = itin; 259} 260class SHLLV_PH_MM_DESC : SHLLV_R3_MM_DESC_BASE< 261 "shllv.ph", int_mips_shll_ph, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag22]>; 262class SHLLV_S_PH_MM_DESC : SHLLV_R3_MM_DESC_BASE< 263 "shllv_s.ph", int_mips_shll_s_ph, NoItinerary, DSPROpnd>, 264 Defs<[DSPOutFlag22]>; 265class SHLLV_QB_MM_DESC : SHLLV_R3_MM_DESC_BASE< 266 "shllv.qb", int_mips_shll_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag22]>; 267class SHLLV_S_W_MM_DESC : SHLLV_R3_MM_DESC_BASE< 268 "shllv_s.w", int_mips_shll_s_w, NoItinerary, GPR32Opnd>, Defs<[DSPOutFlag22]>; 269class SHRAV_PH_MM_DESC : SHLLV_R3_MM_DESC_BASE< 270 "shrav.ph", int_mips_shra_ph, NoItinerary, DSPROpnd>; 271class SHRAV_R_PH_MM_DESC : SHLLV_R3_MM_DESC_BASE< 272 "shrav_r.ph", int_mips_shra_r_ph, NoItinerary, DSPROpnd>; 273class SHRAV_QB_MMR2_DESC : SHLLV_R3_MM_DESC_BASE< 274 "shrav.qb", int_mips_shra_qb, NoItinerary, DSPROpnd>; 275class SHRAV_R_QB_MMR2_DESC : SHLLV_R3_MM_DESC_BASE< 276 "shrav_r.qb", int_mips_shra_r_qb, NoItinerary, DSPROpnd>; 277class SHRAV_R_W_MM_DESC : SHLLV_R3_MM_DESC_BASE< 278 "shrav_r.w", int_mips_shra_r_w, NoItinerary, GPR32Opnd>; 279class SHRLV_PH_MMR2_DESC : SHLLV_R3_MM_DESC_BASE< 280 "shrlv.ph", int_mips_shrl_ph, NoItinerary, DSPROpnd>; 281class SHRLV_QB_MM_DESC : SHLLV_R3_MM_DESC_BASE< 282 "shrlv.qb", int_mips_shrl_qb, NoItinerary, DSPROpnd>; 283 284class EXT_MM_2R_DESC_BASE<string instr_asm> { 285 dag OutOperandList = (outs GPR32Opnd:$rt); 286 dag InOperandList = (ins ACC64DSPOpnd:$ac, GPR32Opnd:$rs); 287 string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $rs"); 288 InstrItinClass Itinerary = NoItinerary; 289} 290class EXT_MM_1R_DESC_BASE<string instr_asm> { 291 dag OutOperandList = (outs GPR32Opnd:$rt); 292 dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm5:$imm); 293 string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $imm"); 294 InstrItinClass Itinerary = NoItinerary; 295} 296 297class EXTP_MM_DESC : EXT_MM_1R_DESC_BASE<"extp">, 298 Uses<[DSPPos]>, 299 Defs<[DSPEFI]>; 300class EXTPDP_MM_DESC : EXT_MM_1R_DESC_BASE<"extpdp">, 301 Uses<[DSPPos]>, 302 Defs<[DSPPos, DSPEFI]>; 303class EXTPDPV_MM_DESC : EXT_MM_2R_DESC_BASE<"extpdpv">, 304 Uses<[DSPPos]>, 305 Defs<[DSPPos, DSPEFI]>; 306class EXTPV_MM_DESC : EXT_MM_2R_DESC_BASE<"extpv">, 307 Uses<[DSPPos]>, 308 Defs<[DSPEFI]>; 309class EXTR_W_MM_DESC : EXT_MM_1R_DESC_BASE<"extr.w">, 310 Defs<[DSPOutFlag23]>; 311class EXTR_R_W_MM_DESC : EXT_MM_1R_DESC_BASE<"extr_r.w">, 312 Defs<[DSPOutFlag23]>; 313class EXTR_RS_W_MM_DESC : EXT_MM_1R_DESC_BASE<"extr_rs.w">, 314 Defs<[DSPOutFlag23]>; 315class EXTR_S_H_MM_DESC : EXT_MM_1R_DESC_BASE<"extr_s.h">, 316 Defs<[DSPOutFlag23]>; 317class EXTRV_W_MM_DESC : EXT_MM_2R_DESC_BASE<"extrv.w">, Defs<[DSPOutFlag23]>; 318class EXTRV_R_W_MM_DESC : EXT_MM_2R_DESC_BASE<"extrv_r.w">, 319 Defs<[DSPOutFlag23]>; 320class EXTRV_RS_W_MM_DESC : EXT_MM_2R_DESC_BASE<"extrv_rs.w">, 321 Defs<[DSPOutFlag23]>; 322class EXTRV_S_H_MM_DESC : EXT_MM_2R_DESC_BASE<"extrv_s.h">, 323 Defs<[DSPOutFlag23]>; 324 325class MFHI_MM_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode, 326 InstrItinClass itin> { 327 dag OutOperandList = (outs GPR32Opnd:$rs); 328 dag InOperandList = (ins RO:$ac); 329 string AsmString = !strconcat(instr_asm, "\t$rs, $ac"); 330 list<dag> Pattern = [(set GPR32Opnd:$rs, (OpNode RO:$ac))]; 331 InstrItinClass Itinerary = itin; 332} 333 334class MFHI_MM_DESC : MFHI_MM_DESC_BASE<"mfhi", ACC64DSPOpnd, MipsMFHI, 335 NoItinerary>; 336class MFLO_MM_DESC : MFHI_MM_DESC_BASE<"mflo", ACC64DSPOpnd, MipsMFLO, 337 NoItinerary>; 338 339class RADDU_W_QB_MM_DESC { 340 dag OutOperandList = (outs GPR32Opnd:$rt); 341 dag InOperandList = (ins DSPROpnd:$rs); 342 string AsmString = !strconcat("raddu.w.qb", "\t$rt, $rs"); 343 list<dag> Pattern = [(set GPR32Opnd:$rt, (int_mips_raddu_w_qb DSPROpnd:$rs))]; 344 InstrItinClass Itinerary = NoItinerary; 345 string BaseOpcode = "raddu.w.qb"; 346} 347 348class RDDSP_MM_DESC { 349 dag OutOperandList = (outs GPR32Opnd:$rt); 350 dag InOperandList = (ins uimm7:$mask); 351 string AsmString = !strconcat("rddsp", "\t$rt, $mask"); 352 list<dag> Pattern = [(set GPR32Opnd:$rt, (int_mips_rddsp timmZExt7:$mask))]; 353 InstrItinClass Itinerary = NoItinerary; 354} 355 356class REPL_QB_MM_DESC { 357 dag OutOperandList = (outs DSPROpnd:$rt); 358 dag InOperandList = (ins uimm8:$imm); 359 string AsmString = !strconcat("repl.qb", "\t$rt, $imm"); 360 list<dag> Pattern = [(set DSPROpnd:$rt, (int_mips_repl_qb immZExt8:$imm))]; 361 InstrItinClass Itinerary = NoItinerary; 362} 363 364class REPLV_PH_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<"replv.ph", int_mips_repl_ph, 365 NoItinerary, DSPROpnd, 366 GPR32Opnd>; 367class REPLV_QB_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<"replv.qb", int_mips_repl_qb, 368 NoItinerary, DSPROpnd, 369 GPR32Opnd>; 370 371class WRDSP_MM_DESC { 372 dag OutOperandList = (outs); 373 dag InOperandList = (ins GPR32Opnd:$rt, uimm7:$mask); 374 string AsmString = !strconcat("wrdsp", "\t$rt, $mask"); 375 list<dag> Pattern = [(int_mips_wrdsp GPR32Opnd:$rt, timmZExt7:$mask)]; 376 InstrItinClass Itinerary = NoItinerary; 377} 378 379class BPOSGE32C_MMR3_DESC { 380 dag OutOperandList = (outs); 381 dag InOperandList = (ins brtarget1SImm16:$offset); 382 string AsmString = !strconcat("bposge32c", "\t$offset"); 383 InstrItinClass Itinerary = NoItinerary; 384 bit isBranch = 1; 385 bit isTerminator = 1; 386 bit hasDelaySlot = 0; 387} 388 389class BALIGN_MMR2_DESC { 390 dag OutOperandList = (outs GPR32Opnd:$rt); 391 dag InOperandList = (ins GPR32Opnd:$rs, uimm2:$bp, GPR32Opnd:$src); 392 string AsmString = !strconcat("balign", "\t$rt, $rs, $bp"); 393 list<dag> Pattern = [(set GPR32Opnd:$rt, (int_mips_balign GPR32Opnd:$src, 394 GPR32Opnd:$rs, 395 immZExt2:$bp))]; 396 InstrItinClass Itinerary = NoItinerary; 397 string Constraints = "$src = $rt"; 398} 399 400class BITREV_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<"bitrev", int_mips_bitrev, 401 NoItinerary, GPR32Opnd>; 402 403class BPOSGE32_MM_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget_mm, 404 NoItinerary>; 405 406let DecoderNamespace = "MicroMipsDSP", Arch = "mmdsp", 407 EncodingPredicates = [InMicroMips], ASEPredicate = [HasDSP] in { 408 def LWDSP_MM : Load<"lw", DSPROpnd, null_frag, II_LW>, DspMMRel, 409 LW_FM_MM<0x3f>; 410 def SWDSP_MM : Store<"sw", DSPROpnd, null_frag, II_SW>, DspMMRel, 411 LW_FM_MM<0x3e>; 412} 413// Instruction defs. 414// microMIPS DSP Rev 1 415def ADDQ_PH_MM : DspMMRel, ADDQ_PH_MM_ENC, ADDQ_PH_DESC; 416def ADDQ_S_PH_MM : DspMMRel, ADDQ_S_PH_MM_ENC, ADDQ_S_PH_DESC; 417def ADDQ_S_W_MM : DspMMRel, ADDQ_S_W_MM_ENC, ADDQ_S_W_DESC; 418def ADDU_QB_MM : DspMMRel, ADDU_QB_MM_ENC, ADDU_QB_DESC; 419def ADDU_S_QB_MM : DspMMRel, ADDU_S_QB_MM_ENC, ADDU_S_QB_DESC; 420def ADDSC_MM : DspMMRel, ADDSC_MM_ENC, ADDSC_DESC; 421def ADDWC_MM : DspMMRel, ADDWC_MM_ENC, ADDWC_DESC; 422def DPAQ_S_W_PH_MM : DspMMRel, DPAQ_S_W_PH_MM_ENC, DPAQ_S_W_PH_DESC; 423def DPAQ_SA_L_W_MM : DspMMRel, DPAQ_SA_L_W_MM_ENC, DPAQ_SA_L_W_DESC; 424def DPAU_H_QBL_MM : DspMMRel, DPAU_H_QBL_MM_ENC, DPAU_H_QBL_DESC; 425def DPAU_H_QBR_MM : DspMMRel, DPAU_H_QBR_MM_ENC, DPAU_H_QBR_DESC; 426def ABSQ_S_PH_MM : DspMMRel, ABSQ_S_PH_MM_ENC, ABSQ_S_PH_MM_DESC; 427def ABSQ_S_W_MM : DspMMRel, ABSQ_S_W_MM_ENC, ABSQ_S_W_MM_DESC; 428def INSV_MM : DspMMRel, INSV_MM_ENC, INSV_DESC; 429def MADD_DSP_MM : DspMMRel, MADD_DSP_MM_ENC, MADD_DSP_DESC; 430def MADDU_DSP_MM : DspMMRel, MADDU_DSP_MM_ENC, MADDU_DSP_DESC; 431def MSUB_DSP_MM : DspMMRel, MSUB_DSP_MM_ENC, MSUB_DSP_DESC; 432def MSUBU_DSP_MM : DspMMRel, MSUBU_DSP_MM_ENC, MSUBU_DSP_DESC; 433def MULT_DSP_MM : DspMMRel, MULT_DSP_MM_ENC, MULT_DSP_DESC; 434def MULTU_DSP_MM : DspMMRel, MULTU_DSP_MM_ENC, MULTU_DSP_DESC; 435def SHLL_PH_MM : DspMMRel, SHLL_PH_MM_ENC, SHLL_PH_MM_DESC; 436def SHLL_S_PH_MM : DspMMRel, SHLL_S_PH_MM_ENC, SHLL_S_PH_MM_DESC; 437def SHLL_QB_MM : DspMMRel, SHLL_QB_MM_ENC, SHLL_QB_MM_DESC; 438def SHLLV_PH_MM : DspMMRel, SHLLV_PH_MM_ENC, SHLLV_PH_MM_DESC; 439def SHLLV_S_PH_MM : DspMMRel, SHLLV_S_PH_MM_ENC, SHLLV_S_PH_MM_DESC; 440def SHLLV_QB_MM : DspMMRel, SHLLV_QB_MM_ENC, SHLLV_QB_MM_DESC; 441def SHLLV_S_W_MM : DspMMRel, SHLLV_S_W_MM_ENC, SHLLV_S_W_MM_DESC; 442def SHLL_S_W_MM : DspMMRel, SHLL_S_W_MM_ENC, SHLL_S_W_MM_DESC; 443def SHRA_PH_MM : DspMMRel, SHRA_PH_MM_ENC, SHRA_PH_MM_DESC; 444def SHRA_R_PH_MM : DspMMRel, SHRA_R_PH_MM_ENC, SHRA_R_PH_MM_DESC; 445def SHRAV_PH_MM : DspMMRel, SHRAV_PH_MM_ENC, SHRAV_PH_MM_DESC; 446def SHRAV_R_PH_MM : DspMMRel, SHRAV_R_PH_MM_ENC, SHRAV_R_PH_MM_DESC; 447def SHRAV_R_W_MM : DspMMRel, SHRAV_R_W_MM_ENC, SHRAV_R_W_MM_DESC; 448def SHRA_R_W_MM : DspMMRel, SHRA_R_W_MM_ENC, SHRA_R_W_MM_DESC; 449def SHRL_QB_MM : DspMMRel, SHRL_QB_MM_ENC, SHRL_QB_MM_DESC; 450def SHRLV_QB_MM : DspMMRel, SHRLV_QB_MM_ENC, SHRLV_QB_MM_DESC; 451def PRECEQ_W_PHL_MM : DspMMRel, PRECEQ_W_PHL_MM_ENC, PRECEQ_W_PHL_MM_DESC; 452def PRECEQ_W_PHR_MM : DspMMRel, PRECEQ_W_PHR_MM_ENC, PRECEQ_W_PHR_MM_DESC; 453def PRECEQU_PH_QBL_MM : DspMMRel, PRECEQU_PH_QBL_MM_ENC, PRECEQU_PH_QBL_MM_DESC; 454def PRECEQU_PH_QBLA_MM : DspMMRel, PRECEQU_PH_QBLA_MM_ENC, 455 PRECEQU_PH_QBLA_MM_DESC; 456def PRECEQU_PH_QBR_MM : DspMMRel, PRECEQU_PH_QBR_MM_ENC, PRECEQU_PH_QBR_MM_DESC; 457def PRECEQU_PH_QBRA_MM : DspMMRel, PRECEQU_PH_QBRA_MM_ENC, 458 PRECEQU_PH_QBRA_MM_DESC; 459def PRECEU_PH_QBL_MM : DspMMRel, PRECEU_PH_QBL_MM_ENC, PRECEU_PH_QBL_MM_DESC; 460def PRECEU_PH_QBLA_MM : DspMMRel, PRECEU_PH_QBLA_MM_ENC, PRECEU_PH_QBLA_MM_DESC; 461def PRECEU_PH_QBR_MM : DspMMRel, PRECEU_PH_QBR_MM_ENC, PRECEU_PH_QBR_MM_DESC; 462def PRECEU_PH_QBRA_MM : DspMMRel, PRECEU_PH_QBRA_MM_ENC, PRECEU_PH_QBRA_MM_DESC; 463def SUBQ_PH_MM : DspMMRel, SUBQ_PH_MM_ENC, SUBQ_PH_DESC; 464def SUBQ_S_PH_MM : DspMMRel, SUBQ_S_PH_MM_ENC, SUBQ_S_PH_DESC; 465def SUBQ_S_W_MM : DspMMRel, SUBQ_S_W_MM_ENC, SUBQ_S_W_DESC; 466def SUBU_QB_MM : DspMMRel, SUBU_QB_MM_ENC, SUBU_QB_DESC; 467def SUBU_S_QB_MM : DspMMRel, SUBU_S_QB_MM_ENC, SUBU_S_QB_DESC; 468def EXTP_MM : DspMMRel, EXTP_MM_ENC, EXTP_MM_DESC; 469def EXTPDP_MM : DspMMRel, EXTPDP_MM_ENC, EXTPDP_MM_DESC; 470def EXTPDPV_MM : DspMMRel, EXTPDPV_MM_ENC, EXTPDPV_MM_DESC; 471def EXTPV_MM : DspMMRel, EXTPV_MM_ENC, EXTPV_MM_DESC; 472def EXTR_W_MM : DspMMRel, EXTR_W_MM_ENC, EXTR_W_MM_DESC; 473def EXTR_R_W_MM : DspMMRel, EXTR_R_W_MM_ENC, EXTR_R_W_MM_DESC; 474def EXTR_RS_W_MM : DspMMRel, EXTR_RS_W_MM_ENC, EXTR_RS_W_MM_DESC; 475def EXTR_S_H_MM : DspMMRel, EXTR_S_H_MM_ENC, EXTR_S_H_MM_DESC; 476def EXTRV_W_MM : DspMMRel, EXTRV_W_MM_ENC, EXTRV_W_MM_DESC; 477def EXTRV_R_W_MM : DspMMRel, EXTRV_R_W_MM_ENC, EXTRV_R_W_MM_DESC; 478def EXTRV_RS_W_MM : DspMMRel, EXTRV_RS_W_MM_ENC, EXTRV_RS_W_MM_DESC; 479def EXTRV_S_H_MM : DspMMRel, EXTRV_S_H_MM_ENC, EXTRV_S_H_MM_DESC; 480def DPSQ_S_W_PH_MM : DspMMRel, DPSQ_S_W_PH_MM_ENC, DPSQ_S_W_PH_DESC; 481def DPSQ_SA_L_W_MM : DspMMRel, DPSQ_SA_L_W_MM_ENC, DPSQ_SA_L_W_DESC; 482def DPSU_H_QBL_MM : DspMMRel, DPSU_H_QBL_MM_ENC, DPSU_H_QBL_DESC; 483def DPSU_H_QBR_MM : DspMMRel, DPSU_H_QBR_MM_ENC, DPSU_H_QBR_DESC; 484def MULEQ_S_W_PHL_MM : DspMMRel, MULEQ_S_W_PHL_MM_ENC, MULEQ_S_W_PHL_DESC; 485def MULEQ_S_W_PHR_MM : DspMMRel, MULEQ_S_W_PHR_MM_ENC, MULEQ_S_W_PHR_DESC; 486def MULEU_S_PH_QBL_MM : DspMMRel, MULEU_S_PH_QBL_MM_ENC, MULEU_S_PH_QBL_DESC; 487def MULEU_S_PH_QBR_MM : DspMMRel, MULEU_S_PH_QBR_MM_ENC, MULEU_S_PH_QBR_DESC; 488def MULQ_RS_PH_MM : DspMMRel, MULQ_RS_PH_MM_ENC, MULQ_RS_PH_DESC; 489def PRECRQ_PH_W_MM : DspMMRel, PRECRQ_PH_W_MM_ENC, PRECRQ_PH_W_DESC; 490def PRECRQ_QB_PH_MM : DspMMRel, PRECRQ_QB_PH_MM_ENC, PRECRQ_QB_PH_DESC; 491def PRECRQU_S_QB_PH_MM : DspMMRel, PRECRQU_S_QB_PH_MM_ENC, PRECRQU_S_QB_PH_DESC; 492def PRECRQ_RS_PH_W_MM : DspMMRel, PRECRQ_RS_PH_W_MM_ENC, PRECRQ_RS_PH_W_DESC; 493def LBUX_MM : DspMMRel, LBUX_MM_ENC, LBUX_DESC; 494def LHX_MM : DspMMRel, LHX_MM_ENC, LHX_DESC; 495def LWX_MM : DspMMRel, LWX_MM_ENC, LWX_DESC; 496def MAQ_S_W_PHL_MM : DspMMRel, MAQ_S_W_PHL_MM_ENC, MAQ_S_W_PHL_DESC; 497def MAQ_SA_W_PHL_MM : DspMMRel, MAQ_SA_W_PHL_MM_ENC, MAQ_SA_W_PHL_DESC; 498def MAQ_S_W_PHR_MM : DspMMRel, MAQ_S_W_PHR_MM_ENC, MAQ_S_W_PHR_DESC; 499def MAQ_SA_W_PHR_MM : DspMMRel, MAQ_SA_W_PHR_MM_ENC, MAQ_SA_W_PHR_DESC; 500def MFHI_DSP_MM : DspMMRel, MFHI_MM_ENC, MFHI_MM_DESC; 501def MFLO_DSP_MM : DspMMRel, MFLO_MM_ENC, MFLO_MM_DESC; 502def MTHI_DSP_MM : DspMMRel, MTHI_MM_ENC, MTHI_DESC; 503def MTLO_DSP_MM : DspMMRel, MTLO_MM_ENC, MTLO_DESC; 504def RADDU_W_QB_MM : DspMMRel, RADDU_W_QB_MM_ENC, RADDU_W_QB_MM_DESC; 505def RDDSP_MM : DspMMRel, RDDSP_MM_ENC, RDDSP_MM_DESC; 506def REPL_PH_MM : DspMMRel, REPL_PH_MM_ENC, REPL_PH_DESC; 507def REPL_QB_MM : DspMMRel, REPL_QB_MM_ENC, REPL_QB_MM_DESC; 508def REPLV_PH_MM : DspMMRel, REPLV_PH_MM_ENC, REPLV_PH_MM_DESC; 509def REPLV_QB_MM : DspMMRel, REPLV_QB_MM_ENC, REPLV_QB_MM_DESC; 510def MTHLIP_MM : DspMMRel, MTHLIP_MM_ENC, MTHLIP_DESC; 511def PACKRL_PH_MM : DspMMRel, PACKRL_PH_MM_ENC, PACKRL_PH_DESC; 512def PICK_PH_MM : DspMMRel, PICK_PH_MM_ENC, PICK_PH_DESC; 513def PICK_QB_MM : DspMMRel, PICK_QB_MM_ENC, PICK_QB_DESC; 514def SHILO_MM : DspMMRel, SHILO_MM_ENC, SHILO_DESC; 515def SHILOV_MM : DspMMRel, SHILOV_MM_ENC, SHILOV_DESC; 516def WRDSP_MM : DspMMRel, WRDSP_MM_ENC, WRDSP_MM_DESC; 517def MODSUB_MM : DspMMRel, MODSUB_MM_ENC, MODSUB_DESC; 518def MULSAQ_S_W_PH_MM : DspMMRel, MULSAQ_S_W_PH_MM_ENC, MULSAQ_S_W_PH_DESC; 519def BITREV_MM : DspMMRel, BITREV_MM_ENC, BITREV_MM_DESC; 520def BPOSGE32_MM : DspMMRel, BPOSGE32_MM_ENC, BPOSGE32_MM_DESC, 521 ISA_MICROMIPS32_NOT_MIPS32R6; 522def CMP_EQ_PH_MM : DspMMRel, CMP_EQ_PH_MM_ENC, CMP_EQ_PH_DESC; 523def CMP_LT_PH_MM : DspMMRel, CMP_LT_PH_MM_ENC, CMP_LT_PH_DESC; 524def CMP_LE_PH_MM : DspMMRel, CMP_LE_PH_MM_ENC, CMP_LE_PH_DESC; 525def CMPGU_EQ_QB_MM : DspMMRel, CMPGU_EQ_QB_MM_ENC, CMPGU_EQ_QB_DESC; 526def CMPGU_LT_QB_MM : DspMMRel, CMPGU_LT_QB_MM_ENC, CMPGU_LT_QB_DESC; 527def CMPGU_LE_QB_MM : DspMMRel, CMPGU_LE_QB_MM_ENC, CMPGU_LE_QB_DESC; 528def CMPU_EQ_QB_MM : DspMMRel, CMPU_EQ_QB_MM_ENC, CMPU_EQ_QB_DESC; 529def CMPU_LT_QB_MM : DspMMRel, CMPU_LT_QB_MM_ENC, CMPU_LT_QB_DESC; 530def CMPU_LE_QB_MM : DspMMRel, CMPU_LE_QB_MM_ENC, CMPU_LE_QB_DESC; 531// microMIPS DSP Rev 2 532def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC, 533 ISA_DSPR2; 534def ADDQH_PH_MMR2 : DspMMRel, ADDQH_PH_MMR2_ENC, ADDQH_PH_DESC, ISA_DSPR2; 535def ADDQH_R_PH_MMR2 : DspMMRel, ADDQH_R_PH_MMR2_ENC, ADDQH_R_PH_DESC, ISA_DSPR2; 536def ADDQH_W_MMR2 : DspMMRel, ADDQH_W_MMR2_ENC, ADDQH_W_DESC, ISA_DSPR2; 537def ADDQH_R_W_MMR2 : DspMMRel, ADDQH_R_W_MMR2_ENC, ADDQH_R_W_DESC, ISA_DSPR2; 538def ADDU_PH_MMR2 : DspMMRel, ADDU_PH_MMR2_ENC, ADDU_PH_DESC, ISA_DSPR2; 539def ADDU_S_PH_MMR2 : DspMMRel, ADDU_S_PH_MMR2_ENC, ADDU_S_PH_DESC, ISA_DSPR2; 540def ADDUH_QB_MMR2 : DspMMRel, ADDUH_QB_MMR2_ENC, ADDUH_QB_DESC, ISA_DSPR2; 541def ADDUH_R_QB_MMR2 : DspMMRel, ADDUH_R_QB_MMR2_ENC, ADDUH_R_QB_DESC, ISA_DSPR2; 542def DPA_W_PH_MMR2 : DspMMRel, DPA_W_PH_MMR2_ENC, DPA_W_PH_DESC, ISA_DSPR2; 543def DPAQX_S_W_PH_MMR2 : DspMMRel, DPAQX_S_W_PH_MMR2_ENC, DPAQX_S_W_PH_DESC, 544 ISA_DSPR2; 545def DPAQX_SA_W_PH_MMR2 : DspMMRel, DPAQX_SA_W_PH_MMR2_ENC, DPAQX_SA_W_PH_DESC, 546 ISA_DSPR2; 547def DPAX_W_PH_MMR2 : DspMMRel, DPAX_W_PH_MMR2_ENC, DPAX_W_PH_DESC, ISA_DSPR2; 548def SHRA_QB_MMR2 : DspMMRel, SHRA_QB_MMR2_ENC, SHRA_QB_MMR2_DESC, ISA_DSPR2; 549def SHRA_R_QB_MMR2 : DspMMRel, SHRA_R_QB_MMR2_ENC, SHRA_R_QB_MMR2_DESC, 550 ISA_DSPR2; 551def SHRAV_QB_MMR2 : DspMMRel, SHRAV_QB_MMR2_ENC, SHRAV_QB_MMR2_DESC, ISA_DSPR2; 552def SHRAV_R_QB_MMR2 : DspMMRel, SHRAV_R_QB_MMR2_ENC, SHRAV_R_QB_MMR2_DESC, 553 ISA_DSPR2; 554def BALIGN_MMR2 : DspMMRel, BALIGN_MMR2_ENC, BALIGN_MMR2_DESC, ISA_DSPR2; 555def CMPGDU_EQ_QB_MMR2 : DspMMRel, CMPGDU_EQ_QB_MMR2_ENC, CMPGDU_EQ_QB_DESC, 556 ISA_DSPR2; 557def CMPGDU_LT_QB_MMR2 : DspMMRel, CMPGDU_LT_QB_MMR2_ENC, CMPGDU_LT_QB_DESC, 558 ISA_DSPR2; 559def CMPGDU_LE_QB_MMR2 : DspMMRel, CMPGDU_LE_QB_MMR2_ENC, CMPGDU_LE_QB_DESC, 560 ISA_DSPR2; 561def SHRL_PH_MMR2 : DspMMRel, SHRL_PH_MMR2_ENC, SHRL_PH_MMR2_DESC, ISA_DSPR2; 562def SHRLV_PH_MMR2 : DspMMRel, SHRLV_PH_MMR2_ENC, SHRLV_PH_MMR2_DESC, ISA_DSPR2; 563def SUBQH_PH_MMR2 : DspMMRel, SUBQH_PH_MMR2_ENC, SUBQH_PH_DESC, ISA_DSPR2; 564def SUBQH_R_PH_MMR2 : DspMMRel, SUBQH_R_PH_MMR2_ENC, SUBQH_R_PH_DESC, ISA_DSPR2; 565def SUBQH_W_MMR2 : DspMMRel, SUBQH_W_MMR2_ENC, SUBQH_W_DESC, ISA_DSPR2; 566def SUBQH_R_W_MMR2 : DspMMRel, SUBQH_R_W_MMR2_ENC, SUBQH_R_W_DESC, ISA_DSPR2; 567def SUBU_PH_MMR2 : DspMMRel, SUBU_PH_MMR2_ENC, SUBU_PH_DESC, ISA_DSPR2; 568def SUBU_S_PH_MMR2 : DspMMRel, SUBU_S_PH_MMR2_ENC, SUBU_S_PH_DESC, ISA_DSPR2; 569def SUBUH_QB_MMR2 : DspMMRel, SUBUH_QB_MMR2_ENC, SUBUH_QB_DESC, ISA_DSPR2; 570def SUBUH_R_QB_MMR2 : DspMMRel, SUBUH_R_QB_MMR2_ENC, SUBUH_R_QB_DESC, ISA_DSPR2; 571def DPS_W_PH_MMR2 : DspMMRel, DPS_W_PH_MMR2_ENC, DPS_W_PH_DESC, ISA_DSPR2; 572def DPSQX_S_W_PH_MMR2 : DspMMRel, DPSQX_S_W_PH_MMR2_ENC, DPSQX_S_W_PH_DESC, 573 ISA_DSPR2; 574def DPSQX_SA_W_PH_MMR2 : DspMMRel, DPSQX_SA_W_PH_MMR2_ENC, DPSQX_SA_W_PH_DESC, 575 ISA_DSPR2; 576def DPSX_W_PH_MMR2 : DspMMRel, DPSX_W_PH_MMR2_ENC, DPSX_W_PH_DESC, ISA_DSPR2; 577def MUL_PH_MMR2 : DspMMRel, MUL_PH_MMR2_ENC, MUL_PH_DESC, ISA_DSPR2; 578def MUL_S_PH_MMR2 : DspMMRel, MUL_S_PH_MMR2_ENC, MUL_S_PH_DESC, ISA_DSPR2; 579def MULQ_RS_W_MMR2 : DspMMRel, MULQ_RS_W_MMR2_ENC, MULQ_RS_W_DESC, ISA_DSPR2; 580def MULQ_S_PH_MMR2 : DspMMRel, MULQ_S_PH_MMR2_ENC, MULQ_S_PH_DESC, ISA_DSPR2; 581def MULQ_S_W_MMR2 : DspMMRel, MULQ_S_W_MMR2_ENC, MULQ_S_W_DESC, ISA_DSPR2; 582def PRECR_QB_PH_MMR2 : DspMMRel, PRECR_QB_PH_MMR2_ENC, PRECR_QB_PH_DESC, 583 ISA_DSPR2; 584def PRECR_SRA_PH_W_MMR2 : DspMMRel, PRECR_SRA_PH_W_MMR2_ENC, 585 PRECR_SRA_PH_W_DESC, ISA_DSPR2; 586def PRECR_SRA_R_PH_W_MMR2 : DspMMRel, PRECR_SRA_R_PH_W_MMR2_ENC, 587 PRECR_SRA_R_PH_W_DESC, ISA_DSPR2; 588def PREPEND_MMR2 : DspMMRel, PREPEND_MMR2_ENC, PREPEND_DESC, ISA_DSPR2; 589 590// Instruction alias. 591def : MMDSPInstAlias<"wrdsp $rt", (WRDSP_MM GPR32Opnd:$rt, 0x1F), 1>; 592def APPEND_MMR2 : DspMMRel, APPEND_MMR2_ENC, APPEND_DESC, ISA_DSPR2; 593def MULSA_W_PH_MMR2 : DspMMRel, MULSA_W_PH_MMR2_ENC, MULSA_W_PH_DESC, ISA_DSPR2; 594// microMIPS DSP Rev 3 595def BPOSGE32C_MMR3 : DspMMRel, BPOSGE32C_MMR3_ENC, BPOSGE32C_MMR3_DESC, 596 ISA_DSPR3; 597