xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td (revision f976241773df2260e6170317080761d1c5814fe5) 
1//=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes microMIPSr6 instructions.
10//
11//===----------------------------------------------------------------------===//
12
13def brtarget21_mm : Operand<OtherVT> {
14  let EncoderMethod = "getBranchTarget21OpValueMM";
15  let OperandType = "OPERAND_PCREL";
16  let DecoderMethod = "DecodeBranchTarget21MM";
17  let ParserMatchClass = MipsJumpTargetAsmOperand;
18}
19
20def brtarget26_mm : Operand<OtherVT> {
21  let EncoderMethod = "getBranchTarget26OpValueMM";
22  let OperandType = "OPERAND_PCREL";
23  let DecoderMethod = "DecodeBranchTarget26MM";
24  let ParserMatchClass = MipsJumpTargetAsmOperand;
25}
26
27def brtargetr6 : Operand<OtherVT> {
28  let EncoderMethod = "getBranchTargetOpValueMMR6";
29  let OperandType = "OPERAND_PCREL";
30  let DecoderMethod = "DecodeBranchTargetMM";
31  let ParserMatchClass = MipsJumpTargetAsmOperand;
32}
33
34def brtarget_lsl2_mm : Operand<OtherVT> {
35  let EncoderMethod = "getBranchTargetOpValueLsl2MMR6";
36  let OperandType = "OPERAND_PCREL";
37  // Instructions that use this operand have their decoder method
38  // set with DecodeDisambiguates
39  let DecoderMethod = "";
40  let ParserMatchClass = MipsJumpTargetAsmOperand;
41}
42
43//===----------------------------------------------------------------------===//
44//
45// Instruction Encodings
46//
47//===----------------------------------------------------------------------===//
48class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
49class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
50class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
51class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
52class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
53class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>;
54class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
55class AUIPC_MMR6_ENC  : PCREL16_FM_MMR6<0b11110>;
56class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>;
57class AUI_MMR6_ENC : AUI_FM_MMR6;
58class BALC_MMR6_ENC  : BRANCH_OFF26_FM<0b101101>;
59class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
60class BC16_MMR6_ENC : BC16_FM_MM16R6;
61class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>;
62class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>;
63class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
64class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
65class BEQZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<"beqzc", 0b100000>;
66class BNEZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<"bnezc", 0b101000>;
67class BGEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgec", 0b111101>,
68                      DecodeDisambiguates<"POP75GroupBranchMMR6">;
69class BGEUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgeuc", 0b110000>,
70                       DecodeDisambiguates<"BlezGroupBranchMMR6">;
71class BLTC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltc", 0b110101>,
72                      DecodeDisambiguates<"POP65GroupBranchMMR6">;
73class BLTUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltuc", 0b111000>,
74                       DecodeDisambiguates<"BgtzGroupBranchMMR6">;
75class BEQC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"beqc", 0b011101>;
76class BNEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bnec", 0b011111>;
77class BLTZC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bltzc", 0b110101>,
78                       DecodeDisambiguates<"POP65GroupBranchMMR6">;
79class BLEZC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"blezc", 0b111101>,
80                       DecodeDisambiguates<"POP75GroupBranchMMR6">;
81class BGEZC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bgezc", 0b111101>,
82                       DecodeDisambiguates<"POP75GroupBranchMMR6">;
83class BGTZC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bgtzc", 0b110101>,
84                       DecodeDisambiguates<"POP65GroupBranchMMR6">;
85class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"beqzalc", 0b011101>,
86                         DecodeDisambiguates<"POP35GroupBranchMMR6">;
87class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bnezalc", 0b011111>,
88                         DecodeDisambiguates<"POP37GroupBranchMMR6">;
89class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bgtzalc", 0b111000>,
90                         MMDecodeDisambiguatedBy<"BgtzGroupBranchMMR6">;
91class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bltzalc", 0b111000>,
92                         MMDecodeDisambiguatedBy<"BgtzGroupBranchMMR6">;
93class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bgezalc", 0b110000>,
94                         MMDecodeDisambiguatedBy<"BlezGroupBranchMMR6">;
95class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"blezalc", 0b110000>,
96                         MMDecodeDisambiguatedBy<"BlezGroupBranchMMR6">;
97class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
98class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
99class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
100class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
101class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
102class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
103class EI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"ei", 0x15d>;
104class DI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"di", 0b0100011101>;
105class ERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0x3cd>;
106class DERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0b1110001101>;
107class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
108class GINVI_MMR6_ENC : POOL32A_GINV_FM_MMR6<"ginvi", 0b00>;
109class GINVT_MMR6_ENC : POOL32A_GINV_FM_MMR6<"ginvt", 0b10>;
110class JALRC16_MMR6_ENC : POOL16C_JALRC_FM_MM16R6<0xb>;
111class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
112class JIC_MMR6_ENC   : JMP_IDX_COMPACT_FM<0b101000>;
113class JRC16_MMR6_ENC: POOL16C_JALRC_FM_MM16R6<0x3>;
114class JRCADDIUSP_MMR6_ENC : POOL16C_JRCADDIUSP_FM_MM16R6<0x13>;
115class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
116class LWPC_MMR6_ENC  : PCREL19_FM_MMR6<0b01>;
117class LWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0x2>;
118class MFC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfc0", 0b00011, 0b111100>;
119class MFC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mfc1", 0b10000000>;
120class MFC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfc2", 0b0100110100>;
121class MFHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfhc0", 0b00011, 0b110100>;
122class MFHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfhc2", 0b1000110100>;
123class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
124class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
125class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
126class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
127class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
128class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
129class MTC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mtc0", 0b01011, 0b111100>;
130class MTC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mtc1", 0b10100000>;
131class MTC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mtc2", 0b0101110100>;
132class MTHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mthc0", 0b01011, 0b110100>;
133class MTHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mthc2", 0b1001110100>;
134class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
135class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
136class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
137class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
138class SB16_MMR6_ENC : LOAD_STORE_FM_MM16<0x22>;
139class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
140class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
141class SH16_MMR6_ENC : LOAD_STORE_FM_MM16<0x2a>;
142class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
143class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
144class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
145class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
146class SW16_MMR6_ENC : LOAD_STORE_FM_MM16<0x3a>;
147class SWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0xa>;
148class SWSP_MMR6_ENC : LOAD_STORE_SP_FM_MM16<0x32>;
149class WRPGPR_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<"wrpgpr", 0x3c5>;
150class WSBH_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<"wsbh", 0x1ec>;
151class LB_MMR6_ENC : LB32_FM_MMR6;
152class LBU_MMR6_ENC : LBU32_FM_MMR6;
153class PAUSE_MMR6_ENC : POOL32A_PAUSE_FM_MMR6<"pause", 0b00101>;
154class RDHWR_MMR6_ENC : POOL32A_RDHWR_FM_MMR6;
155class WAIT_MMR6_ENC : WAIT_FM_MM, MMR6Arch<"wait">;
156class SSNOP_MMR6_ENC : BARRIER_FM_MM<0x1>, MMR6Arch<"ssnop">;
157class SYNC_MMR6_ENC : POOL32A_SYNC_FM_MMR6;
158class SYNCI_MMR6_ENC : POOL32I_SYNCI_FM_MMR6, MMR6Arch<"synci">;
159class RDPGPR_MMR6_ENC : POOL32A_RDPGPR_FM_MMR6<0b1110000101>;
160class SDBBP_MMR6_ENC : SDBBP_FM_MM, MMR6Arch<"sdbbp">;
161class SIGRIE_MMR6_ENC : SIGRIE_FM_MM, MMR6Arch<"sigrie">;
162class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
163class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
164class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
165class ABS_D_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.d", 1, 0b0001101>;
166class FLOOR_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.s", 0, 0b00001100>;
167class FLOOR_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.d", 1, 0b00001100>;
168class FLOOR_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.s", 0, 0b00101100>;
169class FLOOR_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.d", 1, 0b00101100>;
170class CEIL_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.s", 0, 0b01001100>;
171class CEIL_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.d", 1, 0b01001100>;
172class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>;
173class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>;
174class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>;
175class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>;
176class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
177class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
178class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
179class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
180class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
181class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
182class JALRC_HB_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc.hb", 0b0001111100>;
183class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>;
184class RINT_D_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.d", 1>;
185class ROUND_L_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.s", 0,
186                                                       0b11001100>;
187class ROUND_L_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.d", 1,
188                                                       0b11001100>;
189class ROUND_W_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.s", 0,
190                                                       0b11101100>;
191class ROUND_W_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.d", 1,
192                                                       0b11101100>;
193class SEL_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.s", 0, 0b010111000>;
194class SEL_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.d", 1, 0b010111000>;
195class SELEQZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.s", 0, 0b000111000>;
196class SELEQZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.d", 1, 0b000111000>;
197class SELNEZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selnez.s", 0, 0b001111000>;
198class SELNEZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selnez.d", 1, 0b001111000>;
199class CLASS_S_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.s", 0, 0b001100000>;
200class CLASS_D_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.d", 1, 0b001100000>;
201class EXT_MMR6_ENC : POOL32A_EXT_INS_FM_MMR6<"ext", 0b101100>;
202class INS_MMR6_ENC : POOL32A_EXT_INS_FM_MMR6<"ins", 0b001100>;
203class JALRC_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc", 0b0000111100>;
204class BOVC_MMR6_ENC : POP35_BOVC_FM_MMR6<"bovc">;
205class BNVC_MMR6_ENC : POP37_BNVC_FM_MMR6<"bnvc">;
206class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6;
207class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6;
208class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>;
209class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6;
210class OR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1001>;
211class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>;
212class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>;
213class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>;
214class LI16_MMR6_ENC : LI_FM_MM16;
215class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
216class MOVEP_MMR6_ENC  : POOL16C_MOVEP16_FM_MMR6;
217class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
218class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
219class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
220class TLBINV_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinv", 0x10d>;
221class TLBINVF_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinvf", 0x14d>;
222class DVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"dvp", 0b0001100101>;
223class EVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"evp", 0b0011100101>;
224class BC1EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1eqzc", 0b01000>;
225class BC1NEZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1nezc", 0b01001>;
226class BC2EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc2eqzc", 0b01010>;
227class BC2NEZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc2nezc", 0b01011>;
228class LDC1_MMR6_ENC : LDWC1_SDWC1_FM_MMR6<"ldc1", 0b101111>;
229class SDC1_MMR6_ENC : LDWC1_SDWC1_FM_MMR6<"sdc1", 0b101110>;
230class LDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"ldc2", 0b0010>;
231class SDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"sdc2", 0b1010>;
232class LWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"lwc2", 0b0000>;
233class SWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"swc2", 0b1000>;
234
235class LL_MMR6_ENC  : POOL32C_LL_E_SC_E_FM_MMR6<"ll", 0b0011, 0b000>;
236class SC_MMR6_ENC  : POOL32C_LL_E_SC_E_FM_MMR6<"sc", 0b1011, 0b000>;
237
238/// Floating Point Instructions
239class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
240class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
241class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
242class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
243class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
244class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
245class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
246class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
247class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
248class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
249class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
250class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
251class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
252class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>;
253class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>;
254class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>;
255class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>;
256class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>;
257class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>;
258
259class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>;
260class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>;
261class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>;
262class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>;
263class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>;
264class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>;
265
266//===----------------------------------------------------------------------===//
267//
268// Instruction Descriptions
269//
270//===----------------------------------------------------------------------===//
271
272class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
273                                  RegisterOperand GPROpnd>
274    : BRANCH_DESC_BASE {
275  dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
276  dag OutOperandList = (outs);
277  string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
278  list<Register> Defs = [AT];
279  InstrItinClass Itinerary = II_BCCZC;
280}
281
282class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
283                                                      GPR32Opnd> {
284  list<Register> Defs = [RA];
285}
286
287class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
288                                                      GPR32Opnd> {
289  list<Register> Defs = [RA];
290}
291
292class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
293                                                      GPR32Opnd> {
294  list<Register> Defs = [RA];
295}
296
297class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
298                                                      GPR32Opnd> {
299  list<Register> Defs = [RA];
300}
301
302class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
303                                                      GPR32Opnd> {
304  list<Register> Defs = [RA];
305}
306
307class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
308                                                      GPR32Opnd> {
309  list<Register> Defs = [RA];
310}
311
312class BLTZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzc", brtarget_lsl2_mm,
313                                                    GPR32Opnd>;
314class BLEZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezc", brtarget_lsl2_mm,
315                                                    GPR32Opnd>;
316class BGEZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezc", brtarget_lsl2_mm,
317                                                    GPR32Opnd>;
318class BGTZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzc", brtarget_lsl2_mm,
319                                                    GPR32Opnd>;
320
321class CMP_CBR_2R_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
322                                RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
323  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
324  dag OutOperandList = (outs);
325  string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
326  list<Register> Defs = [AT];
327  InstrItinClass Itinerary = II_BCCC;
328}
329
330class BGEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgec", brtarget_lsl2_mm,
331                                                 GPR32Opnd>;
332class BGEUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgeuc", brtarget_lsl2_mm,
333                                                 GPR32Opnd>;
334class BLTC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltc", brtarget_lsl2_mm,
335                                                 GPR32Opnd>;
336class BLTUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltuc", brtarget_lsl2_mm,
337                                                 GPR32Opnd>;
338class BEQC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"beqc", brtarget_lsl2_mm,
339                                                 GPR32Opnd>;
340class BNEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bnec", brtarget_lsl2_mm,
341                                                 GPR32Opnd>;
342
343class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd, 1, II_ADD>;
344class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, add>;
345class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU>;
346class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>;
347class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd, 1, II_MUH, mulhs>;
348class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd, 1, II_MULU>;
349class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd, 1, II_MUHU, mulhu>;
350
351class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd, InstrItinClass Itin>
352    : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
353  dag InOperandList = (ins opnd:$offset);
354  dag OutOperandList = (outs);
355  string AsmString = !strconcat(instr_asm, "\t$offset");
356  bit isBarrier = 1;
357  InstrItinClass Itinerary = Itin;
358}
359
360class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26_mm, II_BALC> {
361  bit isCall = 1;
362  list<Register> Defs = [RA];
363}
364class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26_mm, II_BC> {
365  list<dag> Pattern = [(br bb:$offset)];
366}
367
368class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
369                                       !strconcat("bc16", "\t$offset"), [],
370                                       II_BC, FrmI>,
371                       MMR6Arch<"bc16"> {
372  let isBranch = 1;
373  let isTerminator = 1;
374  let isBarrier = 1;
375  let hasDelaySlot = 0;
376  let AdditionalPredicates = [RelocPIC];
377  let Defs = [AT];
378}
379
380class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
381    : CBranchZeroMM<instr_asm, brtarget7_mm, GPRMM16Opnd>,
382      MMR6Arch<instr_asm> {
383  let isBranch = 1;
384  let isTerminator = 1;
385  let hasDelaySlot = 0;
386  let Defs = [AT];
387}
388class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">;
389class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">;
390
391class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>;
392class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd, 0,II_SUBU>;
393
394class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
395    : MMR6Arch<instr_asm> {
396  dag OutOperandList = (outs GPROpnd:$rd);
397  dag InOperandList = (ins GPROpnd:$rt);
398  string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
399  list<dag> Pattern = [];
400  InstrItinClass Itinerary = II_BITSWAP;
401}
402
403class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
404
405class BRK_MMR6_DESC : BRK_FT<"break">;
406
407class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
408                           RegisterOperand GPROpnd, InstrItinClass Itin>
409      : MMR6Arch<instr_asm> {
410  dag OutOperandList = (outs);
411  dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
412  string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
413  list<dag> Pattern = [];
414  string DecoderMethod = "DecodeCacheOpMM";
415  InstrItinClass Itinerary = Itin;
416}
417
418class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd,
419                                             II_CACHE>;
420class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd,
421                                             II_PREF>;
422
423class LB_LBU_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
424                            RegisterOperand GPROpnd, InstrItinClass Itin>
425    : MMR6Arch<instr_asm> {
426  dag OutOperandList = (outs GPROpnd:$rt);
427  dag InOperandList = (ins MemOpnd:$addr);
428  string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
429  string DecoderMethod = "DecodeLoadByte15";
430  bit mayLoad = 1;
431  InstrItinClass Itinerary = Itin;
432}
433class LB_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lb", mem_mm_16, GPR32Opnd, II_LB>;
434class LBU_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lbu", mem_mm_16, GPR32Opnd,
435                                            II_LBU>;
436
437class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
438                             InstrItinClass Itin> : MMR6Arch<instr_asm> {
439  dag OutOperandList = (outs GPROpnd:$rt);
440  dag InOperandList = (ins GPROpnd:$rs);
441  string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
442  InstrItinClass Itinerary = Itin;
443}
444
445class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd, II_CLO>;
446class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd, II_CLZ>;
447
448class EHB_MMR6_DESC : Barrier<"ehb", II_EHB>;
449class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd, II_EI>;
450class DI_MMR6_DESC : DEI_FT<"di", GPR32Opnd, II_DI>;
451
452class ERET_MMR6_DESC : ER_FT<"eret", II_ERET>;
453class DERET_MMR6_DESC : ER_FT<"deret", II_DERET>;
454class ERETNC_MMR6_DESC : ER_FT<"eretnc", II_ERETNC>;
455
456class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
457    : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
458                      [(MipsJmpLink RO:$rs)], II_JALR, FrmR>,
459      MMR6Arch<opstr> {
460  let isCall = 1;
461  let hasDelaySlot = 0;
462  let Defs = [RA];
463  let hasPostISelHook = 1;
464}
465class JALRC16_MMR6_DESC : JALRC16_MMR6_DESC_BASE<"jalr", GPR32Opnd>;
466
467class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
468                                     RegisterOperand GPROpnd,
469                                     InstrItinClass Itin>
470    : MMR6Arch<opstr> {
471  dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
472  string AsmString = !strconcat(opstr, "\t$rt, $offset");
473  list<dag> Pattern = [];
474  bit isTerminator = 1;
475  bit hasDelaySlot = 0;
476  InstrItinClass Itinerary = Itin;
477}
478
479class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
480                                                       GPR32Opnd, II_JIALC> {
481  bit isCall = 1;
482  list<Register> Defs = [RA];
483}
484
485class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
486                                                     GPR32Opnd, II_JIC> {
487  bit isBarrier = 1;
488  list<Register> Defs = [AT];
489}
490
491class JRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
492    : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
493                      [], II_JR, FrmR>,
494      MMR6Arch<opstr> {
495  let hasDelaySlot = 0;
496  let isBranch = 1;
497  let isIndirectBranch = 1;
498}
499class JRC16_MMR6_DESC : JRC16_MMR6_DESC_BASE<"jrc16", GPR32Opnd>;
500
501class JRCADDIUSP_MMR6_DESC
502    : MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jrcaddiusp\t$imm",
503                      [], II_JRADDIUSP, FrmR>,
504      MMR6Arch<"jrcaddiusp"> {
505  let hasDelaySlot = 0;
506  let isTerminator = 1;
507  let isBarrier = 1;
508  let isBranch = 1;
509  let isIndirectBranch = 1;
510}
511
512class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
513                      Operand ImmOpnd, InstrItinClass Itin>
514    : MMR6Arch<instr_asm> {
515  dag OutOperandList = (outs GPROpnd:$rd);
516  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
517  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
518  list<dag> Pattern = [];
519  InstrItinClass Itinerary = Itin;
520}
521
522class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2,
523                                             II_ALIGN>;
524
525class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
526                         InstrItinClass Itin> : MMR6Arch<instr_asm> {
527  dag OutOperandList = (outs GPROpnd:$rt);
528  dag InOperandList = (ins GPROpnd:$rs, uimm16:$imm);
529  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
530  list<dag> Pattern = [];
531  InstrItinClass Itinerary = Itin;
532}
533
534class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd, II_AUI>;
535
536class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
537                            InstrItinClass Itin> : MMR6Arch<instr_asm> {
538  dag OutOperandList = (outs GPROpnd:$rt);
539  dag InOperandList = (ins simm16:$imm);
540  string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
541  list<dag> Pattern = [];
542  InstrItinClass Itinerary = Itin;
543}
544
545class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd, II_ALUIPC>;
546class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd, II_AUIPC>;
547
548class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
549                         Operand ImmOpnd, InstrItinClass Itin>
550    : MMR6Arch<instr_asm> {
551  dag OutOperandList = (outs GPROpnd:$rd);
552  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
553  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
554  list<dag> Pattern = [];
555  InstrItinClass Itinerary = Itin;
556}
557
558class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1, II_LSA>;
559
560class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
561                           Operand ImmOpnd, InstrItinClass Itin>
562    : MMR6Arch<instr_asm> {
563  dag OutOperandList = (outs GPROpnd:$rt);
564  dag InOperandList = (ins ImmOpnd:$imm);
565  string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
566  list<dag> Pattern = [];
567  InstrItinClass Itinerary = Itin;
568}
569
570class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd,
571                                               simm19_lsl2, II_ADDIUPC>;
572class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2,
573                                           II_LWPC>;
574
575class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
576                               InstrItinClass Itin> : MMR6Arch<instr_asm> {
577  dag OutOperandList = (outs GPROpnd:$rd);
578  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
579  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
580  list<dag> Pattern = [];
581  InstrItinClass Itinerary = Itin;
582}
583
584class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd,
585                                                  II_SELCCZ>;
586class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd,
587                                                  II_SELCCZ>;
588class PAUSE_MMR6_DESC : Barrier<"pause", II_PAUSE>;
589class RDHWR_MMR6_DESC : MMR6Arch<"rdhwr">, MipsR6Inst {
590  dag OutOperandList = (outs GPR32Opnd:$rt);
591  dag InOperandList = (ins HWRegsOpnd:$rs, uimm3:$sel);
592  string AsmString = !strconcat("rdhwr", "\t$rt, $rs, $sel");
593  list<dag> Pattern = [];
594  InstrItinClass Itinerary = II_RDHWR;
595  Format Form = FrmR;
596}
597
598class WAIT_MMR6_DESC : WaitMM<"wait">;
599// FIXME: ssnop should not be defined for R6. Per MD000582 microMIPS32 6.03:
600//        Assemblers targeting specifically Release 6 should reject the SSNOP
601//        instruction with an error.
602class SSNOP_MMR6_DESC : Barrier<"ssnop", II_SSNOP>;
603class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
604
605class DIVMOD_MMR6_DESC_BASE<string opstr, RegisterOperand GPROpnd,
606                            InstrItinClass Itin,
607                            SDPatternOperator OpNode=null_frag>
608    : MipsR6Inst {
609  dag OutOperandList = (outs GPROpnd:$rd);
610  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
611  string AsmString = !strconcat(opstr, "\t$rd, $rs, $rt");
612  list<dag> Pattern = [(set GPROpnd:$rd, (OpNode GPROpnd:$rs, GPROpnd:$rt))];
613  string BaseOpcode = opstr;
614  Format f = FrmR;
615  let isCommutable = 0;
616  let isReMaterializable = 1;
617  InstrItinClass Itinerary = Itin;
618
619  // This instruction doesn't trap division by zero itself. We must insert
620  // teq instructions as well.
621  bit usesCustomInserter = 1;
622}
623class DIV_MMR6_DESC  : DIVMOD_MMR6_DESC_BASE<"div", GPR32Opnd, II_DIV, sdiv>;
624class DIVU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"divu", GPR32Opnd, II_DIVU, udiv>;
625class MOD_MMR6_DESC  : DIVMOD_MMR6_DESC_BASE<"mod", GPR32Opnd, II_MOD, srem>;
626class MODU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"modu", GPR32Opnd, II_MODU, urem>;
627class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>;
628class ANDI_MMR6_DESC : ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI>;
629class NOR_MMR6_DESC : LogicNOR<"nor", GPR32Opnd>;
630class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>;
631class ORI_MMR6_DESC : ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
632                                  or> {
633  int AddedComplexity = 1;
634}
635class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>;
636class XORI_MMR6_DESC : ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI,
637                                   immZExt16, xor>;
638class SW_MMR6_DESC : Store<"sw", GPR32Opnd> {
639  InstrItinClass Itinerary = II_SW;
640}
641class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO,
642                                 InstrItinClass Itin> {
643  dag InOperandList = (ins RO:$rs);
644  dag OutOperandList = (outs RO:$rt);
645  string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
646  list<dag> Pattern = [];
647  Format f = FrmR;
648  string BaseOpcode = instr_asm;
649  bit hasSideEffects = 0;
650  InstrItinClass Itinerary = Itin;
651}
652class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd,
653                                                    II_WRPGPR>;
654class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd, II_WSBH>;
655
656class MTC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
657                         RegisterOperand SrcRC, InstrItinClass Itin> {
658  dag InOperandList = (ins SrcRC:$rt, uimm3:$sel);
659  dag OutOperandList = (outs DstRC:$rs);
660  string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel");
661  list<dag> Pattern = [];
662  Format f = FrmFR;
663  string BaseOpcode = opstr;
664  InstrItinClass Itinerary = Itin;
665}
666class MTC1_MMR6_DESC_BASE<
667      string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
668      InstrItinClass Itin = NoItinerary, SDPatternOperator OpNode = null_frag>
669      : MipsR6Inst {
670  dag InOperandList = (ins SrcRC:$rt);
671  dag OutOperandList = (outs DstRC:$fs);
672  string AsmString = !strconcat(opstr, "\t$rt, $fs");
673  list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))];
674  Format f = FrmFR;
675  InstrItinClass Itinerary = Itin;
676  string BaseOpcode = opstr;
677}
678class MTC1_64_MMR6_DESC_BASE<
679      string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
680      InstrItinClass Itin = NoItinerary> : MipsR6Inst {
681  dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt);
682  dag OutOperandList = (outs DstRC:$fs);
683  string AsmString = !strconcat(opstr, "\t$rt, $fs");
684  list<dag> Pattern = [];
685  Format f = FrmFR;
686  InstrItinClass Itinerary = Itin;
687  string BaseOpcode = opstr;
688  // $fs_in is part of a white lie to work around a widespread bug in the FPU
689  // implementation. See expandBuildPairF64 for details.
690  let Constraints = "$fs = $fs_in";
691}
692class MTC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
693                         RegisterOperand SrcRC, InstrItinClass Itin> {
694  dag InOperandList = (ins SrcRC:$rt);
695  dag OutOperandList = (outs DstRC:$impl);
696  string AsmString = !strconcat(opstr, "\t$rt, $impl");
697  list<dag> Pattern = [];
698  Format f = FrmFR;
699  string BaseOpcode = opstr;
700  InstrItinClass Itinerary = Itin;
701}
702
703class MTC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mtc0", COP0Opnd, GPR32Opnd,
704                                           II_MTC0>;
705class MTC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"mtc1", FGR32Opnd, GPR32Opnd,
706                                           II_MTC1, bitconvert>, HARDFLOAT;
707class MTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mtc2", COP2Opnd, GPR32Opnd,
708                                           II_MTC2>;
709class MTHC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mthc0", COP0Opnd, GPR32Opnd,
710                                            II_MTHC0>;
711class MTHC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mthc2", COP2Opnd, GPR32Opnd,
712                                            II_MTC2>;
713
714class MFC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
715                          RegisterOperand SrcRC, InstrItinClass Itin> {
716  dag InOperandList = (ins SrcRC:$rs, uimm3:$sel);
717  dag OutOperandList = (outs DstRC:$rt);
718  string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel");
719  list<dag> Pattern = [];
720  Format f = FrmFR;
721  string BaseOpcode = opstr;
722  InstrItinClass Itinerary = Itin;
723}
724class MFC1_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
725                          RegisterOperand SrcRC,
726                          InstrItinClass Itin = NoItinerary,
727                          SDPatternOperator OpNode = null_frag> : MipsR6Inst {
728  dag InOperandList = (ins SrcRC:$fs);
729  dag OutOperandList = (outs DstRC:$rt);
730  string AsmString = !strconcat(opstr, "\t$rt, $fs");
731  list<dag> Pattern = [(set DstRC:$rt, (OpNode SrcRC:$fs))];
732  Format f = FrmFR;
733  InstrItinClass Itinerary = Itin;
734  string BaseOpcode = opstr;
735}
736class MFC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
737                          RegisterOperand SrcRC, InstrItinClass Itin> {
738  dag InOperandList = (ins SrcRC:$impl);
739  dag OutOperandList = (outs DstRC:$rt);
740  string AsmString = !strconcat(opstr, "\t$rt, $impl");
741  list<dag> Pattern = [];
742  Format f = FrmFR;
743  string BaseOpcode = opstr;
744  InstrItinClass Itinerary = Itin;
745}
746class MFC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfc0", GPR32Opnd, COP0Opnd,
747                                           II_MFC0>;
748class MFC1_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfc1", GPR32Opnd, FGR32Opnd,
749                                           II_MFC1, bitconvert>, HARDFLOAT;
750class MFC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfc2", GPR32Opnd, COP2Opnd,
751                                           II_MFC2>;
752class MFHC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfhc0", GPR32Opnd, COP0Opnd,
753                                            II_MFHC0>;
754class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd,
755                                            II_MFC2>;
756
757class LDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 {
758  dag InOperandList = (ins mem_mm_16:$addr);
759  dag OutOperandList = (outs FGR64Opnd:$ft);
760  string AsmString = !strconcat("ldc1", "\t$ft, $addr");
761  list<dag> Pattern = [(set FGR64Opnd:$ft, (load addrimm16:$addr))];
762  Format f = FrmFI;
763  InstrItinClass Itinerary = II_LDC1;
764  string BaseOpcode = "ldc1";
765  bit mayLoad = 1;
766  let DecoderMethod = "DecodeFMemMMR2";
767}
768
769class SDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 {
770  dag InOperandList = (ins FGR64Opnd:$ft, mem_mm_16:$addr);
771  dag OutOperandList = (outs);
772  string AsmString = !strconcat("sdc1", "\t$ft, $addr");
773  list<dag> Pattern = [(store FGR64Opnd:$ft, addrimm16:$addr)];
774  Format f = FrmFI;
775  InstrItinClass Itinerary = II_SDC1;
776  string BaseOpcode = "sdc1";
777  bit mayStore = 1;
778  let DecoderMethod = "DecodeFMemMMR2";
779}
780
781class LDC2_LWC2_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
782  dag OutOperandList = (outs COP2Opnd:$rt);
783  dag InOperandList = (ins mem_mm_11:$addr);
784  string AsmString = !strconcat(opstr, "\t$rt, $addr");
785  list<dag> Pattern = [(set COP2Opnd:$rt, (load addrimm11:$addr))];
786  Format f = FrmFI;
787  InstrItinClass Itinerary = itin;
788  string BaseOpcode = opstr;
789  bit mayLoad = 1;
790  string DecoderMethod = "DecodeFMemCop2MMR6";
791}
792class LDC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"ldc2", II_LDC2>;
793class LWC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"lwc2", II_LWC2>;
794
795class SDC2_SWC2_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
796  dag OutOperandList = (outs);
797  dag InOperandList = (ins COP2Opnd:$rt, mem_mm_11:$addr);
798  string AsmString = !strconcat(opstr, "\t$rt, $addr");
799  list<dag> Pattern = [(store COP2Opnd:$rt, addrimm11:$addr)];
800  Format f = FrmFI;
801  InstrItinClass Itinerary = itin;
802  string BaseOpcode = opstr;
803  bit mayStore = 1;
804  string DecoderMethod = "DecodeFMemCop2MMR6";
805}
806class SDC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"sdc2", II_SDC2>;
807class SWC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"swc2", II_SWC2>;
808
809class GINV_MMR6_DESC_BASE<string opstr,
810                          RegisterOperand SrcRC, InstrItinClass Itin> {
811  dag InOperandList = (ins SrcRC:$rs, uimm2:$type);
812  dag OutOperandList = (outs);
813  string AsmString = !strconcat(opstr, "\t$rs, $type");
814  list<dag> Pattern = [];
815  Format f = FrmFR;
816  string BaseOpcode = opstr;
817  InstrItinClass Itinerary = Itin;
818}
819
820class GINVI_MMR6_DESC : GINV_MMR6_DESC_BASE<"ginvi", GPR32Opnd,
821                                            II_GINVI> {
822  dag InOperandList = (ins GPR32Opnd:$rs);
823  string AsmString = "ginvi\t$rs";
824}
825class GINVT_MMR6_DESC : GINV_MMR6_DESC_BASE<"ginvt", GPR32Opnd,
826                                            II_GINVT>;
827
828class SC_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
829  dag OutOperandList = (outs GPR32Opnd:$dst);
830  dag InOperandList = (ins GPR32Opnd:$rt, mem_mm_9:$addr);
831  string AsmString = !strconcat(opstr, "\t$rt, $addr");
832  InstrItinClass Itinerary = itin;
833  string BaseOpcode = opstr;
834  bit mayStore = 1;
835  string Constraints = "$rt = $dst";
836  string DecoderMethod = "DecodeMemMMImm9";
837}
838
839class LL_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
840  dag OutOperandList = (outs GPR32Opnd:$rt);
841  dag InOperandList = (ins mem_mm_9:$addr);
842  string AsmString = !strconcat(opstr, "\t$rt, $addr");
843  InstrItinClass Itinerary = itin;
844  string BaseOpcode = opstr;
845  bit mayLoad = 1;
846  string DecoderMethod = "DecodeMemMMImm9";
847}
848
849class SC_MMR6_DESC : SC_MMR6_DESC_BASE<"sc", II_SC>;
850class LL_MMR6_DESC : LL_MMR6_DESC_BASE<"ll", II_LL>;
851
852/// Floating Point Instructions
853class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
854                            InstrItinClass Itin, bit isComm,
855                            SDPatternOperator OpNode = null_frag> : HARDFLOAT {
856  dag OutOperandList = (outs RC:$fd);
857  dag InOperandList = (ins RC:$ft, RC:$fs);
858  string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
859  list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
860  InstrItinClass Itinerary = Itin;
861  bit isCommutable = isComm;
862}
863class FADD_S_MMR6_DESC
864  : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
865class FSUB_S_MMR6_DESC
866  : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
867class FMUL_S_MMR6_DESC
868  : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
869class FDIV_S_MMR6_DESC
870  : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
871class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd,
872                                            II_MADDF_S>, HARDFLOAT;
873class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd,
874                                            II_MADDF_D>, HARDFLOAT;
875class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd,
876                                            II_MSUBF_S>, HARDFLOAT;
877class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd,
878                                            II_MSUBF_D>, HARDFLOAT;
879
880class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
881                               RegisterOperand SrcRC, InstrItinClass Itin,
882                               SDPatternOperator OpNode = null_frag>
883                               : HARDFLOAT, NeverHasSideEffects {
884  dag OutOperandList = (outs DstRC:$ft);
885  dag InOperandList = (ins SrcRC:$fs);
886  string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
887  list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
888  InstrItinClass Itinerary = Itin;
889  Format Form = FrmFR;
890}
891class FMOV_S_MMR6_DESC
892  : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
893class FMOV_D_MMR6_DESC
894  : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>;
895class FNEG_S_MMR6_DESC
896  : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
897
898class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd, II_MAX_S>,
899                        HARDFLOAT;
900class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd, II_MAX_D>,
901                        HARDFLOAT;
902class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd, II_MIN_S>,
903                        HARDFLOAT;
904class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd, II_MIN_D>,
905                        HARDFLOAT;
906
907class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd, II_MAXA_S>,
908                         HARDFLOAT;
909class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd, II_MAXA_D>,
910                         HARDFLOAT;
911class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd, II_MINA_S>,
912                         HARDFLOAT;
913class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd, II_MINA_D>,
914                         HARDFLOAT;
915
916class CVT_MMR6_DESC_BASE<
917    string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
918    InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
919    : HARDFLOAT, NeverHasSideEffects {
920  dag OutOperandList = (outs DstRC:$ft);
921  dag InOperandList = (ins SrcRC:$fs);
922  string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
923  list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
924  InstrItinClass Itinerary = Itin;
925  Format Form = FrmFR;
926}
927
928class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd,
929                                             II_CVT>;
930class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd,
931                                             II_CVT>;
932class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd,
933                                             II_CVT>;
934class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd,
935                                             II_CVT>, FGR_64;
936class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
937                                             II_CVT>;
938class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
939                                             II_CVT>, FGR_64;
940
941multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
942                       RegisterOperand FGROpnd, InstrItinClass Itin> {
943  def CMP_AF_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
944      !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
945      CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd, Itin>, HARDFLOAT,
946      ISA_MICROMIPS32R6;
947  def CMP_UN_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
948      !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
949      CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, Itin, setuo>, HARDFLOAT,
950      ISA_MICROMIPS32R6;
951  def CMP_EQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
952      !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
953      CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, Itin, setoeq>, HARDFLOAT,
954      ISA_MICROMIPS32R6;
955  def CMP_UEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
956      !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
957      CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, Itin, setueq>, HARDFLOAT,
958      ISA_MICROMIPS32R6;
959  def CMP_LT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
960      !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
961      CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, Itin, setolt>, HARDFLOAT,
962      ISA_MICROMIPS32R6;
963  def CMP_ULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
964      !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
965      CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, Itin, setult>, HARDFLOAT,
966      ISA_MICROMIPS32R6;
967  def CMP_LE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
968      !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
969      CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, Itin, setole>, HARDFLOAT,
970      ISA_MICROMIPS32R6;
971  def CMP_ULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
972      !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
973      CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, Itin, setule>, HARDFLOAT,
974      ISA_MICROMIPS32R6;
975  def CMP_SAF_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
976      !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
977      CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd, Itin>, HARDFLOAT,
978      ISA_MICROMIPS32R6;
979  def CMP_SUN_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
980      !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
981      CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd, Itin>, HARDFLOAT,
982      ISA_MICROMIPS32R6;
983  def CMP_SEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
984      !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
985      CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd, Itin>, HARDFLOAT,
986      ISA_MICROMIPS32R6;
987  def CMP_SUEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
988      !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
989      CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd, Itin>, HARDFLOAT,
990      ISA_MICROMIPS32R6;
991  def CMP_SLT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
992      !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
993      CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd, Itin>, HARDFLOAT,
994      ISA_MICROMIPS32R6;
995  def CMP_SULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
996      !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
997      CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd, Itin>, HARDFLOAT,
998      ISA_MICROMIPS32R6;
999  def CMP_SLE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1000      !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
1001      CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd, Itin>, HARDFLOAT,
1002      ISA_MICROMIPS32R6;
1003  def CMP_SULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1004      !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
1005      CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd, Itin>, HARDFLOAT,
1006      ISA_MICROMIPS32R6;
1007}
1008
1009class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
1010                             RegisterOperand SrcRC, InstrItinClass Itin,
1011                             SDPatternOperator OpNode = null_frag>
1012    : HARDFLOAT, NeverHasSideEffects {
1013  dag OutOperandList = (outs DstRC:$ft);
1014  dag InOperandList  = (ins SrcRC:$fs);
1015  string AsmString   = !strconcat(instr_asm, "\t$ft, $fs");
1016  list<dag>  Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
1017  InstrItinClass Itinerary = Itin;
1018  Format Form = FrmFR;
1019  list<Predicate> EncodingPredicates = [HasStdEnc];
1020}
1021
1022class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd,
1023                                                    FGR32Opnd, II_FLOOR>;
1024class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd,
1025                                                    FGR64Opnd, II_FLOOR>;
1026class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd,
1027                                                    FGR32Opnd, II_FLOOR>;
1028class FLOOR_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd,
1029                                                    AFGR64Opnd, II_FLOOR>;
1030class CEIL_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.s", FGR64Opnd,
1031                                                   FGR32Opnd, II_CEIL>;
1032class CEIL_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.d", FGR64Opnd,
1033                                                   FGR64Opnd, II_CEIL>;
1034class CEIL_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.s", FGR32Opnd,
1035                                                   FGR32Opnd, II_CEIL>;
1036class CEIL_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.d", FGR32Opnd,
1037                                                   AFGR64Opnd, II_CEIL>;
1038class TRUNC_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.s", FGR64Opnd,
1039                                                    FGR32Opnd, II_TRUNC>;
1040class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd,
1041                                                    FGR64Opnd, II_TRUNC>;
1042class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
1043                                                    FGR32Opnd, II_TRUNC>;
1044class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
1045                                                    FGR64Opnd, II_TRUNC>;
1046class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
1047                                                 II_SQRT_S, fsqrt>;
1048class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
1049                                                 II_SQRT_D, fsqrt>;
1050class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd,
1051                                                   FGR32Opnd, II_ROUND>;
1052class ROUND_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd,
1053                                                   FGR64Opnd, II_ROUND>;
1054class ROUND_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.s", FGR32Opnd,
1055                                                   FGR32Opnd, II_ROUND>;
1056class ROUND_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.d", FGR64Opnd,
1057                                                   FGR64Opnd, II_ROUND>;
1058
1059class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd, II_SEL_S>;
1060class SEL_D_MMR6_DESC : COP1_SEL_D_DESC_BASE<"sel.d", FGR64Opnd, II_SEL_D>;
1061
1062class SELEQZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd,
1063                                              II_SELCCZ_S>;
1064class SELEQZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd,
1065                                              II_SELCCZ_D>;
1066class SELNEZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd,
1067                                              II_SELCCZ_S>;
1068class SELNEZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd,
1069                                              II_SELCCZ_D>;
1070class RINT_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd,
1071                                              II_RINT_S>;
1072class RINT_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd,
1073                                              II_RINT_S>;
1074class CLASS_S_MMR6_DESC  : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd,
1075                                              II_CLASS_S>;
1076class CLASS_D_MMR6_DESC  : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd,
1077                                              II_CLASS_S>;
1078
1079class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO,
1080                           InstrItinClass Itin>
1081    : Store<opstr, RO>, MMR6Arch<opstr> {
1082  let DecoderMethod = "DecodeMemMMImm16";
1083  InstrItinClass Itinerary = Itin;
1084}
1085class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd, II_SB>;
1086
1087class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd, II_SH>;
1088class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
1089      MMR6Arch<"addu16"> {
1090  int AddedComplexity = 1;
1091}
1092class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND>,
1093      MMR6Arch<"and16">;
1094class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
1095      MMR6Arch<"andi16">;
1096class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16"> {
1097  int AddedComplexity = 1;
1098}
1099class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR>, MMR6Arch<"or16">;
1100class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
1101      MMR6Arch<"sll16">;
1102class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
1103      MMR6Arch<"srl16">;
1104class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16", II_BREAK>, MMR6Arch<"break16">;
1105class LI16_MMR6_DESC : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>,
1106      MMR6Arch<"li16">, IsAsCheapAsAMove;
1107class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">;
1108class MOVEP_MMR6_DESC : MovePMM16<"movep", GPRMM16OpndMovePPairFirst,
1109                                  GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP>,
1110                        MMR6Arch<"movep">;
1111class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, MMR6Arch<"sdbbp16">;
1112class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
1113      MMR6Arch<"subu16"> {
1114  int AddedComplexity = 1;
1115}
1116class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR>,
1117      MMR6Arch<"xor16">;
1118
1119class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
1120  dag OutOperandList = (outs GPR32Opnd:$rt);
1121  dag InOperandList = (ins mem:$addr);
1122  string AsmString = "lw\t$rt, $addr";
1123  let DecoderMethod = "DecodeMemMMImm16";
1124  let canFoldAsLoad = 1;
1125  let mayLoad = 1;
1126  list<dag> Pattern = [(set GPR32Opnd:$rt, (load addrDefault:$addr))];
1127  InstrItinClass Itinerary = II_LW;
1128}
1129
1130class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{
1131  dag OutOperandList = (outs GPR32Opnd:$rt);
1132  dag InOperandList = (ins uimm16:$imm16);
1133  string AsmString = "lui\t$rt, $imm16";
1134  list<dag> Pattern = [];
1135  bit hasSideEffects = 0;
1136  bit isReMaterializable = 1;
1137  InstrItinClass Itinerary = II_LUI;
1138  Format Form = FrmI;
1139}
1140
1141class SYNC_MMR6_DESC : MMR6Arch<"sync">, MipsR6Inst {
1142  dag OutOperandList = (outs);
1143  dag InOperandList = (ins uimm5:$stype);
1144  string AsmString = !strconcat("sync", "\t$stype");
1145  list<dag> Pattern = [(MipsSync immZExt5:$stype)];
1146  InstrItinClass Itinerary = II_SYNC;
1147  bit HasSideEffects = 1;
1148}
1149
1150class SYNCI_MMR6_DESC : SYNCI_FT<"synci", mem_mm_16> {
1151  let DecoderMethod = "DecodeSynciR6";
1152}
1153
1154class RDPGPR_MMR6_DESC : MMR6Arch<"rdpgpr">, MipsR6Inst {
1155  dag OutOperandList = (outs GPR32Opnd:$rt);
1156  dag InOperandList = (ins GPR32Opnd:$rd);
1157  string AsmString = !strconcat("rdpgpr", "\t$rt, $rd");
1158  InstrItinClass Itinerary = II_RDPGPR;
1159}
1160
1161class SDBBP_MMR6_DESC : MipsR6Inst {
1162  dag OutOperandList = (outs);
1163  dag InOperandList = (ins uimm20:$code_);
1164  string AsmString = !strconcat("sdbbp", "\t$code_");
1165  list<dag> Pattern = [];
1166  InstrItinClass Itinerary = II_SDBBP;
1167}
1168
1169class SIGRIE_MMR6_DESC : MipsR6Inst {
1170  dag OutOperandList = (outs);
1171  dag InOperandList = (ins uimm16:$code_);
1172  string AsmString = !strconcat("sigrie", "\t$code_");
1173  list<dag> Pattern = [];
1174  InstrItinClass Itinerary = II_SIGRIE;
1175}
1176
1177class LWM16_MMR6_DESC
1178    : MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
1179                      !strconcat("lwm16", "\t$rt, $addr"), [],
1180                      II_LWM, FrmI>,
1181      MMR6Arch<"lwm16"> {
1182  let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
1183  let mayLoad = 1;
1184  ComplexPattern Addr = addr;
1185}
1186
1187class SWM16_MMR6_DESC
1188    : MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
1189                      !strconcat("swm16", "\t$rt, $addr"), [],
1190                      II_SWM, FrmI>,
1191      MMR6Arch<"swm16"> {
1192  let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
1193  let mayStore = 1;
1194  ComplexPattern Addr = addr;
1195}
1196
1197class SB16_MMR6_DESC_BASE<string opstr, DAGOperand RTOpnd, DAGOperand RO,
1198                          SDPatternOperator OpNode, InstrItinClass Itin,
1199                          Operand MemOpnd>
1200    : MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
1201                      !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI>,
1202      MMR6Arch<opstr> {
1203  let DecoderMethod = "DecodeMemMMImm4";
1204  let mayStore = 1;
1205}
1206class SB16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sb16", GPRMM16OpndZero, GPRMM16Opnd,
1207                                           truncstorei8, II_SB, mem_mm_4>;
1208class SH16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sh16", GPRMM16OpndZero, GPRMM16Opnd,
1209                                           truncstorei16, II_SH, mem_mm_4_lsl1>;
1210class SW16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sw16", GPRMM16OpndZero, GPRMM16Opnd,
1211                                           store, II_SW, mem_mm_4_lsl2>;
1212
1213class SWSP_MMR6_DESC
1214    : MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset),
1215                      !strconcat("sw", "\t$rt, $offset"), [], II_SW, FrmI>,
1216      MMR6Arch<"swsp"> {
1217  let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
1218  let mayStore = 1;
1219}
1220
1221class JALRC_HB_MMR6_DESC {
1222  dag OutOperandList = (outs GPR32Opnd:$rt);
1223  dag InOperandList = (ins GPR32Opnd:$rs);
1224  string AsmString = !strconcat("jalrc.hb", "\t$rt, $rs");
1225  list<dag> Pattern = [];
1226  InstrItinClass Itinerary = II_JALR_HB;
1227  Format Form = FrmJ;
1228  bit isIndirectBranch = 1;
1229  bit hasDelaySlot = 0;
1230}
1231
1232class TLBINV_MMR6_DESC_BASE<string opstr, InstrItinClass Itin> {
1233  dag OutOperandList = (outs);
1234  dag InOperandList = (ins);
1235  string AsmString = opstr;
1236  list<dag> Pattern = [];
1237  InstrItinClass Itinerary = Itin;
1238}
1239
1240class TLBINV_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinv", II_TLBINV>;
1241class TLBINVF_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinvf", II_TLBINVF>;
1242
1243class DVPEVP_MMR6_DESC_BASE<string opstr, InstrItinClass Itin> {
1244  dag OutOperandList = (outs GPR32Opnd:$rs);
1245  dag InOperandList = (ins);
1246  string AsmString = !strconcat(opstr, "\t$rs");
1247  list<dag> Pattern = [];
1248  InstrItinClass Itinerary = Itin;
1249  bit hasUnModeledSideEffects = 1;
1250}
1251
1252class DVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"dvp", II_DVP>;
1253class EVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"evp", II_EVP>;
1254
1255class BEQZC_MMR6_DESC
1256    : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21_mm, GPR32Opnd>,
1257      MMR6Arch<"beqzc">;
1258class BNEZC_MMR6_DESC
1259    : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21_mm, GPR32Opnd>,
1260      MMR6Arch<"bnezc">;
1261
1262class BRANCH_COP1_MMR6_DESC_BASE<string opstr> :
1263    InstSE<(outs), (ins FGR64Opnd:$rt, brtarget_mm:$offset),
1264           !strconcat(opstr, "\t$rt, $offset"), [], II_BC1CCZ, FrmI>,
1265    HARDFLOAT, BRANCH_DESC_BASE {
1266  list<Register> Defs = [AT];
1267}
1268
1269class BC1EQZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1eqzc">;
1270class BC1NEZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1nezc">;
1271
1272class BRANCH_COP2_MMR6_DESC_BASE<string opstr, InstrItinClass Itin>
1273    : BRANCH_DESC_BASE {
1274  dag InOperandList = (ins COP2Opnd:$rt, brtarget_mm:$offset);
1275  dag OutOperandList = (outs);
1276  string AsmString = !strconcat(opstr, "\t$rt, $offset");
1277  list<Register> Defs = [AT];
1278  InstrItinClass Itinerary = Itin;
1279}
1280
1281class BC2EQZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2eqzc", II_BC2CCZ>;
1282class BC2NEZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2nezc", II_BC2CCZ>;
1283
1284class EXT_MMR6_DESC {
1285  dag OutOperandList = (outs GPR32Opnd:$rt);
1286  dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$pos, uimm5_plus1:$size);
1287  string AsmString = !strconcat("ext", "\t$rt, $rs, $pos, $size");
1288  list<dag> Pattern = [(set GPR32Opnd:$rt, (MipsExt GPR32Opnd:$rs, imm:$pos,
1289                       imm:$size))];
1290  InstrItinClass Itinerary = II_EXT;
1291  Format Form = FrmR;
1292  string BaseOpcode = "ext";
1293}
1294
1295class INS_MMR6_DESC {
1296  dag OutOperandList = (outs GPR32Opnd:$rt);
1297  dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$pos, uimm5_inssize_plus1:$size,
1298                       GPR32Opnd:$src);
1299  string AsmString = !strconcat("ins", "\t$rt, $rs, $pos, $size");
1300  list<dag> Pattern = [(set GPR32Opnd:$rt, (MipsIns GPR32Opnd:$rs, imm:$pos,
1301                       imm:$size, GPR32Opnd:$src))];
1302  InstrItinClass Itinerary = II_INS;
1303  Format Form = FrmR;
1304  string BaseOpcode = "ins";
1305  string Constraints = "$src = $rt";
1306}
1307
1308class JALRC_MMR6_DESC {
1309  dag OutOperandList = (outs GPR32Opnd:$rt);
1310  dag InOperandList = (ins GPR32Opnd:$rs);
1311  string AsmString = !strconcat("jalrc", "\t$rt, $rs");
1312  list<dag> Pattern = [];
1313  InstrItinClass Itinerary = II_JALRC;
1314  bit isCall = 1;
1315  bit hasDelaySlot = 0;
1316  list<Register> Defs = [RA];
1317}
1318
1319class BOVC_BNVC_MMR6_DESC_BASE<string instr_asm, Operand opnd,
1320                               RegisterOperand GPROpnd>
1321    : BRANCH_DESC_BASE {
1322  dag InOperandList = (ins GPROpnd:$rt, GPROpnd:$rs, opnd:$offset);
1323  dag OutOperandList = (outs);
1324  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $offset");
1325  list<Register> Defs = [AT];
1326  InstrItinClass Itinerary = II_BCCC;
1327}
1328
1329class BOVC_MMR6_DESC : BOVC_BNVC_MMR6_DESC_BASE<"bovc", brtargetr6, GPR32Opnd>;
1330class BNVC_MMR6_DESC : BOVC_BNVC_MMR6_DESC_BASE<"bnvc", brtargetr6, GPR32Opnd>;
1331
1332//===----------------------------------------------------------------------===//
1333//
1334// Instruction Definitions
1335//
1336//===----------------------------------------------------------------------===//
1337
1338let DecoderNamespace = "MicroMipsR6" in {
1339def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
1340def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
1341def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
1342def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
1343                   ISA_MICROMIPS32R6;
1344def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
1345                  ISA_MICROMIPS32R6;
1346def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;
1347def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6;
1348def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6;
1349def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6;
1350def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
1351def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
1352def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
1353def BC16_MMR6 : StdMMR6Rel, BC16_MMR6_DESC, BC16_MMR6_ENC, ISA_MICROMIPS32R6;
1354def BEQZC_MMR6 : R6MMR6Rel, BEQZC_MMR6_ENC, BEQZC_MMR6_DESC,
1355                 ISA_MICROMIPS32R6;
1356def BEQZC16_MMR6 : StdMMR6Rel, BEQZC16_MMR6_DESC, BEQZC16_MMR6_ENC,
1357                   ISA_MICROMIPS32R6;
1358def BNEZC_MMR6 : R6MMR6Rel, BNEZC_MMR6_ENC, BNEZC_MMR6_DESC,
1359                 ISA_MICROMIPS32R6;
1360def BNEZC16_MMR6 : StdMMR6Rel, BNEZC16_MMR6_DESC, BNEZC16_MMR6_ENC,
1361                   ISA_MICROMIPS32R6;
1362def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
1363                   ISA_MICROMIPS32R6;
1364def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
1365                   ISA_MICROMIPS32R6;
1366def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
1367                   ISA_MICROMIPS32R6;
1368def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
1369def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
1370def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
1371def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
1372def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
1373def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
1374def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
1375def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
1376def DI_MMR6 : StdMMR6Rel, DI_MMR6_DESC, DI_MMR6_ENC, ISA_MICROMIPS32R6;
1377def ERET_MMR6 : StdMMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
1378def DERET_MMR6 : StdMMR6Rel, DERET_MMR6_DESC, DERET_MMR6_ENC, ISA_MICROMIPS32R6;
1379def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
1380                  ISA_MICROMIPS32R6;
1381def GINVI_MMR6 : R6MMR6Rel, GINVI_MMR6_ENC, GINVI_MMR6_DESC,
1382                 ISA_MICROMIPS32R6, ASE_GINV;
1383def GINVT_MMR6 : R6MMR6Rel, GINVT_MMR6_ENC, GINVT_MMR6_DESC,
1384                 ISA_MICROMIPS32R6, ASE_GINV;
1385let FastISelShouldIgnore = 1 in
1386def JALRC16_MMR6 : R6MMR6Rel, JALRC16_MMR6_DESC, JALRC16_MMR6_ENC,
1387                   ISA_MICROMIPS32R6;
1388def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
1389def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
1390def JRC16_MMR6 : R6MMR6Rel, JRC16_MMR6_DESC, JRC16_MMR6_ENC, ISA_MICROMIPS32R6;
1391def JRCADDIUSP_MMR6 : R6MMR6Rel, JRCADDIUSP_MMR6_DESC, JRCADDIUSP_MMR6_ENC,
1392                      ISA_MICROMIPS32R6;
1393def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
1394def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
1395def LWM16_MMR6 : StdMMR6Rel, LWM16_MMR6_DESC, LWM16_MMR6_ENC, ISA_MICROMIPS32R6;
1396def MTC0_MMR6 : StdMMR6Rel, MTC0_MMR6_ENC, MTC0_MMR6_DESC, ISA_MICROMIPS32R6;
1397def MTC1_MMR6 : StdMMR6Rel, MTC1_MMR6_DESC, MTC1_MMR6_ENC, ISA_MICROMIPS32R6;
1398def MTC2_MMR6 : StdMMR6Rel, MTC2_MMR6_ENC, MTC2_MMR6_DESC, ISA_MICROMIPS32R6;
1399def MTHC0_MMR6 : R6MMR6Rel, MTHC0_MMR6_ENC, MTHC0_MMR6_DESC, ISA_MICROMIPS32R6;
1400def MTHC2_MMR6 : StdMMR6Rel, MTHC2_MMR6_ENC, MTHC2_MMR6_DESC, ISA_MICROMIPS32R6;
1401def MFC0_MMR6 : StdMMR6Rel, MFC0_MMR6_ENC, MFC0_MMR6_DESC, ISA_MICROMIPS32R6;
1402def MFC1_MMR6 : StdMMR6Rel, MFC1_MMR6_DESC, MFC1_MMR6_ENC, ISA_MICROMIPS32R6;
1403def MFC2_MMR6 : StdMMR6Rel, MFC2_MMR6_ENC, MFC2_MMR6_DESC, ISA_MICROMIPS32R6;
1404def MFHC0_MMR6 : R6MMR6Rel, MFHC0_MMR6_ENC, MFHC0_MMR6_DESC, ISA_MICROMIPS32R6;
1405def MFHC2_MMR6 : StdMMR6Rel, MFHC2_MMR6_ENC, MFHC2_MMR6_DESC, ISA_MICROMIPS32R6;
1406def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
1407def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
1408def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
1409def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
1410def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
1411def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
1412def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
1413def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
1414def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
1415def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
1416def SB16_MMR6 : StdMMR6Rel, SB16_MMR6_DESC, SB16_MMR6_ENC, ISA_MICROMIPS32R6;
1417def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
1418                  ISA_MICROMIPS32R6;
1419def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
1420                  ISA_MICROMIPS32R6;
1421def SH16_MMR6 : StdMMR6Rel, SH16_MMR6_DESC, SH16_MMR6_ENC, ISA_MICROMIPS32R6;
1422def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
1423def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
1424def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
1425def SW16_MMR6 : StdMMR6Rel, SW16_MMR6_DESC, SW16_MMR6_ENC, ISA_MICROMIPS32R6;
1426def SWM16_MMR6 : StdMMR6Rel, SWM16_MMR6_DESC, SWM16_MMR6_ENC, ISA_MICROMIPS32R6;
1427def SWSP_MMR6 : StdMMR6Rel, SWSP_MMR6_DESC, SWSP_MMR6_ENC, ISA_MICROMIPS32R6;
1428def WRPGPR_MMR6 : StdMMR6Rel, WRPGPR_MMR6_ENC, WRPGPR_MMR6_DESC,
1429                  ISA_MICROMIPS32R6;
1430def WSBH_MMR6 : StdMMR6Rel, WSBH_MMR6_ENC, WSBH_MMR6_DESC, ISA_MICROMIPS32R6;
1431def LB_MMR6 : R6MMR6Rel, LB_MMR6_ENC, LB_MMR6_DESC, ISA_MICROMIPS32R6;
1432def LBU_MMR6 : R6MMR6Rel, LBU_MMR6_ENC, LBU_MMR6_DESC, ISA_MICROMIPS32R6;
1433def PAUSE_MMR6 : StdMMR6Rel, PAUSE_MMR6_DESC, PAUSE_MMR6_ENC, ISA_MICROMIPS32R6;
1434def RDHWR_MMR6 : R6MMR6Rel, RDHWR_MMR6_DESC, RDHWR_MMR6_ENC, ISA_MICROMIPS32R6;
1435def WAIT_MMR6 : StdMMR6Rel, WAIT_MMR6_DESC, WAIT_MMR6_ENC, ISA_MICROMIPS32R6;
1436def SSNOP_MMR6 : StdMMR6Rel, SSNOP_MMR6_DESC, SSNOP_MMR6_ENC, ISA_MICROMIPS32R6;
1437def SYNC_MMR6 : StdMMR6Rel, SYNC_MMR6_DESC, SYNC_MMR6_ENC, ISA_MICROMIPS32R6;
1438def SYNCI_MMR6 : StdMMR6Rel, SYNCI_MMR6_DESC, SYNCI_MMR6_ENC, ISA_MICROMIPS32R6;
1439def RDPGPR_MMR6 : R6MMR6Rel, RDPGPR_MMR6_DESC, RDPGPR_MMR6_ENC,
1440                  ISA_MICROMIPS32R6;
1441def SDBBP_MMR6 : R6MMR6Rel, SDBBP_MMR6_DESC, SDBBP_MMR6_ENC, ISA_MICROMIPS32R6;
1442def SIGRIE_MMR6 : R6MMR6Rel, SIGRIE_MMR6_DESC, SIGRIE_MMR6_ENC, ISA_MICROMIPS32R6;
1443def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
1444def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
1445let DecoderMethod = "DecodeMemMMImm16" in {
1446  def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
1447}
1448/// Floating Point Instructions
1449def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
1450                  ISA_MICROMIPS32R6;
1451def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC,
1452                  ISA_MICROMIPS32R6;
1453def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC,
1454                  ISA_MICROMIPS32R6;
1455def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC,
1456                  ISA_MICROMIPS32R6;
1457def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC,
1458                   ISA_MICROMIPS32R6;
1459def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
1460                   ISA_MICROMIPS32R6;
1461def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
1462                   ISA_MICROMIPS32R6;
1463def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
1464                   ISA_MICROMIPS32R6;
1465def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
1466                  ISA_MICROMIPS32R6;
1467def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC,
1468                  ISA_MICROMIPS32R6;
1469def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
1470                  ISA_MICROMIPS32R6;
1471def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
1472def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6;
1473def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6;
1474def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6;
1475def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC,
1476                  ISA_MICROMIPS32R6;
1477def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC,
1478                  ISA_MICROMIPS32R6;
1479def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC,
1480                  ISA_MICROMIPS32R6;
1481def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC,
1482                  ISA_MICROMIPS32R6;
1483def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC,
1484                   ISA_MICROMIPS32R6;
1485def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC,
1486                   ISA_MICROMIPS32R6;
1487def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC,
1488                   ISA_MICROMIPS32R6;
1489def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC,
1490                   ISA_MICROMIPS32R6;
1491def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
1492                   ISA_MICROMIPS32R6;
1493def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
1494                   ISA_MICROMIPS32R6;
1495defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd, II_CMP_CC_S>;
1496defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd, II_CMP_CC_D>;
1497def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
1498                     ISA_MICROMIPS32R6;
1499def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC,
1500                     ISA_MICROMIPS32R6;
1501def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC,
1502                     ISA_MICROMIPS32R6;
1503def FLOOR_W_D_MMR6 : StdMMR6Rel, FLOOR_W_D_MMR6_ENC, FLOOR_W_D_MMR6_DESC,
1504                     ISA_MICROMIPS32R6;
1505def CEIL_L_S_MMR6 : StdMMR6Rel, CEIL_L_S_MMR6_ENC, CEIL_L_S_MMR6_DESC,
1506                    ISA_MICROMIPS32R6;
1507def CEIL_L_D_MMR6 : StdMMR6Rel, CEIL_L_D_MMR6_ENC, CEIL_L_D_MMR6_DESC,
1508                    ISA_MICROMIPS32R6;
1509def CEIL_W_S_MMR6 : StdMMR6Rel, CEIL_W_S_MMR6_ENC, CEIL_W_S_MMR6_DESC,
1510                    ISA_MICROMIPS32R6;
1511def CEIL_W_D_MMR6 : StdMMR6Rel, CEIL_W_D_MMR6_ENC, CEIL_W_D_MMR6_DESC,
1512                    ISA_MICROMIPS32R6;
1513def TRUNC_L_S_MMR6 : StdMMR6Rel, TRUNC_L_S_MMR6_ENC, TRUNC_L_S_MMR6_DESC,
1514                     ISA_MICROMIPS32R6;
1515def TRUNC_L_D_MMR6 : StdMMR6Rel, TRUNC_L_D_MMR6_ENC, TRUNC_L_D_MMR6_DESC,
1516                     ISA_MICROMIPS32R6;
1517def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC,
1518                     ISA_MICROMIPS32R6;
1519def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC,
1520                     ISA_MICROMIPS32R6;
1521def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
1522def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
1523def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6;
1524def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6;
1525def ADDU16_MMR6 : StdMMR6Rel, ADDU16_MMR6_DESC, ADDU16_MMR6_ENC,
1526                  ISA_MICROMIPS32R6;
1527def AND16_MMR6 : StdMMR6Rel, AND16_MMR6_DESC, AND16_MMR6_ENC,
1528                  ISA_MICROMIPS32R6;
1529def ANDI16_MMR6 : StdMMR6Rel, ANDI16_MMR6_DESC, ANDI16_MMR6_ENC,
1530                  ISA_MICROMIPS32R6;
1531def NOT16_MMR6 : StdMMR6Rel, NOT16_MMR6_DESC, NOT16_MMR6_ENC,
1532                  ISA_MICROMIPS32R6;
1533def OR16_MMR6 : StdMMR6Rel, OR16_MMR6_DESC, OR16_MMR6_ENC,
1534                  ISA_MICROMIPS32R6;
1535def SLL16_MMR6 : StdMMR6Rel, SLL16_MMR6_DESC, SLL16_MMR6_ENC,
1536                  ISA_MICROMIPS32R6;
1537def SRL16_MMR6 : StdMMR6Rel, SRL16_MMR6_DESC, SRL16_MMR6_ENC,
1538                  ISA_MICROMIPS32R6;
1539def BREAK16_MMR6 : StdMMR6Rel, BREAK16_MMR6_DESC, BREAK16_MMR6_ENC,
1540                   ISA_MICROMIPS32R6;
1541def LI16_MMR6 : StdMMR6Rel, LI16_MMR6_DESC, LI16_MMR6_ENC,
1542                ISA_MICROMIPS32R6;
1543def MOVE16_MMR6 : StdMMR6Rel, MOVE16_MMR6_DESC, MOVE16_MMR6_ENC,
1544                  ISA_MICROMIPS32R6;
1545def MOVEP_MMR6  : StdMMR6Rel, MOVEP_MMR6_DESC, MOVEP_MMR6_ENC,
1546                  ISA_MICROMIPS32R6;
1547def SDBBP16_MMR6 : StdMMR6Rel, SDBBP16_MMR6_DESC, SDBBP16_MMR6_ENC,
1548                   ISA_MICROMIPS32R6;
1549def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC,
1550                  ISA_MICROMIPS32R6;
1551def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC,
1552                 ISA_MICROMIPS32R6;
1553def JALRC_HB_MMR6 : R6MMR6Rel, JALRC_HB_MMR6_ENC, JALRC_HB_MMR6_DESC,
1554                    ISA_MICROMIPS32R6;
1555def EXT_MMR6 : StdMMR6Rel, EXT_MMR6_ENC, EXT_MMR6_DESC, ISA_MICROMIPS32R6;
1556def INS_MMR6 : StdMMR6Rel, INS_MMR6_ENC, INS_MMR6_DESC, ISA_MICROMIPS32R6;
1557def JALRC_MMR6 : R6MMR6Rel, JALRC_MMR6_ENC, JALRC_MMR6_DESC, ISA_MICROMIPS32R6;
1558def RINT_S_MMR6 : StdMMR6Rel, RINT_S_MMR6_ENC, RINT_S_MMR6_DESC,
1559                  ISA_MICROMIPS32R6;
1560def RINT_D_MMR6 : StdMMR6Rel, RINT_D_MMR6_ENC, RINT_D_MMR6_DESC, ISA_MICROMIPS32R6;
1561def ROUND_L_S_MMR6 : StdMMR6Rel, ROUND_L_S_MMR6_ENC, ROUND_L_S_MMR6_DESC,
1562                     ISA_MICROMIPS32R6;
1563def ROUND_L_D_MMR6 : StdMMR6Rel, ROUND_L_D_MMR6_ENC, ROUND_L_D_MMR6_DESC,
1564                     ISA_MICROMIPS32R6;
1565def ROUND_W_S_MMR6 : StdMMR6Rel, ROUND_W_S_MMR6_ENC, ROUND_W_S_MMR6_DESC,
1566                     ISA_MICROMIPS32R6;
1567def ROUND_W_D_MMR6 : StdMMR6Rel, ROUND_W_D_MMR6_ENC, ROUND_W_D_MMR6_DESC,
1568                     ISA_MICROMIPS32R6;
1569def SEL_S_MMR6 : R6MMR6Rel, SEL_S_MMR6_ENC, SEL_S_MMR6_DESC, ISA_MICROMIPS32R6;
1570def SEL_D_MMR6 : R6MMR6Rel, SEL_D_MMR6_ENC, SEL_D_MMR6_DESC, ISA_MICROMIPS32R6;
1571def SELEQZ_S_MMR6 : R6MMR6Rel, SELEQZ_S_MMR6_ENC, SELEQZ_S_MMR6_DESC,
1572                    ISA_MICROMIPS32R6;
1573def SELEQZ_D_MMR6 : R6MMR6Rel, SELEQZ_D_MMR6_ENC, SELEQZ_D_MMR6_DESC,
1574                    ISA_MICROMIPS32R6;
1575def SELNEZ_S_MMR6 : R6MMR6Rel, SELNEZ_S_MMR6_ENC, SELNEZ_S_MMR6_DESC,
1576                    ISA_MICROMIPS32R6;
1577def SELNEZ_D_MMR6 : R6MMR6Rel, SELNEZ_D_MMR6_ENC, SELNEZ_D_MMR6_DESC,
1578                    ISA_MICROMIPS32R6;
1579def CLASS_S_MMR6 : StdMMR6Rel, CLASS_S_MMR6_ENC, CLASS_S_MMR6_DESC,
1580                   ISA_MICROMIPS32R6;
1581def CLASS_D_MMR6 : StdMMR6Rel, CLASS_D_MMR6_ENC, CLASS_D_MMR6_DESC,
1582                   ISA_MICROMIPS32R6;
1583def TLBINV_MMR6 : StdMMR6Rel, TLBINV_MMR6_ENC, TLBINV_MMR6_DESC,
1584                  ISA_MICROMIPS32R6;
1585def TLBINVF_MMR6 : StdMMR6Rel, TLBINVF_MMR6_ENC, TLBINVF_MMR6_DESC,
1586                   ISA_MICROMIPS32R6;
1587def DVP_MMR6 : R6MMR6Rel, DVP_MMR6_ENC, DVP_MMR6_DESC, ISA_MICROMIPS32R6;
1588def EVP_MMR6 : R6MMR6Rel, EVP_MMR6_ENC, EVP_MMR6_DESC, ISA_MICROMIPS32R6;
1589def BC1EQZC_MMR6 : R6MMR6Rel, BC1EQZC_MMR6_DESC, BC1EQZC_MMR6_ENC,
1590                   ISA_MICROMIPS32R6;
1591def BC1NEZC_MMR6 : R6MMR6Rel, BC1NEZC_MMR6_DESC, BC1NEZC_MMR6_ENC,
1592                   ISA_MICROMIPS32R6;
1593def BC2EQZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2EQZC_MMR6_ENC, BC2EQZC_MMR6_DESC,
1594                   ISA_MICROMIPS32R6;
1595def BC2NEZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2NEZC_MMR6_ENC, BC2NEZC_MMR6_DESC,
1596                   ISA_MICROMIPS32R6;
1597let DecoderNamespace = "MicroMipsFP64" in {
1598  def LDC1_D64_MMR6 : StdMMR6Rel, LDC1_D64_MMR6_DESC, LDC1_MMR6_ENC,
1599                      ISA_MICROMIPS32R6 {
1600    let BaseOpcode = "LDC164";
1601  }
1602  def SDC1_D64_MMR6 : StdMMR6Rel, SDC1_D64_MMR6_DESC, SDC1_MMR6_ENC,
1603                      ISA_MICROMIPS32R6;
1604}
1605def LDC2_MMR6 : StdMMR6Rel, LDC2_MMR6_ENC, LDC2_MMR6_DESC, ISA_MICROMIPS32R6;
1606def SDC2_MMR6 : StdMMR6Rel, SDC2_MMR6_ENC, SDC2_MMR6_DESC, ISA_MICROMIPS32R6;
1607def LWC2_MMR6 : StdMMR6Rel, LWC2_MMR6_ENC, LWC2_MMR6_DESC, ISA_MICROMIPS32R6;
1608def SWC2_MMR6 : StdMMR6Rel, SWC2_MMR6_ENC, SWC2_MMR6_DESC, ISA_MICROMIPS32R6;
1609def LL_MMR6   : R6MMR6Rel, LL_MMR6_ENC, LL_MMR6_DESC, ISA_MICROMIPS32R6;
1610def SC_MMR6   : R6MMR6Rel, SC_MMR6_ENC, SC_MMR6_DESC, ISA_MICROMIPS32R6;
1611}
1612
1613def BOVC_MMR6 : R6MMR6Rel, BOVC_MMR6_ENC, BOVC_MMR6_DESC, ISA_MICROMIPS32R6,
1614                MMDecodeDisambiguatedBy<"POP35GroupBranchMMR6">;
1615def BNVC_MMR6 : R6MMR6Rel, BNVC_MMR6_ENC, BNVC_MMR6_DESC, ISA_MICROMIPS32R6,
1616                MMDecodeDisambiguatedBy<"POP37GroupBranchMMR6">;
1617def BGEC_MMR6 : R6MMR6Rel, BGEC_MMR6_ENC, BGEC_MMR6_DESC, ISA_MICROMIPS32R6;
1618def BGEUC_MMR6 : R6MMR6Rel, BGEUC_MMR6_ENC, BGEUC_MMR6_DESC, ISA_MICROMIPS32R6;
1619def BLTC_MMR6 : R6MMR6Rel, BLTC_MMR6_ENC, BLTC_MMR6_DESC, ISA_MICROMIPS32R6;
1620def BLTUC_MMR6 : R6MMR6Rel, BLTUC_MMR6_ENC, BLTUC_MMR6_DESC, ISA_MICROMIPS32R6;
1621def BEQC_MMR6 : R6MMR6Rel, BEQC_MMR6_ENC, BEQC_MMR6_DESC, ISA_MICROMIPS32R6,
1622                DecodeDisambiguates<"POP35GroupBranchMMR6">;
1623def BNEC_MMR6 : R6MMR6Rel, BNEC_MMR6_ENC, BNEC_MMR6_DESC, ISA_MICROMIPS32R6,
1624                DecodeDisambiguates<"POP37GroupBranchMMR6">;
1625def BLTZC_MMR6 : R6MMR6Rel, BLTZC_MMR6_ENC, BLTZC_MMR6_DESC, ISA_MICROMIPS32R6;
1626def BLEZC_MMR6 : R6MMR6Rel, BLEZC_MMR6_ENC, BLEZC_MMR6_DESC, ISA_MICROMIPS32R6;
1627def BGEZC_MMR6 : R6MMR6Rel, BGEZC_MMR6_ENC, BGEZC_MMR6_DESC, ISA_MICROMIPS32R6;
1628def BGTZC_MMR6 : R6MMR6Rel, BGTZC_MMR6_ENC, BGTZC_MMR6_DESC, ISA_MICROMIPS32R6;
1629def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
1630                   ISA_MICROMIPS32R6;
1631def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
1632                   ISA_MICROMIPS32R6;
1633def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
1634                   ISA_MICROMIPS32R6;
1635def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
1636                   ISA_MICROMIPS32R6;
1637
1638//===----------------------------------------------------------------------===//
1639//
1640// MicroMips instruction aliases
1641//
1642//===----------------------------------------------------------------------===//
1643
1644def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
1645def : MipsInstAlias<"di", (DI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
1646def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
1647def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
1648                                      !strconcat("b", "\t$offset")> {
1649  string DecoderNamespace = "MicroMipsR6";
1650}
1651def : MipsInstAlias<"sync", (SYNC_MMR6 0), 1>, ISA_MICROMIPS32R6;
1652def : MipsInstAlias<"sdbbp", (SDBBP_MMR6 0), 1>, ISA_MICROMIPS32R6;
1653def : MipsInstAlias<"sigrie", (SIGRIE_MMR6 0), 1>, ISA_MICROMIPS32R6;
1654def : MipsInstAlias<"rdhwr $rt, $rs",
1655                    (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>,
1656                    ISA_MICROMIPS32R6;
1657def : MipsInstAlias<"mtc0 $rt, $rs",
1658                    (MTC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
1659                    ISA_MICROMIPS32R6;
1660def : MipsInstAlias<"mthc0 $rt, $rs",
1661                    (MTHC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
1662                    ISA_MICROMIPS32R6;
1663def : MipsInstAlias<"mfc0 $rt, $rs",
1664                    (MFC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
1665                    ISA_MICROMIPS32R6;
1666def : MipsInstAlias<"mfhc0 $rt, $rs",
1667                    (MFHC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
1668                    ISA_MICROMIPS32R6;
1669def : MipsInstAlias<"jalrc.hb $rs", (JALRC_HB_MMR6 RA, GPR32Opnd:$rs), 1>,
1670                    ISA_MICROMIPS32R6;
1671def : MipsInstAlias<"jal $offset", (BALC_MMR6 brtarget26_mm:$offset), 0>,
1672                    ISA_MICROMIPS32R6;
1673def : MipsInstAlias<"dvp", (DVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
1674def : MipsInstAlias<"evp", (EVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
1675def : MipsInstAlias<"jalrc $rs", (JALRC_MMR6 RA, GPR32Opnd:$rs), 1>,
1676      ISA_MICROMIPS32R6;
1677def : MipsInstAlias<"and $rs, $rt, $imm",
1678                    (ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
1679                    ISA_MICROMIPS32R6;
1680def : MipsInstAlias<"and $rs, $imm",
1681                    (ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
1682                    ISA_MICROMIPS32R6;
1683def : MipsInstAlias<"or $rs, $rt, $imm",
1684                    (ORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
1685                    ISA_MICROMIPS32R6;
1686def : MipsInstAlias<"or $rs, $imm",
1687                    (ORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
1688                    ISA_MICROMIPS32R6;
1689def : MipsInstAlias<"xor $rs, $rt, $imm",
1690                    (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
1691                    ISA_MICROMIPS32R6;
1692def : MipsInstAlias<"xor $rs, $imm",
1693                    (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
1694                    ISA_MICROMIPS32R6;
1695def : MipsInstAlias<"not $rt, $rs",
1696                    (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>,
1697                    ISA_MICROMIPS32R6;
1698def : MipsInstAlias<"not $rt",
1699                    (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>,
1700                    ISA_MICROMIPS32R6;
1701def : MipsInstAlias<"lapc $rd, $imm",
1702                    (ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm)>,
1703                    ISA_MICROMIPS32R6;
1704def : MipsInstAlias<"neg $rt, $rs",
1705                    (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
1706      ISA_MICROMIPS32R6;
1707def : MipsInstAlias<"neg $rt",
1708                    (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
1709      ISA_MICROMIPS32R6;
1710def : MipsInstAlias<"negu $rt, $rs",
1711                    (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
1712      ISA_MICROMIPS32R6;
1713def : MipsInstAlias<"negu $rt",
1714                    (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
1715      ISA_MICROMIPS32R6;
1716def : MipsInstAlias<"beqz16 $rs, $offset", (BEQZC16_MMR6 GPRMM16Opnd:$rs,
1717                                                         brtarget7_mm:$offset),
1718                    0>, ISA_MICROMIPS32R6;
1719def : MipsInstAlias<"bnez16 $rs, $offset", (BNEZC16_MMR6 GPRMM16Opnd:$rs,
1720                                                         brtarget7_mm:$offset),
1721                    0>, ISA_MICROMIPS32R6;
1722def : MipsInstAlias<"b16 $offset", (BC16_MMR6 brtarget10_mm:$offset), 0>,
1723                    ISA_MICROMIPS32R6;
1724
1725//===----------------------------------------------------------------------===//
1726//
1727// MicroMips arbitrary patterns that map to one or more instructions
1728//
1729//===----------------------------------------------------------------------===//
1730
1731def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
1732              (SW16_MMR6 GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS32R6;
1733def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1734              (SUBU_MMR6 GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS32R6;
1735
1736def : MipsPat<(select i32:$cond, i32:$t, i32:$f),
1737              (OR_MM (SELNEZ_MMR6 i32:$t, i32:$cond),
1738                     (SELEQZ_MMR6 i32:$f, i32:$cond))>,
1739              ISA_MICROMIPS32R6;
1740def : MipsPat<(select i32:$cond, i32:$t, immz),
1741              (SELNEZ_MMR6 i32:$t, i32:$cond)>,
1742              ISA_MICROMIPS32R6;
1743def : MipsPat<(select i32:$cond, immz, i32:$f),
1744              (SELEQZ_MMR6 i32:$f, i32:$cond)>,
1745              ISA_MICROMIPS32R6;
1746
1747defm : SelectInt_Pats<i32, OR_MM, XORI_MMR6, SLTi_MM, SLTiu_MM, SELEQZ_MMR6,
1748                      SELNEZ_MMR6, immZExt16, i32>, ISA_MICROMIPS32R6;
1749
1750defm S_MMR6 : Cmp_Pats<f32, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6;
1751defm D_MMR6 : Cmp_Pats<f64, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6;
1752
1753def : MipsPat<(f32 fpimm0), (MTC1_MMR6 ZERO)>, ISA_MICROMIPS32R6;
1754def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6 (MTC1_MMR6 ZERO))>, ISA_MICROMIPS32R6;
1755def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
1756              (TRUNC_W_D_MMR6 FGR64Opnd:$src)>, ISA_MICROMIPS32R6;
1757def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
1758              (TRUNC_W_S_MMR6 FGR32Opnd:$src)>, ISA_MICROMIPS32R6;
1759
1760def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
1761              (ANDI16_MMR6 GPRMM16:$src, immZExtAndi16:$imm)>,
1762              ISA_MICROMIPS32R6;
1763def : MipsPat<(and GPR32:$src, immZExt16:$imm),
1764              (ANDI_MMR6 GPR32:$src, immZExt16:$imm)>, ISA_MICROMIPS32R6;
1765def : MipsPat<(i32 immZExt16:$imm),
1766              (XORI_MMR6 ZERO, immZExt16:$imm)>, ISA_MICROMIPS32R6;
1767def : MipsPat<(not GPRMM16:$in),
1768              (NOT16_MMR6 GPRMM16:$in)>, ISA_MICROMIPS32R6;
1769def : MipsPat<(not GPR32:$in),
1770              (NOR_MMR6 GPR32Opnd:$in, ZERO)>, ISA_MICROMIPS32R6;
1771// Patterns for load with a reg+imm operand.
1772let AddedComplexity = 41 in {
1773  def : LoadRegImmPat<LDC1_D64_MMR6, f64, load>, FGR_64, ISA_MICROMIPS32R6;
1774  def : StoreRegImmPat<SDC1_D64_MMR6, f64>, FGR_64, ISA_MICROMIPS32R6;
1775}
1776
1777let isCall=1, hasDelaySlot=0, isCTI=1, Defs = [RA] in {
1778  class JumpLinkMMR6<Instruction JumpInst, DAGOperand Opnd> :
1779    PseudoSE<(outs), (ins calltarget:$target), [], II_JAL>,
1780    PseudoInstExpansion<(JumpInst Opnd:$target)>;
1781}
1782
1783def JAL_MMR6 : JumpLinkMMR6<BALC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6;
1784
1785def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1786              (JAL_MMR6 texternalsym:$dst)>, ISA_MICROMIPS32R6;
1787def : MipsPat<(MipsJmpLink (iPTR tglobaladdr:$dst)),
1788              (JAL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6;
1789
1790def TAILCALL_MMR6 : TailCall<BC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6;
1791
1792def TAILCALLREG_MMR6  : TailCallReg<JRC16_MM, GPR32Opnd>, ISA_MICROMIPS32R6;
1793
1794def PseudoIndirectBranch_MMR6 : PseudoIndirectBranchBase<JRC16_MMR6,
1795                                                         GPR32Opnd>,
1796                                ISA_MICROMIPS32R6;
1797
1798def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1799              (TAILCALL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6;
1800
1801def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1802              (TAILCALL_MMR6 texternalsym:$dst)>, ISA_MICROMIPS32R6;
1803
1804
1805def : MipsPat<(brcond (i32 (setne GPR32:$lhs, 0)), bb:$dst),
1806              (BNEZC_MMR6 GPR32:$lhs, bb:$dst)>, ISA_MICROMIPS32R6;
1807def : MipsPat<(brcond (i32 (seteq GPR32:$lhs, 0)), bb:$dst),
1808              (BEQZC_MMR6 GPR32:$lhs, bb:$dst)>, ISA_MICROMIPS32R6;
1809
1810def : MipsPat<(brcond (i32 (setge GPR32:$lhs, GPR32:$rhs)), bb:$dst),
1811              (BEQZC_MMR6 (SLT_MM GPR32:$lhs, GPR32:$rhs), bb:$dst)>,
1812      ISA_MICROMIPS32R6;
1813def : MipsPat<(brcond (i32 (setuge GPR32:$lhs, GPR32:$rhs)), bb:$dst),
1814              (BEQZC_MMR6 (SLTu_MM GPR32:$lhs, GPR32:$rhs), bb:$dst)>,
1815      ISA_MICROMIPS32R6;
1816def : MipsPat<(brcond (i32 (setge GPR32:$lhs, immSExt16:$rhs)), bb:$dst),
1817              (BEQZC_MMR6 (SLTi_MM GPR32:$lhs, immSExt16:$rhs), bb:$dst)>,
1818      ISA_MICROMIPS32R6;
1819def : MipsPat<(brcond (i32 (setuge GPR32:$lhs, immSExt16:$rhs)), bb:$dst),
1820              (BEQZC_MMR6 (SLTiu_MM GPR32:$lhs, immSExt16:$rhs), bb:$dst)>,
1821      ISA_MICROMIPS32R6;
1822def : MipsPat<(brcond (i32 (setgt GPR32:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1823              (BEQZC_MMR6 (SLTi_MM GPR32:$lhs, (Plus1 imm:$rhs)), bb:$dst)>,
1824      ISA_MICROMIPS32R6;
1825def : MipsPat<(brcond (i32 (setugt GPR32:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1826              (BEQZC_MMR6 (SLTiu_MM GPR32:$lhs, (Plus1 imm:$rhs)), bb:$dst)>,
1827      ISA_MICROMIPS32R6;
1828
1829def : MipsPat<(brcond (i32 (setle GPR32:$lhs, GPR32:$rhs)), bb:$dst),
1830              (BEQZC_MMR6  (SLT_MM GPR32:$rhs, GPR32:$lhs), bb:$dst)>,
1831      ISA_MICROMIPS32R6;
1832def : MipsPat<(brcond (i32 (setule GPR32:$lhs, GPR32:$rhs)), bb:$dst),
1833              (BEQZC_MMR6  (SLTu_MM GPR32:$rhs, GPR32:$lhs), bb:$dst)>,
1834      ISA_MICROMIPS32R6;
1835
1836def : MipsPat<(brcond GPR32:$cond, bb:$dst),
1837              (BNEZC_MMR6 GPR32:$cond, bb:$dst)>, ISA_MICROMIPS32R6;
1838