xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td (revision 1165fc9a526630487a1feb63daef65c5aee1a583) 
1//=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes microMIPSr6 instructions.
10//
11//===----------------------------------------------------------------------===//
12
13def brtarget21_mm : Operand<OtherVT> {
14  let EncoderMethod = "getBranchTarget21OpValueMM";
15  let OperandType = "OPERAND_PCREL";
16  let DecoderMethod = "DecodeBranchTarget21MM";
17  let ParserMatchClass = MipsJumpTargetAsmOperand;
18}
19
20def brtarget26_mm : Operand<OtherVT> {
21  let EncoderMethod = "getBranchTarget26OpValueMM";
22  let OperandType = "OPERAND_PCREL";
23  let DecoderMethod = "DecodeBranchTarget26MM";
24  let ParserMatchClass = MipsJumpTargetAsmOperand;
25}
26
27def brtargetr6 : Operand<OtherVT> {
28  let EncoderMethod = "getBranchTargetOpValueMMR6";
29  let OperandType = "OPERAND_PCREL";
30  let DecoderMethod = "DecodeBranchTargetMM";
31  let ParserMatchClass = MipsJumpTargetAsmOperand;
32}
33
34def brtarget_lsl2_mm : Operand<OtherVT> {
35  let EncoderMethod = "getBranchTargetOpValueLsl2MMR6";
36  let OperandType = "OPERAND_PCREL";
37  // Instructions that use this operand have their decoder method
38  // set with DecodeDisambiguates
39  let DecoderMethod = "";
40  let ParserMatchClass = MipsJumpTargetAsmOperand;
41}
42
43//===----------------------------------------------------------------------===//
44//
45// Instruction Encodings
46//
47//===----------------------------------------------------------------------===//
48class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
49class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
50class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
51class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
52class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
53class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>;
54class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
55class AUIPC_MMR6_ENC  : PCREL16_FM_MMR6<0b11110>;
56class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>;
57class AUI_MMR6_ENC : AUI_FM_MMR6;
58class BALC_MMR6_ENC  : BRANCH_OFF26_FM<0b101101>;
59class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
60class BC16_MMR6_ENC : BC16_FM_MM16R6;
61class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>;
62class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>;
63class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
64class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
65class BEQZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<0b100000>;
66class BNEZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<0b101000>;
67class BGEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgec", 0b111101>,
68                      DecodeDisambiguates<"POP75GroupBranchMMR6">;
69class BGEUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgeuc", 0b110000>,
70                       DecodeDisambiguates<"BlezGroupBranchMMR6">;
71class BLTC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltc", 0b110101>,
72                      DecodeDisambiguates<"POP65GroupBranchMMR6">;
73class BLTUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltuc", 0b111000>,
74                       DecodeDisambiguates<"BgtzGroupBranchMMR6">;
75class BEQC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"beqc", 0b011101>;
76class BNEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bnec", 0b011111>;
77class BLTZC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bltzc", 0b110101>,
78                       DecodeDisambiguates<"POP65GroupBranchMMR6">;
79class BLEZC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"blezc", 0b111101>,
80                       DecodeDisambiguates<"POP75GroupBranchMMR6">;
81class BGEZC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bgezc", 0b111101>,
82                       DecodeDisambiguates<"POP75GroupBranchMMR6">;
83class BGTZC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bgtzc", 0b110101>,
84                       DecodeDisambiguates<"POP65GroupBranchMMR6">;
85class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"beqzalc", 0b011101>,
86                         DecodeDisambiguates<"POP35GroupBranchMMR6">;
87class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bnezalc", 0b011111>,
88                         DecodeDisambiguates<"POP37GroupBranchMMR6">;
89class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bgtzalc", 0b111000>,
90                         MMDecodeDisambiguatedBy<"BgtzGroupBranchMMR6">;
91class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bltzalc", 0b111000>,
92                         MMDecodeDisambiguatedBy<"BgtzGroupBranchMMR6">;
93class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bgezalc", 0b110000>,
94                         MMDecodeDisambiguatedBy<"BlezGroupBranchMMR6">;
95class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"blezalc", 0b110000>,
96                         MMDecodeDisambiguatedBy<"BlezGroupBranchMMR6">;
97class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
98class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
99class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
100class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
101class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
102class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
103class EI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"ei", 0x15d>;
104class DI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"di", 0b0100011101>;
105class ERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0x3cd>;
106class DERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0b1110001101>;
107class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
108class GINVI_MMR6_ENC : POOL32A_GINV_FM_MMR6<"ginvi", 0b00>;
109class GINVT_MMR6_ENC : POOL32A_GINV_FM_MMR6<"ginvt", 0b10>;
110class JALRC16_MMR6_ENC : POOL16C_JALRC_FM_MM16R6<0xb>;
111class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
112class JIC_MMR6_ENC   : JMP_IDX_COMPACT_FM<0b101000>;
113class JRC16_MMR6_ENC: POOL16C_JALRC_FM_MM16R6<0x3>;
114class JRCADDIUSP_MMR6_ENC : POOL16C_JRCADDIUSP_FM_MM16R6<0x13>;
115class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
116class LWPC_MMR6_ENC  : PCREL19_FM_MMR6<0b01>;
117class LWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0x2>;
118class MFC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfc0", 0b00011, 0b111100>;
119class MFC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mfc1", 0b10000000>;
120class MFC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfc2", 0b0100110100>;
121class MFHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfhc0", 0b00011, 0b110100>;
122class MFHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfhc2", 0b1000110100>;
123class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
124class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
125class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
126class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
127class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
128class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
129class MTC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mtc0", 0b01011, 0b111100>;
130class MTC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mtc1", 0b10100000>;
131class MTC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mtc2", 0b0101110100>;
132class MTHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mthc0", 0b01011, 0b110100>;
133class MTHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mthc2", 0b1001110100>;
134class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
135class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
136class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
137class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
138class SB16_MMR6_ENC : LOAD_STORE_FM_MM16<0x22>;
139class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
140class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
141class SH16_MMR6_ENC : LOAD_STORE_FM_MM16<0x2a>;
142class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
143class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
144class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
145class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
146class SW16_MMR6_ENC : LOAD_STORE_FM_MM16<0x3a>;
147class SWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0xa>;
148class SWSP_MMR6_ENC : LOAD_STORE_SP_FM_MM16<0x32>;
149class WRPGPR_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<"wrpgpr", 0x3c5>;
150class WSBH_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<"wsbh", 0x1ec>;
151class LB_MMR6_ENC : LB32_FM_MMR6;
152class LBU_MMR6_ENC : LBU32_FM_MMR6;
153class PAUSE_MMR6_ENC : POOL32A_PAUSE_FM_MMR6<"pause", 0b00101>;
154class RDHWR_MMR6_ENC : POOL32A_RDHWR_FM_MMR6;
155class WAIT_MMR6_ENC : WAIT_FM_MM, MMR6Arch<"wait">;
156class SSNOP_MMR6_ENC : BARRIER_FM_MM<0x1>, MMR6Arch<"ssnop">;
157class SYNC_MMR6_ENC : POOL32A_SYNC_FM_MMR6;
158class SYNCI_MMR6_ENC : POOL32I_SYNCI_FM_MMR6, MMR6Arch<"synci">;
159class RDPGPR_MMR6_ENC : POOL32A_RDPGPR_FM_MMR6<0b1110000101>;
160class SDBBP_MMR6_ENC : SDBBP_FM_MM, MMR6Arch<"sdbbp">;
161class SIGRIE_MMR6_ENC : SIGRIE_FM_MM, MMR6Arch<"sigrie">;
162class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
163class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
164class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
165class ABS_D_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.d", 1, 0b0001101>;
166class FLOOR_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.s", 0, 0b00001100>;
167class FLOOR_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.d", 1, 0b00001100>;
168class FLOOR_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.s", 0, 0b00101100>;
169class FLOOR_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.d", 1, 0b00101100>;
170class CEIL_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.s", 0, 0b01001100>;
171class CEIL_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.d", 1, 0b01001100>;
172class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>;
173class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>;
174class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>;
175class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>;
176class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
177class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
178class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
179class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
180class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
181class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
182class JALRC_HB_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc.hb", 0b0001111100>;
183class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>;
184class RINT_D_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.d", 1>;
185class ROUND_L_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.s", 0,
186                                                       0b11001100>;
187class ROUND_L_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.d", 1,
188                                                       0b11001100>;
189class ROUND_W_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.s", 0,
190                                                       0b11101100>;
191class ROUND_W_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.d", 1,
192                                                       0b11101100>;
193class SEL_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.s", 0, 0b010111000>;
194class SEL_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.d", 1, 0b010111000>;
195class SELEQZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.s", 0, 0b000111000>;
196class SELEQZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.d", 1, 0b000111000>;
197class SELNEZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selnez.s", 0, 0b001111000>;
198class SELNEZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selnez.d", 1, 0b001111000>;
199class CLASS_S_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.s", 0, 0b001100000>;
200class CLASS_D_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.d", 1, 0b001100000>;
201class EXT_MMR6_ENC : POOL32A_EXT_INS_FM_MMR6<"ext", 0b101100>;
202class INS_MMR6_ENC : POOL32A_EXT_INS_FM_MMR6<"ins", 0b001100>;
203class JALRC_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc", 0b0000111100>;
204class BOVC_MMR6_ENC : POP35_BOVC_FM_MMR6<"bovc">;
205class BNVC_MMR6_ENC : POP37_BNVC_FM_MMR6<"bnvc">;
206class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6;
207class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6;
208class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>;
209class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6;
210class OR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1001>;
211class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>;
212class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>;
213class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>;
214class LI16_MMR6_ENC : LI_FM_MM16;
215class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
216class MOVEP_MMR6_ENC  : POOL16C_MOVEP16_FM_MMR6;
217class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
218class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
219class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
220class TLBINV_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinv", 0x10d>;
221class TLBINVF_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinvf", 0x14d>;
222class DVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"dvp", 0b0001100101>;
223class EVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"evp", 0b0011100101>;
224class BC1EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1eqzc", 0b01000>;
225class BC1NEZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1nezc", 0b01001>;
226class BC2EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc2eqzc", 0b01010>;
227class BC2NEZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc2nezc", 0b01011>;
228class LDC1_MMR6_ENC : LDWC1_SDWC1_FM_MMR6<"ldc1", 0b101111>;
229class SDC1_MMR6_ENC : LDWC1_SDWC1_FM_MMR6<"sdc1", 0b101110>;
230class LDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"ldc2", 0b0010>;
231class SDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"sdc2", 0b1010>;
232class LWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"lwc2", 0b0000>;
233class SWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"swc2", 0b1000>;
234
235class LL_MMR6_ENC  : POOL32C_LL_E_SC_E_FM_MMR6<"ll", 0b0011, 0b000>;
236class SC_MMR6_ENC  : POOL32C_LL_E_SC_E_FM_MMR6<"sc", 0b1011, 0b000>;
237
238/// Floating Point Instructions
239class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
240class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
241class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
242class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
243class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
244class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
245class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
246class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
247class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
248class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
249class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
250class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
251class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
252class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>;
253class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>;
254class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>;
255class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>;
256class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>;
257class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>;
258
259class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>;
260class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>;
261class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>;
262class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>;
263class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>;
264class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>;
265
266//===----------------------------------------------------------------------===//
267//
268// Instruction Descriptions
269//
270//===----------------------------------------------------------------------===//
271
272class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
273                                  RegisterOperand GPROpnd>
274    : BRANCH_DESC_BASE {
275  dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
276  dag OutOperandList = (outs);
277  string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
278  list<Register> Defs = [AT];
279  InstrItinClass Itinerary = II_BCCZC;
280}
281
282class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
283                                                      GPR32Opnd> {
284  list<Register> Defs = [RA];
285}
286
287class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
288                                                      GPR32Opnd> {
289  list<Register> Defs = [RA];
290}
291
292class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
293                                                      GPR32Opnd> {
294  list<Register> Defs = [RA];
295}
296
297class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
298                                                      GPR32Opnd> {
299  list<Register> Defs = [RA];
300}
301
302class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
303                                                      GPR32Opnd> {
304  list<Register> Defs = [RA];
305}
306
307class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
308                                                      GPR32Opnd> {
309  list<Register> Defs = [RA];
310}
311
312class BLTZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzc", brtarget_lsl2_mm,
313                                                    GPR32Opnd>;
314class BLEZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezc", brtarget_lsl2_mm,
315                                                    GPR32Opnd>;
316class BGEZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezc", brtarget_lsl2_mm,
317                                                    GPR32Opnd>;
318class BGTZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzc", brtarget_lsl2_mm,
319                                                    GPR32Opnd>;
320
321class CMP_CBR_2R_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
322                                RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
323  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
324  dag OutOperandList = (outs);
325  string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
326  list<Register> Defs = [AT];
327  InstrItinClass Itinerary = II_BCCC;
328}
329
330class BGEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgec", brtarget_lsl2_mm,
331                                                 GPR32Opnd>;
332class BGEUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgeuc", brtarget_lsl2_mm,
333                                                 GPR32Opnd>;
334class BLTC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltc", brtarget_lsl2_mm,
335                                                 GPR32Opnd>;
336class BLTUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltuc", brtarget_lsl2_mm,
337                                                 GPR32Opnd>;
338class BEQC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"beqc", brtarget_lsl2_mm,
339                                                 GPR32Opnd>;
340class BNEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bnec", brtarget_lsl2_mm,
341                                                 GPR32Opnd>;
342
343class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd, 1, II_ADD>;
344class ADDIU_MMR6_DESC
345    : ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, add>;
346class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU>;
347class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>;
348class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd, 1, II_MUH, mulhs>;
349class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd, 1, II_MULU>;
350class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd, 1, II_MUHU, mulhu>;
351
352class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd, InstrItinClass Itin>
353    : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
354  dag InOperandList = (ins opnd:$offset);
355  dag OutOperandList = (outs);
356  string AsmString = !strconcat(instr_asm, "\t$offset");
357  bit isBarrier = 1;
358  InstrItinClass Itinerary = Itin;
359}
360
361class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26_mm, II_BALC> {
362  bit isCall = 1;
363  list<Register> Defs = [RA];
364}
365class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26_mm, II_BC> {
366  list<dag> Pattern = [(br bb:$offset)];
367}
368
369class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
370                                       !strconcat("bc16", "\t$offset"), [],
371                                       II_BC, FrmI>,
372                       MMR6Arch<"bc16"> {
373  let isBranch = 1;
374  let isTerminator = 1;
375  let isBarrier = 1;
376  let hasDelaySlot = 0;
377  let AdditionalPredicates = [RelocPIC];
378  let Defs = [AT];
379}
380
381class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
382    : CBranchZeroMM<instr_asm, brtarget7_mm, GPRMM16Opnd>,
383      MMR6Arch<instr_asm> {
384  let isBranch = 1;
385  let isTerminator = 1;
386  let hasDelaySlot = 0;
387  let Defs = [AT];
388}
389class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">;
390class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">;
391
392class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>;
393class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd, 0,II_SUBU>;
394
395class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
396    : MMR6Arch<instr_asm> {
397  dag OutOperandList = (outs GPROpnd:$rd);
398  dag InOperandList = (ins GPROpnd:$rt);
399  string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
400  list<dag> Pattern = [];
401  InstrItinClass Itinerary = II_BITSWAP;
402}
403
404class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
405
406class BRK_MMR6_DESC : BRK_FT<"break">;
407
408class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
409                           InstrItinClass Itin>
410      : MMR6Arch<instr_asm> {
411  dag OutOperandList = (outs);
412  dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
413  string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
414  list<dag> Pattern = [];
415  string DecoderMethod = "DecodeCacheOpMM";
416  InstrItinClass Itinerary = Itin;
417}
418
419class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, II_CACHE>;
420class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, II_PREF>;
421
422class LB_LBU_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
423                            RegisterOperand GPROpnd, InstrItinClass Itin>
424    : MMR6Arch<instr_asm> {
425  dag OutOperandList = (outs GPROpnd:$rt);
426  dag InOperandList = (ins MemOpnd:$addr);
427  string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
428  string DecoderMethod = "DecodeLoadByte15";
429  bit mayLoad = 1;
430  InstrItinClass Itinerary = Itin;
431}
432class LB_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lb", mem_mm_16, GPR32Opnd, II_LB>;
433class LBU_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lbu", mem_mm_16, GPR32Opnd,
434                                            II_LBU>;
435
436class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
437                             InstrItinClass Itin> : MMR6Arch<instr_asm> {
438  dag OutOperandList = (outs GPROpnd:$rt);
439  dag InOperandList = (ins GPROpnd:$rs);
440  string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
441  InstrItinClass Itinerary = Itin;
442}
443
444class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd, II_CLO>;
445class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd, II_CLZ>;
446
447class EHB_MMR6_DESC : Barrier<"ehb", II_EHB>;
448class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd, II_EI>;
449class DI_MMR6_DESC : DEI_FT<"di", GPR32Opnd, II_DI>;
450
451class ERET_MMR6_DESC : ER_FT<"eret", II_ERET>;
452class DERET_MMR6_DESC : ER_FT<"deret", II_DERET>;
453class ERETNC_MMR6_DESC : ER_FT<"eretnc", II_ERETNC>;
454
455class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
456    : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
457                      [(MipsJmpLink RO:$rs)], II_JALR, FrmR>,
458      MMR6Arch<opstr> {
459  let isCall = 1;
460  let hasDelaySlot = 0;
461  let Defs = [RA];
462  let hasPostISelHook = 1;
463}
464class JALRC16_MMR6_DESC : JALRC16_MMR6_DESC_BASE<"jalr", GPR32Opnd>;
465
466class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
467                                     RegisterOperand GPROpnd,
468                                     InstrItinClass Itin>
469    : MMR6Arch<opstr> {
470  dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
471  string AsmString = !strconcat(opstr, "\t$rt, $offset");
472  list<dag> Pattern = [];
473  bit isTerminator = 1;
474  bit hasDelaySlot = 0;
475  InstrItinClass Itinerary = Itin;
476}
477
478class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
479                                                       GPR32Opnd, II_JIALC> {
480  bit isCall = 1;
481  list<Register> Defs = [RA];
482}
483
484class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
485                                                     GPR32Opnd, II_JIC> {
486  bit isBarrier = 1;
487  list<Register> Defs = [AT];
488}
489
490class JRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
491    : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
492                      [], II_JR, FrmR>,
493      MMR6Arch<opstr> {
494  let hasDelaySlot = 0;
495  let isBranch = 1;
496  let isIndirectBranch = 1;
497}
498class JRC16_MMR6_DESC : JRC16_MMR6_DESC_BASE<"jrc16", GPR32Opnd>;
499
500class JRCADDIUSP_MMR6_DESC
501    : MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jrcaddiusp\t$imm",
502                      [], II_JRADDIUSP, FrmR>,
503      MMR6Arch<"jrcaddiusp"> {
504  let hasDelaySlot = 0;
505  let isTerminator = 1;
506  let isBarrier = 1;
507  let isBranch = 1;
508  let isIndirectBranch = 1;
509}
510
511class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
512                      Operand ImmOpnd, InstrItinClass Itin>
513    : MMR6Arch<instr_asm> {
514  dag OutOperandList = (outs GPROpnd:$rd);
515  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
516  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
517  list<dag> Pattern = [];
518  InstrItinClass Itinerary = Itin;
519}
520
521class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2,
522                                             II_ALIGN>;
523
524class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
525                         InstrItinClass Itin> : MMR6Arch<instr_asm> {
526  dag OutOperandList = (outs GPROpnd:$rt);
527  dag InOperandList = (ins GPROpnd:$rs, uimm16:$imm);
528  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
529  list<dag> Pattern = [];
530  InstrItinClass Itinerary = Itin;
531}
532
533class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd, II_AUI>;
534
535class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
536                            InstrItinClass Itin> : MMR6Arch<instr_asm> {
537  dag OutOperandList = (outs GPROpnd:$rt);
538  dag InOperandList = (ins simm16:$imm);
539  string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
540  list<dag> Pattern = [];
541  InstrItinClass Itinerary = Itin;
542}
543
544class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd, II_ALUIPC>;
545class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd, II_AUIPC>;
546
547class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
548                         Operand ImmOpnd, InstrItinClass Itin>
549    : MMR6Arch<instr_asm> {
550  dag OutOperandList = (outs GPROpnd:$rd);
551  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
552  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
553  list<dag> Pattern = [];
554  InstrItinClass Itinerary = Itin;
555}
556
557class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1, II_LSA>;
558
559class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
560                           Operand ImmOpnd, InstrItinClass Itin>
561    : MMR6Arch<instr_asm> {
562  dag OutOperandList = (outs GPROpnd:$rt);
563  dag InOperandList = (ins ImmOpnd:$imm);
564  string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
565  list<dag> Pattern = [];
566  InstrItinClass Itinerary = Itin;
567}
568
569class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd,
570                                               simm19_lsl2, II_ADDIUPC>;
571class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2,
572                                           II_LWPC>;
573
574class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
575                               InstrItinClass Itin> : MMR6Arch<instr_asm> {
576  dag OutOperandList = (outs GPROpnd:$rd);
577  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
578  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
579  list<dag> Pattern = [];
580  InstrItinClass Itinerary = Itin;
581}
582
583class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd,
584                                                  II_SELCCZ>;
585class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd,
586                                                  II_SELCCZ>;
587class PAUSE_MMR6_DESC : Barrier<"pause", II_PAUSE>;
588class RDHWR_MMR6_DESC : MMR6Arch<"rdhwr">, MipsR6Inst {
589  dag OutOperandList = (outs GPR32Opnd:$rt);
590  dag InOperandList = (ins HWRegsOpnd:$rs, uimm3:$sel);
591  string AsmString = !strconcat("rdhwr", "\t$rt, $rs, $sel");
592  list<dag> Pattern = [];
593  InstrItinClass Itinerary = II_RDHWR;
594  Format Form = FrmR;
595}
596
597class WAIT_MMR6_DESC : WaitMM<"wait">;
598// FIXME: ssnop should not be defined for R6. Per MD000582 microMIPS32 6.03:
599//        Assemblers targeting specifically Release 6 should reject the SSNOP
600//        instruction with an error.
601class SSNOP_MMR6_DESC : Barrier<"ssnop", II_SSNOP>;
602class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
603
604class DIVMOD_MMR6_DESC_BASE<string opstr, RegisterOperand GPROpnd,
605                            InstrItinClass Itin,
606                            SDPatternOperator OpNode=null_frag>
607    : MipsR6Inst {
608  dag OutOperandList = (outs GPROpnd:$rd);
609  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
610  string AsmString = !strconcat(opstr, "\t$rd, $rs, $rt");
611  list<dag> Pattern = [(set GPROpnd:$rd, (OpNode GPROpnd:$rs, GPROpnd:$rt))];
612  string BaseOpcode = opstr;
613  Format f = FrmR;
614  let isCommutable = 0;
615  let isReMaterializable = 1;
616  InstrItinClass Itinerary = Itin;
617
618  // This instruction doesn't trap division by zero itself. We must insert
619  // teq instructions as well.
620  bit usesCustomInserter = 1;
621}
622class DIV_MMR6_DESC  : DIVMOD_MMR6_DESC_BASE<"div", GPR32Opnd, II_DIV, sdiv>;
623class DIVU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"divu", GPR32Opnd, II_DIVU, udiv>;
624class MOD_MMR6_DESC  : DIVMOD_MMR6_DESC_BASE<"mod", GPR32Opnd, II_MOD, srem>;
625class MODU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"modu", GPR32Opnd, II_MODU, urem>;
626class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>;
627class ANDI_MMR6_DESC : ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI>;
628class NOR_MMR6_DESC : LogicNOR<"nor", GPR32Opnd>;
629class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>;
630class ORI_MMR6_DESC : ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
631                                  or> {
632  int AddedComplexity = 1;
633}
634class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>;
635class XORI_MMR6_DESC : ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI,
636                                   immZExt16, xor>;
637class SW_MMR6_DESC : Store<"sw", GPR32Opnd> {
638  InstrItinClass Itinerary = II_SW;
639}
640class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO,
641                                 InstrItinClass Itin> {
642  dag InOperandList = (ins RO:$rs);
643  dag OutOperandList = (outs RO:$rt);
644  string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
645  list<dag> Pattern = [];
646  Format f = FrmR;
647  string BaseOpcode = instr_asm;
648  bit hasSideEffects = 0;
649  InstrItinClass Itinerary = Itin;
650}
651class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd,
652                                                    II_WRPGPR>;
653class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd, II_WSBH>;
654
655class MTC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
656                         RegisterOperand SrcRC, InstrItinClass Itin> {
657  dag InOperandList = (ins SrcRC:$rt, uimm3:$sel);
658  dag OutOperandList = (outs DstRC:$rs);
659  string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel");
660  list<dag> Pattern = [];
661  Format f = FrmFR;
662  string BaseOpcode = opstr;
663  InstrItinClass Itinerary = Itin;
664}
665class MTC1_MMR6_DESC_BASE<
666      string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
667      InstrItinClass Itin = NoItinerary, SDPatternOperator OpNode = null_frag>
668      : MipsR6Inst {
669  dag InOperandList = (ins SrcRC:$rt);
670  dag OutOperandList = (outs DstRC:$fs);
671  string AsmString = !strconcat(opstr, "\t$rt, $fs");
672  list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))];
673  Format f = FrmFR;
674  InstrItinClass Itinerary = Itin;
675  string BaseOpcode = opstr;
676}
677class MTC1_64_MMR6_DESC_BASE<
678      string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
679      InstrItinClass Itin = NoItinerary> : MipsR6Inst {
680  dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt);
681  dag OutOperandList = (outs DstRC:$fs);
682  string AsmString = !strconcat(opstr, "\t$rt, $fs");
683  list<dag> Pattern = [];
684  Format f = FrmFR;
685  InstrItinClass Itinerary = Itin;
686  string BaseOpcode = opstr;
687  // $fs_in is part of a white lie to work around a widespread bug in the FPU
688  // implementation. See expandBuildPairF64 for details.
689  let Constraints = "$fs = $fs_in";
690}
691class MTC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
692                         RegisterOperand SrcRC, InstrItinClass Itin> {
693  dag InOperandList = (ins SrcRC:$rt);
694  dag OutOperandList = (outs DstRC:$impl);
695  string AsmString = !strconcat(opstr, "\t$rt, $impl");
696  list<dag> Pattern = [];
697  Format f = FrmFR;
698  string BaseOpcode = opstr;
699  InstrItinClass Itinerary = Itin;
700}
701
702class MTC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mtc0", COP0Opnd, GPR32Opnd,
703                                           II_MTC0>;
704class MTC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"mtc1", FGR32Opnd, GPR32Opnd,
705                                           II_MTC1, bitconvert>, HARDFLOAT;
706class MTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mtc2", COP2Opnd, GPR32Opnd,
707                                           II_MTC2>;
708class MTHC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mthc0", COP0Opnd, GPR32Opnd,
709                                            II_MTHC0>;
710class MTHC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mthc2", COP2Opnd, GPR32Opnd,
711                                            II_MTC2>;
712
713class MFC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
714                          RegisterOperand SrcRC, InstrItinClass Itin> {
715  dag InOperandList = (ins SrcRC:$rs, uimm3:$sel);
716  dag OutOperandList = (outs DstRC:$rt);
717  string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel");
718  list<dag> Pattern = [];
719  Format f = FrmFR;
720  string BaseOpcode = opstr;
721  InstrItinClass Itinerary = Itin;
722}
723class MFC1_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
724                          RegisterOperand SrcRC,
725                          InstrItinClass Itin = NoItinerary,
726                          SDPatternOperator OpNode = null_frag> : MipsR6Inst {
727  dag InOperandList = (ins SrcRC:$fs);
728  dag OutOperandList = (outs DstRC:$rt);
729  string AsmString = !strconcat(opstr, "\t$rt, $fs");
730  list<dag> Pattern = [(set DstRC:$rt, (OpNode SrcRC:$fs))];
731  Format f = FrmFR;
732  InstrItinClass Itinerary = Itin;
733  string BaseOpcode = opstr;
734}
735class MFC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
736                          RegisterOperand SrcRC, InstrItinClass Itin> {
737  dag InOperandList = (ins SrcRC:$impl);
738  dag OutOperandList = (outs DstRC:$rt);
739  string AsmString = !strconcat(opstr, "\t$rt, $impl");
740  list<dag> Pattern = [];
741  Format f = FrmFR;
742  string BaseOpcode = opstr;
743  InstrItinClass Itinerary = Itin;
744}
745class MFC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfc0", GPR32Opnd, COP0Opnd,
746                                           II_MFC0>;
747class MFC1_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfc1", GPR32Opnd, FGR32Opnd,
748                                           II_MFC1, bitconvert>, HARDFLOAT;
749class MFC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfc2", GPR32Opnd, COP2Opnd,
750                                           II_MFC2>;
751class MFHC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfhc0", GPR32Opnd, COP0Opnd,
752                                            II_MFHC0>;
753class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd,
754                                            II_MFC2>;
755
756class LDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 {
757  dag InOperandList = (ins mem_mm_16:$addr);
758  dag OutOperandList = (outs FGR64Opnd:$ft);
759  string AsmString = !strconcat("ldc1", "\t$ft, $addr");
760  list<dag> Pattern = [(set FGR64Opnd:$ft, (load addrimm16:$addr))];
761  Format f = FrmFI;
762  InstrItinClass Itinerary = II_LDC1;
763  string BaseOpcode = "ldc1";
764  bit mayLoad = 1;
765  let DecoderMethod = "DecodeFMemMMR2";
766}
767
768class SDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 {
769  dag InOperandList = (ins FGR64Opnd:$ft, mem_mm_16:$addr);
770  dag OutOperandList = (outs);
771  string AsmString = !strconcat("sdc1", "\t$ft, $addr");
772  list<dag> Pattern = [(store FGR64Opnd:$ft, addrimm16:$addr)];
773  Format f = FrmFI;
774  InstrItinClass Itinerary = II_SDC1;
775  string BaseOpcode = "sdc1";
776  bit mayStore = 1;
777  let DecoderMethod = "DecodeFMemMMR2";
778}
779
780class LDC2_LWC2_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
781  dag OutOperandList = (outs COP2Opnd:$rt);
782  dag InOperandList = (ins mem_mm_11:$addr);
783  string AsmString = !strconcat(opstr, "\t$rt, $addr");
784  list<dag> Pattern = [(set COP2Opnd:$rt, (load addrimm11:$addr))];
785  Format f = FrmFI;
786  InstrItinClass Itinerary = itin;
787  string BaseOpcode = opstr;
788  bit mayLoad = 1;
789  string DecoderMethod = "DecodeFMemCop2MMR6";
790}
791class LDC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"ldc2", II_LDC2>;
792class LWC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"lwc2", II_LWC2>;
793
794class SDC2_SWC2_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
795  dag OutOperandList = (outs);
796  dag InOperandList = (ins COP2Opnd:$rt, mem_mm_11:$addr);
797  string AsmString = !strconcat(opstr, "\t$rt, $addr");
798  list<dag> Pattern = [(store COP2Opnd:$rt, addrimm11:$addr)];
799  Format f = FrmFI;
800  InstrItinClass Itinerary = itin;
801  string BaseOpcode = opstr;
802  bit mayStore = 1;
803  string DecoderMethod = "DecodeFMemCop2MMR6";
804}
805class SDC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"sdc2", II_SDC2>;
806class SWC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"swc2", II_SWC2>;
807
808class GINV_MMR6_DESC_BASE<string opstr,
809                          RegisterOperand SrcRC, InstrItinClass Itin> {
810  dag InOperandList = (ins SrcRC:$rs, uimm2:$type);
811  dag OutOperandList = (outs);
812  string AsmString = !strconcat(opstr, "\t$rs, $type");
813  list<dag> Pattern = [];
814  Format f = FrmFR;
815  string BaseOpcode = opstr;
816  InstrItinClass Itinerary = Itin;
817}
818
819class GINVI_MMR6_DESC : GINV_MMR6_DESC_BASE<"ginvi", GPR32Opnd,
820                                            II_GINVI> {
821  dag InOperandList = (ins GPR32Opnd:$rs);
822  string AsmString = "ginvi\t$rs";
823}
824class GINVT_MMR6_DESC : GINV_MMR6_DESC_BASE<"ginvt", GPR32Opnd,
825                                            II_GINVT>;
826
827class SC_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
828  dag OutOperandList = (outs GPR32Opnd:$dst);
829  dag InOperandList = (ins GPR32Opnd:$rt, mem_mm_9:$addr);
830  string AsmString = !strconcat(opstr, "\t$rt, $addr");
831  InstrItinClass Itinerary = itin;
832  string BaseOpcode = opstr;
833  bit mayStore = 1;
834  string Constraints = "$rt = $dst";
835  string DecoderMethod = "DecodeMemMMImm9";
836}
837
838class LL_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
839  dag OutOperandList = (outs GPR32Opnd:$rt);
840  dag InOperandList = (ins mem_mm_9:$addr);
841  string AsmString = !strconcat(opstr, "\t$rt, $addr");
842  InstrItinClass Itinerary = itin;
843  string BaseOpcode = opstr;
844  bit mayLoad = 1;
845  string DecoderMethod = "DecodeMemMMImm9";
846}
847
848class SC_MMR6_DESC : SC_MMR6_DESC_BASE<"sc", II_SC>;
849class LL_MMR6_DESC : LL_MMR6_DESC_BASE<"ll", II_LL>;
850
851/// Floating Point Instructions
852class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
853                            InstrItinClass Itin, bit isComm,
854                            SDPatternOperator OpNode = null_frag> : HARDFLOAT {
855  dag OutOperandList = (outs RC:$fd);
856  dag InOperandList = (ins RC:$ft, RC:$fs);
857  string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
858  list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
859  InstrItinClass Itinerary = Itin;
860  bit isCommutable = isComm;
861}
862class FADD_S_MMR6_DESC
863  : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
864class FSUB_S_MMR6_DESC
865  : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
866class FMUL_S_MMR6_DESC
867  : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
868class FDIV_S_MMR6_DESC
869  : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
870class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd,
871                                            II_MADDF_S>, HARDFLOAT;
872class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd,
873                                            II_MADDF_D>, HARDFLOAT;
874class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd,
875                                            II_MSUBF_S>, HARDFLOAT;
876class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd,
877                                            II_MSUBF_D>, HARDFLOAT;
878
879class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
880                               RegisterOperand SrcRC, InstrItinClass Itin,
881                               SDPatternOperator OpNode = null_frag>
882                               : HARDFLOAT, NeverHasSideEffects {
883  dag OutOperandList = (outs DstRC:$ft);
884  dag InOperandList = (ins SrcRC:$fs);
885  string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
886  list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
887  InstrItinClass Itinerary = Itin;
888  Format Form = FrmFR;
889}
890class FMOV_S_MMR6_DESC
891  : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
892class FMOV_D_MMR6_DESC
893  : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>;
894class FNEG_S_MMR6_DESC
895  : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
896
897class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd, II_MAX_S>,
898                        HARDFLOAT;
899class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd, II_MAX_D>,
900                        HARDFLOAT;
901class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd, II_MIN_S>,
902                        HARDFLOAT;
903class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd, II_MIN_D>,
904                        HARDFLOAT;
905
906class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd, II_MAXA_S>,
907                         HARDFLOAT;
908class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd, II_MAXA_D>,
909                         HARDFLOAT;
910class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd, II_MINA_S>,
911                         HARDFLOAT;
912class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd, II_MINA_D>,
913                         HARDFLOAT;
914
915class CVT_MMR6_DESC_BASE<
916    string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
917    InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
918    : HARDFLOAT, NeverHasSideEffects {
919  dag OutOperandList = (outs DstRC:$ft);
920  dag InOperandList = (ins SrcRC:$fs);
921  string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
922  list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
923  InstrItinClass Itinerary = Itin;
924  Format Form = FrmFR;
925}
926
927class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd,
928                                             II_CVT>;
929class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd,
930                                             II_CVT>;
931class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd,
932                                             II_CVT>;
933class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd,
934                                             II_CVT>, FGR_64;
935class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
936                                             II_CVT>;
937class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
938                                             II_CVT>, FGR_64;
939
940multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
941                       RegisterOperand FGROpnd, InstrItinClass Itin> {
942  def CMP_AF_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
943      !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
944      CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd, Itin>, HARDFLOAT,
945      ISA_MICROMIPS32R6;
946  def CMP_UN_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
947      !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
948      CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, Itin, setuo>, HARDFLOAT,
949      ISA_MICROMIPS32R6;
950  def CMP_EQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
951      !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
952      CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, Itin, setoeq>, HARDFLOAT,
953      ISA_MICROMIPS32R6;
954  def CMP_UEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
955      !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
956      CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, Itin, setueq>, HARDFLOAT,
957      ISA_MICROMIPS32R6;
958  def CMP_LT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
959      !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
960      CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, Itin, setolt>, HARDFLOAT,
961      ISA_MICROMIPS32R6;
962  def CMP_ULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
963      !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
964      CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, Itin, setult>, HARDFLOAT,
965      ISA_MICROMIPS32R6;
966  def CMP_LE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
967      !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
968      CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, Itin, setole>, HARDFLOAT,
969      ISA_MICROMIPS32R6;
970  def CMP_ULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
971      !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
972      CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, Itin, setule>, HARDFLOAT,
973      ISA_MICROMIPS32R6;
974  def CMP_SAF_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
975      !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
976      CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd, Itin>, HARDFLOAT,
977      ISA_MICROMIPS32R6;
978  def CMP_SUN_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
979      !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
980      CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd, Itin>, HARDFLOAT,
981      ISA_MICROMIPS32R6;
982  def CMP_SEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
983      !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
984      CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd, Itin>, HARDFLOAT,
985      ISA_MICROMIPS32R6;
986  def CMP_SUEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
987      !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
988      CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd, Itin>, HARDFLOAT,
989      ISA_MICROMIPS32R6;
990  def CMP_SLT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
991      !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
992      CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd, Itin>, HARDFLOAT,
993      ISA_MICROMIPS32R6;
994  def CMP_SULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
995      !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
996      CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd, Itin>, HARDFLOAT,
997      ISA_MICROMIPS32R6;
998  def CMP_SLE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
999      !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
1000      CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd, Itin>, HARDFLOAT,
1001      ISA_MICROMIPS32R6;
1002  def CMP_SULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1003      !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
1004      CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd, Itin>, HARDFLOAT,
1005      ISA_MICROMIPS32R6;
1006}
1007
1008class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
1009                             RegisterOperand SrcRC, InstrItinClass Itin,
1010                             SDPatternOperator OpNode = null_frag>
1011    : HARDFLOAT, NeverHasSideEffects {
1012  dag OutOperandList = (outs DstRC:$ft);
1013  dag InOperandList  = (ins SrcRC:$fs);
1014  string AsmString   = !strconcat(instr_asm, "\t$ft, $fs");
1015  list<dag>  Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
1016  InstrItinClass Itinerary = Itin;
1017  Format Form = FrmFR;
1018  list<Predicate> EncodingPredicates = [HasStdEnc];
1019}
1020
1021class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd,
1022                                                    FGR32Opnd, II_FLOOR>;
1023class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd,
1024                                                    FGR64Opnd, II_FLOOR>;
1025class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd,
1026                                                    FGR32Opnd, II_FLOOR>;
1027class FLOOR_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd,
1028                                                    AFGR64Opnd, II_FLOOR>;
1029class CEIL_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.s", FGR64Opnd,
1030                                                   FGR32Opnd, II_CEIL>;
1031class CEIL_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.d", FGR64Opnd,
1032                                                   FGR64Opnd, II_CEIL>;
1033class CEIL_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.s", FGR32Opnd,
1034                                                   FGR32Opnd, II_CEIL>;
1035class CEIL_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.d", FGR32Opnd,
1036                                                   AFGR64Opnd, II_CEIL>;
1037class TRUNC_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.s", FGR64Opnd,
1038                                                    FGR32Opnd, II_TRUNC>;
1039class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd,
1040                                                    FGR64Opnd, II_TRUNC>;
1041class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
1042                                                    FGR32Opnd, II_TRUNC>;
1043class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
1044                                                    FGR64Opnd, II_TRUNC>;
1045class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
1046                                                 II_SQRT_S, fsqrt>;
1047class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd,
1048                                                AFGR64Opnd, II_SQRT_D, fsqrt>;
1049class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd,
1050                                                   FGR32Opnd, II_ROUND>;
1051class ROUND_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd,
1052                                                   FGR64Opnd, II_ROUND>;
1053class ROUND_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.s", FGR32Opnd,
1054                                                   FGR32Opnd, II_ROUND>;
1055class ROUND_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.d", FGR64Opnd,
1056                                                   FGR64Opnd, II_ROUND>;
1057
1058class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd, II_SEL_S>;
1059class SEL_D_MMR6_DESC : COP1_SEL_D_DESC_BASE<"sel.d", FGR64Opnd, II_SEL_D>;
1060
1061class SELEQZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd,
1062                                              II_SELCCZ_S>;
1063class SELEQZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd,
1064                                              II_SELCCZ_D>;
1065class SELNEZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd,
1066                                              II_SELCCZ_S>;
1067class SELNEZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd,
1068                                              II_SELCCZ_D>;
1069class RINT_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd,
1070                                              II_RINT_S>;
1071class RINT_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd,
1072                                              II_RINT_S>;
1073class CLASS_S_MMR6_DESC  : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd,
1074                                              II_CLASS_S>;
1075class CLASS_D_MMR6_DESC  : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd,
1076                                              II_CLASS_S>;
1077
1078class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO,
1079                           InstrItinClass Itin>
1080    : Store<opstr, RO>, MMR6Arch<opstr> {
1081  let DecoderMethod = "DecodeMemMMImm16";
1082  InstrItinClass Itinerary = Itin;
1083}
1084class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd, II_SB>;
1085
1086class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd, II_SH>;
1087class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
1088      MMR6Arch<"addu16"> {
1089  int AddedComplexity = 1;
1090}
1091class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND>,
1092      MMR6Arch<"and16">;
1093class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
1094      MMR6Arch<"andi16">;
1095class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16"> {
1096  int AddedComplexity = 1;
1097}
1098class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR>, MMR6Arch<"or16">;
1099class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
1100      MMR6Arch<"sll16">;
1101class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
1102      MMR6Arch<"srl16">;
1103class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16", II_BREAK>,
1104                          MMR6Arch<"break16">;
1105class LI16_MMR6_DESC : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>,
1106      MMR6Arch<"li16">, IsAsCheapAsAMove;
1107class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">;
1108class MOVEP_MMR6_DESC : MovePMM16<"movep", GPRMM16OpndMovePPairFirst,
1109                                  GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP>,
1110                        MMR6Arch<"movep">;
1111class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16", II_SDBBP>,
1112                          MMR6Arch<"sdbbp16">;
1113class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
1114      MMR6Arch<"subu16"> {
1115  int AddedComplexity = 1;
1116}
1117class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR>,
1118      MMR6Arch<"xor16">;
1119
1120class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
1121  dag OutOperandList = (outs GPR32Opnd:$rt);
1122  dag InOperandList = (ins mem:$addr);
1123  string AsmString = "lw\t$rt, $addr";
1124  let DecoderMethod = "DecodeMemMMImm16";
1125  let canFoldAsLoad = 1;
1126  let mayLoad = 1;
1127  list<dag> Pattern = [(set GPR32Opnd:$rt, (load addrDefault:$addr))];
1128  InstrItinClass Itinerary = II_LW;
1129}
1130
1131class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{
1132  dag OutOperandList = (outs GPR32Opnd:$rt);
1133  dag InOperandList = (ins uimm16:$imm16);
1134  string AsmString = "lui\t$rt, $imm16";
1135  list<dag> Pattern = [];
1136  bit hasSideEffects = 0;
1137  bit isReMaterializable = 1;
1138  InstrItinClass Itinerary = II_LUI;
1139  Format Form = FrmI;
1140}
1141
1142class SYNC_MMR6_DESC : MMR6Arch<"sync">, MipsR6Inst {
1143  dag OutOperandList = (outs);
1144  dag InOperandList = (ins uimm5:$stype);
1145  string AsmString = !strconcat("sync", "\t$stype");
1146  list<dag> Pattern = [(MipsSync immZExt5:$stype)];
1147  InstrItinClass Itinerary = II_SYNC;
1148  bit HasSideEffects = 1;
1149}
1150
1151class SYNCI_MMR6_DESC : SYNCI_FT<"synci", mem_mm_16> {
1152  let DecoderMethod = "DecodeSynciR6";
1153}
1154
1155class RDPGPR_MMR6_DESC : MMR6Arch<"rdpgpr">, MipsR6Inst {
1156  dag OutOperandList = (outs GPR32Opnd:$rt);
1157  dag InOperandList = (ins GPR32Opnd:$rd);
1158  string AsmString = !strconcat("rdpgpr", "\t$rt, $rd");
1159  InstrItinClass Itinerary = II_RDPGPR;
1160}
1161
1162class SDBBP_MMR6_DESC : MipsR6Inst {
1163  dag OutOperandList = (outs);
1164  dag InOperandList = (ins uimm20:$code_);
1165  string AsmString = !strconcat("sdbbp", "\t$code_");
1166  list<dag> Pattern = [];
1167  InstrItinClass Itinerary = II_SDBBP;
1168}
1169
1170class SIGRIE_MMR6_DESC : MipsR6Inst {
1171  dag OutOperandList = (outs);
1172  dag InOperandList = (ins uimm16:$code_);
1173  string AsmString = !strconcat("sigrie", "\t$code_");
1174  list<dag> Pattern = [];
1175  InstrItinClass Itinerary = II_SIGRIE;
1176}
1177
1178class LWM16_MMR6_DESC
1179    : MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
1180                      !strconcat("lwm16", "\t$rt, $addr"), [],
1181                      II_LWM, FrmI>,
1182      MMR6Arch<"lwm16"> {
1183  let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
1184  let mayLoad = 1;
1185  ComplexPattern Addr = addr;
1186}
1187
1188class SWM16_MMR6_DESC
1189    : MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
1190                      !strconcat("swm16", "\t$rt, $addr"), [],
1191                      II_SWM, FrmI>,
1192      MMR6Arch<"swm16"> {
1193  let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
1194  let mayStore = 1;
1195  ComplexPattern Addr = addr;
1196}
1197
1198class SB16_MMR6_DESC_BASE<string opstr, DAGOperand RTOpnd,
1199                          InstrItinClass Itin, Operand MemOpnd>
1200    : MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
1201                      !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI>,
1202      MMR6Arch<opstr> {
1203  let DecoderMethod = "DecodeMemMMImm4";
1204  let mayStore = 1;
1205}
1206
1207class SB16_MMR6_DESC
1208    : SB16_MMR6_DESC_BASE<"sb16", GPRMM16OpndZero, II_SB, mem_mm_4>;
1209class SH16_MMR6_DESC
1210    : SB16_MMR6_DESC_BASE<"sh16", GPRMM16OpndZero, II_SH, mem_mm_4_lsl1>;
1211class SW16_MMR6_DESC
1212    : SB16_MMR6_DESC_BASE<"sw16", GPRMM16OpndZero, II_SW, mem_mm_4_lsl2>;
1213
1214class SWSP_MMR6_DESC
1215    : MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset),
1216                      !strconcat("sw", "\t$rt, $offset"), [], II_SW, FrmI>,
1217      MMR6Arch<"swsp"> {
1218  let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
1219  let mayStore = 1;
1220}
1221
1222class JALRC_HB_MMR6_DESC {
1223  dag OutOperandList = (outs GPR32Opnd:$rt);
1224  dag InOperandList = (ins GPR32Opnd:$rs);
1225  string AsmString = !strconcat("jalrc.hb", "\t$rt, $rs");
1226  list<dag> Pattern = [];
1227  InstrItinClass Itinerary = II_JALR_HB;
1228  Format Form = FrmJ;
1229  bit isIndirectBranch = 1;
1230  bit hasDelaySlot = 0;
1231}
1232
1233class TLBINV_MMR6_DESC_BASE<string opstr, InstrItinClass Itin> {
1234  dag OutOperandList = (outs);
1235  dag InOperandList = (ins);
1236  string AsmString = opstr;
1237  list<dag> Pattern = [];
1238  InstrItinClass Itinerary = Itin;
1239}
1240
1241class TLBINV_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinv", II_TLBINV>;
1242class TLBINVF_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinvf", II_TLBINVF>;
1243
1244class DVPEVP_MMR6_DESC_BASE<string opstr, InstrItinClass Itin> {
1245  dag OutOperandList = (outs GPR32Opnd:$rs);
1246  dag InOperandList = (ins);
1247  string AsmString = !strconcat(opstr, "\t$rs");
1248  list<dag> Pattern = [];
1249  InstrItinClass Itinerary = Itin;
1250  bit hasUnModeledSideEffects = 1;
1251}
1252
1253class DVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"dvp", II_DVP>;
1254class EVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"evp", II_EVP>;
1255
1256class BEQZC_MMR6_DESC
1257    : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21_mm, GPR32Opnd>,
1258      MMR6Arch<"beqzc">;
1259class BNEZC_MMR6_DESC
1260    : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21_mm, GPR32Opnd>,
1261      MMR6Arch<"bnezc">;
1262
1263class BRANCH_COP1_MMR6_DESC_BASE<string opstr> :
1264    InstSE<(outs), (ins FGR64Opnd:$rt, brtarget_mm:$offset),
1265           !strconcat(opstr, "\t$rt, $offset"), [], II_BC1CCZ, FrmI>,
1266    HARDFLOAT, BRANCH_DESC_BASE {
1267  list<Register> Defs = [AT];
1268}
1269
1270class BC1EQZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1eqzc">;
1271class BC1NEZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1nezc">;
1272
1273class BRANCH_COP2_MMR6_DESC_BASE<string opstr, InstrItinClass Itin>
1274    : BRANCH_DESC_BASE {
1275  dag InOperandList = (ins COP2Opnd:$rt, brtarget_mm:$offset);
1276  dag OutOperandList = (outs);
1277  string AsmString = !strconcat(opstr, "\t$rt, $offset");
1278  list<Register> Defs = [AT];
1279  InstrItinClass Itinerary = Itin;
1280}
1281
1282class BC2EQZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2eqzc", II_BC2CCZ>;
1283class BC2NEZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2nezc", II_BC2CCZ>;
1284
1285class EXT_MMR6_DESC {
1286  dag OutOperandList = (outs GPR32Opnd:$rt);
1287  dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$pos, uimm5_plus1:$size);
1288  string AsmString = !strconcat("ext", "\t$rt, $rs, $pos, $size");
1289  list<dag> Pattern = [(set GPR32Opnd:$rt, (MipsExt GPR32Opnd:$rs, imm:$pos,
1290                       imm:$size))];
1291  InstrItinClass Itinerary = II_EXT;
1292  Format Form = FrmR;
1293  string BaseOpcode = "ext";
1294}
1295
1296class INS_MMR6_DESC {
1297  dag OutOperandList = (outs GPR32Opnd:$rt);
1298  dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$pos, uimm5_inssize_plus1:$size,
1299                       GPR32Opnd:$src);
1300  string AsmString = !strconcat("ins", "\t$rt, $rs, $pos, $size");
1301  list<dag> Pattern = [(set GPR32Opnd:$rt, (MipsIns GPR32Opnd:$rs, imm:$pos,
1302                       imm:$size, GPR32Opnd:$src))];
1303  InstrItinClass Itinerary = II_INS;
1304  Format Form = FrmR;
1305  string BaseOpcode = "ins";
1306  string Constraints = "$src = $rt";
1307}
1308
1309class JALRC_MMR6_DESC {
1310  dag OutOperandList = (outs GPR32Opnd:$rt);
1311  dag InOperandList = (ins GPR32Opnd:$rs);
1312  string AsmString = !strconcat("jalrc", "\t$rt, $rs");
1313  list<dag> Pattern = [];
1314  InstrItinClass Itinerary = II_JALRC;
1315  bit isCall = 1;
1316  bit hasDelaySlot = 0;
1317  list<Register> Defs = [RA];
1318}
1319
1320class BOVC_BNVC_MMR6_DESC_BASE<string instr_asm, Operand opnd,
1321                               RegisterOperand GPROpnd>
1322    : BRANCH_DESC_BASE {
1323  dag InOperandList = (ins GPROpnd:$rt, GPROpnd:$rs, opnd:$offset);
1324  dag OutOperandList = (outs);
1325  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $offset");
1326  list<Register> Defs = [AT];
1327  InstrItinClass Itinerary = II_BCCC;
1328}
1329
1330class BOVC_MMR6_DESC : BOVC_BNVC_MMR6_DESC_BASE<"bovc", brtargetr6, GPR32Opnd>;
1331class BNVC_MMR6_DESC : BOVC_BNVC_MMR6_DESC_BASE<"bnvc", brtargetr6, GPR32Opnd>;
1332
1333//===----------------------------------------------------------------------===//
1334//
1335// Instruction Definitions
1336//
1337//===----------------------------------------------------------------------===//
1338
1339let DecoderNamespace = "MicroMipsR6" in {
1340def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
1341def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
1342def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
1343def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
1344                   ISA_MICROMIPS32R6;
1345def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
1346                  ISA_MICROMIPS32R6;
1347def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;
1348def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6;
1349def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6;
1350def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6;
1351def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
1352def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
1353def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
1354def BC16_MMR6 : StdMMR6Rel, BC16_MMR6_DESC, BC16_MMR6_ENC, ISA_MICROMIPS32R6;
1355def BEQZC_MMR6 : R6MMR6Rel, BEQZC_MMR6_ENC, BEQZC_MMR6_DESC,
1356                 ISA_MICROMIPS32R6;
1357def BEQZC16_MMR6 : StdMMR6Rel, BEQZC16_MMR6_DESC, BEQZC16_MMR6_ENC,
1358                   ISA_MICROMIPS32R6;
1359def BNEZC_MMR6 : R6MMR6Rel, BNEZC_MMR6_ENC, BNEZC_MMR6_DESC,
1360                 ISA_MICROMIPS32R6;
1361def BNEZC16_MMR6 : StdMMR6Rel, BNEZC16_MMR6_DESC, BNEZC16_MMR6_ENC,
1362                   ISA_MICROMIPS32R6;
1363def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
1364                   ISA_MICROMIPS32R6;
1365def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
1366                   ISA_MICROMIPS32R6;
1367def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
1368                   ISA_MICROMIPS32R6;
1369def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
1370def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
1371def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
1372def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
1373def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
1374def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
1375def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
1376def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
1377def DI_MMR6 : StdMMR6Rel, DI_MMR6_DESC, DI_MMR6_ENC, ISA_MICROMIPS32R6;
1378def ERET_MMR6 : StdMMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
1379def DERET_MMR6 : StdMMR6Rel, DERET_MMR6_DESC, DERET_MMR6_ENC, ISA_MICROMIPS32R6;
1380def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
1381                  ISA_MICROMIPS32R6;
1382def GINVI_MMR6 : R6MMR6Rel, GINVI_MMR6_ENC, GINVI_MMR6_DESC,
1383                 ISA_MICROMIPS32R6, ASE_GINV;
1384def GINVT_MMR6 : R6MMR6Rel, GINVT_MMR6_ENC, GINVT_MMR6_DESC,
1385                 ISA_MICROMIPS32R6, ASE_GINV;
1386let FastISelShouldIgnore = 1 in
1387def JALRC16_MMR6 : R6MMR6Rel, JALRC16_MMR6_DESC, JALRC16_MMR6_ENC,
1388                   ISA_MICROMIPS32R6;
1389def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
1390def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
1391def JRC16_MMR6 : R6MMR6Rel, JRC16_MMR6_DESC, JRC16_MMR6_ENC, ISA_MICROMIPS32R6;
1392def JRCADDIUSP_MMR6 : R6MMR6Rel, JRCADDIUSP_MMR6_DESC, JRCADDIUSP_MMR6_ENC,
1393                      ISA_MICROMIPS32R6;
1394def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
1395def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
1396def LWM16_MMR6 : StdMMR6Rel, LWM16_MMR6_DESC, LWM16_MMR6_ENC, ISA_MICROMIPS32R6;
1397def MTC0_MMR6 : StdMMR6Rel, MTC0_MMR6_ENC, MTC0_MMR6_DESC, ISA_MICROMIPS32R6;
1398def MTC1_MMR6 : StdMMR6Rel, MTC1_MMR6_DESC, MTC1_MMR6_ENC, ISA_MICROMIPS32R6;
1399def MTC2_MMR6 : StdMMR6Rel, MTC2_MMR6_ENC, MTC2_MMR6_DESC, ISA_MICROMIPS32R6;
1400def MTHC0_MMR6 : R6MMR6Rel, MTHC0_MMR6_ENC, MTHC0_MMR6_DESC, ISA_MICROMIPS32R6;
1401def MTHC2_MMR6 : StdMMR6Rel, MTHC2_MMR6_ENC, MTHC2_MMR6_DESC, ISA_MICROMIPS32R6;
1402def MFC0_MMR6 : StdMMR6Rel, MFC0_MMR6_ENC, MFC0_MMR6_DESC, ISA_MICROMIPS32R6;
1403def MFC1_MMR6 : StdMMR6Rel, MFC1_MMR6_DESC, MFC1_MMR6_ENC, ISA_MICROMIPS32R6;
1404def MFC2_MMR6 : StdMMR6Rel, MFC2_MMR6_ENC, MFC2_MMR6_DESC, ISA_MICROMIPS32R6;
1405def MFHC0_MMR6 : R6MMR6Rel, MFHC0_MMR6_ENC, MFHC0_MMR6_DESC, ISA_MICROMIPS32R6;
1406def MFHC2_MMR6 : StdMMR6Rel, MFHC2_MMR6_ENC, MFHC2_MMR6_DESC, ISA_MICROMIPS32R6;
1407def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
1408def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
1409def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
1410def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
1411def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
1412def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
1413def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
1414def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
1415def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
1416def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
1417def SB16_MMR6 : StdMMR6Rel, SB16_MMR6_DESC, SB16_MMR6_ENC, ISA_MICROMIPS32R6;
1418def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
1419                  ISA_MICROMIPS32R6;
1420def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
1421                  ISA_MICROMIPS32R6;
1422def SH16_MMR6 : StdMMR6Rel, SH16_MMR6_DESC, SH16_MMR6_ENC, ISA_MICROMIPS32R6;
1423def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
1424def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
1425def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
1426def SW16_MMR6 : StdMMR6Rel, SW16_MMR6_DESC, SW16_MMR6_ENC, ISA_MICROMIPS32R6;
1427def SWM16_MMR6 : StdMMR6Rel, SWM16_MMR6_DESC, SWM16_MMR6_ENC, ISA_MICROMIPS32R6;
1428def SWSP_MMR6 : StdMMR6Rel, SWSP_MMR6_DESC, SWSP_MMR6_ENC, ISA_MICROMIPS32R6;
1429def WRPGPR_MMR6 : StdMMR6Rel, WRPGPR_MMR6_ENC, WRPGPR_MMR6_DESC,
1430                  ISA_MICROMIPS32R6;
1431def WSBH_MMR6 : StdMMR6Rel, WSBH_MMR6_ENC, WSBH_MMR6_DESC, ISA_MICROMIPS32R6;
1432def LB_MMR6 : R6MMR6Rel, LB_MMR6_ENC, LB_MMR6_DESC, ISA_MICROMIPS32R6;
1433def LBU_MMR6 : R6MMR6Rel, LBU_MMR6_ENC, LBU_MMR6_DESC, ISA_MICROMIPS32R6;
1434def PAUSE_MMR6 : StdMMR6Rel, PAUSE_MMR6_DESC, PAUSE_MMR6_ENC, ISA_MICROMIPS32R6;
1435def RDHWR_MMR6 : R6MMR6Rel, RDHWR_MMR6_DESC, RDHWR_MMR6_ENC, ISA_MICROMIPS32R6;
1436def WAIT_MMR6 : StdMMR6Rel, WAIT_MMR6_DESC, WAIT_MMR6_ENC, ISA_MICROMIPS32R6;
1437def SSNOP_MMR6 : StdMMR6Rel, SSNOP_MMR6_DESC, SSNOP_MMR6_ENC, ISA_MICROMIPS32R6;
1438def SYNC_MMR6 : StdMMR6Rel, SYNC_MMR6_DESC, SYNC_MMR6_ENC, ISA_MICROMIPS32R6;
1439def SYNCI_MMR6 : StdMMR6Rel, SYNCI_MMR6_DESC, SYNCI_MMR6_ENC, ISA_MICROMIPS32R6;
1440def RDPGPR_MMR6 : R6MMR6Rel, RDPGPR_MMR6_DESC, RDPGPR_MMR6_ENC,
1441                  ISA_MICROMIPS32R6;
1442def SDBBP_MMR6 : R6MMR6Rel, SDBBP_MMR6_DESC, SDBBP_MMR6_ENC, ISA_MICROMIPS32R6;
1443def SIGRIE_MMR6 : R6MMR6Rel, SIGRIE_MMR6_DESC, SIGRIE_MMR6_ENC,
1444                  ISA_MICROMIPS32R6;
1445def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
1446def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
1447let DecoderMethod = "DecodeMemMMImm16" in {
1448  def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
1449}
1450/// Floating Point Instructions
1451def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
1452                  ISA_MICROMIPS32R6;
1453def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC,
1454                  ISA_MICROMIPS32R6;
1455def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC,
1456                  ISA_MICROMIPS32R6;
1457def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC,
1458                  ISA_MICROMIPS32R6;
1459def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC,
1460                   ISA_MICROMIPS32R6;
1461def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
1462                   ISA_MICROMIPS32R6;
1463def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
1464                   ISA_MICROMIPS32R6;
1465def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
1466                   ISA_MICROMIPS32R6;
1467def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
1468                  ISA_MICROMIPS32R6;
1469def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC,
1470                  ISA_MICROMIPS32R6;
1471def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
1472                  ISA_MICROMIPS32R6;
1473def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
1474def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6;
1475def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6;
1476def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6;
1477def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC,
1478                  ISA_MICROMIPS32R6;
1479def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC,
1480                  ISA_MICROMIPS32R6;
1481def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC,
1482                  ISA_MICROMIPS32R6;
1483def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC,
1484                  ISA_MICROMIPS32R6;
1485def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC,
1486                   ISA_MICROMIPS32R6;
1487def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC,
1488                   ISA_MICROMIPS32R6;
1489def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC,
1490                   ISA_MICROMIPS32R6;
1491def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC,
1492                   ISA_MICROMIPS32R6;
1493def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
1494                   ISA_MICROMIPS32R6;
1495def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
1496                   ISA_MICROMIPS32R6;
1497defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd, II_CMP_CC_S>;
1498defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd, II_CMP_CC_D>;
1499def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
1500                     ISA_MICROMIPS32R6;
1501def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC,
1502                     ISA_MICROMIPS32R6;
1503def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC,
1504                     ISA_MICROMIPS32R6;
1505def FLOOR_W_D_MMR6 : StdMMR6Rel, FLOOR_W_D_MMR6_ENC, FLOOR_W_D_MMR6_DESC,
1506                     ISA_MICROMIPS32R6;
1507def CEIL_L_S_MMR6 : StdMMR6Rel, CEIL_L_S_MMR6_ENC, CEIL_L_S_MMR6_DESC,
1508                    ISA_MICROMIPS32R6;
1509def CEIL_L_D_MMR6 : StdMMR6Rel, CEIL_L_D_MMR6_ENC, CEIL_L_D_MMR6_DESC,
1510                    ISA_MICROMIPS32R6;
1511def CEIL_W_S_MMR6 : StdMMR6Rel, CEIL_W_S_MMR6_ENC, CEIL_W_S_MMR6_DESC,
1512                    ISA_MICROMIPS32R6;
1513def CEIL_W_D_MMR6 : StdMMR6Rel, CEIL_W_D_MMR6_ENC, CEIL_W_D_MMR6_DESC,
1514                    ISA_MICROMIPS32R6;
1515def TRUNC_L_S_MMR6 : StdMMR6Rel, TRUNC_L_S_MMR6_ENC, TRUNC_L_S_MMR6_DESC,
1516                     ISA_MICROMIPS32R6;
1517def TRUNC_L_D_MMR6 : StdMMR6Rel, TRUNC_L_D_MMR6_ENC, TRUNC_L_D_MMR6_DESC,
1518                     ISA_MICROMIPS32R6;
1519def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC,
1520                     ISA_MICROMIPS32R6;
1521def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC,
1522                     ISA_MICROMIPS32R6;
1523def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
1524def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
1525def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6;
1526def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6;
1527def ADDU16_MMR6 : StdMMR6Rel, ADDU16_MMR6_DESC, ADDU16_MMR6_ENC,
1528                  ISA_MICROMIPS32R6;
1529def AND16_MMR6 : StdMMR6Rel, AND16_MMR6_DESC, AND16_MMR6_ENC,
1530                  ISA_MICROMIPS32R6;
1531def ANDI16_MMR6 : StdMMR6Rel, ANDI16_MMR6_DESC, ANDI16_MMR6_ENC,
1532                  ISA_MICROMIPS32R6;
1533def NOT16_MMR6 : StdMMR6Rel, NOT16_MMR6_DESC, NOT16_MMR6_ENC,
1534                  ISA_MICROMIPS32R6;
1535def OR16_MMR6 : StdMMR6Rel, OR16_MMR6_DESC, OR16_MMR6_ENC,
1536                  ISA_MICROMIPS32R6;
1537def SLL16_MMR6 : StdMMR6Rel, SLL16_MMR6_DESC, SLL16_MMR6_ENC,
1538                  ISA_MICROMIPS32R6;
1539def SRL16_MMR6 : StdMMR6Rel, SRL16_MMR6_DESC, SRL16_MMR6_ENC,
1540                  ISA_MICROMIPS32R6;
1541def BREAK16_MMR6 : StdMMR6Rel, BREAK16_MMR6_DESC, BREAK16_MMR6_ENC,
1542                   ISA_MICROMIPS32R6;
1543def LI16_MMR6 : StdMMR6Rel, LI16_MMR6_DESC, LI16_MMR6_ENC,
1544                ISA_MICROMIPS32R6;
1545def MOVE16_MMR6 : StdMMR6Rel, MOVE16_MMR6_DESC, MOVE16_MMR6_ENC,
1546                  ISA_MICROMIPS32R6;
1547def MOVEP_MMR6  : StdMMR6Rel, MOVEP_MMR6_DESC, MOVEP_MMR6_ENC,
1548                  ISA_MICROMIPS32R6;
1549def SDBBP16_MMR6 : StdMMR6Rel, SDBBP16_MMR6_DESC, SDBBP16_MMR6_ENC,
1550                   ISA_MICROMIPS32R6;
1551def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC,
1552                  ISA_MICROMIPS32R6;
1553def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC,
1554                 ISA_MICROMIPS32R6;
1555def JALRC_HB_MMR6 : R6MMR6Rel, JALRC_HB_MMR6_ENC, JALRC_HB_MMR6_DESC,
1556                    ISA_MICROMIPS32R6;
1557def EXT_MMR6 : StdMMR6Rel, EXT_MMR6_ENC, EXT_MMR6_DESC, ISA_MICROMIPS32R6;
1558def INS_MMR6 : StdMMR6Rel, INS_MMR6_ENC, INS_MMR6_DESC, ISA_MICROMIPS32R6;
1559def JALRC_MMR6 : R6MMR6Rel, JALRC_MMR6_ENC, JALRC_MMR6_DESC, ISA_MICROMIPS32R6;
1560def RINT_S_MMR6 : StdMMR6Rel, RINT_S_MMR6_ENC, RINT_S_MMR6_DESC,
1561                  ISA_MICROMIPS32R6;
1562def RINT_D_MMR6 : StdMMR6Rel, RINT_D_MMR6_ENC, RINT_D_MMR6_DESC,
1563                  ISA_MICROMIPS32R6;
1564def ROUND_L_S_MMR6 : StdMMR6Rel, ROUND_L_S_MMR6_ENC, ROUND_L_S_MMR6_DESC,
1565                     ISA_MICROMIPS32R6;
1566def ROUND_L_D_MMR6 : StdMMR6Rel, ROUND_L_D_MMR6_ENC, ROUND_L_D_MMR6_DESC,
1567                     ISA_MICROMIPS32R6;
1568def ROUND_W_S_MMR6 : StdMMR6Rel, ROUND_W_S_MMR6_ENC, ROUND_W_S_MMR6_DESC,
1569                     ISA_MICROMIPS32R6;
1570def ROUND_W_D_MMR6 : StdMMR6Rel, ROUND_W_D_MMR6_ENC, ROUND_W_D_MMR6_DESC,
1571                     ISA_MICROMIPS32R6;
1572def SEL_S_MMR6 : R6MMR6Rel, SEL_S_MMR6_ENC, SEL_S_MMR6_DESC, ISA_MICROMIPS32R6;
1573def SEL_D_MMR6 : R6MMR6Rel, SEL_D_MMR6_ENC, SEL_D_MMR6_DESC, ISA_MICROMIPS32R6;
1574def SELEQZ_S_MMR6 : R6MMR6Rel, SELEQZ_S_MMR6_ENC, SELEQZ_S_MMR6_DESC,
1575                    ISA_MICROMIPS32R6;
1576def SELEQZ_D_MMR6 : R6MMR6Rel, SELEQZ_D_MMR6_ENC, SELEQZ_D_MMR6_DESC,
1577                    ISA_MICROMIPS32R6;
1578def SELNEZ_S_MMR6 : R6MMR6Rel, SELNEZ_S_MMR6_ENC, SELNEZ_S_MMR6_DESC,
1579                    ISA_MICROMIPS32R6;
1580def SELNEZ_D_MMR6 : R6MMR6Rel, SELNEZ_D_MMR6_ENC, SELNEZ_D_MMR6_DESC,
1581                    ISA_MICROMIPS32R6;
1582def CLASS_S_MMR6 : StdMMR6Rel, CLASS_S_MMR6_ENC, CLASS_S_MMR6_DESC,
1583                   ISA_MICROMIPS32R6;
1584def CLASS_D_MMR6 : StdMMR6Rel, CLASS_D_MMR6_ENC, CLASS_D_MMR6_DESC,
1585                   ISA_MICROMIPS32R6;
1586def TLBINV_MMR6 : StdMMR6Rel, TLBINV_MMR6_ENC, TLBINV_MMR6_DESC,
1587                  ISA_MICROMIPS32R6;
1588def TLBINVF_MMR6 : StdMMR6Rel, TLBINVF_MMR6_ENC, TLBINVF_MMR6_DESC,
1589                   ISA_MICROMIPS32R6;
1590def DVP_MMR6 : R6MMR6Rel, DVP_MMR6_ENC, DVP_MMR6_DESC, ISA_MICROMIPS32R6;
1591def EVP_MMR6 : R6MMR6Rel, EVP_MMR6_ENC, EVP_MMR6_DESC, ISA_MICROMIPS32R6;
1592def BC1EQZC_MMR6 : R6MMR6Rel, BC1EQZC_MMR6_DESC, BC1EQZC_MMR6_ENC,
1593                   ISA_MICROMIPS32R6;
1594def BC1NEZC_MMR6 : R6MMR6Rel, BC1NEZC_MMR6_DESC, BC1NEZC_MMR6_ENC,
1595                   ISA_MICROMIPS32R6;
1596def BC2EQZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2EQZC_MMR6_ENC, BC2EQZC_MMR6_DESC,
1597                   ISA_MICROMIPS32R6;
1598def BC2NEZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2NEZC_MMR6_ENC, BC2NEZC_MMR6_DESC,
1599                   ISA_MICROMIPS32R6;
1600let DecoderNamespace = "MicroMipsFP64" in {
1601  def LDC1_D64_MMR6 : StdMMR6Rel, LDC1_D64_MMR6_DESC, LDC1_MMR6_ENC,
1602                      ISA_MICROMIPS32R6 {
1603    let BaseOpcode = "LDC164";
1604  }
1605  def SDC1_D64_MMR6 : StdMMR6Rel, SDC1_D64_MMR6_DESC, SDC1_MMR6_ENC,
1606                      ISA_MICROMIPS32R6;
1607}
1608def LDC2_MMR6 : StdMMR6Rel, LDC2_MMR6_ENC, LDC2_MMR6_DESC, ISA_MICROMIPS32R6;
1609def SDC2_MMR6 : StdMMR6Rel, SDC2_MMR6_ENC, SDC2_MMR6_DESC, ISA_MICROMIPS32R6;
1610def LWC2_MMR6 : StdMMR6Rel, LWC2_MMR6_ENC, LWC2_MMR6_DESC, ISA_MICROMIPS32R6;
1611def SWC2_MMR6 : StdMMR6Rel, SWC2_MMR6_ENC, SWC2_MMR6_DESC, ISA_MICROMIPS32R6;
1612def LL_MMR6   : R6MMR6Rel, LL_MMR6_ENC, LL_MMR6_DESC, ISA_MICROMIPS32R6;
1613def SC_MMR6   : R6MMR6Rel, SC_MMR6_ENC, SC_MMR6_DESC, ISA_MICROMIPS32R6;
1614}
1615
1616def BOVC_MMR6 : R6MMR6Rel, BOVC_MMR6_ENC, BOVC_MMR6_DESC, ISA_MICROMIPS32R6,
1617                MMDecodeDisambiguatedBy<"POP35GroupBranchMMR6">;
1618def BNVC_MMR6 : R6MMR6Rel, BNVC_MMR6_ENC, BNVC_MMR6_DESC, ISA_MICROMIPS32R6,
1619                MMDecodeDisambiguatedBy<"POP37GroupBranchMMR6">;
1620def BGEC_MMR6 : R6MMR6Rel, BGEC_MMR6_ENC, BGEC_MMR6_DESC, ISA_MICROMIPS32R6;
1621def BGEUC_MMR6 : R6MMR6Rel, BGEUC_MMR6_ENC, BGEUC_MMR6_DESC, ISA_MICROMIPS32R6;
1622def BLTC_MMR6 : R6MMR6Rel, BLTC_MMR6_ENC, BLTC_MMR6_DESC, ISA_MICROMIPS32R6;
1623def BLTUC_MMR6 : R6MMR6Rel, BLTUC_MMR6_ENC, BLTUC_MMR6_DESC, ISA_MICROMIPS32R6;
1624def BEQC_MMR6 : R6MMR6Rel, BEQC_MMR6_ENC, BEQC_MMR6_DESC, ISA_MICROMIPS32R6,
1625                DecodeDisambiguates<"POP35GroupBranchMMR6">;
1626def BNEC_MMR6 : R6MMR6Rel, BNEC_MMR6_ENC, BNEC_MMR6_DESC, ISA_MICROMIPS32R6,
1627                DecodeDisambiguates<"POP37GroupBranchMMR6">;
1628def BLTZC_MMR6 : R6MMR6Rel, BLTZC_MMR6_ENC, BLTZC_MMR6_DESC, ISA_MICROMIPS32R6;
1629def BLEZC_MMR6 : R6MMR6Rel, BLEZC_MMR6_ENC, BLEZC_MMR6_DESC, ISA_MICROMIPS32R6;
1630def BGEZC_MMR6 : R6MMR6Rel, BGEZC_MMR6_ENC, BGEZC_MMR6_DESC, ISA_MICROMIPS32R6;
1631def BGTZC_MMR6 : R6MMR6Rel, BGTZC_MMR6_ENC, BGTZC_MMR6_DESC, ISA_MICROMIPS32R6;
1632def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
1633                   ISA_MICROMIPS32R6;
1634def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
1635                   ISA_MICROMIPS32R6;
1636def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
1637                   ISA_MICROMIPS32R6;
1638def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
1639                   ISA_MICROMIPS32R6;
1640
1641//===----------------------------------------------------------------------===//
1642//
1643// MicroMips instruction aliases
1644//
1645//===----------------------------------------------------------------------===//
1646
1647def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
1648def : MipsInstAlias<"di", (DI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
1649def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
1650def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
1651                                      !strconcat("b", "\t$offset")> {
1652  string DecoderNamespace = "MicroMipsR6";
1653}
1654def : MipsInstAlias<"sync", (SYNC_MMR6 0), 1>, ISA_MICROMIPS32R6;
1655def : MipsInstAlias<"sdbbp", (SDBBP_MMR6 0), 1>, ISA_MICROMIPS32R6;
1656def : MipsInstAlias<"sigrie", (SIGRIE_MMR6 0), 1>, ISA_MICROMIPS32R6;
1657def : MipsInstAlias<"rdhwr $rt, $rs",
1658                    (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>,
1659                    ISA_MICROMIPS32R6;
1660def : MipsInstAlias<"mtc0 $rt, $rs",
1661                    (MTC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
1662                    ISA_MICROMIPS32R6;
1663def : MipsInstAlias<"mthc0 $rt, $rs",
1664                    (MTHC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
1665                    ISA_MICROMIPS32R6;
1666def : MipsInstAlias<"mfc0 $rt, $rs",
1667                    (MFC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
1668                    ISA_MICROMIPS32R6;
1669def : MipsInstAlias<"mfhc0 $rt, $rs",
1670                    (MFHC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
1671                    ISA_MICROMIPS32R6;
1672def : MipsInstAlias<"jalrc.hb $rs", (JALRC_HB_MMR6 RA, GPR32Opnd:$rs), 1>,
1673                    ISA_MICROMIPS32R6;
1674def : MipsInstAlias<"jal $offset", (BALC_MMR6 brtarget26_mm:$offset), 0>,
1675                    ISA_MICROMIPS32R6;
1676def : MipsInstAlias<"dvp", (DVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
1677def : MipsInstAlias<"evp", (EVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
1678def : MipsInstAlias<"jalrc $rs", (JALRC_MMR6 RA, GPR32Opnd:$rs), 1>,
1679      ISA_MICROMIPS32R6;
1680def : MipsInstAlias<"and $rs, $rt, $imm",
1681                    (ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
1682                    ISA_MICROMIPS32R6;
1683def : MipsInstAlias<"and $rs, $imm",
1684                    (ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
1685                    ISA_MICROMIPS32R6;
1686def : MipsInstAlias<"or $rs, $rt, $imm",
1687                    (ORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
1688                    ISA_MICROMIPS32R6;
1689def : MipsInstAlias<"or $rs, $imm",
1690                    (ORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
1691                    ISA_MICROMIPS32R6;
1692def : MipsInstAlias<"xor $rs, $rt, $imm",
1693                    (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
1694                    ISA_MICROMIPS32R6;
1695def : MipsInstAlias<"xor $rs, $imm",
1696                    (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
1697                    ISA_MICROMIPS32R6;
1698def : MipsInstAlias<"not $rt, $rs",
1699                    (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>,
1700                    ISA_MICROMIPS32R6;
1701def : MipsInstAlias<"not $rt",
1702                    (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>,
1703                    ISA_MICROMIPS32R6;
1704def : MipsInstAlias<"lapc $rd, $imm",
1705                    (ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm)>,
1706                    ISA_MICROMIPS32R6;
1707def : MipsInstAlias<"neg $rt, $rs",
1708                    (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
1709      ISA_MICROMIPS32R6;
1710def : MipsInstAlias<"neg $rt",
1711                    (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
1712      ISA_MICROMIPS32R6;
1713def : MipsInstAlias<"negu $rt, $rs",
1714                    (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
1715      ISA_MICROMIPS32R6;
1716def : MipsInstAlias<"negu $rt",
1717                    (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
1718      ISA_MICROMIPS32R6;
1719def : MipsInstAlias<"beqz16 $rs, $offset", (BEQZC16_MMR6 GPRMM16Opnd:$rs,
1720                                                         brtarget7_mm:$offset),
1721                    0>, ISA_MICROMIPS32R6;
1722def : MipsInstAlias<"bnez16 $rs, $offset", (BNEZC16_MMR6 GPRMM16Opnd:$rs,
1723                                                         brtarget7_mm:$offset),
1724                    0>, ISA_MICROMIPS32R6;
1725def : MipsInstAlias<"b16 $offset", (BC16_MMR6 brtarget10_mm:$offset), 0>,
1726                    ISA_MICROMIPS32R6;
1727
1728//===----------------------------------------------------------------------===//
1729//
1730// MicroMips arbitrary patterns that map to one or more instructions
1731//
1732//===----------------------------------------------------------------------===//
1733
1734def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
1735              (SW16_MMR6 GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS32R6;
1736def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1737              (SUBU_MMR6 GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS32R6;
1738
1739def : MipsPat<(select i32:$cond, i32:$t, i32:$f),
1740              (OR_MM (SELNEZ_MMR6 i32:$t, i32:$cond),
1741                     (SELEQZ_MMR6 i32:$f, i32:$cond))>,
1742              ISA_MICROMIPS32R6;
1743def : MipsPat<(select i32:$cond, i32:$t, immz),
1744              (SELNEZ_MMR6 i32:$t, i32:$cond)>,
1745              ISA_MICROMIPS32R6;
1746def : MipsPat<(select i32:$cond, immz, i32:$f),
1747              (SELEQZ_MMR6 i32:$f, i32:$cond)>,
1748              ISA_MICROMIPS32R6;
1749
1750defm : SelectInt_Pats<i32, OR_MM, XORI_MMR6, SLTi_MM, SLTiu_MM, SELEQZ_MMR6,
1751                      SELNEZ_MMR6, immZExt16, i32>, ISA_MICROMIPS32R6;
1752
1753defm S_MMR6 : Cmp_Pats<f32, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6;
1754defm D_MMR6 : Cmp_Pats<f64, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6;
1755
1756def : MipsPat<(f32 fpimm0), (MTC1_MMR6 ZERO)>, ISA_MICROMIPS32R6;
1757def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6(MTC1_MMR6 ZERO))>,
1758      ISA_MICROMIPS32R6;
1759def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
1760              (TRUNC_W_D_MMR6 FGR64Opnd:$src)>, ISA_MICROMIPS32R6;
1761def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
1762              (TRUNC_W_S_MMR6 FGR32Opnd:$src)>, ISA_MICROMIPS32R6;
1763
1764def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
1765              (ANDI16_MMR6 GPRMM16:$src, immZExtAndi16:$imm)>,
1766              ISA_MICROMIPS32R6;
1767def : MipsPat<(and GPR32:$src, immZExt16:$imm),
1768              (ANDI_MMR6 GPR32:$src, immZExt16:$imm)>, ISA_MICROMIPS32R6;
1769def : MipsPat<(i32 immZExt16:$imm),
1770              (XORI_MMR6 ZERO, immZExt16:$imm)>, ISA_MICROMIPS32R6;
1771def : MipsPat<(not GPRMM16:$in),
1772              (NOT16_MMR6 GPRMM16:$in)>, ISA_MICROMIPS32R6;
1773def : MipsPat<(not GPR32:$in),
1774              (NOR_MMR6 GPR32Opnd:$in, ZERO)>, ISA_MICROMIPS32R6;
1775// Patterns for load with a reg+imm operand.
1776let AddedComplexity = 41 in {
1777  def : LoadRegImmPat<LDC1_D64_MMR6, f64, load>, FGR_64, ISA_MICROMIPS32R6;
1778  def : StoreRegImmPat<SDC1_D64_MMR6, f64>, FGR_64, ISA_MICROMIPS32R6;
1779}
1780
1781let isCall=1, hasDelaySlot=0, isCTI=1, Defs = [RA] in {
1782  class JumpLinkMMR6<Instruction JumpInst, DAGOperand Opnd> :
1783    PseudoSE<(outs), (ins calltarget:$target), [], II_JAL>,
1784    PseudoInstExpansion<(JumpInst Opnd:$target)>;
1785}
1786
1787def JAL_MMR6 : JumpLinkMMR6<BALC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6;
1788
1789def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1790              (JAL_MMR6 texternalsym:$dst)>, ISA_MICROMIPS32R6;
1791def : MipsPat<(MipsJmpLink (iPTR tglobaladdr:$dst)),
1792              (JAL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6;
1793
1794def TAILCALL_MMR6 : TailCall<BC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6;
1795
1796def TAILCALLREG_MMR6  : TailCallReg<JRC16_MM, GPR32Opnd>, ISA_MICROMIPS32R6;
1797
1798def PseudoIndirectBranch_MMR6 : PseudoIndirectBranchBase<JRC16_MMR6,
1799                                                         GPR32Opnd>,
1800                                ISA_MICROMIPS32R6;
1801
1802def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1803              (TAILCALL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6;
1804
1805def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1806              (TAILCALL_MMR6 texternalsym:$dst)>, ISA_MICROMIPS32R6;
1807
1808
1809def : MipsPat<(brcond (i32 (setne GPR32:$lhs, 0)), bb:$dst),
1810              (BNEZC_MMR6 GPR32:$lhs, bb:$dst)>, ISA_MICROMIPS32R6;
1811def : MipsPat<(brcond (i32 (seteq GPR32:$lhs, 0)), bb:$dst),
1812              (BEQZC_MMR6 GPR32:$lhs, bb:$dst)>, ISA_MICROMIPS32R6;
1813
1814def : MipsPat<(brcond (i32 (setge GPR32:$lhs, GPR32:$rhs)), bb:$dst),
1815              (BEQZC_MMR6 (SLT_MM GPR32:$lhs, GPR32:$rhs), bb:$dst)>,
1816      ISA_MICROMIPS32R6;
1817def : MipsPat<(brcond (i32 (setuge GPR32:$lhs, GPR32:$rhs)), bb:$dst),
1818              (BEQZC_MMR6 (SLTu_MM GPR32:$lhs, GPR32:$rhs), bb:$dst)>,
1819      ISA_MICROMIPS32R6;
1820def : MipsPat<(brcond (i32 (setge GPR32:$lhs, immSExt16:$rhs)), bb:$dst),
1821              (BEQZC_MMR6 (SLTi_MM GPR32:$lhs, immSExt16:$rhs), bb:$dst)>,
1822      ISA_MICROMIPS32R6;
1823def : MipsPat<(brcond (i32 (setuge GPR32:$lhs, immSExt16:$rhs)), bb:$dst),
1824              (BEQZC_MMR6 (SLTiu_MM GPR32:$lhs, immSExt16:$rhs), bb:$dst)>,
1825      ISA_MICROMIPS32R6;
1826def : MipsPat<(brcond (i32 (setgt GPR32:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1827              (BEQZC_MMR6 (SLTi_MM GPR32:$lhs, (Plus1 imm:$rhs)), bb:$dst)>,
1828      ISA_MICROMIPS32R6;
1829def : MipsPat<(brcond (i32 (setugt GPR32:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1830              (BEQZC_MMR6 (SLTiu_MM GPR32:$lhs, (Plus1 imm:$rhs)), bb:$dst)>,
1831      ISA_MICROMIPS32R6;
1832
1833def : MipsPat<(brcond (i32 (setle GPR32:$lhs, GPR32:$rhs)), bb:$dst),
1834              (BEQZC_MMR6  (SLT_MM GPR32:$rhs, GPR32:$lhs), bb:$dst)>,
1835      ISA_MICROMIPS32R6;
1836def : MipsPat<(brcond (i32 (setule GPR32:$lhs, GPR32:$rhs)), bb:$dst),
1837              (BEQZC_MMR6  (SLTu_MM GPR32:$rhs, GPR32:$lhs), bb:$dst)>,
1838      ISA_MICROMIPS32R6;
1839
1840def : MipsPat<(brcond GPR32:$cond, bb:$dst),
1841              (BNEZC_MMR6 GPR32:$cond, bb:$dst)>, ISA_MICROMIPS32R6;
1842