xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td (revision 02e9120893770924227138ba49df1edb3896112a) 
1//=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes microMIPSr6 instructions.
10//
11//===----------------------------------------------------------------------===//
12
13def brtarget21_mm : Operand<OtherVT> {
14  let EncoderMethod = "getBranchTarget21OpValueMM";
15  let OperandType = "OPERAND_PCREL";
16  let DecoderMethod = "DecodeBranchTarget21MM";
17  let ParserMatchClass = MipsJumpTargetAsmOperand;
18  let PrintMethod = "printBranchOperand";
19}
20
21def brtarget26_mm : Operand<OtherVT> {
22  let EncoderMethod = "getBranchTarget26OpValueMM";
23  let OperandType = "OPERAND_PCREL";
24  let DecoderMethod = "DecodeBranchTarget26MM";
25  let ParserMatchClass = MipsJumpTargetAsmOperand;
26  let PrintMethod = "printBranchOperand";
27}
28
29def brtargetr6 : Operand<OtherVT> {
30  let EncoderMethod = "getBranchTargetOpValueMMR6";
31  let OperandType = "OPERAND_PCREL";
32  let DecoderMethod = "DecodeBranchTargetMM";
33  let ParserMatchClass = MipsJumpTargetAsmOperand;
34  let PrintMethod = "printBranchOperand";
35}
36
37def brtarget_lsl2_mm : Operand<OtherVT> {
38  let EncoderMethod = "getBranchTargetOpValueLsl2MMR6";
39  let OperandType = "OPERAND_PCREL";
40  // Instructions that use this operand have their decoder method
41  // set with DecodeDisambiguates
42  let DecoderMethod = "";
43  let ParserMatchClass = MipsJumpTargetAsmOperand;
44  let PrintMethod = "printBranchOperand";
45}
46
47//===----------------------------------------------------------------------===//
48//
49// Instruction Encodings
50//
51//===----------------------------------------------------------------------===//
52class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
53class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
54class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
55class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
56class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
57class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>;
58class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
59class AUIPC_MMR6_ENC  : PCREL16_FM_MMR6<0b11110>;
60class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>;
61class AUI_MMR6_ENC : AUI_FM_MMR6;
62class BALC_MMR6_ENC  : BRANCH_OFF26_FM<0b101101>;
63class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
64class BC16_MMR6_ENC : BC16_FM_MM16R6;
65class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>;
66class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>;
67class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
68class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
69class BEQZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<0b100000>;
70class BNEZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<0b101000>;
71class BGEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgec", 0b111101>,
72                      DecodeDisambiguates<"POP75GroupBranchMMR6">;
73class BGEUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgeuc", 0b110000>,
74                       DecodeDisambiguates<"BlezGroupBranchMMR6">;
75class BLTC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltc", 0b110101>,
76                      DecodeDisambiguates<"POP65GroupBranchMMR6">;
77class BLTUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltuc", 0b111000>,
78                       DecodeDisambiguates<"BgtzGroupBranchMMR6">;
79class BEQC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"beqc", 0b011101>;
80class BNEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bnec", 0b011111>;
81class BLTZC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bltzc", 0b110101>,
82                       DecodeDisambiguates<"POP65GroupBranchMMR6">;
83class BLEZC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"blezc", 0b111101>,
84                       DecodeDisambiguates<"POP75GroupBranchMMR6">;
85class BGEZC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bgezc", 0b111101>,
86                       DecodeDisambiguates<"POP75GroupBranchMMR6">;
87class BGTZC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bgtzc", 0b110101>,
88                       DecodeDisambiguates<"POP65GroupBranchMMR6">;
89class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"beqzalc", 0b011101>,
90                         DecodeDisambiguates<"POP35GroupBranchMMR6">;
91class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bnezalc", 0b011111>,
92                         DecodeDisambiguates<"POP37GroupBranchMMR6">;
93class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bgtzalc", 0b111000>,
94                         MMDecodeDisambiguatedBy<"BgtzGroupBranchMMR6">;
95class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bltzalc", 0b111000>,
96                         MMDecodeDisambiguatedBy<"BgtzGroupBranchMMR6">;
97class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bgezalc", 0b110000>,
98                         MMDecodeDisambiguatedBy<"BlezGroupBranchMMR6">;
99class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"blezalc", 0b110000>,
100                         MMDecodeDisambiguatedBy<"BlezGroupBranchMMR6">;
101class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
102class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
103class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
104class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
105class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
106class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
107class EI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"ei", 0x15d>;
108class DI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"di", 0b0100011101>;
109class ERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0x3cd>;
110class DERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0b1110001101>;
111class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
112class GINVI_MMR6_ENC : POOL32A_GINV_FM_MMR6<"ginvi", 0b00>;
113class GINVT_MMR6_ENC : POOL32A_GINV_FM_MMR6<"ginvt", 0b10>;
114class JALRC16_MMR6_ENC : POOL16C_JALRC_FM_MM16R6<0xb>;
115class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
116class JIC_MMR6_ENC   : JMP_IDX_COMPACT_FM<0b101000>;
117class JRC16_MMR6_ENC: POOL16C_JALRC_FM_MM16R6<0x3>;
118class JRCADDIUSP_MMR6_ENC : POOL16C_JRCADDIUSP_FM_MM16R6<0x13>;
119class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
120class LWPC_MMR6_ENC  : PCREL19_FM_MMR6<0b01>;
121class LWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0x2>;
122class MFC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfc0", 0b00011, 0b111100>;
123class MFC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mfc1", 0b10000000>;
124class MFC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfc2", 0b0100110100>;
125class MFHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfhc0", 0b00011, 0b110100>;
126class MFHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfhc2", 0b1000110100>;
127class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
128class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
129class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
130class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
131class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
132class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
133class MTC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mtc0", 0b01011, 0b111100>;
134class MTC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mtc1", 0b10100000>;
135class MTC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mtc2", 0b0101110100>;
136class MTHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mthc0", 0b01011, 0b110100>;
137class MTHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mthc2", 0b1001110100>;
138class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
139class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
140class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
141class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
142class SB16_MMR6_ENC : LOAD_STORE_FM_MM16<0x22>;
143class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
144class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
145class SH16_MMR6_ENC : LOAD_STORE_FM_MM16<0x2a>;
146class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
147class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
148class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
149class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
150class SW16_MMR6_ENC : LOAD_STORE_FM_MM16<0x3a>;
151class SWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0xa>;
152class SWSP_MMR6_ENC : LOAD_STORE_SP_FM_MM16<0x32>;
153class WRPGPR_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<"wrpgpr", 0x3c5>;
154class WSBH_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<"wsbh", 0x1ec>;
155class LB_MMR6_ENC : LB32_FM_MMR6;
156class LBU_MMR6_ENC : LBU32_FM_MMR6;
157class PAUSE_MMR6_ENC : POOL32A_PAUSE_FM_MMR6<"pause", 0b00101>;
158class RDHWR_MMR6_ENC : POOL32A_RDHWR_FM_MMR6;
159class WAIT_MMR6_ENC : WAIT_FM_MM, MMR6Arch<"wait">;
160class SSNOP_MMR6_ENC : BARRIER_FM_MM<0x1>, MMR6Arch<"ssnop">;
161class SYNC_MMR6_ENC : POOL32A_SYNC_FM_MMR6;
162class SYNCI_MMR6_ENC : POOL32I_SYNCI_FM_MMR6, MMR6Arch<"synci">;
163class RDPGPR_MMR6_ENC : POOL32A_RDPGPR_FM_MMR6<0b1110000101>;
164class SDBBP_MMR6_ENC : SDBBP_FM_MM, MMR6Arch<"sdbbp">;
165class SIGRIE_MMR6_ENC : SIGRIE_FM_MM, MMR6Arch<"sigrie">;
166class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
167class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
168class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
169class ABS_D_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.d", 1, 0b0001101>;
170class FLOOR_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.s", 0, 0b00001100>;
171class FLOOR_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.d", 1, 0b00001100>;
172class FLOOR_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.s", 0, 0b00101100>;
173class FLOOR_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.d", 1, 0b00101100>;
174class CEIL_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.s", 0, 0b01001100>;
175class CEIL_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.d", 1, 0b01001100>;
176class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>;
177class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>;
178class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>;
179class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>;
180class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
181class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
182class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
183class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
184class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
185class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
186class JALRC_HB_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc.hb", 0b0001111100>;
187class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>;
188class RINT_D_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.d", 1>;
189class ROUND_L_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.s", 0,
190                                                       0b11001100>;
191class ROUND_L_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.d", 1,
192                                                       0b11001100>;
193class ROUND_W_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.s", 0,
194                                                       0b11101100>;
195class ROUND_W_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.d", 1,
196                                                       0b11101100>;
197class SEL_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.s", 0, 0b010111000>;
198class SEL_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.d", 1, 0b010111000>;
199class SELEQZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.s", 0, 0b000111000>;
200class SELEQZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.d", 1, 0b000111000>;
201class SELNEZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selnez.s", 0, 0b001111000>;
202class SELNEZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selnez.d", 1, 0b001111000>;
203class CLASS_S_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.s", 0, 0b001100000>;
204class CLASS_D_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.d", 1, 0b001100000>;
205class EXT_MMR6_ENC : POOL32A_EXT_INS_FM_MMR6<"ext", 0b101100>;
206class INS_MMR6_ENC : POOL32A_EXT_INS_FM_MMR6<"ins", 0b001100>;
207class JALRC_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc", 0b0000111100>;
208class BOVC_MMR6_ENC : POP35_BOVC_FM_MMR6<"bovc">;
209class BNVC_MMR6_ENC : POP37_BNVC_FM_MMR6<"bnvc">;
210class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6;
211class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6;
212class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>;
213class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6;
214class OR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1001>;
215class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>;
216class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>;
217class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>;
218class LI16_MMR6_ENC : LI_FM_MM16;
219class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
220class MOVEP_MMR6_ENC  : POOL16C_MOVEP16_FM_MMR6;
221class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
222class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
223class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
224class TLBINV_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinv", 0x10d>;
225class TLBINVF_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinvf", 0x14d>;
226class DVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"dvp", 0b0001100101>;
227class EVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"evp", 0b0011100101>;
228class BC1EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1eqzc", 0b01000>;
229class BC1NEZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1nezc", 0b01001>;
230class BC2EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc2eqzc", 0b01010>;
231class BC2NEZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc2nezc", 0b01011>;
232class LDC1_MMR6_ENC : LDWC1_SDWC1_FM_MMR6<"ldc1", 0b101111>;
233class SDC1_MMR6_ENC : LDWC1_SDWC1_FM_MMR6<"sdc1", 0b101110>;
234class LDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"ldc2", 0b0010>;
235class SDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"sdc2", 0b1010>;
236class LWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"lwc2", 0b0000>;
237class SWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"swc2", 0b1000>;
238
239class LL_MMR6_ENC  : POOL32C_LL_E_SC_E_FM_MMR6<"ll", 0b0011, 0b000>;
240class SC_MMR6_ENC  : POOL32C_LL_E_SC_E_FM_MMR6<"sc", 0b1011, 0b000>;
241
242/// Floating Point Instructions
243class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
244class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
245class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
246class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
247class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
248class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
249class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
250class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
251class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
252class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
253class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
254class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
255class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
256class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>;
257class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>;
258class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>;
259class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>;
260class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>;
261class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>;
262
263class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>;
264class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>;
265class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>;
266class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>;
267class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>;
268class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>;
269
270//===----------------------------------------------------------------------===//
271//
272// Instruction Descriptions
273//
274//===----------------------------------------------------------------------===//
275
276class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
277                                  RegisterOperand GPROpnd>
278    : BRANCH_DESC_BASE {
279  dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
280  dag OutOperandList = (outs);
281  string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
282  list<Register> Defs = [AT];
283  InstrItinClass Itinerary = II_BCCZC;
284}
285
286class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
287                                                      GPR32Opnd> {
288  list<Register> Defs = [RA];
289}
290
291class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
292                                                      GPR32Opnd> {
293  list<Register> Defs = [RA];
294}
295
296class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
297                                                      GPR32Opnd> {
298  list<Register> Defs = [RA];
299}
300
301class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
302                                                      GPR32Opnd> {
303  list<Register> Defs = [RA];
304}
305
306class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
307                                                      GPR32Opnd> {
308  list<Register> Defs = [RA];
309}
310
311class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
312                                                      GPR32Opnd> {
313  list<Register> Defs = [RA];
314}
315
316class BLTZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzc", brtarget_lsl2_mm,
317                                                    GPR32Opnd>;
318class BLEZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezc", brtarget_lsl2_mm,
319                                                    GPR32Opnd>;
320class BGEZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezc", brtarget_lsl2_mm,
321                                                    GPR32Opnd>;
322class BGTZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzc", brtarget_lsl2_mm,
323                                                    GPR32Opnd>;
324
325class CMP_CBR_2R_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
326                                RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
327  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
328  dag OutOperandList = (outs);
329  string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
330  list<Register> Defs = [AT];
331  InstrItinClass Itinerary = II_BCCC;
332}
333
334class BGEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgec", brtarget_lsl2_mm,
335                                                 GPR32Opnd>;
336class BGEUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgeuc", brtarget_lsl2_mm,
337                                                 GPR32Opnd>;
338class BLTC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltc", brtarget_lsl2_mm,
339                                                 GPR32Opnd>;
340class BLTUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltuc", brtarget_lsl2_mm,
341                                                 GPR32Opnd>;
342class BEQC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"beqc", brtarget_lsl2_mm,
343                                                 GPR32Opnd>;
344class BNEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bnec", brtarget_lsl2_mm,
345                                                 GPR32Opnd>;
346
347class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd, 1, II_ADD>;
348class ADDIU_MMR6_DESC
349    : ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, add>;
350class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU>;
351class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>;
352class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd, 1, II_MUH, mulhs>;
353class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd, 1, II_MULU>;
354class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd, 1, II_MUHU, mulhu>;
355
356class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd, InstrItinClass Itin>
357    : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
358  dag InOperandList = (ins opnd:$offset);
359  dag OutOperandList = (outs);
360  string AsmString = !strconcat(instr_asm, "\t$offset");
361  bit isBarrier = 1;
362  InstrItinClass Itinerary = Itin;
363}
364
365class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26_mm, II_BALC> {
366  bit isCall = 1;
367  list<Register> Defs = [RA];
368}
369class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26_mm, II_BC> {
370  list<dag> Pattern = [(br bb:$offset)];
371}
372
373class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
374                                       !strconcat("bc16", "\t$offset"), [],
375                                       II_BC, FrmI>,
376                       MMR6Arch<"bc16"> {
377  let isBranch = 1;
378  let isTerminator = 1;
379  let isBarrier = 1;
380  let hasDelaySlot = 0;
381  let AdditionalPredicates = [RelocPIC];
382  let Defs = [AT];
383}
384
385class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
386    : CBranchZeroMM<instr_asm, brtarget7_mm, GPRMM16Opnd>,
387      MMR6Arch<instr_asm> {
388  let isBranch = 1;
389  let isTerminator = 1;
390  let hasDelaySlot = 0;
391  let Defs = [AT];
392}
393class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">;
394class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">;
395
396class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>;
397class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd, 0,II_SUBU>;
398
399class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
400    : MMR6Arch<instr_asm> {
401  dag OutOperandList = (outs GPROpnd:$rd);
402  dag InOperandList = (ins GPROpnd:$rt);
403  string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
404  list<dag> Pattern = [];
405  InstrItinClass Itinerary = II_BITSWAP;
406}
407
408class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
409
410class BRK_MMR6_DESC : BRK_FT<"break">;
411
412class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
413                           InstrItinClass Itin>
414      : MMR6Arch<instr_asm> {
415  dag OutOperandList = (outs);
416  dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
417  string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
418  list<dag> Pattern = [];
419  string DecoderMethod = "DecodeCacheOpMM";
420  InstrItinClass Itinerary = Itin;
421}
422
423class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, II_CACHE>;
424class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, II_PREF>;
425
426class LB_LBU_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
427                            RegisterOperand GPROpnd, InstrItinClass Itin>
428    : MMR6Arch<instr_asm> {
429  dag OutOperandList = (outs GPROpnd:$rt);
430  dag InOperandList = (ins MemOpnd:$addr);
431  string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
432  string DecoderMethod = "DecodeLoadByte15";
433  bit mayLoad = 1;
434  InstrItinClass Itinerary = Itin;
435}
436class LB_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lb", mem_mm_16, GPR32Opnd, II_LB>;
437class LBU_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lbu", mem_mm_16, GPR32Opnd,
438                                            II_LBU>;
439
440class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
441                             InstrItinClass Itin> : MMR6Arch<instr_asm> {
442  dag OutOperandList = (outs GPROpnd:$rt);
443  dag InOperandList = (ins GPROpnd:$rs);
444  string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
445  InstrItinClass Itinerary = Itin;
446}
447
448class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd, II_CLO>;
449class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd, II_CLZ>;
450
451class EHB_MMR6_DESC : Barrier<"ehb", II_EHB>;
452class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd, II_EI>;
453class DI_MMR6_DESC : DEI_FT<"di", GPR32Opnd, II_DI>;
454
455class ERET_MMR6_DESC : ER_FT<"eret", II_ERET>;
456class DERET_MMR6_DESC : ER_FT<"deret", II_DERET>;
457class ERETNC_MMR6_DESC : ER_FT<"eretnc", II_ERETNC>;
458
459class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
460    : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
461                      [(MipsJmpLink RO:$rs)], II_JALR, FrmR>,
462      MMR6Arch<opstr> {
463  let isCall = 1;
464  let hasDelaySlot = 0;
465  let Defs = [RA];
466  let hasPostISelHook = 1;
467}
468class JALRC16_MMR6_DESC : JALRC16_MMR6_DESC_BASE<"jalr", GPR32Opnd>;
469
470class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
471                                     RegisterOperand GPROpnd,
472                                     InstrItinClass Itin>
473    : MMR6Arch<opstr> {
474  dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
475  string AsmString = !strconcat(opstr, "\t$rt, $offset");
476  list<dag> Pattern = [];
477  bit isTerminator = 1;
478  bit hasDelaySlot = 0;
479  InstrItinClass Itinerary = Itin;
480}
481
482class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
483                                                       GPR32Opnd, II_JIALC> {
484  bit isCall = 1;
485  list<Register> Defs = [RA];
486}
487
488class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
489                                                     GPR32Opnd, II_JIC> {
490  bit isBarrier = 1;
491  list<Register> Defs = [AT];
492}
493
494class JRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
495    : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
496                      [], II_JR, FrmR>,
497      MMR6Arch<opstr> {
498  let hasDelaySlot = 0;
499  let isBranch = 1;
500  let isIndirectBranch = 1;
501}
502class JRC16_MMR6_DESC : JRC16_MMR6_DESC_BASE<"jrc16", GPR32Opnd>;
503
504class JRCADDIUSP_MMR6_DESC
505    : MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jrcaddiusp\t$imm",
506                      [], II_JRADDIUSP, FrmR>,
507      MMR6Arch<"jrcaddiusp"> {
508  let hasDelaySlot = 0;
509  let isTerminator = 1;
510  let isBarrier = 1;
511  let isBranch = 1;
512  let isIndirectBranch = 1;
513}
514
515class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
516                      Operand ImmOpnd, InstrItinClass Itin>
517    : MMR6Arch<instr_asm> {
518  dag OutOperandList = (outs GPROpnd:$rd);
519  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
520  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
521  list<dag> Pattern = [];
522  InstrItinClass Itinerary = Itin;
523}
524
525class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2,
526                                             II_ALIGN>;
527
528class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
529                         InstrItinClass Itin> : MMR6Arch<instr_asm> {
530  dag OutOperandList = (outs GPROpnd:$rt);
531  dag InOperandList = (ins GPROpnd:$rs, uimm16:$imm);
532  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
533  list<dag> Pattern = [];
534  InstrItinClass Itinerary = Itin;
535}
536
537class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd, II_AUI>;
538
539class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
540                            InstrItinClass Itin> : MMR6Arch<instr_asm> {
541  dag OutOperandList = (outs GPROpnd:$rt);
542  dag InOperandList = (ins simm16:$imm);
543  string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
544  list<dag> Pattern = [];
545  InstrItinClass Itinerary = Itin;
546}
547
548class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd, II_ALUIPC>;
549class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd, II_AUIPC>;
550
551class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
552                         Operand ImmOpnd, InstrItinClass Itin>
553    : MMR6Arch<instr_asm> {
554  dag OutOperandList = (outs GPROpnd:$rd);
555  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
556  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
557  list<dag> Pattern = [];
558  InstrItinClass Itinerary = Itin;
559}
560
561class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1, II_LSA>;
562
563class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
564                           Operand ImmOpnd, InstrItinClass Itin>
565    : MMR6Arch<instr_asm> {
566  dag OutOperandList = (outs GPROpnd:$rt);
567  dag InOperandList = (ins ImmOpnd:$imm);
568  string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
569  list<dag> Pattern = [];
570  InstrItinClass Itinerary = Itin;
571}
572
573class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd,
574                                               simm19_lsl2, II_ADDIUPC>;
575class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2,
576                                           II_LWPC>;
577
578class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
579                               InstrItinClass Itin> : MMR6Arch<instr_asm> {
580  dag OutOperandList = (outs GPROpnd:$rd);
581  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
582  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
583  list<dag> Pattern = [];
584  InstrItinClass Itinerary = Itin;
585}
586
587class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd,
588                                                  II_SELCCZ>;
589class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd,
590                                                  II_SELCCZ>;
591class PAUSE_MMR6_DESC : Barrier<"pause", II_PAUSE>;
592class RDHWR_MMR6_DESC : MMR6Arch<"rdhwr">, MipsR6Inst {
593  dag OutOperandList = (outs GPR32Opnd:$rt);
594  dag InOperandList = (ins HWRegsOpnd:$rs, uimm3:$sel);
595  string AsmString = !strconcat("rdhwr", "\t$rt, $rs, $sel");
596  list<dag> Pattern = [];
597  InstrItinClass Itinerary = II_RDHWR;
598  Format Form = FrmR;
599}
600
601class WAIT_MMR6_DESC : WaitMM<"wait">;
602// FIXME: ssnop should not be defined for R6. Per MD000582 microMIPS32 6.03:
603//        Assemblers targeting specifically Release 6 should reject the SSNOP
604//        instruction with an error.
605class SSNOP_MMR6_DESC : Barrier<"ssnop", II_SSNOP>;
606class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
607
608class DIVMOD_MMR6_DESC_BASE<string opstr, RegisterOperand GPROpnd,
609                            InstrItinClass Itin,
610                            SDPatternOperator OpNode=null_frag>
611    : MipsR6Inst {
612  dag OutOperandList = (outs GPROpnd:$rd);
613  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
614  string AsmString = !strconcat(opstr, "\t$rd, $rs, $rt");
615  list<dag> Pattern = [(set GPROpnd:$rd, (OpNode GPROpnd:$rs, GPROpnd:$rt))];
616  string BaseOpcode = opstr;
617  Format f = FrmR;
618  let isCommutable = 0;
619  let isReMaterializable = 1;
620  InstrItinClass Itinerary = Itin;
621
622  // This instruction doesn't trap division by zero itself. We must insert
623  // teq instructions as well.
624  bit usesCustomInserter = 1;
625}
626class DIV_MMR6_DESC  : DIVMOD_MMR6_DESC_BASE<"div", GPR32Opnd, II_DIV, sdiv>;
627class DIVU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"divu", GPR32Opnd, II_DIVU, udiv>;
628class MOD_MMR6_DESC  : DIVMOD_MMR6_DESC_BASE<"mod", GPR32Opnd, II_MOD, srem>;
629class MODU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"modu", GPR32Opnd, II_MODU, urem>;
630class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>;
631class ANDI_MMR6_DESC : ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI>;
632class NOR_MMR6_DESC : LogicNOR<"nor", GPR32Opnd>;
633class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>;
634class ORI_MMR6_DESC : ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
635                                  or> {
636  int AddedComplexity = 1;
637}
638class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>;
639class XORI_MMR6_DESC : ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI,
640                                   immZExt16, xor>;
641class SW_MMR6_DESC : Store<"sw", GPR32Opnd> {
642  InstrItinClass Itinerary = II_SW;
643}
644class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO,
645                                 InstrItinClass Itin> {
646  dag InOperandList = (ins RO:$rs);
647  dag OutOperandList = (outs RO:$rt);
648  string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
649  list<dag> Pattern = [];
650  Format f = FrmR;
651  string BaseOpcode = instr_asm;
652  bit hasSideEffects = 0;
653  InstrItinClass Itinerary = Itin;
654}
655class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd,
656                                                    II_WRPGPR>;
657class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd, II_WSBH>;
658
659class MTC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
660                         RegisterOperand SrcRC, InstrItinClass Itin> {
661  dag InOperandList = (ins SrcRC:$rt, uimm3:$sel);
662  dag OutOperandList = (outs DstRC:$rs);
663  string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel");
664  list<dag> Pattern = [];
665  Format f = FrmFR;
666  string BaseOpcode = opstr;
667  InstrItinClass Itinerary = Itin;
668}
669class MTC1_MMR6_DESC_BASE<
670      string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
671      InstrItinClass Itin = NoItinerary, SDPatternOperator OpNode = null_frag>
672      : MipsR6Inst {
673  dag InOperandList = (ins SrcRC:$rt);
674  dag OutOperandList = (outs DstRC:$fs);
675  string AsmString = !strconcat(opstr, "\t$rt, $fs");
676  list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))];
677  Format f = FrmFR;
678  InstrItinClass Itinerary = Itin;
679  string BaseOpcode = opstr;
680}
681class MTC1_64_MMR6_DESC_BASE<
682      string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
683      InstrItinClass Itin = NoItinerary> : MipsR6Inst {
684  dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt);
685  dag OutOperandList = (outs DstRC:$fs);
686  string AsmString = !strconcat(opstr, "\t$rt, $fs");
687  list<dag> Pattern = [];
688  Format f = FrmFR;
689  InstrItinClass Itinerary = Itin;
690  string BaseOpcode = opstr;
691  // $fs_in is part of a white lie to work around a widespread bug in the FPU
692  // implementation. See expandBuildPairF64 for details.
693  let Constraints = "$fs = $fs_in";
694}
695class MTC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
696                         RegisterOperand SrcRC, InstrItinClass Itin> {
697  dag InOperandList = (ins SrcRC:$rt);
698  dag OutOperandList = (outs DstRC:$impl);
699  string AsmString = !strconcat(opstr, "\t$rt, $impl");
700  list<dag> Pattern = [];
701  Format f = FrmFR;
702  string BaseOpcode = opstr;
703  InstrItinClass Itinerary = Itin;
704}
705
706class MTC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mtc0", COP0Opnd, GPR32Opnd,
707                                           II_MTC0>;
708class MTC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"mtc1", FGR32Opnd, GPR32Opnd,
709                                           II_MTC1, bitconvert>, HARDFLOAT;
710class MTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mtc2", COP2Opnd, GPR32Opnd,
711                                           II_MTC2>;
712class MTHC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mthc0", COP0Opnd, GPR32Opnd,
713                                            II_MTHC0>;
714class MTHC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mthc2", COP2Opnd, GPR32Opnd,
715                                            II_MTC2>;
716
717class MFC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
718                          RegisterOperand SrcRC, InstrItinClass Itin> {
719  dag InOperandList = (ins SrcRC:$rs, uimm3:$sel);
720  dag OutOperandList = (outs DstRC:$rt);
721  string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel");
722  list<dag> Pattern = [];
723  Format f = FrmFR;
724  string BaseOpcode = opstr;
725  InstrItinClass Itinerary = Itin;
726}
727class MFC1_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
728                          RegisterOperand SrcRC,
729                          InstrItinClass Itin = NoItinerary,
730                          SDPatternOperator OpNode = null_frag> : MipsR6Inst {
731  dag InOperandList = (ins SrcRC:$fs);
732  dag OutOperandList = (outs DstRC:$rt);
733  string AsmString = !strconcat(opstr, "\t$rt, $fs");
734  list<dag> Pattern = [(set DstRC:$rt, (OpNode SrcRC:$fs))];
735  Format f = FrmFR;
736  InstrItinClass Itinerary = Itin;
737  string BaseOpcode = opstr;
738}
739class MFC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
740                          RegisterOperand SrcRC, InstrItinClass Itin> {
741  dag InOperandList = (ins SrcRC:$impl);
742  dag OutOperandList = (outs DstRC:$rt);
743  string AsmString = !strconcat(opstr, "\t$rt, $impl");
744  list<dag> Pattern = [];
745  Format f = FrmFR;
746  string BaseOpcode = opstr;
747  InstrItinClass Itinerary = Itin;
748}
749class MFC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfc0", GPR32Opnd, COP0Opnd,
750                                           II_MFC0>;
751class MFC1_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfc1", GPR32Opnd, FGR32Opnd,
752                                           II_MFC1, bitconvert>, HARDFLOAT;
753class MFC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfc2", GPR32Opnd, COP2Opnd,
754                                           II_MFC2>;
755class MFHC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfhc0", GPR32Opnd, COP0Opnd,
756                                            II_MFHC0>;
757class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd,
758                                            II_MFC2>;
759
760class LDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 {
761  dag InOperandList = (ins mem_mm_16:$addr);
762  dag OutOperandList = (outs FGR64Opnd:$ft);
763  string AsmString = !strconcat("ldc1", "\t$ft, $addr");
764  list<dag> Pattern = [(set FGR64Opnd:$ft, (load addrimm16:$addr))];
765  Format f = FrmFI;
766  InstrItinClass Itinerary = II_LDC1;
767  string BaseOpcode = "ldc1";
768  bit mayLoad = 1;
769  let DecoderMethod = "DecodeFMemMMR2";
770}
771
772class SDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 {
773  dag InOperandList = (ins FGR64Opnd:$ft, mem_mm_16:$addr);
774  dag OutOperandList = (outs);
775  string AsmString = !strconcat("sdc1", "\t$ft, $addr");
776  list<dag> Pattern = [(store FGR64Opnd:$ft, addrimm16:$addr)];
777  Format f = FrmFI;
778  InstrItinClass Itinerary = II_SDC1;
779  string BaseOpcode = "sdc1";
780  bit mayStore = 1;
781  let DecoderMethod = "DecodeFMemMMR2";
782}
783
784class LDC2_LWC2_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
785  dag OutOperandList = (outs COP2Opnd:$rt);
786  dag InOperandList = (ins mem_mm_11:$addr);
787  string AsmString = !strconcat(opstr, "\t$rt, $addr");
788  list<dag> Pattern = [(set COP2Opnd:$rt, (load addrimm11:$addr))];
789  Format f = FrmFI;
790  InstrItinClass Itinerary = itin;
791  string BaseOpcode = opstr;
792  bit mayLoad = 1;
793  string DecoderMethod = "DecodeFMemCop2MMR6";
794}
795class LDC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"ldc2", II_LDC2>;
796class LWC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"lwc2", II_LWC2>;
797
798class SDC2_SWC2_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
799  dag OutOperandList = (outs);
800  dag InOperandList = (ins COP2Opnd:$rt, mem_mm_11:$addr);
801  string AsmString = !strconcat(opstr, "\t$rt, $addr");
802  list<dag> Pattern = [(store COP2Opnd:$rt, addrimm11:$addr)];
803  Format f = FrmFI;
804  InstrItinClass Itinerary = itin;
805  string BaseOpcode = opstr;
806  bit mayStore = 1;
807  string DecoderMethod = "DecodeFMemCop2MMR6";
808}
809class SDC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"sdc2", II_SDC2>;
810class SWC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"swc2", II_SWC2>;
811
812class GINV_MMR6_DESC_BASE<string opstr,
813                          RegisterOperand SrcRC, InstrItinClass Itin> {
814  dag InOperandList = (ins SrcRC:$rs, uimm2:$type);
815  dag OutOperandList = (outs);
816  string AsmString = !strconcat(opstr, "\t$rs, $type");
817  list<dag> Pattern = [];
818  Format f = FrmFR;
819  string BaseOpcode = opstr;
820  InstrItinClass Itinerary = Itin;
821}
822
823class GINVI_MMR6_DESC : GINV_MMR6_DESC_BASE<"ginvi", GPR32Opnd,
824                                            II_GINVI> {
825  bits<2> type = 0b00;
826  dag InOperandList = (ins GPR32Opnd:$rs);
827  string AsmString = "ginvi\t$rs";
828}
829class GINVT_MMR6_DESC : GINV_MMR6_DESC_BASE<"ginvt", GPR32Opnd,
830                                            II_GINVT>;
831
832class SC_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
833  dag OutOperandList = (outs GPR32Opnd:$dst);
834  dag InOperandList = (ins GPR32Opnd:$rt, mem_mm_9:$addr);
835  string AsmString = !strconcat(opstr, "\t$rt, $addr");
836  InstrItinClass Itinerary = itin;
837  string BaseOpcode = opstr;
838  bit mayStore = 1;
839  string Constraints = "$rt = $dst";
840  string DecoderMethod = "DecodeMemMMImm9";
841}
842
843class LL_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
844  dag OutOperandList = (outs GPR32Opnd:$rt);
845  dag InOperandList = (ins mem_mm_9:$addr);
846  string AsmString = !strconcat(opstr, "\t$rt, $addr");
847  InstrItinClass Itinerary = itin;
848  string BaseOpcode = opstr;
849  bit mayLoad = 1;
850  string DecoderMethod = "DecodeMemMMImm9";
851}
852
853class SC_MMR6_DESC : SC_MMR6_DESC_BASE<"sc", II_SC>;
854class LL_MMR6_DESC : LL_MMR6_DESC_BASE<"ll", II_LL>;
855
856/// Floating Point Instructions
857class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
858                            InstrItinClass Itin, bit isComm,
859                            SDPatternOperator OpNode = null_frag> : HARDFLOAT {
860  dag OutOperandList = (outs RC:$fd);
861  dag InOperandList = (ins RC:$ft, RC:$fs);
862  string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
863  list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
864  InstrItinClass Itinerary = Itin;
865  bit isCommutable = isComm;
866}
867class FADD_S_MMR6_DESC
868  : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
869class FSUB_S_MMR6_DESC
870  : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
871class FMUL_S_MMR6_DESC
872  : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
873class FDIV_S_MMR6_DESC
874  : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
875class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd,
876                                            II_MADDF_S>, HARDFLOAT;
877class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd,
878                                            II_MADDF_D>, HARDFLOAT;
879class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd,
880                                            II_MSUBF_S>, HARDFLOAT;
881class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd,
882                                            II_MSUBF_D>, HARDFLOAT;
883
884class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
885                               RegisterOperand SrcRC, InstrItinClass Itin,
886                               SDPatternOperator OpNode = null_frag>
887                               : HARDFLOAT, NeverHasSideEffects {
888  dag OutOperandList = (outs DstRC:$ft);
889  dag InOperandList = (ins SrcRC:$fs);
890  string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
891  list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
892  InstrItinClass Itinerary = Itin;
893  Format Form = FrmFR;
894}
895class FMOV_S_MMR6_DESC
896  : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
897class FMOV_D_MMR6_DESC
898  : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>;
899class FNEG_S_MMR6_DESC
900  : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
901
902class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd, II_MAX_S>,
903                        HARDFLOAT;
904class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd, II_MAX_D>,
905                        HARDFLOAT;
906class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd, II_MIN_S>,
907                        HARDFLOAT;
908class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd, II_MIN_D>,
909                        HARDFLOAT;
910
911class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd, II_MAXA_S>,
912                         HARDFLOAT;
913class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd, II_MAXA_D>,
914                         HARDFLOAT;
915class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd, II_MINA_S>,
916                         HARDFLOAT;
917class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd, II_MINA_D>,
918                         HARDFLOAT;
919
920class CVT_MMR6_DESC_BASE<
921    string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
922    InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
923    : HARDFLOAT, NeverHasSideEffects {
924  dag OutOperandList = (outs DstRC:$ft);
925  dag InOperandList = (ins SrcRC:$fs);
926  string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
927  list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
928  InstrItinClass Itinerary = Itin;
929  Format Form = FrmFR;
930}
931
932class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd,
933                                             II_CVT>;
934class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd,
935                                             II_CVT>;
936class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd,
937                                             II_CVT>;
938class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd,
939                                             II_CVT>, FGR_64;
940class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
941                                             II_CVT>;
942class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
943                                             II_CVT>, FGR_64;
944
945multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
946                       RegisterOperand FGROpnd, InstrItinClass Itin> {
947  def CMP_AF_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
948      !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
949      CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd, Itin>, HARDFLOAT,
950      ISA_MICROMIPS32R6;
951  def CMP_UN_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
952      !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
953      CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, Itin, setuo>, HARDFLOAT,
954      ISA_MICROMIPS32R6;
955  def CMP_EQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
956      !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
957      CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, Itin, setoeq>, HARDFLOAT,
958      ISA_MICROMIPS32R6;
959  def CMP_UEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
960      !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
961      CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, Itin, setueq>, HARDFLOAT,
962      ISA_MICROMIPS32R6;
963  def CMP_LT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
964      !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
965      CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, Itin, setolt>, HARDFLOAT,
966      ISA_MICROMIPS32R6;
967  def CMP_ULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
968      !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
969      CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, Itin, setult>, HARDFLOAT,
970      ISA_MICROMIPS32R6;
971  def CMP_LE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
972      !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
973      CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, Itin, setole>, HARDFLOAT,
974      ISA_MICROMIPS32R6;
975  def CMP_ULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
976      !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
977      CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, Itin, setule>, HARDFLOAT,
978      ISA_MICROMIPS32R6;
979  def CMP_SAF_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
980      !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
981      CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd, Itin>, HARDFLOAT,
982      ISA_MICROMIPS32R6;
983  def CMP_SUN_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
984      !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
985      CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd, Itin>, HARDFLOAT,
986      ISA_MICROMIPS32R6;
987  def CMP_SEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
988      !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
989      CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd, Itin>, HARDFLOAT,
990      ISA_MICROMIPS32R6;
991  def CMP_SUEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
992      !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
993      CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd, Itin>, HARDFLOAT,
994      ISA_MICROMIPS32R6;
995  def CMP_SLT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
996      !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
997      CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd, Itin>, HARDFLOAT,
998      ISA_MICROMIPS32R6;
999  def CMP_SULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1000      !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
1001      CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd, Itin>, HARDFLOAT,
1002      ISA_MICROMIPS32R6;
1003  def CMP_SLE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1004      !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
1005      CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd, Itin>, HARDFLOAT,
1006      ISA_MICROMIPS32R6;
1007  def CMP_SULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1008      !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
1009      CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd, Itin>, HARDFLOAT,
1010      ISA_MICROMIPS32R6;
1011}
1012
1013class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
1014                             RegisterOperand SrcRC, InstrItinClass Itin,
1015                             SDPatternOperator OpNode = null_frag>
1016    : HARDFLOAT, NeverHasSideEffects {
1017  dag OutOperandList = (outs DstRC:$ft);
1018  dag InOperandList  = (ins SrcRC:$fs);
1019  string AsmString   = !strconcat(instr_asm, "\t$ft, $fs");
1020  list<dag>  Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
1021  InstrItinClass Itinerary = Itin;
1022  Format Form = FrmFR;
1023  list<Predicate> EncodingPredicates = [HasStdEnc];
1024}
1025
1026class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd,
1027                                                    FGR32Opnd, II_FLOOR>;
1028class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd,
1029                                                    FGR64Opnd, II_FLOOR>;
1030class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd,
1031                                                    FGR32Opnd, II_FLOOR>;
1032class FLOOR_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd,
1033                                                    AFGR64Opnd, II_FLOOR>;
1034class CEIL_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.s", FGR64Opnd,
1035                                                   FGR32Opnd, II_CEIL>;
1036class CEIL_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.d", FGR64Opnd,
1037                                                   FGR64Opnd, II_CEIL>;
1038class CEIL_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.s", FGR32Opnd,
1039                                                   FGR32Opnd, II_CEIL>;
1040class CEIL_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.d", FGR32Opnd,
1041                                                   AFGR64Opnd, II_CEIL>;
1042class TRUNC_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.s", FGR64Opnd,
1043                                                    FGR32Opnd, II_TRUNC>;
1044class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd,
1045                                                    FGR64Opnd, II_TRUNC>;
1046class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
1047                                                    FGR32Opnd, II_TRUNC>;
1048class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
1049                                                    FGR64Opnd, II_TRUNC>;
1050class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
1051                                                 II_SQRT_S, fsqrt>;
1052class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd,
1053                                                AFGR64Opnd, II_SQRT_D, fsqrt>;
1054class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd,
1055                                                   FGR32Opnd, II_ROUND>;
1056class ROUND_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd,
1057                                                   FGR64Opnd, II_ROUND>;
1058class ROUND_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.s", FGR32Opnd,
1059                                                   FGR32Opnd, II_ROUND>;
1060class ROUND_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.d", FGR64Opnd,
1061                                                   FGR64Opnd, II_ROUND>;
1062
1063class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd, II_SEL_S>;
1064class SEL_D_MMR6_DESC : COP1_SEL_D_DESC_BASE<"sel.d", FGR64Opnd, II_SEL_D>;
1065
1066class SELEQZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd,
1067                                              II_SELCCZ_S>;
1068class SELEQZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd,
1069                                              II_SELCCZ_D>;
1070class SELNEZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd,
1071                                              II_SELCCZ_S>;
1072class SELNEZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd,
1073                                              II_SELCCZ_D>;
1074class RINT_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd,
1075                                              II_RINT_S>;
1076class RINT_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd,
1077                                              II_RINT_S>;
1078class CLASS_S_MMR6_DESC  : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd,
1079                                              II_CLASS_S>;
1080class CLASS_D_MMR6_DESC  : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd,
1081                                              II_CLASS_S>;
1082
1083class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO,
1084                           InstrItinClass Itin>
1085    : Store<opstr, RO>, MMR6Arch<opstr> {
1086  let DecoderMethod = "DecodeMemMMImm16";
1087  InstrItinClass Itinerary = Itin;
1088}
1089class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd, II_SB>;
1090
1091class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd, II_SH>;
1092class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
1093      MMR6Arch<"addu16"> {
1094  int AddedComplexity = 1;
1095}
1096class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND>,
1097      MMR6Arch<"and16">;
1098class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
1099      MMR6Arch<"andi16">;
1100class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16"> {
1101  int AddedComplexity = 1;
1102}
1103class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR>, MMR6Arch<"or16">;
1104class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
1105      MMR6Arch<"sll16">;
1106class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
1107      MMR6Arch<"srl16">;
1108class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16", II_BREAK>,
1109                          MMR6Arch<"break16">;
1110class LI16_MMR6_DESC : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>,
1111      MMR6Arch<"li16">, IsAsCheapAsAMove;
1112class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">;
1113class MOVEP_MMR6_DESC : MovePMM16<"movep", GPRMM16OpndMovePPairFirst,
1114                                  GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP>,
1115                        MMR6Arch<"movep">;
1116class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16", II_SDBBP>,
1117                          MMR6Arch<"sdbbp16">;
1118class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
1119      MMR6Arch<"subu16"> {
1120  int AddedComplexity = 1;
1121}
1122class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR>,
1123      MMR6Arch<"xor16">;
1124
1125class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
1126  dag OutOperandList = (outs GPR32Opnd:$rt);
1127  dag InOperandList = (ins mem:$addr);
1128  string AsmString = "lw\t$rt, $addr";
1129  let DecoderMethod = "DecodeMemMMImm16";
1130  let canFoldAsLoad = 1;
1131  let mayLoad = 1;
1132  list<dag> Pattern = [(set GPR32Opnd:$rt, (load addrDefault:$addr))];
1133  InstrItinClass Itinerary = II_LW;
1134}
1135
1136class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{
1137  dag OutOperandList = (outs GPR32Opnd:$rt);
1138  dag InOperandList = (ins uimm16:$imm16);
1139  string AsmString = "lui\t$rt, $imm16";
1140  list<dag> Pattern = [];
1141  bit hasSideEffects = 0;
1142  bit isReMaterializable = 1;
1143  InstrItinClass Itinerary = II_LUI;
1144  Format Form = FrmI;
1145}
1146
1147class SYNC_MMR6_DESC : MMR6Arch<"sync">, MipsR6Inst {
1148  dag OutOperandList = (outs);
1149  dag InOperandList = (ins uimm5:$stype);
1150  string AsmString = !strconcat("sync", "\t$stype");
1151  list<dag> Pattern = [(MipsSync immZExt5:$stype)];
1152  InstrItinClass Itinerary = II_SYNC;
1153  bit HasSideEffects = 1;
1154}
1155
1156class SYNCI_MMR6_DESC : SYNCI_FT<"synci", mem_mm_16> {
1157  let DecoderMethod = "DecodeSynciR6";
1158}
1159
1160class RDPGPR_MMR6_DESC : MMR6Arch<"rdpgpr">, MipsR6Inst {
1161  dag OutOperandList = (outs GPR32Opnd:$rt);
1162  dag InOperandList = (ins GPR32Opnd:$rd);
1163  string AsmString = !strconcat("rdpgpr", "\t$rt, $rd");
1164  InstrItinClass Itinerary = II_RDPGPR;
1165}
1166
1167class SDBBP_MMR6_DESC : MipsR6Inst {
1168  dag OutOperandList = (outs);
1169  dag InOperandList = (ins uimm20:$code_);
1170  string AsmString = !strconcat("sdbbp", "\t$code_");
1171  list<dag> Pattern = [];
1172  InstrItinClass Itinerary = II_SDBBP;
1173}
1174
1175class SIGRIE_MMR6_DESC : MipsR6Inst {
1176  dag OutOperandList = (outs);
1177  dag InOperandList = (ins uimm16:$code_);
1178  string AsmString = !strconcat("sigrie", "\t$code_");
1179  list<dag> Pattern = [];
1180  InstrItinClass Itinerary = II_SIGRIE;
1181}
1182
1183class LWM16_MMR6_DESC
1184    : MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
1185                      !strconcat("lwm16", "\t$rt, $addr"), [],
1186                      II_LWM, FrmI>,
1187      MMR6Arch<"lwm16"> {
1188  let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
1189  let mayLoad = 1;
1190  ComplexPattern Addr = addr;
1191}
1192
1193class SWM16_MMR6_DESC
1194    : MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
1195                      !strconcat("swm16", "\t$rt, $addr"), [],
1196                      II_SWM, FrmI>,
1197      MMR6Arch<"swm16"> {
1198  let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
1199  let mayStore = 1;
1200  ComplexPattern Addr = addr;
1201}
1202
1203class SB16_MMR6_DESC_BASE<string opstr, DAGOperand RTOpnd,
1204                          InstrItinClass Itin, Operand MemOpnd>
1205    : MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
1206                      !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI>,
1207      MMR6Arch<opstr> {
1208  let DecoderMethod = "DecodeMemMMImm4";
1209  let mayStore = 1;
1210}
1211
1212class SB16_MMR6_DESC
1213    : SB16_MMR6_DESC_BASE<"sb16", GPRMM16OpndZero, II_SB, mem_mm_4>;
1214class SH16_MMR6_DESC
1215    : SB16_MMR6_DESC_BASE<"sh16", GPRMM16OpndZero, II_SH, mem_mm_4_lsl1>;
1216class SW16_MMR6_DESC
1217    : SB16_MMR6_DESC_BASE<"sw16", GPRMM16OpndZero, II_SW, mem_mm_4_lsl2>;
1218
1219class SWSP_MMR6_DESC
1220    : MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset),
1221                      !strconcat("sw", "\t$rt, $offset"), [], II_SW, FrmI>,
1222      MMR6Arch<"swsp"> {
1223  let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
1224  let mayStore = 1;
1225}
1226
1227class JALRC_HB_MMR6_DESC {
1228  dag OutOperandList = (outs GPR32Opnd:$rt);
1229  dag InOperandList = (ins GPR32Opnd:$rs);
1230  string AsmString = !strconcat("jalrc.hb", "\t$rt, $rs");
1231  list<dag> Pattern = [];
1232  InstrItinClass Itinerary = II_JALR_HB;
1233  Format Form = FrmJ;
1234  bit isIndirectBranch = 1;
1235  bit hasDelaySlot = 0;
1236}
1237
1238class TLBINV_MMR6_DESC_BASE<string opstr, InstrItinClass Itin> {
1239  dag OutOperandList = (outs);
1240  dag InOperandList = (ins);
1241  string AsmString = opstr;
1242  list<dag> Pattern = [];
1243  InstrItinClass Itinerary = Itin;
1244}
1245
1246class TLBINV_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinv", II_TLBINV>;
1247class TLBINVF_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinvf", II_TLBINVF>;
1248
1249class DVPEVP_MMR6_DESC_BASE<string opstr, InstrItinClass Itin> {
1250  dag OutOperandList = (outs GPR32Opnd:$rs);
1251  dag InOperandList = (ins);
1252  string AsmString = !strconcat(opstr, "\t$rs");
1253  list<dag> Pattern = [];
1254  InstrItinClass Itinerary = Itin;
1255  bit hasUnModeledSideEffects = 1;
1256}
1257
1258class DVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"dvp", II_DVP>;
1259class EVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"evp", II_EVP>;
1260
1261class BEQZC_MMR6_DESC
1262    : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21_mm, GPR32Opnd>,
1263      MMR6Arch<"beqzc">;
1264class BNEZC_MMR6_DESC
1265    : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21_mm, GPR32Opnd>,
1266      MMR6Arch<"bnezc">;
1267
1268class BRANCH_COP1_MMR6_DESC_BASE<string opstr> :
1269    InstSE<(outs), (ins FGR64Opnd:$rt, brtarget_mm:$offset),
1270           !strconcat(opstr, "\t$rt, $offset"), [], II_BC1CCZ, FrmI>,
1271    HARDFLOAT, BRANCH_DESC_BASE {
1272  list<Register> Defs = [AT];
1273}
1274
1275class BC1EQZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1eqzc">;
1276class BC1NEZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1nezc">;
1277
1278class BRANCH_COP2_MMR6_DESC_BASE<string opstr, InstrItinClass Itin>
1279    : BRANCH_DESC_BASE {
1280  dag InOperandList = (ins COP2Opnd:$rt, brtarget_mm:$offset);
1281  dag OutOperandList = (outs);
1282  string AsmString = !strconcat(opstr, "\t$rt, $offset");
1283  list<Register> Defs = [AT];
1284  InstrItinClass Itinerary = Itin;
1285}
1286
1287class BC2EQZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2eqzc", II_BC2CCZ>;
1288class BC2NEZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2nezc", II_BC2CCZ>;
1289
1290class EXT_MMR6_DESC {
1291  dag OutOperandList = (outs GPR32Opnd:$rt);
1292  dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$pos, uimm5_plus1:$size);
1293  string AsmString = !strconcat("ext", "\t$rt, $rs, $pos, $size");
1294  list<dag> Pattern = [(set GPR32Opnd:$rt, (MipsExt GPR32Opnd:$rs, imm:$pos,
1295                       imm:$size))];
1296  InstrItinClass Itinerary = II_EXT;
1297  Format Form = FrmR;
1298  string BaseOpcode = "ext";
1299}
1300
1301class INS_MMR6_DESC {
1302  dag OutOperandList = (outs GPR32Opnd:$rt);
1303  dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$pos, uimm5_inssize_plus1:$size,
1304                       GPR32Opnd:$src);
1305  string AsmString = !strconcat("ins", "\t$rt, $rs, $pos, $size");
1306  list<dag> Pattern = [(set GPR32Opnd:$rt, (MipsIns GPR32Opnd:$rs, imm:$pos,
1307                       imm:$size, GPR32Opnd:$src))];
1308  InstrItinClass Itinerary = II_INS;
1309  Format Form = FrmR;
1310  string BaseOpcode = "ins";
1311  string Constraints = "$src = $rt";
1312}
1313
1314class JALRC_MMR6_DESC {
1315  dag OutOperandList = (outs GPR32Opnd:$rt);
1316  dag InOperandList = (ins GPR32Opnd:$rs);
1317  string AsmString = !strconcat("jalrc", "\t$rt, $rs");
1318  list<dag> Pattern = [];
1319  InstrItinClass Itinerary = II_JALRC;
1320  bit isCall = 1;
1321  bit hasDelaySlot = 0;
1322  list<Register> Defs = [RA];
1323}
1324
1325class BOVC_BNVC_MMR6_DESC_BASE<string instr_asm, Operand opnd,
1326                               RegisterOperand GPROpnd>
1327    : BRANCH_DESC_BASE {
1328  dag InOperandList = (ins GPROpnd:$rt, GPROpnd:$rs, opnd:$offset);
1329  dag OutOperandList = (outs);
1330  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $offset");
1331  list<Register> Defs = [AT];
1332  InstrItinClass Itinerary = II_BCCC;
1333}
1334
1335class BOVC_MMR6_DESC : BOVC_BNVC_MMR6_DESC_BASE<"bovc", brtargetr6, GPR32Opnd>;
1336class BNVC_MMR6_DESC : BOVC_BNVC_MMR6_DESC_BASE<"bnvc", brtargetr6, GPR32Opnd>;
1337
1338//===----------------------------------------------------------------------===//
1339//
1340// Instruction Definitions
1341//
1342//===----------------------------------------------------------------------===//
1343
1344let DecoderNamespace = "MicroMipsR6" in {
1345def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
1346def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
1347def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
1348def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
1349                   ISA_MICROMIPS32R6;
1350def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
1351                  ISA_MICROMIPS32R6;
1352def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;
1353def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6;
1354def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6;
1355def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6;
1356def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
1357def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
1358def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
1359def BC16_MMR6 : StdMMR6Rel, BC16_MMR6_DESC, BC16_MMR6_ENC, ISA_MICROMIPS32R6;
1360def BEQZC_MMR6 : R6MMR6Rel, BEQZC_MMR6_ENC, BEQZC_MMR6_DESC,
1361                 ISA_MICROMIPS32R6;
1362def BEQZC16_MMR6 : StdMMR6Rel, BEQZC16_MMR6_DESC, BEQZC16_MMR6_ENC,
1363                   ISA_MICROMIPS32R6;
1364def BNEZC_MMR6 : R6MMR6Rel, BNEZC_MMR6_ENC, BNEZC_MMR6_DESC,
1365                 ISA_MICROMIPS32R6;
1366def BNEZC16_MMR6 : StdMMR6Rel, BNEZC16_MMR6_DESC, BNEZC16_MMR6_ENC,
1367                   ISA_MICROMIPS32R6;
1368def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
1369                   ISA_MICROMIPS32R6;
1370def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
1371                   ISA_MICROMIPS32R6;
1372def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
1373                   ISA_MICROMIPS32R6;
1374def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
1375def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
1376def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
1377def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
1378def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
1379def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
1380def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
1381def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
1382def DI_MMR6 : StdMMR6Rel, DI_MMR6_DESC, DI_MMR6_ENC, ISA_MICROMIPS32R6;
1383def ERET_MMR6 : StdMMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
1384def DERET_MMR6 : StdMMR6Rel, DERET_MMR6_DESC, DERET_MMR6_ENC, ISA_MICROMIPS32R6;
1385def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
1386                  ISA_MICROMIPS32R6;
1387def GINVI_MMR6 : R6MMR6Rel, GINVI_MMR6_ENC, GINVI_MMR6_DESC,
1388                 ISA_MICROMIPS32R6, ASE_GINV;
1389def GINVT_MMR6 : R6MMR6Rel, GINVT_MMR6_ENC, GINVT_MMR6_DESC,
1390                 ISA_MICROMIPS32R6, ASE_GINV;
1391let FastISelShouldIgnore = 1 in
1392def JALRC16_MMR6 : R6MMR6Rel, JALRC16_MMR6_DESC, JALRC16_MMR6_ENC,
1393                   ISA_MICROMIPS32R6;
1394def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
1395def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
1396def JRC16_MMR6 : R6MMR6Rel, JRC16_MMR6_DESC, JRC16_MMR6_ENC, ISA_MICROMIPS32R6;
1397def JRCADDIUSP_MMR6 : R6MMR6Rel, JRCADDIUSP_MMR6_DESC, JRCADDIUSP_MMR6_ENC,
1398                      ISA_MICROMIPS32R6;
1399def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
1400def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
1401def LWM16_MMR6 : StdMMR6Rel, LWM16_MMR6_DESC, LWM16_MMR6_ENC, ISA_MICROMIPS32R6;
1402def MTC0_MMR6 : StdMMR6Rel, MTC0_MMR6_ENC, MTC0_MMR6_DESC, ISA_MICROMIPS32R6;
1403def MTC1_MMR6 : StdMMR6Rel, MTC1_MMR6_DESC, MTC1_MMR6_ENC, ISA_MICROMIPS32R6;
1404def MTC2_MMR6 : StdMMR6Rel, MTC2_MMR6_ENC, MTC2_MMR6_DESC, ISA_MICROMIPS32R6;
1405def MTHC0_MMR6 : R6MMR6Rel, MTHC0_MMR6_ENC, MTHC0_MMR6_DESC, ISA_MICROMIPS32R6;
1406def MTHC2_MMR6 : StdMMR6Rel, MTHC2_MMR6_ENC, MTHC2_MMR6_DESC, ISA_MICROMIPS32R6;
1407def MFC0_MMR6 : StdMMR6Rel, MFC0_MMR6_ENC, MFC0_MMR6_DESC, ISA_MICROMIPS32R6;
1408def MFC1_MMR6 : StdMMR6Rel, MFC1_MMR6_DESC, MFC1_MMR6_ENC, ISA_MICROMIPS32R6;
1409def MFC2_MMR6 : StdMMR6Rel, MFC2_MMR6_ENC, MFC2_MMR6_DESC, ISA_MICROMIPS32R6;
1410def MFHC0_MMR6 : R6MMR6Rel, MFHC0_MMR6_ENC, MFHC0_MMR6_DESC, ISA_MICROMIPS32R6;
1411def MFHC2_MMR6 : StdMMR6Rel, MFHC2_MMR6_ENC, MFHC2_MMR6_DESC, ISA_MICROMIPS32R6;
1412def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
1413def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
1414def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
1415def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
1416def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
1417def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
1418def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
1419def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
1420def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
1421def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
1422def SB16_MMR6 : StdMMR6Rel, SB16_MMR6_DESC, SB16_MMR6_ENC, ISA_MICROMIPS32R6;
1423def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
1424                  ISA_MICROMIPS32R6;
1425def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
1426                  ISA_MICROMIPS32R6;
1427def SH16_MMR6 : StdMMR6Rel, SH16_MMR6_DESC, SH16_MMR6_ENC, ISA_MICROMIPS32R6;
1428def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
1429def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
1430def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
1431def SW16_MMR6 : StdMMR6Rel, SW16_MMR6_DESC, SW16_MMR6_ENC, ISA_MICROMIPS32R6;
1432def SWM16_MMR6 : StdMMR6Rel, SWM16_MMR6_DESC, SWM16_MMR6_ENC, ISA_MICROMIPS32R6;
1433def SWSP_MMR6 : StdMMR6Rel, SWSP_MMR6_DESC, SWSP_MMR6_ENC, ISA_MICROMIPS32R6;
1434def WRPGPR_MMR6 : StdMMR6Rel, WRPGPR_MMR6_ENC, WRPGPR_MMR6_DESC,
1435                  ISA_MICROMIPS32R6;
1436def WSBH_MMR6 : StdMMR6Rel, WSBH_MMR6_ENC, WSBH_MMR6_DESC, ISA_MICROMIPS32R6;
1437def LB_MMR6 : R6MMR6Rel, LB_MMR6_ENC, LB_MMR6_DESC, ISA_MICROMIPS32R6;
1438def LBU_MMR6 : R6MMR6Rel, LBU_MMR6_ENC, LBU_MMR6_DESC, ISA_MICROMIPS32R6;
1439def PAUSE_MMR6 : StdMMR6Rel, PAUSE_MMR6_DESC, PAUSE_MMR6_ENC, ISA_MICROMIPS32R6;
1440def RDHWR_MMR6 : R6MMR6Rel, RDHWR_MMR6_DESC, RDHWR_MMR6_ENC, ISA_MICROMIPS32R6;
1441def WAIT_MMR6 : StdMMR6Rel, WAIT_MMR6_DESC, WAIT_MMR6_ENC, ISA_MICROMIPS32R6;
1442def SSNOP_MMR6 : StdMMR6Rel, SSNOP_MMR6_DESC, SSNOP_MMR6_ENC, ISA_MICROMIPS32R6;
1443def SYNC_MMR6 : StdMMR6Rel, SYNC_MMR6_DESC, SYNC_MMR6_ENC, ISA_MICROMIPS32R6;
1444def SYNCI_MMR6 : StdMMR6Rel, SYNCI_MMR6_DESC, SYNCI_MMR6_ENC, ISA_MICROMIPS32R6;
1445def RDPGPR_MMR6 : R6MMR6Rel, RDPGPR_MMR6_DESC, RDPGPR_MMR6_ENC,
1446                  ISA_MICROMIPS32R6;
1447def SDBBP_MMR6 : R6MMR6Rel, SDBBP_MMR6_DESC, SDBBP_MMR6_ENC, ISA_MICROMIPS32R6;
1448def SIGRIE_MMR6 : R6MMR6Rel, SIGRIE_MMR6_DESC, SIGRIE_MMR6_ENC,
1449                  ISA_MICROMIPS32R6;
1450def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
1451def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
1452let DecoderMethod = "DecodeMemMMImm16" in {
1453  def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
1454}
1455/// Floating Point Instructions
1456def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
1457                  ISA_MICROMIPS32R6;
1458def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC,
1459                  ISA_MICROMIPS32R6;
1460def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC,
1461                  ISA_MICROMIPS32R6;
1462def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC,
1463                  ISA_MICROMIPS32R6;
1464def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC,
1465                   ISA_MICROMIPS32R6;
1466def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
1467                   ISA_MICROMIPS32R6;
1468def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
1469                   ISA_MICROMIPS32R6;
1470def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
1471                   ISA_MICROMIPS32R6;
1472def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
1473                  ISA_MICROMIPS32R6;
1474def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC,
1475                  ISA_MICROMIPS32R6;
1476def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
1477                  ISA_MICROMIPS32R6;
1478def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
1479def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6;
1480def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6;
1481def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6;
1482def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC,
1483                  ISA_MICROMIPS32R6;
1484def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC,
1485                  ISA_MICROMIPS32R6;
1486def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC,
1487                  ISA_MICROMIPS32R6;
1488def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC,
1489                  ISA_MICROMIPS32R6;
1490def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC,
1491                   ISA_MICROMIPS32R6;
1492def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC,
1493                   ISA_MICROMIPS32R6;
1494def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC,
1495                   ISA_MICROMIPS32R6;
1496def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC,
1497                   ISA_MICROMIPS32R6;
1498def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
1499                   ISA_MICROMIPS32R6;
1500def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
1501                   ISA_MICROMIPS32R6;
1502defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd, II_CMP_CC_S>;
1503defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd, II_CMP_CC_D>;
1504def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
1505                     ISA_MICROMIPS32R6;
1506def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC,
1507                     ISA_MICROMIPS32R6;
1508def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC,
1509                     ISA_MICROMIPS32R6;
1510def FLOOR_W_D_MMR6 : StdMMR6Rel, FLOOR_W_D_MMR6_ENC, FLOOR_W_D_MMR6_DESC,
1511                     ISA_MICROMIPS32R6;
1512def CEIL_L_S_MMR6 : StdMMR6Rel, CEIL_L_S_MMR6_ENC, CEIL_L_S_MMR6_DESC,
1513                    ISA_MICROMIPS32R6;
1514def CEIL_L_D_MMR6 : StdMMR6Rel, CEIL_L_D_MMR6_ENC, CEIL_L_D_MMR6_DESC,
1515                    ISA_MICROMIPS32R6;
1516def CEIL_W_S_MMR6 : StdMMR6Rel, CEIL_W_S_MMR6_ENC, CEIL_W_S_MMR6_DESC,
1517                    ISA_MICROMIPS32R6;
1518def CEIL_W_D_MMR6 : StdMMR6Rel, CEIL_W_D_MMR6_ENC, CEIL_W_D_MMR6_DESC,
1519                    ISA_MICROMIPS32R6;
1520def TRUNC_L_S_MMR6 : StdMMR6Rel, TRUNC_L_S_MMR6_ENC, TRUNC_L_S_MMR6_DESC,
1521                     ISA_MICROMIPS32R6;
1522def TRUNC_L_D_MMR6 : StdMMR6Rel, TRUNC_L_D_MMR6_ENC, TRUNC_L_D_MMR6_DESC,
1523                     ISA_MICROMIPS32R6;
1524def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC,
1525                     ISA_MICROMIPS32R6;
1526def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC,
1527                     ISA_MICROMIPS32R6;
1528def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
1529def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
1530def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6;
1531def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6;
1532def ADDU16_MMR6 : StdMMR6Rel, ADDU16_MMR6_DESC, ADDU16_MMR6_ENC,
1533                  ISA_MICROMIPS32R6;
1534def AND16_MMR6 : StdMMR6Rel, AND16_MMR6_DESC, AND16_MMR6_ENC,
1535                  ISA_MICROMIPS32R6;
1536def ANDI16_MMR6 : StdMMR6Rel, ANDI16_MMR6_DESC, ANDI16_MMR6_ENC,
1537                  ISA_MICROMIPS32R6;
1538def NOT16_MMR6 : StdMMR6Rel, NOT16_MMR6_DESC, NOT16_MMR6_ENC,
1539                  ISA_MICROMIPS32R6;
1540def OR16_MMR6 : StdMMR6Rel, OR16_MMR6_DESC, OR16_MMR6_ENC,
1541                  ISA_MICROMIPS32R6;
1542def SLL16_MMR6 : StdMMR6Rel, SLL16_MMR6_DESC, SLL16_MMR6_ENC,
1543                  ISA_MICROMIPS32R6;
1544def SRL16_MMR6 : StdMMR6Rel, SRL16_MMR6_DESC, SRL16_MMR6_ENC,
1545                  ISA_MICROMIPS32R6;
1546def BREAK16_MMR6 : StdMMR6Rel, BREAK16_MMR6_DESC, BREAK16_MMR6_ENC,
1547                   ISA_MICROMIPS32R6;
1548def LI16_MMR6 : StdMMR6Rel, LI16_MMR6_DESC, LI16_MMR6_ENC,
1549                ISA_MICROMIPS32R6;
1550def MOVE16_MMR6 : StdMMR6Rel, MOVE16_MMR6_DESC, MOVE16_MMR6_ENC,
1551                  ISA_MICROMIPS32R6;
1552def MOVEP_MMR6  : StdMMR6Rel, MOVEP_MMR6_DESC, MOVEP_MMR6_ENC,
1553                  ISA_MICROMIPS32R6;
1554def SDBBP16_MMR6 : StdMMR6Rel, SDBBP16_MMR6_DESC, SDBBP16_MMR6_ENC,
1555                   ISA_MICROMIPS32R6;
1556def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC,
1557                  ISA_MICROMIPS32R6;
1558def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC,
1559                 ISA_MICROMIPS32R6;
1560def JALRC_HB_MMR6 : R6MMR6Rel, JALRC_HB_MMR6_ENC, JALRC_HB_MMR6_DESC,
1561                    ISA_MICROMIPS32R6;
1562def EXT_MMR6 : StdMMR6Rel, EXT_MMR6_ENC, EXT_MMR6_DESC, ISA_MICROMIPS32R6;
1563def INS_MMR6 : StdMMR6Rel, INS_MMR6_ENC, INS_MMR6_DESC, ISA_MICROMIPS32R6;
1564def JALRC_MMR6 : R6MMR6Rel, JALRC_MMR6_ENC, JALRC_MMR6_DESC, ISA_MICROMIPS32R6;
1565def RINT_S_MMR6 : StdMMR6Rel, RINT_S_MMR6_ENC, RINT_S_MMR6_DESC,
1566                  ISA_MICROMIPS32R6;
1567def RINT_D_MMR6 : StdMMR6Rel, RINT_D_MMR6_ENC, RINT_D_MMR6_DESC,
1568                  ISA_MICROMIPS32R6;
1569def ROUND_L_S_MMR6 : StdMMR6Rel, ROUND_L_S_MMR6_ENC, ROUND_L_S_MMR6_DESC,
1570                     ISA_MICROMIPS32R6;
1571def ROUND_L_D_MMR6 : StdMMR6Rel, ROUND_L_D_MMR6_ENC, ROUND_L_D_MMR6_DESC,
1572                     ISA_MICROMIPS32R6;
1573def ROUND_W_S_MMR6 : StdMMR6Rel, ROUND_W_S_MMR6_ENC, ROUND_W_S_MMR6_DESC,
1574                     ISA_MICROMIPS32R6;
1575def ROUND_W_D_MMR6 : StdMMR6Rel, ROUND_W_D_MMR6_ENC, ROUND_W_D_MMR6_DESC,
1576                     ISA_MICROMIPS32R6;
1577def SEL_S_MMR6 : R6MMR6Rel, SEL_S_MMR6_ENC, SEL_S_MMR6_DESC, ISA_MICROMIPS32R6;
1578def SEL_D_MMR6 : R6MMR6Rel, SEL_D_MMR6_ENC, SEL_D_MMR6_DESC, ISA_MICROMIPS32R6;
1579def SELEQZ_S_MMR6 : R6MMR6Rel, SELEQZ_S_MMR6_ENC, SELEQZ_S_MMR6_DESC,
1580                    ISA_MICROMIPS32R6;
1581def SELEQZ_D_MMR6 : R6MMR6Rel, SELEQZ_D_MMR6_ENC, SELEQZ_D_MMR6_DESC,
1582                    ISA_MICROMIPS32R6;
1583def SELNEZ_S_MMR6 : R6MMR6Rel, SELNEZ_S_MMR6_ENC, SELNEZ_S_MMR6_DESC,
1584                    ISA_MICROMIPS32R6;
1585def SELNEZ_D_MMR6 : R6MMR6Rel, SELNEZ_D_MMR6_ENC, SELNEZ_D_MMR6_DESC,
1586                    ISA_MICROMIPS32R6;
1587def CLASS_S_MMR6 : StdMMR6Rel, CLASS_S_MMR6_ENC, CLASS_S_MMR6_DESC,
1588                   ISA_MICROMIPS32R6;
1589def CLASS_D_MMR6 : StdMMR6Rel, CLASS_D_MMR6_ENC, CLASS_D_MMR6_DESC,
1590                   ISA_MICROMIPS32R6;
1591def TLBINV_MMR6 : StdMMR6Rel, TLBINV_MMR6_ENC, TLBINV_MMR6_DESC,
1592                  ISA_MICROMIPS32R6;
1593def TLBINVF_MMR6 : StdMMR6Rel, TLBINVF_MMR6_ENC, TLBINVF_MMR6_DESC,
1594                   ISA_MICROMIPS32R6;
1595def DVP_MMR6 : R6MMR6Rel, DVP_MMR6_ENC, DVP_MMR6_DESC, ISA_MICROMIPS32R6;
1596def EVP_MMR6 : R6MMR6Rel, EVP_MMR6_ENC, EVP_MMR6_DESC, ISA_MICROMIPS32R6;
1597def BC1EQZC_MMR6 : R6MMR6Rel, BC1EQZC_MMR6_DESC, BC1EQZC_MMR6_ENC,
1598                   ISA_MICROMIPS32R6;
1599def BC1NEZC_MMR6 : R6MMR6Rel, BC1NEZC_MMR6_DESC, BC1NEZC_MMR6_ENC,
1600                   ISA_MICROMIPS32R6;
1601def BC2EQZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2EQZC_MMR6_ENC, BC2EQZC_MMR6_DESC,
1602                   ISA_MICROMIPS32R6;
1603def BC2NEZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2NEZC_MMR6_ENC, BC2NEZC_MMR6_DESC,
1604                   ISA_MICROMIPS32R6;
1605let DecoderNamespace = "MicroMipsFP64" in {
1606  def LDC1_D64_MMR6 : StdMMR6Rel, LDC1_D64_MMR6_DESC, LDC1_MMR6_ENC,
1607                      ISA_MICROMIPS32R6 {
1608    let BaseOpcode = "LDC164";
1609  }
1610  def SDC1_D64_MMR6 : StdMMR6Rel, SDC1_D64_MMR6_DESC, SDC1_MMR6_ENC,
1611                      ISA_MICROMIPS32R6;
1612}
1613def LDC2_MMR6 : StdMMR6Rel, LDC2_MMR6_ENC, LDC2_MMR6_DESC, ISA_MICROMIPS32R6;
1614def SDC2_MMR6 : StdMMR6Rel, SDC2_MMR6_ENC, SDC2_MMR6_DESC, ISA_MICROMIPS32R6;
1615def LWC2_MMR6 : StdMMR6Rel, LWC2_MMR6_ENC, LWC2_MMR6_DESC, ISA_MICROMIPS32R6;
1616def SWC2_MMR6 : StdMMR6Rel, SWC2_MMR6_ENC, SWC2_MMR6_DESC, ISA_MICROMIPS32R6;
1617def LL_MMR6   : R6MMR6Rel, LL_MMR6_ENC, LL_MMR6_DESC, ISA_MICROMIPS32R6;
1618def SC_MMR6   : R6MMR6Rel, SC_MMR6_ENC, SC_MMR6_DESC, ISA_MICROMIPS32R6;
1619}
1620
1621def BOVC_MMR6 : R6MMR6Rel, BOVC_MMR6_ENC, BOVC_MMR6_DESC, ISA_MICROMIPS32R6,
1622                MMDecodeDisambiguatedBy<"POP35GroupBranchMMR6">;
1623def BNVC_MMR6 : R6MMR6Rel, BNVC_MMR6_ENC, BNVC_MMR6_DESC, ISA_MICROMIPS32R6,
1624                MMDecodeDisambiguatedBy<"POP37GroupBranchMMR6">;
1625def BGEC_MMR6 : R6MMR6Rel, BGEC_MMR6_ENC, BGEC_MMR6_DESC, ISA_MICROMIPS32R6;
1626def BGEUC_MMR6 : R6MMR6Rel, BGEUC_MMR6_ENC, BGEUC_MMR6_DESC, ISA_MICROMIPS32R6;
1627def BLTC_MMR6 : R6MMR6Rel, BLTC_MMR6_ENC, BLTC_MMR6_DESC, ISA_MICROMIPS32R6;
1628def BLTUC_MMR6 : R6MMR6Rel, BLTUC_MMR6_ENC, BLTUC_MMR6_DESC, ISA_MICROMIPS32R6;
1629def BEQC_MMR6 : R6MMR6Rel, BEQC_MMR6_ENC, BEQC_MMR6_DESC, ISA_MICROMIPS32R6,
1630                DecodeDisambiguates<"POP35GroupBranchMMR6">;
1631def BNEC_MMR6 : R6MMR6Rel, BNEC_MMR6_ENC, BNEC_MMR6_DESC, ISA_MICROMIPS32R6,
1632                DecodeDisambiguates<"POP37GroupBranchMMR6">;
1633def BLTZC_MMR6 : R6MMR6Rel, BLTZC_MMR6_ENC, BLTZC_MMR6_DESC, ISA_MICROMIPS32R6;
1634def BLEZC_MMR6 : R6MMR6Rel, BLEZC_MMR6_ENC, BLEZC_MMR6_DESC, ISA_MICROMIPS32R6;
1635def BGEZC_MMR6 : R6MMR6Rel, BGEZC_MMR6_ENC, BGEZC_MMR6_DESC, ISA_MICROMIPS32R6;
1636def BGTZC_MMR6 : R6MMR6Rel, BGTZC_MMR6_ENC, BGTZC_MMR6_DESC, ISA_MICROMIPS32R6;
1637def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
1638                   ISA_MICROMIPS32R6;
1639def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
1640                   ISA_MICROMIPS32R6;
1641def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
1642                   ISA_MICROMIPS32R6;
1643def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
1644                   ISA_MICROMIPS32R6;
1645
1646//===----------------------------------------------------------------------===//
1647//
1648// MicroMips instruction aliases
1649//
1650//===----------------------------------------------------------------------===//
1651
1652def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
1653def : MipsInstAlias<"di", (DI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
1654def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
1655def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
1656                                      !strconcat("b", "\t$offset")> {
1657  string DecoderNamespace = "MicroMipsR6";
1658}
1659def : MipsInstAlias<"sync", (SYNC_MMR6 0), 1>, ISA_MICROMIPS32R6;
1660def : MipsInstAlias<"sdbbp", (SDBBP_MMR6 0), 1>, ISA_MICROMIPS32R6;
1661def : MipsInstAlias<"sigrie", (SIGRIE_MMR6 0), 1>, ISA_MICROMIPS32R6;
1662def : MipsInstAlias<"rdhwr $rt, $rs",
1663                    (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>,
1664                    ISA_MICROMIPS32R6;
1665def : MipsInstAlias<"mtc0 $rt, $rs",
1666                    (MTC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
1667                    ISA_MICROMIPS32R6;
1668def : MipsInstAlias<"mthc0 $rt, $rs",
1669                    (MTHC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
1670                    ISA_MICROMIPS32R6;
1671def : MipsInstAlias<"mfc0 $rt, $rs",
1672                    (MFC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
1673                    ISA_MICROMIPS32R6;
1674def : MipsInstAlias<"mfhc0 $rt, $rs",
1675                    (MFHC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
1676                    ISA_MICROMIPS32R6;
1677def : MipsInstAlias<"jalrc.hb $rs", (JALRC_HB_MMR6 RA, GPR32Opnd:$rs), 1>,
1678                    ISA_MICROMIPS32R6;
1679def : MipsInstAlias<"jal $offset", (BALC_MMR6 brtarget26_mm:$offset), 0>,
1680                    ISA_MICROMIPS32R6;
1681def : MipsInstAlias<"dvp", (DVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
1682def : MipsInstAlias<"evp", (EVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
1683def : MipsInstAlias<"jalrc $rs", (JALRC_MMR6 RA, GPR32Opnd:$rs), 1>,
1684      ISA_MICROMIPS32R6;
1685def : MipsInstAlias<"and $rs, $rt, $imm",
1686                    (ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
1687                    ISA_MICROMIPS32R6;
1688def : MipsInstAlias<"and $rs, $imm",
1689                    (ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
1690                    ISA_MICROMIPS32R6;
1691def : MipsInstAlias<"or $rs, $rt, $imm",
1692                    (ORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
1693                    ISA_MICROMIPS32R6;
1694def : MipsInstAlias<"or $rs, $imm",
1695                    (ORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
1696                    ISA_MICROMIPS32R6;
1697def : MipsInstAlias<"xor $rs, $rt, $imm",
1698                    (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
1699                    ISA_MICROMIPS32R6;
1700def : MipsInstAlias<"xor $rs, $imm",
1701                    (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
1702                    ISA_MICROMIPS32R6;
1703def : MipsInstAlias<"not $rt, $rs",
1704                    (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>,
1705                    ISA_MICROMIPS32R6;
1706def : MipsInstAlias<"not $rt",
1707                    (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>,
1708                    ISA_MICROMIPS32R6;
1709def : MipsInstAlias<"lapc $rd, $imm",
1710                    (ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm)>,
1711                    ISA_MICROMIPS32R6;
1712def : MipsInstAlias<"neg $rt, $rs",
1713                    (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
1714      ISA_MICROMIPS32R6;
1715def : MipsInstAlias<"neg $rt",
1716                    (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
1717      ISA_MICROMIPS32R6;
1718def : MipsInstAlias<"negu $rt, $rs",
1719                    (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
1720      ISA_MICROMIPS32R6;
1721def : MipsInstAlias<"negu $rt",
1722                    (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
1723      ISA_MICROMIPS32R6;
1724def : MipsInstAlias<"beqz16 $rs, $offset", (BEQZC16_MMR6 GPRMM16Opnd:$rs,
1725                                                         brtarget7_mm:$offset),
1726                    0>, ISA_MICROMIPS32R6;
1727def : MipsInstAlias<"bnez16 $rs, $offset", (BNEZC16_MMR6 GPRMM16Opnd:$rs,
1728                                                         brtarget7_mm:$offset),
1729                    0>, ISA_MICROMIPS32R6;
1730def : MipsInstAlias<"b16 $offset", (BC16_MMR6 brtarget10_mm:$offset), 0>,
1731                    ISA_MICROMIPS32R6;
1732
1733//===----------------------------------------------------------------------===//
1734//
1735// MicroMips arbitrary patterns that map to one or more instructions
1736//
1737//===----------------------------------------------------------------------===//
1738
1739def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
1740              (SW16_MMR6 GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS32R6;
1741def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1742              (SUBU_MMR6 GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS32R6;
1743
1744def : MipsPat<(select i32:$cond, i32:$t, i32:$f),
1745              (OR_MM (SELNEZ_MMR6 i32:$t, i32:$cond),
1746                     (SELEQZ_MMR6 i32:$f, i32:$cond))>,
1747              ISA_MICROMIPS32R6;
1748def : MipsPat<(select i32:$cond, i32:$t, immz),
1749              (SELNEZ_MMR6 i32:$t, i32:$cond)>,
1750              ISA_MICROMIPS32R6;
1751def : MipsPat<(select i32:$cond, immz, i32:$f),
1752              (SELEQZ_MMR6 i32:$f, i32:$cond)>,
1753              ISA_MICROMIPS32R6;
1754
1755defm : SelectInt_Pats<i32, OR_MM, XORI_MMR6, SLTi_MM, SLTiu_MM, SELEQZ_MMR6,
1756                      SELNEZ_MMR6, immZExt16, i32>, ISA_MICROMIPS32R6;
1757
1758defm S_MMR6 : Cmp_Pats<f32, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6;
1759defm D_MMR6 : Cmp_Pats<f64, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6;
1760
1761def : MipsPat<(f32 fpimm0), (MTC1_MMR6 ZERO)>, ISA_MICROMIPS32R6;
1762def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6(MTC1_MMR6 ZERO))>,
1763      ISA_MICROMIPS32R6;
1764def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
1765              (TRUNC_W_D_MMR6 FGR64Opnd:$src)>, ISA_MICROMIPS32R6;
1766def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
1767              (TRUNC_W_S_MMR6 FGR32Opnd:$src)>, ISA_MICROMIPS32R6;
1768
1769def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
1770              (ANDI16_MMR6 GPRMM16:$src, immZExtAndi16:$imm)>,
1771              ISA_MICROMIPS32R6;
1772def : MipsPat<(and GPR32:$src, immZExt16:$imm),
1773              (ANDI_MMR6 GPR32:$src, immZExt16:$imm)>, ISA_MICROMIPS32R6;
1774def : MipsPat<(i32 immZExt16:$imm),
1775              (XORI_MMR6 ZERO, immZExt16:$imm)>, ISA_MICROMIPS32R6;
1776def : MipsPat<(not GPRMM16:$in),
1777              (NOT16_MMR6 GPRMM16:$in)>, ISA_MICROMIPS32R6;
1778def : MipsPat<(not GPR32:$in),
1779              (NOR_MMR6 GPR32Opnd:$in, ZERO)>, ISA_MICROMIPS32R6;
1780// Patterns for load with a reg+imm operand.
1781let AddedComplexity = 41 in {
1782  def : LoadRegImmPat<LDC1_D64_MMR6, f64, load>, FGR_64, ISA_MICROMIPS32R6;
1783  def : StoreRegImmPat<SDC1_D64_MMR6, f64>, FGR_64, ISA_MICROMIPS32R6;
1784}
1785
1786let isCall=1, hasDelaySlot=0, isCTI=1, Defs = [RA] in {
1787  class JumpLinkMMR6<Instruction JumpInst, DAGOperand Opnd> :
1788    PseudoSE<(outs), (ins calltarget:$target), [], II_JAL>,
1789    PseudoInstExpansion<(JumpInst Opnd:$target)>;
1790}
1791
1792def JAL_MMR6 : JumpLinkMMR6<BALC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6;
1793
1794def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1795              (JAL_MMR6 texternalsym:$dst)>, ISA_MICROMIPS32R6;
1796def : MipsPat<(MipsJmpLink (iPTR tglobaladdr:$dst)),
1797              (JAL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6;
1798
1799def TAILCALL_MMR6 : TailCall<BC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6;
1800
1801def TAILCALLREG_MMR6  : TailCallReg<JRC16_MM, GPR32Opnd>, ISA_MICROMIPS32R6;
1802
1803def PseudoIndirectBranch_MMR6 : PseudoIndirectBranchBase<JRC16_MMR6,
1804                                                         GPR32Opnd>,
1805                                ISA_MICROMIPS32R6;
1806
1807def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1808              (TAILCALL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6;
1809
1810def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1811              (TAILCALL_MMR6 texternalsym:$dst)>, ISA_MICROMIPS32R6;
1812
1813
1814def : MipsPat<(brcond (i32 (setne GPR32:$lhs, 0)), bb:$dst),
1815              (BNEZC_MMR6 GPR32:$lhs, bb:$dst)>, ISA_MICROMIPS32R6;
1816def : MipsPat<(brcond (i32 (seteq GPR32:$lhs, 0)), bb:$dst),
1817              (BEQZC_MMR6 GPR32:$lhs, bb:$dst)>, ISA_MICROMIPS32R6;
1818
1819def : MipsPat<(brcond (i32 (setge GPR32:$lhs, GPR32:$rhs)), bb:$dst),
1820              (BEQZC_MMR6 (SLT_MM GPR32:$lhs, GPR32:$rhs), bb:$dst)>,
1821      ISA_MICROMIPS32R6;
1822def : MipsPat<(brcond (i32 (setuge GPR32:$lhs, GPR32:$rhs)), bb:$dst),
1823              (BEQZC_MMR6 (SLTu_MM GPR32:$lhs, GPR32:$rhs), bb:$dst)>,
1824      ISA_MICROMIPS32R6;
1825def : MipsPat<(brcond (i32 (setge GPR32:$lhs, immSExt16:$rhs)), bb:$dst),
1826              (BEQZC_MMR6 (SLTi_MM GPR32:$lhs, immSExt16:$rhs), bb:$dst)>,
1827      ISA_MICROMIPS32R6;
1828def : MipsPat<(brcond (i32 (setuge GPR32:$lhs, immSExt16:$rhs)), bb:$dst),
1829              (BEQZC_MMR6 (SLTiu_MM GPR32:$lhs, immSExt16:$rhs), bb:$dst)>,
1830      ISA_MICROMIPS32R6;
1831def : MipsPat<(brcond (i32 (setgt GPR32:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1832              (BEQZC_MMR6 (SLTi_MM GPR32:$lhs, (Plus1 imm:$rhs)), bb:$dst)>,
1833      ISA_MICROMIPS32R6;
1834def : MipsPat<(brcond (i32 (setugt GPR32:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1835              (BEQZC_MMR6 (SLTiu_MM GPR32:$lhs, (Plus1 imm:$rhs)), bb:$dst)>,
1836      ISA_MICROMIPS32R6;
1837
1838def : MipsPat<(brcond (i32 (setle GPR32:$lhs, GPR32:$rhs)), bb:$dst),
1839              (BEQZC_MMR6  (SLT_MM GPR32:$rhs, GPR32:$lhs), bb:$dst)>,
1840      ISA_MICROMIPS32R6;
1841def : MipsPat<(brcond (i32 (setule GPR32:$lhs, GPR32:$rhs)), bb:$dst),
1842              (BEQZC_MMR6  (SLTu_MM GPR32:$rhs, GPR32:$lhs), bb:$dst)>,
1843      ISA_MICROMIPS32R6;
1844
1845def : MipsPat<(brcond GPR32:$cond, bb:$dst),
1846              (BNEZC_MMR6 GPR32:$cond, bb:$dst)>, ISA_MICROMIPS32R6;
1847