xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp (revision b4af4f93c682e445bf159f0d1ec90b636296c946) 
1 //===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Mips specific target streamer methods.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsTargetStreamer.h"
14 #include "MipsInstPrinter.h"
15 #include "MCTargetDesc/MipsABIInfo.h"
16 #include "MipsELFStreamer.h"
17 #include "MipsMCExpr.h"
18 #include "MipsMCTargetDesc.h"
19 #include "MipsTargetObjectFile.h"
20 #include "llvm/BinaryFormat/ELF.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCSectionELF.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCSymbolELF.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/FormattedStream.h"
28 
29 using namespace llvm;
30 
31 namespace {
32 static cl::opt<bool> RoundSectionSizes(
33     "mips-round-section-sizes", cl::init(false),
34     cl::desc("Round section sizes up to the section alignment"), cl::Hidden);
35 } // end anonymous namespace
36 
37 static bool isMicroMips(const MCSubtargetInfo *STI) {
38   return STI->getFeatureBits()[Mips::FeatureMicroMips];
39 }
40 
41 MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S)
42     : MCTargetStreamer(S), GPReg(Mips::GP), ModuleDirectiveAllowed(true) {
43   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
44 }
45 void MipsTargetStreamer::emitDirectiveSetMicroMips() {}
46 void MipsTargetStreamer::emitDirectiveSetNoMicroMips() {}
47 void MipsTargetStreamer::setUsesMicroMips() {}
48 void MipsTargetStreamer::emitDirectiveSetMips16() {}
49 void MipsTargetStreamer::emitDirectiveSetNoMips16() { forbidModuleDirective(); }
50 void MipsTargetStreamer::emitDirectiveSetReorder() { forbidModuleDirective(); }
51 void MipsTargetStreamer::emitDirectiveSetNoReorder() {}
52 void MipsTargetStreamer::emitDirectiveSetMacro() { forbidModuleDirective(); }
53 void MipsTargetStreamer::emitDirectiveSetNoMacro() { forbidModuleDirective(); }
54 void MipsTargetStreamer::emitDirectiveSetMsa() { forbidModuleDirective(); }
55 void MipsTargetStreamer::emitDirectiveSetNoMsa() { forbidModuleDirective(); }
56 void MipsTargetStreamer::emitDirectiveSetMt() {}
57 void MipsTargetStreamer::emitDirectiveSetNoMt() { forbidModuleDirective(); }
58 void MipsTargetStreamer::emitDirectiveSetCRC() {}
59 void MipsTargetStreamer::emitDirectiveSetNoCRC() {}
60 void MipsTargetStreamer::emitDirectiveSetVirt() {}
61 void MipsTargetStreamer::emitDirectiveSetNoVirt() {}
62 void MipsTargetStreamer::emitDirectiveSetGINV() {}
63 void MipsTargetStreamer::emitDirectiveSetNoGINV() {}
64 void MipsTargetStreamer::emitDirectiveSetAt() { forbidModuleDirective(); }
65 void MipsTargetStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
66   forbidModuleDirective();
67 }
68 void MipsTargetStreamer::emitDirectiveSetNoAt() { forbidModuleDirective(); }
69 void MipsTargetStreamer::emitDirectiveEnd(StringRef Name) {}
70 void MipsTargetStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {}
71 void MipsTargetStreamer::emitDirectiveAbiCalls() {}
72 void MipsTargetStreamer::emitDirectiveNaN2008() {}
73 void MipsTargetStreamer::emitDirectiveNaNLegacy() {}
74 void MipsTargetStreamer::emitDirectiveOptionPic0() {}
75 void MipsTargetStreamer::emitDirectiveOptionPic2() {}
76 void MipsTargetStreamer::emitDirectiveInsn() { forbidModuleDirective(); }
77 void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
78                                    unsigned ReturnReg) {}
79 void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
80 void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
81 }
82 void MipsTargetStreamer::emitDirectiveSetArch(StringRef Arch) {
83   forbidModuleDirective();
84 }
85 void MipsTargetStreamer::emitDirectiveSetMips0() { forbidModuleDirective(); }
86 void MipsTargetStreamer::emitDirectiveSetMips1() { forbidModuleDirective(); }
87 void MipsTargetStreamer::emitDirectiveSetMips2() { forbidModuleDirective(); }
88 void MipsTargetStreamer::emitDirectiveSetMips3() { forbidModuleDirective(); }
89 void MipsTargetStreamer::emitDirectiveSetMips4() { forbidModuleDirective(); }
90 void MipsTargetStreamer::emitDirectiveSetMips5() { forbidModuleDirective(); }
91 void MipsTargetStreamer::emitDirectiveSetMips32() { forbidModuleDirective(); }
92 void MipsTargetStreamer::emitDirectiveSetMips32R2() { forbidModuleDirective(); }
93 void MipsTargetStreamer::emitDirectiveSetMips32R3() { forbidModuleDirective(); }
94 void MipsTargetStreamer::emitDirectiveSetMips32R5() { forbidModuleDirective(); }
95 void MipsTargetStreamer::emitDirectiveSetMips32R6() { forbidModuleDirective(); }
96 void MipsTargetStreamer::emitDirectiveSetMips64() { forbidModuleDirective(); }
97 void MipsTargetStreamer::emitDirectiveSetMips64R2() { forbidModuleDirective(); }
98 void MipsTargetStreamer::emitDirectiveSetMips64R3() { forbidModuleDirective(); }
99 void MipsTargetStreamer::emitDirectiveSetMips64R5() { forbidModuleDirective(); }
100 void MipsTargetStreamer::emitDirectiveSetMips64R6() { forbidModuleDirective(); }
101 void MipsTargetStreamer::emitDirectiveSetPop() { forbidModuleDirective(); }
102 void MipsTargetStreamer::emitDirectiveSetPush() { forbidModuleDirective(); }
103 void MipsTargetStreamer::emitDirectiveSetSoftFloat() {
104   forbidModuleDirective();
105 }
106 void MipsTargetStreamer::emitDirectiveSetHardFloat() {
107   forbidModuleDirective();
108 }
109 void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); }
110 void MipsTargetStreamer::emitDirectiveSetDspr2() { forbidModuleDirective(); }
111 void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); }
112 void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {}
113 void MipsTargetStreamer::emitDirectiveCpLocal(unsigned RegNo) {
114   // .cplocal $reg
115   // This directive forces to use the alternate register for context pointer.
116   // For example
117   //   .cplocal $4
118   //   jal foo
119   // expands to
120   //   ld    $25, %call16(foo)($4)
121   //   jalr  $25
122 
123   if (!getABI().IsN32() && !getABI().IsN64())
124     return;
125 
126   GPReg = RegNo;
127 
128   forbidModuleDirective();
129 }
130 bool MipsTargetStreamer::emitDirectiveCpRestore(
131     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
132     const MCSubtargetInfo *STI) {
133   forbidModuleDirective();
134   return true;
135 }
136 void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
137                                               const MCSymbol &Sym, bool IsReg) {
138 }
139 void MipsTargetStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
140                                                bool SaveLocationIsRegister) {}
141 
142 void MipsTargetStreamer::emitDirectiveModuleFP() {}
143 
144 void MipsTargetStreamer::emitDirectiveModuleOddSPReg() {
145   if (!ABIFlagsSection.OddSPReg && !ABIFlagsSection.Is32BitABI)
146     report_fatal_error("+nooddspreg is only valid for O32");
147 }
148 void MipsTargetStreamer::emitDirectiveModuleSoftFloat() {}
149 void MipsTargetStreamer::emitDirectiveModuleHardFloat() {}
150 void MipsTargetStreamer::emitDirectiveModuleMT() {}
151 void MipsTargetStreamer::emitDirectiveModuleCRC() {}
152 void MipsTargetStreamer::emitDirectiveModuleNoCRC() {}
153 void MipsTargetStreamer::emitDirectiveModuleVirt() {}
154 void MipsTargetStreamer::emitDirectiveModuleNoVirt() {}
155 void MipsTargetStreamer::emitDirectiveModuleGINV() {}
156 void MipsTargetStreamer::emitDirectiveModuleNoGINV() {}
157 void MipsTargetStreamer::emitDirectiveSetFp(
158     MipsABIFlagsSection::FpABIKind Value) {
159   forbidModuleDirective();
160 }
161 void MipsTargetStreamer::emitDirectiveSetOddSPReg() { forbidModuleDirective(); }
162 void MipsTargetStreamer::emitDirectiveSetNoOddSPReg() {
163   forbidModuleDirective();
164 }
165 
166 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
167                                const MCSubtargetInfo *STI) {
168   MCInst TmpInst;
169   TmpInst.setOpcode(Opcode);
170   TmpInst.addOperand(MCOperand::createReg(Reg0));
171   TmpInst.setLoc(IDLoc);
172   getStreamer().EmitInstruction(TmpInst, *STI);
173 }
174 
175 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1,
176                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
177   MCInst TmpInst;
178   TmpInst.setOpcode(Opcode);
179   TmpInst.addOperand(MCOperand::createReg(Reg0));
180   TmpInst.addOperand(Op1);
181   TmpInst.setLoc(IDLoc);
182   getStreamer().EmitInstruction(TmpInst, *STI);
183 }
184 
185 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm,
186                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
187   emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI);
188 }
189 
190 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
191                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
192   emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI);
193 }
194 
195 void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2,
196                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
197   MCInst TmpInst;
198   TmpInst.setOpcode(Opcode);
199   TmpInst.addOperand(MCOperand::createImm(Imm1));
200   TmpInst.addOperand(MCOperand::createImm(Imm2));
201   TmpInst.setLoc(IDLoc);
202   getStreamer().EmitInstruction(TmpInst, *STI);
203 }
204 
205 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
206                                  MCOperand Op2, SMLoc IDLoc,
207                                  const MCSubtargetInfo *STI) {
208   MCInst TmpInst;
209   TmpInst.setOpcode(Opcode);
210   TmpInst.addOperand(MCOperand::createReg(Reg0));
211   TmpInst.addOperand(MCOperand::createReg(Reg1));
212   TmpInst.addOperand(Op2);
213   TmpInst.setLoc(IDLoc);
214   getStreamer().EmitInstruction(TmpInst, *STI);
215 }
216 
217 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
218                                  unsigned Reg2, SMLoc IDLoc,
219                                  const MCSubtargetInfo *STI) {
220   emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI);
221 }
222 
223 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
224                                   unsigned Reg2, MCOperand Op3, SMLoc IDLoc,
225                                   const MCSubtargetInfo *STI) {
226   MCInst TmpInst;
227   TmpInst.setOpcode(Opcode);
228   TmpInst.addOperand(MCOperand::createReg(Reg0));
229   TmpInst.addOperand(MCOperand::createReg(Reg1));
230   TmpInst.addOperand(MCOperand::createReg(Reg2));
231   TmpInst.addOperand(Op3);
232   TmpInst.setLoc(IDLoc);
233   getStreamer().EmitInstruction(TmpInst, *STI);
234 }
235 
236 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1,
237                                  int16_t Imm, SMLoc IDLoc,
238                                  const MCSubtargetInfo *STI) {
239   emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI);
240 }
241 
242 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0,
243                                    unsigned Reg1, int16_t Imm0, int16_t Imm1,
244                                    int16_t Imm2, SMLoc IDLoc,
245                                    const MCSubtargetInfo *STI) {
246   MCInst TmpInst;
247   TmpInst.setOpcode(Opcode);
248   TmpInst.addOperand(MCOperand::createReg(Reg0));
249   TmpInst.addOperand(MCOperand::createReg(Reg1));
250   TmpInst.addOperand(MCOperand::createImm(Imm0));
251   TmpInst.addOperand(MCOperand::createImm(Imm1));
252   TmpInst.addOperand(MCOperand::createImm(Imm2));
253   TmpInst.setLoc(IDLoc);
254   getStreamer().EmitInstruction(TmpInst, *STI);
255 }
256 
257 void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg,
258                                   unsigned TrgReg, bool Is64Bit,
259                                   const MCSubtargetInfo *STI) {
260   emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
261           STI);
262 }
263 
264 void MipsTargetStreamer::emitDSLL(unsigned DstReg, unsigned SrcReg,
265                                   int16_t ShiftAmount, SMLoc IDLoc,
266                                   const MCSubtargetInfo *STI) {
267   if (ShiftAmount >= 32) {
268     emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI);
269     return;
270   }
271 
272   emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI);
273 }
274 
275 void MipsTargetStreamer::emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc,
276                                             const MCSubtargetInfo *STI) {
277   if (hasShortDelaySlot)
278     emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
279   else
280     emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
281 }
282 
283 void MipsTargetStreamer::emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI) {
284   if (isMicroMips(STI))
285     emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
286   else
287     emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
288 }
289 
290 /// Emit the $gp restore operation for .cprestore.
291 void MipsTargetStreamer::emitGPRestore(int Offset, SMLoc IDLoc,
292                                        const MCSubtargetInfo *STI) {
293   emitLoadWithImmOffset(Mips::LW, GPReg, Mips::SP, Offset, GPReg, IDLoc, STI);
294 }
295 
296 /// Emit a store instruction with an immediate offset.
297 void MipsTargetStreamer::emitStoreWithImmOffset(
298     unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset,
299     function_ref<unsigned()> GetATReg, SMLoc IDLoc,
300     const MCSubtargetInfo *STI) {
301   if (isInt<16>(Offset)) {
302     emitRRI(Opcode, SrcReg, BaseReg, Offset, IDLoc, STI);
303     return;
304   }
305 
306   // sw $8, offset($8) => lui $at, %hi(offset)
307   //                      add $at, $at, $8
308   //                      sw $8, %lo(offset)($at)
309 
310   unsigned ATReg = GetATReg();
311   if (!ATReg)
312     return;
313 
314   unsigned LoOffset = Offset & 0x0000ffff;
315   unsigned HiOffset = (Offset & 0xffff0000) >> 16;
316 
317   // If msb of LoOffset is 1(negative number) we must increment HiOffset
318   // to account for the sign-extension of the low part.
319   if (LoOffset & 0x8000)
320     HiOffset++;
321 
322   // Generate the base address in ATReg.
323   emitRI(Mips::LUi, ATReg, HiOffset, IDLoc, STI);
324   if (BaseReg != Mips::ZERO)
325     emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
326   // Emit the store with the adjusted base and offset.
327   emitRRI(Opcode, SrcReg, ATReg, LoOffset, IDLoc, STI);
328 }
329 
330 /// Emit a load instruction with an immediate offset. DstReg and TmpReg are
331 /// permitted to be the same register iff DstReg is distinct from BaseReg and
332 /// DstReg is a GPR. It is the callers responsibility to identify such cases
333 /// and pass the appropriate register in TmpReg.
334 void MipsTargetStreamer::emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg,
335                                                unsigned BaseReg, int64_t Offset,
336                                                unsigned TmpReg, SMLoc IDLoc,
337                                                const MCSubtargetInfo *STI) {
338   if (isInt<16>(Offset)) {
339     emitRRI(Opcode, DstReg, BaseReg, Offset, IDLoc, STI);
340     return;
341   }
342 
343   // 1) lw $8, offset($9) => lui $8, %hi(offset)
344   //                         add $8, $8, $9
345   //                         lw $8, %lo(offset)($9)
346   // 2) lw $8, offset($8) => lui $at, %hi(offset)
347   //                         add $at, $at, $8
348   //                         lw $8, %lo(offset)($at)
349 
350   unsigned LoOffset = Offset & 0x0000ffff;
351   unsigned HiOffset = (Offset & 0xffff0000) >> 16;
352 
353   // If msb of LoOffset is 1(negative number) we must increment HiOffset
354   // to account for the sign-extension of the low part.
355   if (LoOffset & 0x8000)
356     HiOffset++;
357 
358   // Generate the base address in TmpReg.
359   emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI);
360   if (BaseReg != Mips::ZERO)
361     emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
362   // Emit the load with the adjusted base and offset.
363   emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI);
364 }
365 
366 MipsTargetAsmStreamer::MipsTargetAsmStreamer(MCStreamer &S,
367                                              formatted_raw_ostream &OS)
368     : MipsTargetStreamer(S), OS(OS) {}
369 
370 void MipsTargetAsmStreamer::emitDirectiveSetMicroMips() {
371   OS << "\t.set\tmicromips\n";
372   forbidModuleDirective();
373 }
374 
375 void MipsTargetAsmStreamer::emitDirectiveSetNoMicroMips() {
376   OS << "\t.set\tnomicromips\n";
377   forbidModuleDirective();
378 }
379 
380 void MipsTargetAsmStreamer::emitDirectiveSetMips16() {
381   OS << "\t.set\tmips16\n";
382   forbidModuleDirective();
383 }
384 
385 void MipsTargetAsmStreamer::emitDirectiveSetNoMips16() {
386   OS << "\t.set\tnomips16\n";
387   MipsTargetStreamer::emitDirectiveSetNoMips16();
388 }
389 
390 void MipsTargetAsmStreamer::emitDirectiveSetReorder() {
391   OS << "\t.set\treorder\n";
392   MipsTargetStreamer::emitDirectiveSetReorder();
393 }
394 
395 void MipsTargetAsmStreamer::emitDirectiveSetNoReorder() {
396   OS << "\t.set\tnoreorder\n";
397   forbidModuleDirective();
398 }
399 
400 void MipsTargetAsmStreamer::emitDirectiveSetMacro() {
401   OS << "\t.set\tmacro\n";
402   MipsTargetStreamer::emitDirectiveSetMacro();
403 }
404 
405 void MipsTargetAsmStreamer::emitDirectiveSetNoMacro() {
406   OS << "\t.set\tnomacro\n";
407   MipsTargetStreamer::emitDirectiveSetNoMacro();
408 }
409 
410 void MipsTargetAsmStreamer::emitDirectiveSetMsa() {
411   OS << "\t.set\tmsa\n";
412   MipsTargetStreamer::emitDirectiveSetMsa();
413 }
414 
415 void MipsTargetAsmStreamer::emitDirectiveSetNoMsa() {
416   OS << "\t.set\tnomsa\n";
417   MipsTargetStreamer::emitDirectiveSetNoMsa();
418 }
419 
420 void MipsTargetAsmStreamer::emitDirectiveSetMt() {
421   OS << "\t.set\tmt\n";
422   MipsTargetStreamer::emitDirectiveSetMt();
423 }
424 
425 void MipsTargetAsmStreamer::emitDirectiveSetNoMt() {
426   OS << "\t.set\tnomt\n";
427   MipsTargetStreamer::emitDirectiveSetNoMt();
428 }
429 
430 void MipsTargetAsmStreamer::emitDirectiveSetCRC() {
431   OS << "\t.set\tcrc\n";
432   MipsTargetStreamer::emitDirectiveSetCRC();
433 }
434 
435 void MipsTargetAsmStreamer::emitDirectiveSetNoCRC() {
436   OS << "\t.set\tnocrc\n";
437   MipsTargetStreamer::emitDirectiveSetNoCRC();
438 }
439 
440 void MipsTargetAsmStreamer::emitDirectiveSetVirt() {
441   OS << "\t.set\tvirt\n";
442   MipsTargetStreamer::emitDirectiveSetVirt();
443 }
444 
445 void MipsTargetAsmStreamer::emitDirectiveSetNoVirt() {
446   OS << "\t.set\tnovirt\n";
447   MipsTargetStreamer::emitDirectiveSetNoVirt();
448 }
449 
450 void MipsTargetAsmStreamer::emitDirectiveSetGINV() {
451   OS << "\t.set\tginv\n";
452   MipsTargetStreamer::emitDirectiveSetGINV();
453 }
454 
455 void MipsTargetAsmStreamer::emitDirectiveSetNoGINV() {
456   OS << "\t.set\tnoginv\n";
457   MipsTargetStreamer::emitDirectiveSetNoGINV();
458 }
459 
460 void MipsTargetAsmStreamer::emitDirectiveSetAt() {
461   OS << "\t.set\tat\n";
462   MipsTargetStreamer::emitDirectiveSetAt();
463 }
464 
465 void MipsTargetAsmStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
466   OS << "\t.set\tat=$" << Twine(RegNo) << "\n";
467   MipsTargetStreamer::emitDirectiveSetAtWithArg(RegNo);
468 }
469 
470 void MipsTargetAsmStreamer::emitDirectiveSetNoAt() {
471   OS << "\t.set\tnoat\n";
472   MipsTargetStreamer::emitDirectiveSetNoAt();
473 }
474 
475 void MipsTargetAsmStreamer::emitDirectiveEnd(StringRef Name) {
476   OS << "\t.end\t" << Name << '\n';
477 }
478 
479 void MipsTargetAsmStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
480   OS << "\t.ent\t" << Symbol.getName() << '\n';
481 }
482 
483 void MipsTargetAsmStreamer::emitDirectiveAbiCalls() { OS << "\t.abicalls\n"; }
484 
485 void MipsTargetAsmStreamer::emitDirectiveNaN2008() { OS << "\t.nan\t2008\n"; }
486 
487 void MipsTargetAsmStreamer::emitDirectiveNaNLegacy() {
488   OS << "\t.nan\tlegacy\n";
489 }
490 
491 void MipsTargetAsmStreamer::emitDirectiveOptionPic0() {
492   OS << "\t.option\tpic0\n";
493 }
494 
495 void MipsTargetAsmStreamer::emitDirectiveOptionPic2() {
496   OS << "\t.option\tpic2\n";
497 }
498 
499 void MipsTargetAsmStreamer::emitDirectiveInsn() {
500   MipsTargetStreamer::emitDirectiveInsn();
501   OS << "\t.insn\n";
502 }
503 
504 void MipsTargetAsmStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
505                                       unsigned ReturnReg) {
506   OS << "\t.frame\t$"
507      << StringRef(MipsInstPrinter::getRegisterName(StackReg)).lower() << ","
508      << StackSize << ",$"
509      << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n';
510 }
511 
512 void MipsTargetAsmStreamer::emitDirectiveSetArch(StringRef Arch) {
513   OS << "\t.set arch=" << Arch << "\n";
514   MipsTargetStreamer::emitDirectiveSetArch(Arch);
515 }
516 
517 void MipsTargetAsmStreamer::emitDirectiveSetMips0() {
518   OS << "\t.set\tmips0\n";
519   MipsTargetStreamer::emitDirectiveSetMips0();
520 }
521 
522 void MipsTargetAsmStreamer::emitDirectiveSetMips1() {
523   OS << "\t.set\tmips1\n";
524   MipsTargetStreamer::emitDirectiveSetMips1();
525 }
526 
527 void MipsTargetAsmStreamer::emitDirectiveSetMips2() {
528   OS << "\t.set\tmips2\n";
529   MipsTargetStreamer::emitDirectiveSetMips2();
530 }
531 
532 void MipsTargetAsmStreamer::emitDirectiveSetMips3() {
533   OS << "\t.set\tmips3\n";
534   MipsTargetStreamer::emitDirectiveSetMips3();
535 }
536 
537 void MipsTargetAsmStreamer::emitDirectiveSetMips4() {
538   OS << "\t.set\tmips4\n";
539   MipsTargetStreamer::emitDirectiveSetMips4();
540 }
541 
542 void MipsTargetAsmStreamer::emitDirectiveSetMips5() {
543   OS << "\t.set\tmips5\n";
544   MipsTargetStreamer::emitDirectiveSetMips5();
545 }
546 
547 void MipsTargetAsmStreamer::emitDirectiveSetMips32() {
548   OS << "\t.set\tmips32\n";
549   MipsTargetStreamer::emitDirectiveSetMips32();
550 }
551 
552 void MipsTargetAsmStreamer::emitDirectiveSetMips32R2() {
553   OS << "\t.set\tmips32r2\n";
554   MipsTargetStreamer::emitDirectiveSetMips32R2();
555 }
556 
557 void MipsTargetAsmStreamer::emitDirectiveSetMips32R3() {
558   OS << "\t.set\tmips32r3\n";
559   MipsTargetStreamer::emitDirectiveSetMips32R3();
560 }
561 
562 void MipsTargetAsmStreamer::emitDirectiveSetMips32R5() {
563   OS << "\t.set\tmips32r5\n";
564   MipsTargetStreamer::emitDirectiveSetMips32R5();
565 }
566 
567 void MipsTargetAsmStreamer::emitDirectiveSetMips32R6() {
568   OS << "\t.set\tmips32r6\n";
569   MipsTargetStreamer::emitDirectiveSetMips32R6();
570 }
571 
572 void MipsTargetAsmStreamer::emitDirectiveSetMips64() {
573   OS << "\t.set\tmips64\n";
574   MipsTargetStreamer::emitDirectiveSetMips64();
575 }
576 
577 void MipsTargetAsmStreamer::emitDirectiveSetMips64R2() {
578   OS << "\t.set\tmips64r2\n";
579   MipsTargetStreamer::emitDirectiveSetMips64R2();
580 }
581 
582 void MipsTargetAsmStreamer::emitDirectiveSetMips64R3() {
583   OS << "\t.set\tmips64r3\n";
584   MipsTargetStreamer::emitDirectiveSetMips64R3();
585 }
586 
587 void MipsTargetAsmStreamer::emitDirectiveSetMips64R5() {
588   OS << "\t.set\tmips64r5\n";
589   MipsTargetStreamer::emitDirectiveSetMips64R5();
590 }
591 
592 void MipsTargetAsmStreamer::emitDirectiveSetMips64R6() {
593   OS << "\t.set\tmips64r6\n";
594   MipsTargetStreamer::emitDirectiveSetMips64R6();
595 }
596 
597 void MipsTargetAsmStreamer::emitDirectiveSetDsp() {
598   OS << "\t.set\tdsp\n";
599   MipsTargetStreamer::emitDirectiveSetDsp();
600 }
601 
602 void MipsTargetAsmStreamer::emitDirectiveSetDspr2() {
603   OS << "\t.set\tdspr2\n";
604   MipsTargetStreamer::emitDirectiveSetDspr2();
605 }
606 
607 void MipsTargetAsmStreamer::emitDirectiveSetNoDsp() {
608   OS << "\t.set\tnodsp\n";
609   MipsTargetStreamer::emitDirectiveSetNoDsp();
610 }
611 
612 void MipsTargetAsmStreamer::emitDirectiveSetPop() {
613   OS << "\t.set\tpop\n";
614   MipsTargetStreamer::emitDirectiveSetPop();
615 }
616 
617 void MipsTargetAsmStreamer::emitDirectiveSetPush() {
618  OS << "\t.set\tpush\n";
619  MipsTargetStreamer::emitDirectiveSetPush();
620 }
621 
622 void MipsTargetAsmStreamer::emitDirectiveSetSoftFloat() {
623   OS << "\t.set\tsoftfloat\n";
624   MipsTargetStreamer::emitDirectiveSetSoftFloat();
625 }
626 
627 void MipsTargetAsmStreamer::emitDirectiveSetHardFloat() {
628   OS << "\t.set\thardfloat\n";
629   MipsTargetStreamer::emitDirectiveSetHardFloat();
630 }
631 
632 // Print a 32 bit hex number with all numbers.
633 static void printHex32(unsigned Value, raw_ostream &OS) {
634   OS << "0x";
635   for (int i = 7; i >= 0; i--)
636     OS.write_hex((Value & (0xF << (i * 4))) >> (i * 4));
637 }
638 
639 void MipsTargetAsmStreamer::emitMask(unsigned CPUBitmask,
640                                      int CPUTopSavedRegOff) {
641   OS << "\t.mask \t";
642   printHex32(CPUBitmask, OS);
643   OS << ',' << CPUTopSavedRegOff << '\n';
644 }
645 
646 void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask,
647                                       int FPUTopSavedRegOff) {
648   OS << "\t.fmask\t";
649   printHex32(FPUBitmask, OS);
650   OS << "," << FPUTopSavedRegOff << '\n';
651 }
652 
653 void MipsTargetAsmStreamer::emitDirectiveCpLoad(unsigned RegNo) {
654   OS << "\t.cpload\t$"
655      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
656   forbidModuleDirective();
657 }
658 
659 void MipsTargetAsmStreamer::emitDirectiveCpLocal(unsigned RegNo) {
660   OS << "\t.cplocal\t$"
661      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
662   MipsTargetStreamer::emitDirectiveCpLocal(RegNo);
663 }
664 
665 bool MipsTargetAsmStreamer::emitDirectiveCpRestore(
666     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
667     const MCSubtargetInfo *STI) {
668   MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
669   OS << "\t.cprestore\t" << Offset << "\n";
670   return true;
671 }
672 
673 void MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned RegNo,
674                                                  int RegOrOffset,
675                                                  const MCSymbol &Sym,
676                                                  bool IsReg) {
677   OS << "\t.cpsetup\t$"
678      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << ", ";
679 
680   if (IsReg)
681     OS << "$"
682        << StringRef(MipsInstPrinter::getRegisterName(RegOrOffset)).lower();
683   else
684     OS << RegOrOffset;
685 
686   OS << ", ";
687 
688   OS << Sym.getName();
689   forbidModuleDirective();
690 }
691 
692 void MipsTargetAsmStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
693                                                   bool SaveLocationIsRegister) {
694   OS << "\t.cpreturn";
695   forbidModuleDirective();
696 }
697 
698 void MipsTargetAsmStreamer::emitDirectiveModuleFP() {
699   MipsABIFlagsSection::FpABIKind FpABI = ABIFlagsSection.getFpABI();
700   if (FpABI == MipsABIFlagsSection::FpABIKind::SOFT)
701     OS << "\t.module\tsoftfloat\n";
702   else
703     OS << "\t.module\tfp=" << ABIFlagsSection.getFpABIString(FpABI) << "\n";
704 }
705 
706 void MipsTargetAsmStreamer::emitDirectiveSetFp(
707     MipsABIFlagsSection::FpABIKind Value) {
708   MipsTargetStreamer::emitDirectiveSetFp(Value);
709 
710   OS << "\t.set\tfp=";
711   OS << ABIFlagsSection.getFpABIString(Value) << "\n";
712 }
713 
714 void MipsTargetAsmStreamer::emitDirectiveModuleOddSPReg() {
715   MipsTargetStreamer::emitDirectiveModuleOddSPReg();
716 
717   OS << "\t.module\t" << (ABIFlagsSection.OddSPReg ? "" : "no") << "oddspreg\n";
718 }
719 
720 void MipsTargetAsmStreamer::emitDirectiveSetOddSPReg() {
721   MipsTargetStreamer::emitDirectiveSetOddSPReg();
722   OS << "\t.set\toddspreg\n";
723 }
724 
725 void MipsTargetAsmStreamer::emitDirectiveSetNoOddSPReg() {
726   MipsTargetStreamer::emitDirectiveSetNoOddSPReg();
727   OS << "\t.set\tnooddspreg\n";
728 }
729 
730 void MipsTargetAsmStreamer::emitDirectiveModuleSoftFloat() {
731   OS << "\t.module\tsoftfloat\n";
732 }
733 
734 void MipsTargetAsmStreamer::emitDirectiveModuleHardFloat() {
735   OS << "\t.module\thardfloat\n";
736 }
737 
738 void MipsTargetAsmStreamer::emitDirectiveModuleMT() {
739   OS << "\t.module\tmt\n";
740 }
741 
742 void MipsTargetAsmStreamer::emitDirectiveModuleCRC() {
743   OS << "\t.module\tcrc\n";
744 }
745 
746 void MipsTargetAsmStreamer::emitDirectiveModuleNoCRC() {
747   OS << "\t.module\tnocrc\n";
748 }
749 
750 void MipsTargetAsmStreamer::emitDirectiveModuleVirt() {
751   OS << "\t.module\tvirt\n";
752 }
753 
754 void MipsTargetAsmStreamer::emitDirectiveModuleNoVirt() {
755   OS << "\t.module\tnovirt\n";
756 }
757 
758 void MipsTargetAsmStreamer::emitDirectiveModuleGINV() {
759   OS << "\t.module\tginv\n";
760 }
761 
762 void MipsTargetAsmStreamer::emitDirectiveModuleNoGINV() {
763   OS << "\t.module\tnoginv\n";
764 }
765 
766 // This part is for ELF object output.
767 MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
768                                              const MCSubtargetInfo &STI)
769     : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
770   MCAssembler &MCA = getStreamer().getAssembler();
771 
772   // It's possible that MCObjectFileInfo isn't fully initialized at this point
773   // due to an initialization order problem where LLVMTargetMachine creates the
774   // target streamer before TargetLoweringObjectFile calls
775   // InitializeMCObjectFileInfo. There doesn't seem to be a single place that
776   // covers all cases so this statement covers most cases and direct object
777   // emission must call setPic() once MCObjectFileInfo has been initialized. The
778   // cases we don't handle here are covered by MipsAsmPrinter.
779   Pic = MCA.getContext().getObjectFileInfo()->isPositionIndependent();
780 
781   const FeatureBitset &Features = STI.getFeatureBits();
782 
783   // Set the header flags that we can in the constructor.
784   // FIXME: This is a fairly terrible hack. We set the rest
785   // of these in the destructor. The problem here is two-fold:
786   //
787   // a: Some of the eflags can be set/reset by directives.
788   // b: There aren't any usage paths that initialize the ABI
789   //    pointer until after we initialize either an assembler
790   //    or the target machine.
791   // We can fix this by making the target streamer construct
792   // the ABI, but this is fraught with wide ranging dependency
793   // issues as well.
794   unsigned EFlags = MCA.getELFHeaderEFlags();
795 
796   // FIXME: Fix a dependency issue by instantiating the ABI object to some
797   // default based off the triple. The triple doesn't describe the target
798   // fully, but any external user of the API that uses the MCTargetStreamer
799   // would otherwise crash on assertion failure.
800 
801   ABI = MipsABIInfo(
802       STI.getTargetTriple().getArch() == Triple::ArchType::mipsel ||
803               STI.getTargetTriple().getArch() == Triple::ArchType::mips
804           ? MipsABIInfo::O32()
805           : MipsABIInfo::N64());
806 
807   // Architecture
808   if (Features[Mips::FeatureMips64r6])
809     EFlags |= ELF::EF_MIPS_ARCH_64R6;
810   else if (Features[Mips::FeatureMips64r2] ||
811            Features[Mips::FeatureMips64r3] ||
812            Features[Mips::FeatureMips64r5])
813     EFlags |= ELF::EF_MIPS_ARCH_64R2;
814   else if (Features[Mips::FeatureMips64])
815     EFlags |= ELF::EF_MIPS_ARCH_64;
816   else if (Features[Mips::FeatureMips5])
817     EFlags |= ELF::EF_MIPS_ARCH_5;
818   else if (Features[Mips::FeatureMips4])
819     EFlags |= ELF::EF_MIPS_ARCH_4;
820   else if (Features[Mips::FeatureMips3])
821     EFlags |= ELF::EF_MIPS_ARCH_3;
822   else if (Features[Mips::FeatureMips32r6])
823     EFlags |= ELF::EF_MIPS_ARCH_32R6;
824   else if (Features[Mips::FeatureMips32r2] ||
825            Features[Mips::FeatureMips32r3] ||
826            Features[Mips::FeatureMips32r5])
827     EFlags |= ELF::EF_MIPS_ARCH_32R2;
828   else if (Features[Mips::FeatureMips32])
829     EFlags |= ELF::EF_MIPS_ARCH_32;
830   else if (Features[Mips::FeatureMips2])
831     EFlags |= ELF::EF_MIPS_ARCH_2;
832   else
833     EFlags |= ELF::EF_MIPS_ARCH_1;
834 
835   // Machine
836   if (Features[Mips::FeatureCnMips])
837     EFlags |= ELF::EF_MIPS_MACH_OCTEON;
838 
839   // Other options.
840   if (Features[Mips::FeatureNaN2008])
841     EFlags |= ELF::EF_MIPS_NAN2008;
842 
843   MCA.setELFHeaderEFlags(EFlags);
844 }
845 
846 void MipsTargetELFStreamer::emitLabel(MCSymbol *S) {
847   auto *Symbol = cast<MCSymbolELF>(S);
848   getStreamer().getAssembler().registerSymbol(*Symbol);
849   uint8_t Type = Symbol->getType();
850   if (Type != ELF::STT_FUNC)
851     return;
852 
853   if (isMicroMipsEnabled())
854     Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
855 }
856 
857 void MipsTargetELFStreamer::finish() {
858   MCAssembler &MCA = getStreamer().getAssembler();
859   const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo();
860 
861   // .bss, .text and .data are always at least 16-byte aligned.
862   MCSection &TextSection = *OFI.getTextSection();
863   MCA.registerSection(TextSection);
864   MCSection &DataSection = *OFI.getDataSection();
865   MCA.registerSection(DataSection);
866   MCSection &BSSSection = *OFI.getBSSSection();
867   MCA.registerSection(BSSSection);
868 
869   TextSection.setAlignment(Align(std::max(16u, TextSection.getAlignment())));
870   DataSection.setAlignment(Align(std::max(16u, DataSection.getAlignment())));
871   BSSSection.setAlignment(Align(std::max(16u, BSSSection.getAlignment())));
872 
873   if (RoundSectionSizes) {
874     // Make sections sizes a multiple of the alignment. This is useful for
875     // verifying the output of IAS against the output of other assemblers but
876     // it's not necessary to produce a correct object and increases section
877     // size.
878     MCStreamer &OS = getStreamer();
879     for (MCSection &S : MCA) {
880       MCSectionELF &Section = static_cast<MCSectionELF &>(S);
881 
882       unsigned Alignment = Section.getAlignment();
883       if (Alignment) {
884         OS.SwitchSection(&Section);
885         if (Section.UseCodeAlign())
886           OS.EmitCodeAlignment(Alignment, Alignment);
887         else
888           OS.EmitValueToAlignment(Alignment, 0, 1, Alignment);
889       }
890     }
891   }
892 
893   const FeatureBitset &Features = STI.getFeatureBits();
894 
895   // Update e_header flags. See the FIXME and comment above in
896   // the constructor for a full rundown on this.
897   unsigned EFlags = MCA.getELFHeaderEFlags();
898 
899   // ABI
900   // N64 does not require any ABI bits.
901   if (getABI().IsO32())
902     EFlags |= ELF::EF_MIPS_ABI_O32;
903   else if (getABI().IsN32())
904     EFlags |= ELF::EF_MIPS_ABI2;
905 
906   if (Features[Mips::FeatureGP64Bit]) {
907     if (getABI().IsO32())
908       EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
909   } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
910     EFlags |= ELF::EF_MIPS_32BITMODE;
911 
912   // -mplt is not implemented but we should act as if it was
913   // given.
914   if (!Features[Mips::FeatureNoABICalls])
915     EFlags |= ELF::EF_MIPS_CPIC;
916 
917   if (Pic)
918     EFlags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
919 
920   MCA.setELFHeaderEFlags(EFlags);
921 
922   // Emit all the option records.
923   // At the moment we are only emitting .Mips.options (ODK_REGINFO) and
924   // .reginfo.
925   MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
926   MEF.EmitMipsOptionRecords();
927 
928   emitMipsAbiFlags();
929 }
930 
931 void MipsTargetELFStreamer::emitAssignment(MCSymbol *S, const MCExpr *Value) {
932   auto *Symbol = cast<MCSymbolELF>(S);
933   // If on rhs is micromips symbol then mark Symbol as microMips.
934   if (Value->getKind() != MCExpr::SymbolRef)
935     return;
936   const auto &RhsSym = cast<MCSymbolELF>(
937       static_cast<const MCSymbolRefExpr *>(Value)->getSymbol());
938 
939   if (!(RhsSym.getOther() & ELF::STO_MIPS_MICROMIPS))
940     return;
941 
942   Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
943 }
944 
945 MCELFStreamer &MipsTargetELFStreamer::getStreamer() {
946   return static_cast<MCELFStreamer &>(Streamer);
947 }
948 
949 void MipsTargetELFStreamer::emitDirectiveSetMicroMips() {
950   MicroMipsEnabled = true;
951   forbidModuleDirective();
952 }
953 
954 void MipsTargetELFStreamer::emitDirectiveSetNoMicroMips() {
955   MicroMipsEnabled = false;
956   forbidModuleDirective();
957 }
958 
959 void MipsTargetELFStreamer::setUsesMicroMips() {
960   MCAssembler &MCA = getStreamer().getAssembler();
961   unsigned Flags = MCA.getELFHeaderEFlags();
962   Flags |= ELF::EF_MIPS_MICROMIPS;
963   MCA.setELFHeaderEFlags(Flags);
964 }
965 
966 void MipsTargetELFStreamer::emitDirectiveSetMips16() {
967   MCAssembler &MCA = getStreamer().getAssembler();
968   unsigned Flags = MCA.getELFHeaderEFlags();
969   Flags |= ELF::EF_MIPS_ARCH_ASE_M16;
970   MCA.setELFHeaderEFlags(Flags);
971   forbidModuleDirective();
972 }
973 
974 void MipsTargetELFStreamer::emitDirectiveSetNoReorder() {
975   MCAssembler &MCA = getStreamer().getAssembler();
976   unsigned Flags = MCA.getELFHeaderEFlags();
977   Flags |= ELF::EF_MIPS_NOREORDER;
978   MCA.setELFHeaderEFlags(Flags);
979   forbidModuleDirective();
980 }
981 
982 void MipsTargetELFStreamer::emitDirectiveEnd(StringRef Name) {
983   MCAssembler &MCA = getStreamer().getAssembler();
984   MCContext &Context = MCA.getContext();
985   MCStreamer &OS = getStreamer();
986 
987   MCSectionELF *Sec = Context.getELFSection(".pdr", ELF::SHT_PROGBITS, 0);
988 
989   MCSymbol *Sym = Context.getOrCreateSymbol(Name);
990   const MCSymbolRefExpr *ExprRef =
991       MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Context);
992 
993   MCA.registerSection(*Sec);
994   Sec->setAlignment(Align(4));
995 
996   OS.PushSection();
997 
998   OS.SwitchSection(Sec);
999 
1000   OS.EmitValueImpl(ExprRef, 4);
1001 
1002   OS.EmitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask
1003   OS.EmitIntValue(GPRInfoSet ? GPROffset : 0, 4);  // reg_offset
1004 
1005   OS.EmitIntValue(FPRInfoSet ? FPRBitMask : 0, 4); // fpreg_mask
1006   OS.EmitIntValue(FPRInfoSet ? FPROffset : 0, 4);  // fpreg_offset
1007 
1008   OS.EmitIntValue(FrameInfoSet ? FrameOffset : 0, 4); // frame_offset
1009   OS.EmitIntValue(FrameInfoSet ? FrameReg : 0, 4);    // frame_reg
1010   OS.EmitIntValue(FrameInfoSet ? ReturnReg : 0, 4);   // return_reg
1011 
1012   // The .end directive marks the end of a procedure. Invalidate
1013   // the information gathered up until this point.
1014   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1015 
1016   OS.PopSection();
1017 
1018   // .end also implicitly sets the size.
1019   MCSymbol *CurPCSym = Context.createTempSymbol();
1020   OS.EmitLabel(CurPCSym);
1021   const MCExpr *Size = MCBinaryExpr::createSub(
1022       MCSymbolRefExpr::create(CurPCSym, MCSymbolRefExpr::VK_None, Context),
1023       ExprRef, Context);
1024 
1025   // The ELFObjectWriter can determine the absolute size as it has access to
1026   // the layout information of the assembly file, so a size expression rather
1027   // than an absolute value is ok here.
1028   static_cast<MCSymbolELF *>(Sym)->setSize(Size);
1029 }
1030 
1031 void MipsTargetELFStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
1032   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1033 
1034   // .ent also acts like an implicit '.type symbol, STT_FUNC'
1035   static_cast<const MCSymbolELF &>(Symbol).setType(ELF::STT_FUNC);
1036 }
1037 
1038 void MipsTargetELFStreamer::emitDirectiveAbiCalls() {
1039   MCAssembler &MCA = getStreamer().getAssembler();
1040   unsigned Flags = MCA.getELFHeaderEFlags();
1041   Flags |= ELF::EF_MIPS_CPIC | ELF::EF_MIPS_PIC;
1042   MCA.setELFHeaderEFlags(Flags);
1043 }
1044 
1045 void MipsTargetELFStreamer::emitDirectiveNaN2008() {
1046   MCAssembler &MCA = getStreamer().getAssembler();
1047   unsigned Flags = MCA.getELFHeaderEFlags();
1048   Flags |= ELF::EF_MIPS_NAN2008;
1049   MCA.setELFHeaderEFlags(Flags);
1050 }
1051 
1052 void MipsTargetELFStreamer::emitDirectiveNaNLegacy() {
1053   MCAssembler &MCA = getStreamer().getAssembler();
1054   unsigned Flags = MCA.getELFHeaderEFlags();
1055   Flags &= ~ELF::EF_MIPS_NAN2008;
1056   MCA.setELFHeaderEFlags(Flags);
1057 }
1058 
1059 void MipsTargetELFStreamer::emitDirectiveOptionPic0() {
1060   MCAssembler &MCA = getStreamer().getAssembler();
1061   unsigned Flags = MCA.getELFHeaderEFlags();
1062   // This option overrides other PIC options like -KPIC.
1063   Pic = false;
1064   Flags &= ~ELF::EF_MIPS_PIC;
1065   MCA.setELFHeaderEFlags(Flags);
1066 }
1067 
1068 void MipsTargetELFStreamer::emitDirectiveOptionPic2() {
1069   MCAssembler &MCA = getStreamer().getAssembler();
1070   unsigned Flags = MCA.getELFHeaderEFlags();
1071   Pic = true;
1072   // NOTE: We are following the GAS behaviour here which means the directive
1073   // 'pic2' also sets the CPIC bit in the ELF header. This is different from
1074   // what is stated in the SYSV ABI which consider the bits EF_MIPS_PIC and
1075   // EF_MIPS_CPIC to be mutually exclusive.
1076   Flags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
1077   MCA.setELFHeaderEFlags(Flags);
1078 }
1079 
1080 void MipsTargetELFStreamer::emitDirectiveInsn() {
1081   MipsTargetStreamer::emitDirectiveInsn();
1082   MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
1083   MEF.createPendingLabelRelocs();
1084 }
1085 
1086 void MipsTargetELFStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
1087                                       unsigned ReturnReg_) {
1088   MCContext &Context = getStreamer().getAssembler().getContext();
1089   const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
1090 
1091   FrameInfoSet = true;
1092   FrameReg = RegInfo->getEncodingValue(StackReg);
1093   FrameOffset = StackSize;
1094   ReturnReg = RegInfo->getEncodingValue(ReturnReg_);
1095 }
1096 
1097 void MipsTargetELFStreamer::emitMask(unsigned CPUBitmask,
1098                                      int CPUTopSavedRegOff) {
1099   GPRInfoSet = true;
1100   GPRBitMask = CPUBitmask;
1101   GPROffset = CPUTopSavedRegOff;
1102 }
1103 
1104 void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask,
1105                                       int FPUTopSavedRegOff) {
1106   FPRInfoSet = true;
1107   FPRBitMask = FPUBitmask;
1108   FPROffset = FPUTopSavedRegOff;
1109 }
1110 
1111 void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) {
1112   // .cpload $reg
1113   // This directive expands to:
1114   // lui   $gp, %hi(_gp_disp)
1115   // addui $gp, $gp, %lo(_gp_disp)
1116   // addu  $gp, $gp, $reg
1117   // when support for position independent code is enabled.
1118   if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1119     return;
1120 
1121   // There's a GNU extension controlled by -mno-shared that allows
1122   // locally-binding symbols to be accessed using absolute addresses.
1123   // This is currently not supported. When supported -mno-shared makes
1124   // .cpload expand to:
1125   //   lui     $gp, %hi(__gnu_local_gp)
1126   //   addiu   $gp, $gp, %lo(__gnu_local_gp)
1127 
1128   StringRef SymName("_gp_disp");
1129   MCAssembler &MCA = getStreamer().getAssembler();
1130   MCSymbol *GP_Disp = MCA.getContext().getOrCreateSymbol(SymName);
1131   MCA.registerSymbol(*GP_Disp);
1132 
1133   MCInst TmpInst;
1134   TmpInst.setOpcode(Mips::LUi);
1135   TmpInst.addOperand(MCOperand::createReg(GPReg));
1136   const MCExpr *HiSym = MipsMCExpr::create(
1137       MipsMCExpr::MEK_HI,
1138       MCSymbolRefExpr::create("_gp_disp", MCSymbolRefExpr::VK_None,
1139                               MCA.getContext()),
1140       MCA.getContext());
1141   TmpInst.addOperand(MCOperand::createExpr(HiSym));
1142   getStreamer().EmitInstruction(TmpInst, STI);
1143 
1144   TmpInst.clear();
1145 
1146   TmpInst.setOpcode(Mips::ADDiu);
1147   TmpInst.addOperand(MCOperand::createReg(GPReg));
1148   TmpInst.addOperand(MCOperand::createReg(GPReg));
1149   const MCExpr *LoSym = MipsMCExpr::create(
1150       MipsMCExpr::MEK_LO,
1151       MCSymbolRefExpr::create("_gp_disp", MCSymbolRefExpr::VK_None,
1152                               MCA.getContext()),
1153       MCA.getContext());
1154   TmpInst.addOperand(MCOperand::createExpr(LoSym));
1155   getStreamer().EmitInstruction(TmpInst, STI);
1156 
1157   TmpInst.clear();
1158 
1159   TmpInst.setOpcode(Mips::ADDu);
1160   TmpInst.addOperand(MCOperand::createReg(GPReg));
1161   TmpInst.addOperand(MCOperand::createReg(GPReg));
1162   TmpInst.addOperand(MCOperand::createReg(RegNo));
1163   getStreamer().EmitInstruction(TmpInst, STI);
1164 
1165   forbidModuleDirective();
1166 }
1167 
1168 void MipsTargetELFStreamer::emitDirectiveCpLocal(unsigned RegNo) {
1169   if (Pic)
1170     MipsTargetStreamer::emitDirectiveCpLocal(RegNo);
1171 }
1172 
1173 bool MipsTargetELFStreamer::emitDirectiveCpRestore(
1174     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
1175     const MCSubtargetInfo *STI) {
1176   MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
1177   // .cprestore offset
1178   // When PIC mode is enabled and the O32 ABI is used, this directive expands
1179   // to:
1180   //    sw $gp, offset($sp)
1181   // and adds a corresponding LW after every JAL.
1182 
1183   // Note that .cprestore is ignored if used with the N32 and N64 ABIs or if it
1184   // is used in non-PIC mode.
1185   if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1186     return true;
1187 
1188   // Store the $gp on the stack.
1189   emitStoreWithImmOffset(Mips::SW, GPReg, Mips::SP, Offset, GetATReg, IDLoc,
1190                          STI);
1191   return true;
1192 }
1193 
1194 void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo,
1195                                                  int RegOrOffset,
1196                                                  const MCSymbol &Sym,
1197                                                  bool IsReg) {
1198   // Only N32 and N64 emit anything for .cpsetup iff PIC is set.
1199   if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1200     return;
1201 
1202   forbidModuleDirective();
1203 
1204   MCAssembler &MCA = getStreamer().getAssembler();
1205   MCInst Inst;
1206 
1207   // Either store the old $gp in a register or on the stack
1208   if (IsReg) {
1209     // move $save, $gpreg
1210     emitRRR(Mips::OR64, RegOrOffset, GPReg, Mips::ZERO, SMLoc(), &STI);
1211   } else {
1212     // sd $gpreg, offset($sp)
1213     emitRRI(Mips::SD, GPReg, Mips::SP, RegOrOffset, SMLoc(), &STI);
1214   }
1215 
1216   if (getABI().IsN32()) {
1217     MCSymbol *GPSym = MCA.getContext().getOrCreateSymbol("__gnu_local_gp");
1218     const MipsMCExpr *HiExpr = MipsMCExpr::create(
1219         MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
1220         MCA.getContext());
1221     const MipsMCExpr *LoExpr = MipsMCExpr::create(
1222         MipsMCExpr::MEK_LO, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
1223         MCA.getContext());
1224 
1225     // lui $gp, %hi(__gnu_local_gp)
1226     emitRX(Mips::LUi, GPReg, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1227 
1228     // addiu  $gp, $gp, %lo(__gnu_local_gp)
1229     emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(),
1230             &STI);
1231 
1232     return;
1233   }
1234 
1235   const MipsMCExpr *HiExpr = MipsMCExpr::createGpOff(
1236       MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(&Sym, MCA.getContext()),
1237       MCA.getContext());
1238   const MipsMCExpr *LoExpr = MipsMCExpr::createGpOff(
1239       MipsMCExpr::MEK_LO, MCSymbolRefExpr::create(&Sym, MCA.getContext()),
1240       MCA.getContext());
1241 
1242   // lui $gp, %hi(%neg(%gp_rel(funcSym)))
1243   emitRX(Mips::LUi, GPReg, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1244 
1245   // addiu  $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
1246   emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(),
1247           &STI);
1248 
1249   // daddu  $gp, $gp, $funcreg
1250   emitRRR(Mips::DADDu, GPReg, GPReg, RegNo, SMLoc(), &STI);
1251 }
1252 
1253 void MipsTargetELFStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
1254                                                   bool SaveLocationIsRegister) {
1255   // Only N32 and N64 emit anything for .cpreturn iff PIC is set.
1256   if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1257     return;
1258 
1259   MCInst Inst;
1260   // Either restore the old $gp from a register or on the stack
1261   if (SaveLocationIsRegister) {
1262     Inst.setOpcode(Mips::OR);
1263     Inst.addOperand(MCOperand::createReg(GPReg));
1264     Inst.addOperand(MCOperand::createReg(SaveLocation));
1265     Inst.addOperand(MCOperand::createReg(Mips::ZERO));
1266   } else {
1267     Inst.setOpcode(Mips::LD);
1268     Inst.addOperand(MCOperand::createReg(GPReg));
1269     Inst.addOperand(MCOperand::createReg(Mips::SP));
1270     Inst.addOperand(MCOperand::createImm(SaveLocation));
1271   }
1272   getStreamer().EmitInstruction(Inst, STI);
1273 
1274   forbidModuleDirective();
1275 }
1276 
1277 void MipsTargetELFStreamer::emitMipsAbiFlags() {
1278   MCAssembler &MCA = getStreamer().getAssembler();
1279   MCContext &Context = MCA.getContext();
1280   MCStreamer &OS = getStreamer();
1281   MCSectionELF *Sec = Context.getELFSection(
1282       ".MIPS.abiflags", ELF::SHT_MIPS_ABIFLAGS, ELF::SHF_ALLOC, 24, "");
1283   MCA.registerSection(*Sec);
1284   Sec->setAlignment(Align(8));
1285   OS.SwitchSection(Sec);
1286 
1287   OS << ABIFlagsSection;
1288 }
1289