xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp (revision 6966ac055c3b7a39266fb982493330df7a097997) 
1 //===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Mips specific target streamer methods.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsTargetStreamer.h"
14 #include "MipsInstPrinter.h"
15 #include "MCTargetDesc/MipsABIInfo.h"
16 #include "MipsELFStreamer.h"
17 #include "MipsMCExpr.h"
18 #include "MipsMCTargetDesc.h"
19 #include "MipsTargetObjectFile.h"
20 #include "llvm/BinaryFormat/ELF.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCSectionELF.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCSymbolELF.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/FormattedStream.h"
28 
29 using namespace llvm;
30 
31 namespace {
32 static cl::opt<bool> RoundSectionSizes(
33     "mips-round-section-sizes", cl::init(false),
34     cl::desc("Round section sizes up to the section alignment"), cl::Hidden);
35 } // end anonymous namespace
36 
37 MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S)
38     : MCTargetStreamer(S), GPReg(Mips::GP), ModuleDirectiveAllowed(true) {
39   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
40 }
41 void MipsTargetStreamer::emitDirectiveSetMicroMips() {}
42 void MipsTargetStreamer::emitDirectiveSetNoMicroMips() {}
43 void MipsTargetStreamer::setUsesMicroMips() {}
44 void MipsTargetStreamer::emitDirectiveSetMips16() {}
45 void MipsTargetStreamer::emitDirectiveSetNoMips16() { forbidModuleDirective(); }
46 void MipsTargetStreamer::emitDirectiveSetReorder() { forbidModuleDirective(); }
47 void MipsTargetStreamer::emitDirectiveSetNoReorder() {}
48 void MipsTargetStreamer::emitDirectiveSetMacro() { forbidModuleDirective(); }
49 void MipsTargetStreamer::emitDirectiveSetNoMacro() { forbidModuleDirective(); }
50 void MipsTargetStreamer::emitDirectiveSetMsa() { forbidModuleDirective(); }
51 void MipsTargetStreamer::emitDirectiveSetNoMsa() { forbidModuleDirective(); }
52 void MipsTargetStreamer::emitDirectiveSetMt() {}
53 void MipsTargetStreamer::emitDirectiveSetNoMt() { forbidModuleDirective(); }
54 void MipsTargetStreamer::emitDirectiveSetCRC() {}
55 void MipsTargetStreamer::emitDirectiveSetNoCRC() {}
56 void MipsTargetStreamer::emitDirectiveSetVirt() {}
57 void MipsTargetStreamer::emitDirectiveSetNoVirt() {}
58 void MipsTargetStreamer::emitDirectiveSetGINV() {}
59 void MipsTargetStreamer::emitDirectiveSetNoGINV() {}
60 void MipsTargetStreamer::emitDirectiveSetAt() { forbidModuleDirective(); }
61 void MipsTargetStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
62   forbidModuleDirective();
63 }
64 void MipsTargetStreamer::emitDirectiveSetNoAt() { forbidModuleDirective(); }
65 void MipsTargetStreamer::emitDirectiveEnd(StringRef Name) {}
66 void MipsTargetStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {}
67 void MipsTargetStreamer::emitDirectiveAbiCalls() {}
68 void MipsTargetStreamer::emitDirectiveNaN2008() {}
69 void MipsTargetStreamer::emitDirectiveNaNLegacy() {}
70 void MipsTargetStreamer::emitDirectiveOptionPic0() {}
71 void MipsTargetStreamer::emitDirectiveOptionPic2() {}
72 void MipsTargetStreamer::emitDirectiveInsn() { forbidModuleDirective(); }
73 void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
74                                    unsigned ReturnReg) {}
75 void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
76 void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
77 }
78 void MipsTargetStreamer::emitDirectiveSetArch(StringRef Arch) {
79   forbidModuleDirective();
80 }
81 void MipsTargetStreamer::emitDirectiveSetMips0() { forbidModuleDirective(); }
82 void MipsTargetStreamer::emitDirectiveSetMips1() { forbidModuleDirective(); }
83 void MipsTargetStreamer::emitDirectiveSetMips2() { forbidModuleDirective(); }
84 void MipsTargetStreamer::emitDirectiveSetMips3() { forbidModuleDirective(); }
85 void MipsTargetStreamer::emitDirectiveSetMips4() { forbidModuleDirective(); }
86 void MipsTargetStreamer::emitDirectiveSetMips5() { forbidModuleDirective(); }
87 void MipsTargetStreamer::emitDirectiveSetMips32() { forbidModuleDirective(); }
88 void MipsTargetStreamer::emitDirectiveSetMips32R2() { forbidModuleDirective(); }
89 void MipsTargetStreamer::emitDirectiveSetMips32R3() { forbidModuleDirective(); }
90 void MipsTargetStreamer::emitDirectiveSetMips32R5() { forbidModuleDirective(); }
91 void MipsTargetStreamer::emitDirectiveSetMips32R6() { forbidModuleDirective(); }
92 void MipsTargetStreamer::emitDirectiveSetMips64() { forbidModuleDirective(); }
93 void MipsTargetStreamer::emitDirectiveSetMips64R2() { forbidModuleDirective(); }
94 void MipsTargetStreamer::emitDirectiveSetMips64R3() { forbidModuleDirective(); }
95 void MipsTargetStreamer::emitDirectiveSetMips64R5() { forbidModuleDirective(); }
96 void MipsTargetStreamer::emitDirectiveSetMips64R6() { forbidModuleDirective(); }
97 void MipsTargetStreamer::emitDirectiveSetPop() { forbidModuleDirective(); }
98 void MipsTargetStreamer::emitDirectiveSetPush() { forbidModuleDirective(); }
99 void MipsTargetStreamer::emitDirectiveSetSoftFloat() {
100   forbidModuleDirective();
101 }
102 void MipsTargetStreamer::emitDirectiveSetHardFloat() {
103   forbidModuleDirective();
104 }
105 void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); }
106 void MipsTargetStreamer::emitDirectiveSetDspr2() { forbidModuleDirective(); }
107 void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); }
108 void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {}
109 void MipsTargetStreamer::emitDirectiveCpLocal(unsigned RegNo) {
110   // .cplocal $reg
111   // This directive forces to use the alternate register for context pointer.
112   // For example
113   //   .cplocal $4
114   //   jal foo
115   // expands to
116   //   ld    $25, %call16(foo)($4)
117   //   jalr  $25
118 
119   if (!getABI().IsN32() && !getABI().IsN64())
120     return;
121 
122   GPReg = RegNo;
123 
124   forbidModuleDirective();
125 }
126 bool MipsTargetStreamer::emitDirectiveCpRestore(
127     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
128     const MCSubtargetInfo *STI) {
129   forbidModuleDirective();
130   return true;
131 }
132 void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
133                                               const MCSymbol &Sym, bool IsReg) {
134 }
135 void MipsTargetStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
136                                                bool SaveLocationIsRegister) {}
137 
138 void MipsTargetStreamer::emitDirectiveModuleFP() {}
139 
140 void MipsTargetStreamer::emitDirectiveModuleOddSPReg() {
141   if (!ABIFlagsSection.OddSPReg && !ABIFlagsSection.Is32BitABI)
142     report_fatal_error("+nooddspreg is only valid for O32");
143 }
144 void MipsTargetStreamer::emitDirectiveModuleSoftFloat() {}
145 void MipsTargetStreamer::emitDirectiveModuleHardFloat() {}
146 void MipsTargetStreamer::emitDirectiveModuleMT() {}
147 void MipsTargetStreamer::emitDirectiveModuleCRC() {}
148 void MipsTargetStreamer::emitDirectiveModuleNoCRC() {}
149 void MipsTargetStreamer::emitDirectiveModuleVirt() {}
150 void MipsTargetStreamer::emitDirectiveModuleNoVirt() {}
151 void MipsTargetStreamer::emitDirectiveModuleGINV() {}
152 void MipsTargetStreamer::emitDirectiveModuleNoGINV() {}
153 void MipsTargetStreamer::emitDirectiveSetFp(
154     MipsABIFlagsSection::FpABIKind Value) {
155   forbidModuleDirective();
156 }
157 void MipsTargetStreamer::emitDirectiveSetOddSPReg() { forbidModuleDirective(); }
158 void MipsTargetStreamer::emitDirectiveSetNoOddSPReg() {
159   forbidModuleDirective();
160 }
161 
162 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
163                                const MCSubtargetInfo *STI) {
164   MCInst TmpInst;
165   TmpInst.setOpcode(Opcode);
166   TmpInst.addOperand(MCOperand::createReg(Reg0));
167   TmpInst.setLoc(IDLoc);
168   getStreamer().EmitInstruction(TmpInst, *STI);
169 }
170 
171 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1,
172                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
173   MCInst TmpInst;
174   TmpInst.setOpcode(Opcode);
175   TmpInst.addOperand(MCOperand::createReg(Reg0));
176   TmpInst.addOperand(Op1);
177   TmpInst.setLoc(IDLoc);
178   getStreamer().EmitInstruction(TmpInst, *STI);
179 }
180 
181 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm,
182                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
183   emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI);
184 }
185 
186 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
187                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
188   emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI);
189 }
190 
191 void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2,
192                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
193   MCInst TmpInst;
194   TmpInst.setOpcode(Opcode);
195   TmpInst.addOperand(MCOperand::createImm(Imm1));
196   TmpInst.addOperand(MCOperand::createImm(Imm2));
197   TmpInst.setLoc(IDLoc);
198   getStreamer().EmitInstruction(TmpInst, *STI);
199 }
200 
201 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
202                                  MCOperand Op2, SMLoc IDLoc,
203                                  const MCSubtargetInfo *STI) {
204   MCInst TmpInst;
205   TmpInst.setOpcode(Opcode);
206   TmpInst.addOperand(MCOperand::createReg(Reg0));
207   TmpInst.addOperand(MCOperand::createReg(Reg1));
208   TmpInst.addOperand(Op2);
209   TmpInst.setLoc(IDLoc);
210   getStreamer().EmitInstruction(TmpInst, *STI);
211 }
212 
213 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
214                                  unsigned Reg2, SMLoc IDLoc,
215                                  const MCSubtargetInfo *STI) {
216   emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI);
217 }
218 
219 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1,
220                                  int16_t Imm, SMLoc IDLoc,
221                                  const MCSubtargetInfo *STI) {
222   emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI);
223 }
224 
225 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0,
226                                    unsigned Reg1, int16_t Imm0, int16_t Imm1,
227                                    int16_t Imm2, SMLoc IDLoc,
228                                    const MCSubtargetInfo *STI) {
229   MCInst TmpInst;
230   TmpInst.setOpcode(Opcode);
231   TmpInst.addOperand(MCOperand::createReg(Reg0));
232   TmpInst.addOperand(MCOperand::createReg(Reg1));
233   TmpInst.addOperand(MCOperand::createImm(Imm0));
234   TmpInst.addOperand(MCOperand::createImm(Imm1));
235   TmpInst.addOperand(MCOperand::createImm(Imm2));
236   TmpInst.setLoc(IDLoc);
237   getStreamer().EmitInstruction(TmpInst, *STI);
238 }
239 
240 void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg,
241                                   unsigned TrgReg, bool Is64Bit,
242                                   const MCSubtargetInfo *STI) {
243   emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
244           STI);
245 }
246 
247 void MipsTargetStreamer::emitDSLL(unsigned DstReg, unsigned SrcReg,
248                                   int16_t ShiftAmount, SMLoc IDLoc,
249                                   const MCSubtargetInfo *STI) {
250   if (ShiftAmount >= 32) {
251     emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI);
252     return;
253   }
254 
255   emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI);
256 }
257 
258 void MipsTargetStreamer::emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc,
259                                             const MCSubtargetInfo *STI) {
260   if (hasShortDelaySlot)
261     emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
262   else
263     emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
264 }
265 
266 void MipsTargetStreamer::emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI) {
267   const FeatureBitset &Features = STI->getFeatureBits();
268   if (Features[Mips::FeatureMicroMips])
269     emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
270   else
271     emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
272 }
273 
274 /// Emit the $gp restore operation for .cprestore.
275 void MipsTargetStreamer::emitGPRestore(int Offset, SMLoc IDLoc,
276                                        const MCSubtargetInfo *STI) {
277   emitLoadWithImmOffset(Mips::LW, GPReg, Mips::SP, Offset, GPReg, IDLoc, STI);
278 }
279 
280 /// Emit a store instruction with an immediate offset.
281 void MipsTargetStreamer::emitStoreWithImmOffset(
282     unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset,
283     function_ref<unsigned()> GetATReg, SMLoc IDLoc,
284     const MCSubtargetInfo *STI) {
285   if (isInt<16>(Offset)) {
286     emitRRI(Opcode, SrcReg, BaseReg, Offset, IDLoc, STI);
287     return;
288   }
289 
290   // sw $8, offset($8) => lui $at, %hi(offset)
291   //                      add $at, $at, $8
292   //                      sw $8, %lo(offset)($at)
293 
294   unsigned ATReg = GetATReg();
295   if (!ATReg)
296     return;
297 
298   unsigned LoOffset = Offset & 0x0000ffff;
299   unsigned HiOffset = (Offset & 0xffff0000) >> 16;
300 
301   // If msb of LoOffset is 1(negative number) we must increment HiOffset
302   // to account for the sign-extension of the low part.
303   if (LoOffset & 0x8000)
304     HiOffset++;
305 
306   // Generate the base address in ATReg.
307   emitRI(Mips::LUi, ATReg, HiOffset, IDLoc, STI);
308   if (BaseReg != Mips::ZERO)
309     emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
310   // Emit the store with the adjusted base and offset.
311   emitRRI(Opcode, SrcReg, ATReg, LoOffset, IDLoc, STI);
312 }
313 
314 /// Emit a store instruction with an symbol offset. Symbols are assumed to be
315 /// out of range for a simm16 will be expanded to appropriate instructions.
316 void MipsTargetStreamer::emitStoreWithSymOffset(
317     unsigned Opcode, unsigned SrcReg, unsigned BaseReg, MCOperand &HiOperand,
318     MCOperand &LoOperand, unsigned ATReg, SMLoc IDLoc,
319     const MCSubtargetInfo *STI) {
320   // sw $8, sym => lui $at, %hi(sym)
321   //               sw $8, %lo(sym)($at)
322 
323   // Generate the base address in ATReg.
324   emitRX(Mips::LUi, ATReg, HiOperand, IDLoc, STI);
325   if (BaseReg != Mips::ZERO)
326     emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
327   // Emit the store with the adjusted base and offset.
328   emitRRX(Opcode, SrcReg, ATReg, LoOperand, IDLoc, STI);
329 }
330 
331 /// Emit a load instruction with an immediate offset. DstReg and TmpReg are
332 /// permitted to be the same register iff DstReg is distinct from BaseReg and
333 /// DstReg is a GPR. It is the callers responsibility to identify such cases
334 /// and pass the appropriate register in TmpReg.
335 void MipsTargetStreamer::emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg,
336                                                unsigned BaseReg, int64_t Offset,
337                                                unsigned TmpReg, SMLoc IDLoc,
338                                                const MCSubtargetInfo *STI) {
339   if (isInt<16>(Offset)) {
340     emitRRI(Opcode, DstReg, BaseReg, Offset, IDLoc, STI);
341     return;
342   }
343 
344   // 1) lw $8, offset($9) => lui $8, %hi(offset)
345   //                         add $8, $8, $9
346   //                         lw $8, %lo(offset)($9)
347   // 2) lw $8, offset($8) => lui $at, %hi(offset)
348   //                         add $at, $at, $8
349   //                         lw $8, %lo(offset)($at)
350 
351   unsigned LoOffset = Offset & 0x0000ffff;
352   unsigned HiOffset = (Offset & 0xffff0000) >> 16;
353 
354   // If msb of LoOffset is 1(negative number) we must increment HiOffset
355   // to account for the sign-extension of the low part.
356   if (LoOffset & 0x8000)
357     HiOffset++;
358 
359   // Generate the base address in TmpReg.
360   emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI);
361   if (BaseReg != Mips::ZERO)
362     emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
363   // Emit the load with the adjusted base and offset.
364   emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI);
365 }
366 
367 /// Emit a load instruction with an symbol offset. Symbols are assumed to be
368 /// out of range for a simm16 will be expanded to appropriate instructions.
369 /// DstReg and TmpReg are permitted to be the same register iff DstReg is a
370 /// GPR. It is the callers responsibility to identify such cases and pass the
371 /// appropriate register in TmpReg.
372 void MipsTargetStreamer::emitLoadWithSymOffset(unsigned Opcode, unsigned DstReg,
373                                                unsigned BaseReg,
374                                                MCOperand &HiOperand,
375                                                MCOperand &LoOperand,
376                                                unsigned TmpReg, SMLoc IDLoc,
377                                                const MCSubtargetInfo *STI) {
378   // 1) lw $8, sym        => lui $8, %hi(sym)
379   //                         lw $8, %lo(sym)($8)
380   // 2) ldc1 $f0, sym     => lui $at, %hi(sym)
381   //                         ldc1 $f0, %lo(sym)($at)
382 
383   // Generate the base address in TmpReg.
384   emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI);
385   if (BaseReg != Mips::ZERO)
386     emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
387   // Emit the load with the adjusted base and offset.
388   emitRRX(Opcode, DstReg, TmpReg, LoOperand, IDLoc, STI);
389 }
390 
391 MipsTargetAsmStreamer::MipsTargetAsmStreamer(MCStreamer &S,
392                                              formatted_raw_ostream &OS)
393     : MipsTargetStreamer(S), OS(OS) {}
394 
395 void MipsTargetAsmStreamer::emitDirectiveSetMicroMips() {
396   OS << "\t.set\tmicromips\n";
397   forbidModuleDirective();
398 }
399 
400 void MipsTargetAsmStreamer::emitDirectiveSetNoMicroMips() {
401   OS << "\t.set\tnomicromips\n";
402   forbidModuleDirective();
403 }
404 
405 void MipsTargetAsmStreamer::emitDirectiveSetMips16() {
406   OS << "\t.set\tmips16\n";
407   forbidModuleDirective();
408 }
409 
410 void MipsTargetAsmStreamer::emitDirectiveSetNoMips16() {
411   OS << "\t.set\tnomips16\n";
412   MipsTargetStreamer::emitDirectiveSetNoMips16();
413 }
414 
415 void MipsTargetAsmStreamer::emitDirectiveSetReorder() {
416   OS << "\t.set\treorder\n";
417   MipsTargetStreamer::emitDirectiveSetReorder();
418 }
419 
420 void MipsTargetAsmStreamer::emitDirectiveSetNoReorder() {
421   OS << "\t.set\tnoreorder\n";
422   forbidModuleDirective();
423 }
424 
425 void MipsTargetAsmStreamer::emitDirectiveSetMacro() {
426   OS << "\t.set\tmacro\n";
427   MipsTargetStreamer::emitDirectiveSetMacro();
428 }
429 
430 void MipsTargetAsmStreamer::emitDirectiveSetNoMacro() {
431   OS << "\t.set\tnomacro\n";
432   MipsTargetStreamer::emitDirectiveSetNoMacro();
433 }
434 
435 void MipsTargetAsmStreamer::emitDirectiveSetMsa() {
436   OS << "\t.set\tmsa\n";
437   MipsTargetStreamer::emitDirectiveSetMsa();
438 }
439 
440 void MipsTargetAsmStreamer::emitDirectiveSetNoMsa() {
441   OS << "\t.set\tnomsa\n";
442   MipsTargetStreamer::emitDirectiveSetNoMsa();
443 }
444 
445 void MipsTargetAsmStreamer::emitDirectiveSetMt() {
446   OS << "\t.set\tmt\n";
447   MipsTargetStreamer::emitDirectiveSetMt();
448 }
449 
450 void MipsTargetAsmStreamer::emitDirectiveSetNoMt() {
451   OS << "\t.set\tnomt\n";
452   MipsTargetStreamer::emitDirectiveSetNoMt();
453 }
454 
455 void MipsTargetAsmStreamer::emitDirectiveSetCRC() {
456   OS << "\t.set\tcrc\n";
457   MipsTargetStreamer::emitDirectiveSetCRC();
458 }
459 
460 void MipsTargetAsmStreamer::emitDirectiveSetNoCRC() {
461   OS << "\t.set\tnocrc\n";
462   MipsTargetStreamer::emitDirectiveSetNoCRC();
463 }
464 
465 void MipsTargetAsmStreamer::emitDirectiveSetVirt() {
466   OS << "\t.set\tvirt\n";
467   MipsTargetStreamer::emitDirectiveSetVirt();
468 }
469 
470 void MipsTargetAsmStreamer::emitDirectiveSetNoVirt() {
471   OS << "\t.set\tnovirt\n";
472   MipsTargetStreamer::emitDirectiveSetNoVirt();
473 }
474 
475 void MipsTargetAsmStreamer::emitDirectiveSetGINV() {
476   OS << "\t.set\tginv\n";
477   MipsTargetStreamer::emitDirectiveSetGINV();
478 }
479 
480 void MipsTargetAsmStreamer::emitDirectiveSetNoGINV() {
481   OS << "\t.set\tnoginv\n";
482   MipsTargetStreamer::emitDirectiveSetNoGINV();
483 }
484 
485 void MipsTargetAsmStreamer::emitDirectiveSetAt() {
486   OS << "\t.set\tat\n";
487   MipsTargetStreamer::emitDirectiveSetAt();
488 }
489 
490 void MipsTargetAsmStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
491   OS << "\t.set\tat=$" << Twine(RegNo) << "\n";
492   MipsTargetStreamer::emitDirectiveSetAtWithArg(RegNo);
493 }
494 
495 void MipsTargetAsmStreamer::emitDirectiveSetNoAt() {
496   OS << "\t.set\tnoat\n";
497   MipsTargetStreamer::emitDirectiveSetNoAt();
498 }
499 
500 void MipsTargetAsmStreamer::emitDirectiveEnd(StringRef Name) {
501   OS << "\t.end\t" << Name << '\n';
502 }
503 
504 void MipsTargetAsmStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
505   OS << "\t.ent\t" << Symbol.getName() << '\n';
506 }
507 
508 void MipsTargetAsmStreamer::emitDirectiveAbiCalls() { OS << "\t.abicalls\n"; }
509 
510 void MipsTargetAsmStreamer::emitDirectiveNaN2008() { OS << "\t.nan\t2008\n"; }
511 
512 void MipsTargetAsmStreamer::emitDirectiveNaNLegacy() {
513   OS << "\t.nan\tlegacy\n";
514 }
515 
516 void MipsTargetAsmStreamer::emitDirectiveOptionPic0() {
517   OS << "\t.option\tpic0\n";
518 }
519 
520 void MipsTargetAsmStreamer::emitDirectiveOptionPic2() {
521   OS << "\t.option\tpic2\n";
522 }
523 
524 void MipsTargetAsmStreamer::emitDirectiveInsn() {
525   MipsTargetStreamer::emitDirectiveInsn();
526   OS << "\t.insn\n";
527 }
528 
529 void MipsTargetAsmStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
530                                       unsigned ReturnReg) {
531   OS << "\t.frame\t$"
532      << StringRef(MipsInstPrinter::getRegisterName(StackReg)).lower() << ","
533      << StackSize << ",$"
534      << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n';
535 }
536 
537 void MipsTargetAsmStreamer::emitDirectiveSetArch(StringRef Arch) {
538   OS << "\t.set arch=" << Arch << "\n";
539   MipsTargetStreamer::emitDirectiveSetArch(Arch);
540 }
541 
542 void MipsTargetAsmStreamer::emitDirectiveSetMips0() {
543   OS << "\t.set\tmips0\n";
544   MipsTargetStreamer::emitDirectiveSetMips0();
545 }
546 
547 void MipsTargetAsmStreamer::emitDirectiveSetMips1() {
548   OS << "\t.set\tmips1\n";
549   MipsTargetStreamer::emitDirectiveSetMips1();
550 }
551 
552 void MipsTargetAsmStreamer::emitDirectiveSetMips2() {
553   OS << "\t.set\tmips2\n";
554   MipsTargetStreamer::emitDirectiveSetMips2();
555 }
556 
557 void MipsTargetAsmStreamer::emitDirectiveSetMips3() {
558   OS << "\t.set\tmips3\n";
559   MipsTargetStreamer::emitDirectiveSetMips3();
560 }
561 
562 void MipsTargetAsmStreamer::emitDirectiveSetMips4() {
563   OS << "\t.set\tmips4\n";
564   MipsTargetStreamer::emitDirectiveSetMips4();
565 }
566 
567 void MipsTargetAsmStreamer::emitDirectiveSetMips5() {
568   OS << "\t.set\tmips5\n";
569   MipsTargetStreamer::emitDirectiveSetMips5();
570 }
571 
572 void MipsTargetAsmStreamer::emitDirectiveSetMips32() {
573   OS << "\t.set\tmips32\n";
574   MipsTargetStreamer::emitDirectiveSetMips32();
575 }
576 
577 void MipsTargetAsmStreamer::emitDirectiveSetMips32R2() {
578   OS << "\t.set\tmips32r2\n";
579   MipsTargetStreamer::emitDirectiveSetMips32R2();
580 }
581 
582 void MipsTargetAsmStreamer::emitDirectiveSetMips32R3() {
583   OS << "\t.set\tmips32r3\n";
584   MipsTargetStreamer::emitDirectiveSetMips32R3();
585 }
586 
587 void MipsTargetAsmStreamer::emitDirectiveSetMips32R5() {
588   OS << "\t.set\tmips32r5\n";
589   MipsTargetStreamer::emitDirectiveSetMips32R5();
590 }
591 
592 void MipsTargetAsmStreamer::emitDirectiveSetMips32R6() {
593   OS << "\t.set\tmips32r6\n";
594   MipsTargetStreamer::emitDirectiveSetMips32R6();
595 }
596 
597 void MipsTargetAsmStreamer::emitDirectiveSetMips64() {
598   OS << "\t.set\tmips64\n";
599   MipsTargetStreamer::emitDirectiveSetMips64();
600 }
601 
602 void MipsTargetAsmStreamer::emitDirectiveSetMips64R2() {
603   OS << "\t.set\tmips64r2\n";
604   MipsTargetStreamer::emitDirectiveSetMips64R2();
605 }
606 
607 void MipsTargetAsmStreamer::emitDirectiveSetMips64R3() {
608   OS << "\t.set\tmips64r3\n";
609   MipsTargetStreamer::emitDirectiveSetMips64R3();
610 }
611 
612 void MipsTargetAsmStreamer::emitDirectiveSetMips64R5() {
613   OS << "\t.set\tmips64r5\n";
614   MipsTargetStreamer::emitDirectiveSetMips64R5();
615 }
616 
617 void MipsTargetAsmStreamer::emitDirectiveSetMips64R6() {
618   OS << "\t.set\tmips64r6\n";
619   MipsTargetStreamer::emitDirectiveSetMips64R6();
620 }
621 
622 void MipsTargetAsmStreamer::emitDirectiveSetDsp() {
623   OS << "\t.set\tdsp\n";
624   MipsTargetStreamer::emitDirectiveSetDsp();
625 }
626 
627 void MipsTargetAsmStreamer::emitDirectiveSetDspr2() {
628   OS << "\t.set\tdspr2\n";
629   MipsTargetStreamer::emitDirectiveSetDspr2();
630 }
631 
632 void MipsTargetAsmStreamer::emitDirectiveSetNoDsp() {
633   OS << "\t.set\tnodsp\n";
634   MipsTargetStreamer::emitDirectiveSetNoDsp();
635 }
636 
637 void MipsTargetAsmStreamer::emitDirectiveSetPop() {
638   OS << "\t.set\tpop\n";
639   MipsTargetStreamer::emitDirectiveSetPop();
640 }
641 
642 void MipsTargetAsmStreamer::emitDirectiveSetPush() {
643  OS << "\t.set\tpush\n";
644  MipsTargetStreamer::emitDirectiveSetPush();
645 }
646 
647 void MipsTargetAsmStreamer::emitDirectiveSetSoftFloat() {
648   OS << "\t.set\tsoftfloat\n";
649   MipsTargetStreamer::emitDirectiveSetSoftFloat();
650 }
651 
652 void MipsTargetAsmStreamer::emitDirectiveSetHardFloat() {
653   OS << "\t.set\thardfloat\n";
654   MipsTargetStreamer::emitDirectiveSetHardFloat();
655 }
656 
657 // Print a 32 bit hex number with all numbers.
658 static void printHex32(unsigned Value, raw_ostream &OS) {
659   OS << "0x";
660   for (int i = 7; i >= 0; i--)
661     OS.write_hex((Value & (0xF << (i * 4))) >> (i * 4));
662 }
663 
664 void MipsTargetAsmStreamer::emitMask(unsigned CPUBitmask,
665                                      int CPUTopSavedRegOff) {
666   OS << "\t.mask \t";
667   printHex32(CPUBitmask, OS);
668   OS << ',' << CPUTopSavedRegOff << '\n';
669 }
670 
671 void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask,
672                                       int FPUTopSavedRegOff) {
673   OS << "\t.fmask\t";
674   printHex32(FPUBitmask, OS);
675   OS << "," << FPUTopSavedRegOff << '\n';
676 }
677 
678 void MipsTargetAsmStreamer::emitDirectiveCpLoad(unsigned RegNo) {
679   OS << "\t.cpload\t$"
680      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
681   forbidModuleDirective();
682 }
683 
684 void MipsTargetAsmStreamer::emitDirectiveCpLocal(unsigned RegNo) {
685   OS << "\t.cplocal\t$"
686      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
687   MipsTargetStreamer::emitDirectiveCpLocal(RegNo);
688 }
689 
690 bool MipsTargetAsmStreamer::emitDirectiveCpRestore(
691     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
692     const MCSubtargetInfo *STI) {
693   MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
694   OS << "\t.cprestore\t" << Offset << "\n";
695   return true;
696 }
697 
698 void MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned RegNo,
699                                                  int RegOrOffset,
700                                                  const MCSymbol &Sym,
701                                                  bool IsReg) {
702   OS << "\t.cpsetup\t$"
703      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << ", ";
704 
705   if (IsReg)
706     OS << "$"
707        << StringRef(MipsInstPrinter::getRegisterName(RegOrOffset)).lower();
708   else
709     OS << RegOrOffset;
710 
711   OS << ", ";
712 
713   OS << Sym.getName();
714   forbidModuleDirective();
715 }
716 
717 void MipsTargetAsmStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
718                                                   bool SaveLocationIsRegister) {
719   OS << "\t.cpreturn";
720   forbidModuleDirective();
721 }
722 
723 void MipsTargetAsmStreamer::emitDirectiveModuleFP() {
724   MipsABIFlagsSection::FpABIKind FpABI = ABIFlagsSection.getFpABI();
725   if (FpABI == MipsABIFlagsSection::FpABIKind::SOFT)
726     OS << "\t.module\tsoftfloat\n";
727   else
728     OS << "\t.module\tfp=" << ABIFlagsSection.getFpABIString(FpABI) << "\n";
729 }
730 
731 void MipsTargetAsmStreamer::emitDirectiveSetFp(
732     MipsABIFlagsSection::FpABIKind Value) {
733   MipsTargetStreamer::emitDirectiveSetFp(Value);
734 
735   OS << "\t.set\tfp=";
736   OS << ABIFlagsSection.getFpABIString(Value) << "\n";
737 }
738 
739 void MipsTargetAsmStreamer::emitDirectiveModuleOddSPReg() {
740   MipsTargetStreamer::emitDirectiveModuleOddSPReg();
741 
742   OS << "\t.module\t" << (ABIFlagsSection.OddSPReg ? "" : "no") << "oddspreg\n";
743 }
744 
745 void MipsTargetAsmStreamer::emitDirectiveSetOddSPReg() {
746   MipsTargetStreamer::emitDirectiveSetOddSPReg();
747   OS << "\t.set\toddspreg\n";
748 }
749 
750 void MipsTargetAsmStreamer::emitDirectiveSetNoOddSPReg() {
751   MipsTargetStreamer::emitDirectiveSetNoOddSPReg();
752   OS << "\t.set\tnooddspreg\n";
753 }
754 
755 void MipsTargetAsmStreamer::emitDirectiveModuleSoftFloat() {
756   OS << "\t.module\tsoftfloat\n";
757 }
758 
759 void MipsTargetAsmStreamer::emitDirectiveModuleHardFloat() {
760   OS << "\t.module\thardfloat\n";
761 }
762 
763 void MipsTargetAsmStreamer::emitDirectiveModuleMT() {
764   OS << "\t.module\tmt\n";
765 }
766 
767 void MipsTargetAsmStreamer::emitDirectiveModuleCRC() {
768   OS << "\t.module\tcrc\n";
769 }
770 
771 void MipsTargetAsmStreamer::emitDirectiveModuleNoCRC() {
772   OS << "\t.module\tnocrc\n";
773 }
774 
775 void MipsTargetAsmStreamer::emitDirectiveModuleVirt() {
776   OS << "\t.module\tvirt\n";
777 }
778 
779 void MipsTargetAsmStreamer::emitDirectiveModuleNoVirt() {
780   OS << "\t.module\tnovirt\n";
781 }
782 
783 void MipsTargetAsmStreamer::emitDirectiveModuleGINV() {
784   OS << "\t.module\tginv\n";
785 }
786 
787 void MipsTargetAsmStreamer::emitDirectiveModuleNoGINV() {
788   OS << "\t.module\tnoginv\n";
789 }
790 
791 // This part is for ELF object output.
792 MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
793                                              const MCSubtargetInfo &STI)
794     : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
795   MCAssembler &MCA = getStreamer().getAssembler();
796 
797   // It's possible that MCObjectFileInfo isn't fully initialized at this point
798   // due to an initialization order problem where LLVMTargetMachine creates the
799   // target streamer before TargetLoweringObjectFile calls
800   // InitializeMCObjectFileInfo. There doesn't seem to be a single place that
801   // covers all cases so this statement covers most cases and direct object
802   // emission must call setPic() once MCObjectFileInfo has been initialized. The
803   // cases we don't handle here are covered by MipsAsmPrinter.
804   Pic = MCA.getContext().getObjectFileInfo()->isPositionIndependent();
805 
806   const FeatureBitset &Features = STI.getFeatureBits();
807 
808   // Set the header flags that we can in the constructor.
809   // FIXME: This is a fairly terrible hack. We set the rest
810   // of these in the destructor. The problem here is two-fold:
811   //
812   // a: Some of the eflags can be set/reset by directives.
813   // b: There aren't any usage paths that initialize the ABI
814   //    pointer until after we initialize either an assembler
815   //    or the target machine.
816   // We can fix this by making the target streamer construct
817   // the ABI, but this is fraught with wide ranging dependency
818   // issues as well.
819   unsigned EFlags = MCA.getELFHeaderEFlags();
820 
821   // FIXME: Fix a dependency issue by instantiating the ABI object to some
822   // default based off the triple. The triple doesn't describe the target
823   // fully, but any external user of the API that uses the MCTargetStreamer
824   // would otherwise crash on assertion failure.
825 
826   ABI = MipsABIInfo(
827       STI.getTargetTriple().getArch() == Triple::ArchType::mipsel ||
828               STI.getTargetTriple().getArch() == Triple::ArchType::mips
829           ? MipsABIInfo::O32()
830           : MipsABIInfo::N64());
831 
832   // Architecture
833   if (Features[Mips::FeatureMips64r6])
834     EFlags |= ELF::EF_MIPS_ARCH_64R6;
835   else if (Features[Mips::FeatureMips64r2] ||
836            Features[Mips::FeatureMips64r3] ||
837            Features[Mips::FeatureMips64r5])
838     EFlags |= ELF::EF_MIPS_ARCH_64R2;
839   else if (Features[Mips::FeatureMips64])
840     EFlags |= ELF::EF_MIPS_ARCH_64;
841   else if (Features[Mips::FeatureMips5])
842     EFlags |= ELF::EF_MIPS_ARCH_5;
843   else if (Features[Mips::FeatureMips4])
844     EFlags |= ELF::EF_MIPS_ARCH_4;
845   else if (Features[Mips::FeatureMips3])
846     EFlags |= ELF::EF_MIPS_ARCH_3;
847   else if (Features[Mips::FeatureMips32r6])
848     EFlags |= ELF::EF_MIPS_ARCH_32R6;
849   else if (Features[Mips::FeatureMips32r2] ||
850            Features[Mips::FeatureMips32r3] ||
851            Features[Mips::FeatureMips32r5])
852     EFlags |= ELF::EF_MIPS_ARCH_32R2;
853   else if (Features[Mips::FeatureMips32])
854     EFlags |= ELF::EF_MIPS_ARCH_32;
855   else if (Features[Mips::FeatureMips2])
856     EFlags |= ELF::EF_MIPS_ARCH_2;
857   else
858     EFlags |= ELF::EF_MIPS_ARCH_1;
859 
860   // Machine
861   if (Features[Mips::FeatureCnMips])
862     EFlags |= ELF::EF_MIPS_MACH_OCTEON;
863 
864   // Other options.
865   if (Features[Mips::FeatureNaN2008])
866     EFlags |= ELF::EF_MIPS_NAN2008;
867 
868   MCA.setELFHeaderEFlags(EFlags);
869 }
870 
871 void MipsTargetELFStreamer::emitLabel(MCSymbol *S) {
872   auto *Symbol = cast<MCSymbolELF>(S);
873   getStreamer().getAssembler().registerSymbol(*Symbol);
874   uint8_t Type = Symbol->getType();
875   if (Type != ELF::STT_FUNC)
876     return;
877 
878   if (isMicroMipsEnabled())
879     Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
880 }
881 
882 void MipsTargetELFStreamer::finish() {
883   MCAssembler &MCA = getStreamer().getAssembler();
884   const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo();
885 
886   // .bss, .text and .data are always at least 16-byte aligned.
887   MCSection &TextSection = *OFI.getTextSection();
888   MCA.registerSection(TextSection);
889   MCSection &DataSection = *OFI.getDataSection();
890   MCA.registerSection(DataSection);
891   MCSection &BSSSection = *OFI.getBSSSection();
892   MCA.registerSection(BSSSection);
893 
894   TextSection.setAlignment(std::max(16u, TextSection.getAlignment()));
895   DataSection.setAlignment(std::max(16u, DataSection.getAlignment()));
896   BSSSection.setAlignment(std::max(16u, BSSSection.getAlignment()));
897 
898   if (RoundSectionSizes) {
899     // Make sections sizes a multiple of the alignment. This is useful for
900     // verifying the output of IAS against the output of other assemblers but
901     // it's not necessary to produce a correct object and increases section
902     // size.
903     MCStreamer &OS = getStreamer();
904     for (MCSection &S : MCA) {
905       MCSectionELF &Section = static_cast<MCSectionELF &>(S);
906 
907       unsigned Alignment = Section.getAlignment();
908       if (Alignment) {
909         OS.SwitchSection(&Section);
910         if (Section.UseCodeAlign())
911           OS.EmitCodeAlignment(Alignment, Alignment);
912         else
913           OS.EmitValueToAlignment(Alignment, 0, 1, Alignment);
914       }
915     }
916   }
917 
918   const FeatureBitset &Features = STI.getFeatureBits();
919 
920   // Update e_header flags. See the FIXME and comment above in
921   // the constructor for a full rundown on this.
922   unsigned EFlags = MCA.getELFHeaderEFlags();
923 
924   // ABI
925   // N64 does not require any ABI bits.
926   if (getABI().IsO32())
927     EFlags |= ELF::EF_MIPS_ABI_O32;
928   else if (getABI().IsN32())
929     EFlags |= ELF::EF_MIPS_ABI2;
930 
931   if (Features[Mips::FeatureGP64Bit]) {
932     if (getABI().IsO32())
933       EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
934   } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
935     EFlags |= ELF::EF_MIPS_32BITMODE;
936 
937   // -mplt is not implemented but we should act as if it was
938   // given.
939   if (!Features[Mips::FeatureNoABICalls])
940     EFlags |= ELF::EF_MIPS_CPIC;
941 
942   if (Pic)
943     EFlags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
944 
945   MCA.setELFHeaderEFlags(EFlags);
946 
947   // Emit all the option records.
948   // At the moment we are only emitting .Mips.options (ODK_REGINFO) and
949   // .reginfo.
950   MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
951   MEF.EmitMipsOptionRecords();
952 
953   emitMipsAbiFlags();
954 }
955 
956 void MipsTargetELFStreamer::emitAssignment(MCSymbol *S, const MCExpr *Value) {
957   auto *Symbol = cast<MCSymbolELF>(S);
958   // If on rhs is micromips symbol then mark Symbol as microMips.
959   if (Value->getKind() != MCExpr::SymbolRef)
960     return;
961   const auto &RhsSym = cast<MCSymbolELF>(
962       static_cast<const MCSymbolRefExpr *>(Value)->getSymbol());
963 
964   if (!(RhsSym.getOther() & ELF::STO_MIPS_MICROMIPS))
965     return;
966 
967   Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
968 }
969 
970 MCELFStreamer &MipsTargetELFStreamer::getStreamer() {
971   return static_cast<MCELFStreamer &>(Streamer);
972 }
973 
974 void MipsTargetELFStreamer::emitDirectiveSetMicroMips() {
975   MicroMipsEnabled = true;
976   forbidModuleDirective();
977 }
978 
979 void MipsTargetELFStreamer::emitDirectiveSetNoMicroMips() {
980   MicroMipsEnabled = false;
981   forbidModuleDirective();
982 }
983 
984 void MipsTargetELFStreamer::setUsesMicroMips() {
985   MCAssembler &MCA = getStreamer().getAssembler();
986   unsigned Flags = MCA.getELFHeaderEFlags();
987   Flags |= ELF::EF_MIPS_MICROMIPS;
988   MCA.setELFHeaderEFlags(Flags);
989 }
990 
991 void MipsTargetELFStreamer::emitDirectiveSetMips16() {
992   MCAssembler &MCA = getStreamer().getAssembler();
993   unsigned Flags = MCA.getELFHeaderEFlags();
994   Flags |= ELF::EF_MIPS_ARCH_ASE_M16;
995   MCA.setELFHeaderEFlags(Flags);
996   forbidModuleDirective();
997 }
998 
999 void MipsTargetELFStreamer::emitDirectiveSetNoReorder() {
1000   MCAssembler &MCA = getStreamer().getAssembler();
1001   unsigned Flags = MCA.getELFHeaderEFlags();
1002   Flags |= ELF::EF_MIPS_NOREORDER;
1003   MCA.setELFHeaderEFlags(Flags);
1004   forbidModuleDirective();
1005 }
1006 
1007 void MipsTargetELFStreamer::emitDirectiveEnd(StringRef Name) {
1008   MCAssembler &MCA = getStreamer().getAssembler();
1009   MCContext &Context = MCA.getContext();
1010   MCStreamer &OS = getStreamer();
1011 
1012   MCSectionELF *Sec = Context.getELFSection(".pdr", ELF::SHT_PROGBITS, 0);
1013 
1014   MCSymbol *Sym = Context.getOrCreateSymbol(Name);
1015   const MCSymbolRefExpr *ExprRef =
1016       MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Context);
1017 
1018   MCA.registerSection(*Sec);
1019   Sec->setAlignment(4);
1020 
1021   OS.PushSection();
1022 
1023   OS.SwitchSection(Sec);
1024 
1025   OS.EmitValueImpl(ExprRef, 4);
1026 
1027   OS.EmitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask
1028   OS.EmitIntValue(GPRInfoSet ? GPROffset : 0, 4);  // reg_offset
1029 
1030   OS.EmitIntValue(FPRInfoSet ? FPRBitMask : 0, 4); // fpreg_mask
1031   OS.EmitIntValue(FPRInfoSet ? FPROffset : 0, 4);  // fpreg_offset
1032 
1033   OS.EmitIntValue(FrameInfoSet ? FrameOffset : 0, 4); // frame_offset
1034   OS.EmitIntValue(FrameInfoSet ? FrameReg : 0, 4);    // frame_reg
1035   OS.EmitIntValue(FrameInfoSet ? ReturnReg : 0, 4);   // return_reg
1036 
1037   // The .end directive marks the end of a procedure. Invalidate
1038   // the information gathered up until this point.
1039   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1040 
1041   OS.PopSection();
1042 
1043   // .end also implicitly sets the size.
1044   MCSymbol *CurPCSym = Context.createTempSymbol();
1045   OS.EmitLabel(CurPCSym);
1046   const MCExpr *Size = MCBinaryExpr::createSub(
1047       MCSymbolRefExpr::create(CurPCSym, MCSymbolRefExpr::VK_None, Context),
1048       ExprRef, Context);
1049 
1050   // The ELFObjectWriter can determine the absolute size as it has access to
1051   // the layout information of the assembly file, so a size expression rather
1052   // than an absolute value is ok here.
1053   static_cast<MCSymbolELF *>(Sym)->setSize(Size);
1054 }
1055 
1056 void MipsTargetELFStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
1057   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1058 
1059   // .ent also acts like an implicit '.type symbol, STT_FUNC'
1060   static_cast<const MCSymbolELF &>(Symbol).setType(ELF::STT_FUNC);
1061 }
1062 
1063 void MipsTargetELFStreamer::emitDirectiveAbiCalls() {
1064   MCAssembler &MCA = getStreamer().getAssembler();
1065   unsigned Flags = MCA.getELFHeaderEFlags();
1066   Flags |= ELF::EF_MIPS_CPIC | ELF::EF_MIPS_PIC;
1067   MCA.setELFHeaderEFlags(Flags);
1068 }
1069 
1070 void MipsTargetELFStreamer::emitDirectiveNaN2008() {
1071   MCAssembler &MCA = getStreamer().getAssembler();
1072   unsigned Flags = MCA.getELFHeaderEFlags();
1073   Flags |= ELF::EF_MIPS_NAN2008;
1074   MCA.setELFHeaderEFlags(Flags);
1075 }
1076 
1077 void MipsTargetELFStreamer::emitDirectiveNaNLegacy() {
1078   MCAssembler &MCA = getStreamer().getAssembler();
1079   unsigned Flags = MCA.getELFHeaderEFlags();
1080   Flags &= ~ELF::EF_MIPS_NAN2008;
1081   MCA.setELFHeaderEFlags(Flags);
1082 }
1083 
1084 void MipsTargetELFStreamer::emitDirectiveOptionPic0() {
1085   MCAssembler &MCA = getStreamer().getAssembler();
1086   unsigned Flags = MCA.getELFHeaderEFlags();
1087   // This option overrides other PIC options like -KPIC.
1088   Pic = false;
1089   Flags &= ~ELF::EF_MIPS_PIC;
1090   MCA.setELFHeaderEFlags(Flags);
1091 }
1092 
1093 void MipsTargetELFStreamer::emitDirectiveOptionPic2() {
1094   MCAssembler &MCA = getStreamer().getAssembler();
1095   unsigned Flags = MCA.getELFHeaderEFlags();
1096   Pic = true;
1097   // NOTE: We are following the GAS behaviour here which means the directive
1098   // 'pic2' also sets the CPIC bit in the ELF header. This is different from
1099   // what is stated in the SYSV ABI which consider the bits EF_MIPS_PIC and
1100   // EF_MIPS_CPIC to be mutually exclusive.
1101   Flags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
1102   MCA.setELFHeaderEFlags(Flags);
1103 }
1104 
1105 void MipsTargetELFStreamer::emitDirectiveInsn() {
1106   MipsTargetStreamer::emitDirectiveInsn();
1107   MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
1108   MEF.createPendingLabelRelocs();
1109 }
1110 
1111 void MipsTargetELFStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
1112                                       unsigned ReturnReg_) {
1113   MCContext &Context = getStreamer().getAssembler().getContext();
1114   const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
1115 
1116   FrameInfoSet = true;
1117   FrameReg = RegInfo->getEncodingValue(StackReg);
1118   FrameOffset = StackSize;
1119   ReturnReg = RegInfo->getEncodingValue(ReturnReg_);
1120 }
1121 
1122 void MipsTargetELFStreamer::emitMask(unsigned CPUBitmask,
1123                                      int CPUTopSavedRegOff) {
1124   GPRInfoSet = true;
1125   GPRBitMask = CPUBitmask;
1126   GPROffset = CPUTopSavedRegOff;
1127 }
1128 
1129 void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask,
1130                                       int FPUTopSavedRegOff) {
1131   FPRInfoSet = true;
1132   FPRBitMask = FPUBitmask;
1133   FPROffset = FPUTopSavedRegOff;
1134 }
1135 
1136 void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) {
1137   // .cpload $reg
1138   // This directive expands to:
1139   // lui   $gp, %hi(_gp_disp)
1140   // addui $gp, $gp, %lo(_gp_disp)
1141   // addu  $gp, $gp, $reg
1142   // when support for position independent code is enabled.
1143   if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1144     return;
1145 
1146   // There's a GNU extension controlled by -mno-shared that allows
1147   // locally-binding symbols to be accessed using absolute addresses.
1148   // This is currently not supported. When supported -mno-shared makes
1149   // .cpload expand to:
1150   //   lui     $gp, %hi(__gnu_local_gp)
1151   //   addiu   $gp, $gp, %lo(__gnu_local_gp)
1152 
1153   StringRef SymName("_gp_disp");
1154   MCAssembler &MCA = getStreamer().getAssembler();
1155   MCSymbol *GP_Disp = MCA.getContext().getOrCreateSymbol(SymName);
1156   MCA.registerSymbol(*GP_Disp);
1157 
1158   MCInst TmpInst;
1159   TmpInst.setOpcode(Mips::LUi);
1160   TmpInst.addOperand(MCOperand::createReg(GPReg));
1161   const MCExpr *HiSym = MipsMCExpr::create(
1162       MipsMCExpr::MEK_HI,
1163       MCSymbolRefExpr::create("_gp_disp", MCSymbolRefExpr::VK_None,
1164                               MCA.getContext()),
1165       MCA.getContext());
1166   TmpInst.addOperand(MCOperand::createExpr(HiSym));
1167   getStreamer().EmitInstruction(TmpInst, STI);
1168 
1169   TmpInst.clear();
1170 
1171   TmpInst.setOpcode(Mips::ADDiu);
1172   TmpInst.addOperand(MCOperand::createReg(GPReg));
1173   TmpInst.addOperand(MCOperand::createReg(GPReg));
1174   const MCExpr *LoSym = MipsMCExpr::create(
1175       MipsMCExpr::MEK_LO,
1176       MCSymbolRefExpr::create("_gp_disp", MCSymbolRefExpr::VK_None,
1177                               MCA.getContext()),
1178       MCA.getContext());
1179   TmpInst.addOperand(MCOperand::createExpr(LoSym));
1180   getStreamer().EmitInstruction(TmpInst, STI);
1181 
1182   TmpInst.clear();
1183 
1184   TmpInst.setOpcode(Mips::ADDu);
1185   TmpInst.addOperand(MCOperand::createReg(GPReg));
1186   TmpInst.addOperand(MCOperand::createReg(GPReg));
1187   TmpInst.addOperand(MCOperand::createReg(RegNo));
1188   getStreamer().EmitInstruction(TmpInst, STI);
1189 
1190   forbidModuleDirective();
1191 }
1192 
1193 void MipsTargetELFStreamer::emitDirectiveCpLocal(unsigned RegNo) {
1194   if (Pic)
1195     MipsTargetStreamer::emitDirectiveCpLocal(RegNo);
1196 }
1197 
1198 bool MipsTargetELFStreamer::emitDirectiveCpRestore(
1199     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
1200     const MCSubtargetInfo *STI) {
1201   MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
1202   // .cprestore offset
1203   // When PIC mode is enabled and the O32 ABI is used, this directive expands
1204   // to:
1205   //    sw $gp, offset($sp)
1206   // and adds a corresponding LW after every JAL.
1207 
1208   // Note that .cprestore is ignored if used with the N32 and N64 ABIs or if it
1209   // is used in non-PIC mode.
1210   if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1211     return true;
1212 
1213   // Store the $gp on the stack.
1214   emitStoreWithImmOffset(Mips::SW, GPReg, Mips::SP, Offset, GetATReg, IDLoc,
1215                          STI);
1216   return true;
1217 }
1218 
1219 void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo,
1220                                                  int RegOrOffset,
1221                                                  const MCSymbol &Sym,
1222                                                  bool IsReg) {
1223   // Only N32 and N64 emit anything for .cpsetup iff PIC is set.
1224   if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1225     return;
1226 
1227   forbidModuleDirective();
1228 
1229   MCAssembler &MCA = getStreamer().getAssembler();
1230   MCInst Inst;
1231 
1232   // Either store the old $gp in a register or on the stack
1233   if (IsReg) {
1234     // move $save, $gpreg
1235     emitRRR(Mips::OR64, RegOrOffset, GPReg, Mips::ZERO, SMLoc(), &STI);
1236   } else {
1237     // sd $gpreg, offset($sp)
1238     emitRRI(Mips::SD, GPReg, Mips::SP, RegOrOffset, SMLoc(), &STI);
1239   }
1240 
1241   if (getABI().IsN32()) {
1242     MCSymbol *GPSym = MCA.getContext().getOrCreateSymbol("__gnu_local_gp");
1243     const MipsMCExpr *HiExpr = MipsMCExpr::create(
1244         MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
1245         MCA.getContext());
1246     const MipsMCExpr *LoExpr = MipsMCExpr::create(
1247         MipsMCExpr::MEK_LO, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
1248         MCA.getContext());
1249 
1250     // lui $gp, %hi(__gnu_local_gp)
1251     emitRX(Mips::LUi, GPReg, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1252 
1253     // addiu  $gp, $gp, %lo(__gnu_local_gp)
1254     emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(),
1255             &STI);
1256 
1257     return;
1258   }
1259 
1260   const MipsMCExpr *HiExpr = MipsMCExpr::createGpOff(
1261       MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(&Sym, MCA.getContext()),
1262       MCA.getContext());
1263   const MipsMCExpr *LoExpr = MipsMCExpr::createGpOff(
1264       MipsMCExpr::MEK_LO, MCSymbolRefExpr::create(&Sym, MCA.getContext()),
1265       MCA.getContext());
1266 
1267   // lui $gp, %hi(%neg(%gp_rel(funcSym)))
1268   emitRX(Mips::LUi, GPReg, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1269 
1270   // addiu  $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
1271   emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(),
1272           &STI);
1273 
1274   // daddu  $gp, $gp, $funcreg
1275   emitRRR(Mips::DADDu, GPReg, GPReg, RegNo, SMLoc(), &STI);
1276 }
1277 
1278 void MipsTargetELFStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
1279                                                   bool SaveLocationIsRegister) {
1280   // Only N32 and N64 emit anything for .cpreturn iff PIC is set.
1281   if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1282     return;
1283 
1284   MCInst Inst;
1285   // Either restore the old $gp from a register or on the stack
1286   if (SaveLocationIsRegister) {
1287     Inst.setOpcode(Mips::OR);
1288     Inst.addOperand(MCOperand::createReg(GPReg));
1289     Inst.addOperand(MCOperand::createReg(SaveLocation));
1290     Inst.addOperand(MCOperand::createReg(Mips::ZERO));
1291   } else {
1292     Inst.setOpcode(Mips::LD);
1293     Inst.addOperand(MCOperand::createReg(GPReg));
1294     Inst.addOperand(MCOperand::createReg(Mips::SP));
1295     Inst.addOperand(MCOperand::createImm(SaveLocation));
1296   }
1297   getStreamer().EmitInstruction(Inst, STI);
1298 
1299   forbidModuleDirective();
1300 }
1301 
1302 void MipsTargetELFStreamer::emitMipsAbiFlags() {
1303   MCAssembler &MCA = getStreamer().getAssembler();
1304   MCContext &Context = MCA.getContext();
1305   MCStreamer &OS = getStreamer();
1306   MCSectionELF *Sec = Context.getELFSection(
1307       ".MIPS.abiflags", ELF::SHT_MIPS_ABIFLAGS, ELF::SHF_ALLOC, 24, "");
1308   MCA.registerSection(*Sec);
1309   Sec->setAlignment(8);
1310   OS.SwitchSection(Sec);
1311 
1312   OS << ABIFlagsSection;
1313 }
1314