1 //===-- MipsMCTargetDesc.h - Mips Target Descriptions -----------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides Mips specific target descriptions. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H 14 #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H 15 16 #include "llvm/Support/DataTypes.h" 17 18 #include <memory> 19 20 namespace llvm { 21 class MCAsmBackend; 22 class MCCodeEmitter; 23 class MCContext; 24 class MCInstrInfo; 25 class MCObjectTargetWriter; 26 class MCRegisterInfo; 27 class MCSubtargetInfo; 28 class MCTargetOptions; 29 class StringRef; 30 class Target; 31 class Triple; 32 33 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, 34 const MCRegisterInfo &MRI, 35 MCContext &Ctx); 36 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, 37 const MCRegisterInfo &MRI, 38 MCContext &Ctx); 39 40 MCAsmBackend *createMipsAsmBackend(const Target &T, const MCSubtargetInfo &STI, 41 const MCRegisterInfo &MRI, 42 const MCTargetOptions &Options); 43 44 std::unique_ptr<MCObjectTargetWriter> 45 createMipsELFObjectWriter(const Triple &TT, bool IsN32); 46 47 namespace MIPS_MC { 48 StringRef selectMipsCPU(const Triple &TT, StringRef CPU); 49 } 50 51 } // End llvm namespace 52 53 // Defines symbolic names for Mips registers. This defines a mapping from 54 // register name to register number. 55 #define GET_REGINFO_ENUM 56 #include "MipsGenRegisterInfo.inc" 57 58 // Defines symbolic names for the Mips instructions. 59 #define GET_INSTRINFO_ENUM 60 #include "MipsGenInstrInfo.inc" 61 62 #define GET_SUBTARGETINFO_ENUM 63 #include "MipsGenSubtargetInfo.inc" 64 65 #endif 66