10b57cec5SDimitry Andric //===-- MipsMCTargetDesc.h - Mips Target Descriptions -----------*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric // This file provides Mips specific target descriptions. 100b57cec5SDimitry Andric // 110b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric 130b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H 140b57cec5SDimitry Andric #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H 150b57cec5SDimitry Andric 160b57cec5SDimitry Andric #include "llvm/Support/DataTypes.h" 170b57cec5SDimitry Andric 180b57cec5SDimitry Andric #include <memory> 190b57cec5SDimitry Andric 200b57cec5SDimitry Andric namespace llvm { 210b57cec5SDimitry Andric class MCAsmBackend; 220b57cec5SDimitry Andric class MCCodeEmitter; 230b57cec5SDimitry Andric class MCContext; 240b57cec5SDimitry Andric class MCInstrInfo; 250b57cec5SDimitry Andric class MCObjectTargetWriter; 260b57cec5SDimitry Andric class MCRegisterInfo; 270b57cec5SDimitry Andric class MCSubtargetInfo; 280b57cec5SDimitry Andric class MCTargetOptions; 290b57cec5SDimitry Andric class StringRef; 300b57cec5SDimitry Andric class Target; 310b57cec5SDimitry Andric class Triple; 320b57cec5SDimitry Andric 330b57cec5SDimitry Andric MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, 340b57cec5SDimitry Andric MCContext &Ctx); 350b57cec5SDimitry Andric MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, 360b57cec5SDimitry Andric MCContext &Ctx); 370b57cec5SDimitry Andric 380b57cec5SDimitry Andric MCAsmBackend *createMipsAsmBackend(const Target &T, const MCSubtargetInfo &STI, 390b57cec5SDimitry Andric const MCRegisterInfo &MRI, 400b57cec5SDimitry Andric const MCTargetOptions &Options); 410b57cec5SDimitry Andric 420b57cec5SDimitry Andric std::unique_ptr<MCObjectTargetWriter> 430b57cec5SDimitry Andric createMipsELFObjectWriter(const Triple &TT, bool IsN32); 440b57cec5SDimitry Andric 450b57cec5SDimitry Andric namespace MIPS_MC { 460b57cec5SDimitry Andric StringRef selectMipsCPU(const Triple &TT, StringRef CPU); 470b57cec5SDimitry Andric } 480b57cec5SDimitry Andric 490b57cec5SDimitry Andric } // End llvm namespace 500b57cec5SDimitry Andric 510b57cec5SDimitry Andric // Defines symbolic names for Mips registers. This defines a mapping from 520b57cec5SDimitry Andric // register name to register number. 530b57cec5SDimitry Andric #define GET_REGINFO_ENUM 540b57cec5SDimitry Andric #include "MipsGenRegisterInfo.inc" 550b57cec5SDimitry Andric 560b57cec5SDimitry Andric // Defines symbolic names for the Mips instructions. 570b57cec5SDimitry Andric #define GET_INSTRINFO_ENUM 58*753f127fSDimitry Andric #define GET_INSTRINFO_MC_HELPER_DECLS 590b57cec5SDimitry Andric #include "MipsGenInstrInfo.inc" 600b57cec5SDimitry Andric 610b57cec5SDimitry Andric #define GET_SUBTARGETINFO_ENUM 620b57cec5SDimitry Andric #include "MipsGenSubtargetInfo.inc" 630b57cec5SDimitry Andric 640b57cec5SDimitry Andric #endif 65