1 //===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides Mips specific target descriptions. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MipsMCTargetDesc.h" 14 #include "MipsAsmBackend.h" 15 #include "MipsELFStreamer.h" 16 #include "MipsInstPrinter.h" 17 #include "MipsMCAsmInfo.h" 18 #include "MipsMCNaCl.h" 19 #include "MipsTargetStreamer.h" 20 #include "TargetInfo/MipsTargetInfo.h" 21 #include "llvm/ADT/Triple.h" 22 #include "llvm/MC/MCCodeEmitter.h" 23 #include "llvm/MC/MCELFStreamer.h" 24 #include "llvm/MC/MCInstrAnalysis.h" 25 #include "llvm/MC/MCInstrInfo.h" 26 #include "llvm/MC/MCObjectWriter.h" 27 #include "llvm/MC/MCRegisterInfo.h" 28 #include "llvm/MC/MCSubtargetInfo.h" 29 #include "llvm/MC/MCSymbol.h" 30 #include "llvm/MC/MachineLocation.h" 31 #include "llvm/Support/ErrorHandling.h" 32 #include "llvm/Support/FormattedStream.h" 33 #include "llvm/Support/TargetRegistry.h" 34 35 using namespace llvm; 36 37 #define GET_INSTRINFO_MC_DESC 38 #include "MipsGenInstrInfo.inc" 39 40 #define GET_SUBTARGETINFO_MC_DESC 41 #include "MipsGenSubtargetInfo.inc" 42 43 #define GET_REGINFO_MC_DESC 44 #include "MipsGenRegisterInfo.inc" 45 46 /// Select the Mips CPU for the given triple and cpu name. 47 /// FIXME: Merge with the copy in MipsSubtarget.cpp 48 StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) { 49 if (CPU.empty() || CPU == "generic") { 50 if (TT.getSubArch() == llvm::Triple::MipsSubArch_r6) { 51 if (TT.isMIPS32()) 52 CPU = "mips32r6"; 53 else 54 CPU = "mips64r6"; 55 } else { 56 if (TT.isMIPS32()) 57 CPU = "mips32"; 58 else 59 CPU = "mips64"; 60 } 61 } 62 return CPU; 63 } 64 65 static MCInstrInfo *createMipsMCInstrInfo() { 66 MCInstrInfo *X = new MCInstrInfo(); 67 InitMipsMCInstrInfo(X); 68 return X; 69 } 70 71 static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) { 72 MCRegisterInfo *X = new MCRegisterInfo(); 73 InitMipsMCRegisterInfo(X, Mips::RA); 74 return X; 75 } 76 77 static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT, 78 StringRef CPU, StringRef FS) { 79 CPU = MIPS_MC::selectMipsCPU(TT, CPU); 80 return createMipsMCSubtargetInfoImpl(TT, CPU, FS); 81 } 82 83 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, 84 const Triple &TT) { 85 MCAsmInfo *MAI = new MipsMCAsmInfo(TT); 86 87 unsigned SP = MRI.getDwarfRegNum(Mips::SP, true); 88 MCCFIInstruction Inst = MCCFIInstruction::createDefCfaRegister(nullptr, SP); 89 MAI->addInitialFrameState(Inst); 90 91 return MAI; 92 } 93 94 static MCInstPrinter *createMipsMCInstPrinter(const Triple &T, 95 unsigned SyntaxVariant, 96 const MCAsmInfo &MAI, 97 const MCInstrInfo &MII, 98 const MCRegisterInfo &MRI) { 99 return new MipsInstPrinter(MAI, MII, MRI); 100 } 101 102 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context, 103 std::unique_ptr<MCAsmBackend> &&MAB, 104 std::unique_ptr<MCObjectWriter> &&OW, 105 std::unique_ptr<MCCodeEmitter> &&Emitter, 106 bool RelaxAll) { 107 MCStreamer *S; 108 if (!T.isOSNaCl()) 109 S = createMipsELFStreamer(Context, std::move(MAB), std::move(OW), 110 std::move(Emitter), RelaxAll); 111 else 112 S = createMipsNaClELFStreamer(Context, std::move(MAB), std::move(OW), 113 std::move(Emitter), RelaxAll); 114 return S; 115 } 116 117 static MCTargetStreamer *createMipsAsmTargetStreamer(MCStreamer &S, 118 formatted_raw_ostream &OS, 119 MCInstPrinter *InstPrint, 120 bool isVerboseAsm) { 121 return new MipsTargetAsmStreamer(S, OS); 122 } 123 124 static MCTargetStreamer *createMipsNullTargetStreamer(MCStreamer &S) { 125 return new MipsTargetStreamer(S); 126 } 127 128 static MCTargetStreamer * 129 createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { 130 return new MipsTargetELFStreamer(S, STI); 131 } 132 133 namespace { 134 135 class MipsMCInstrAnalysis : public MCInstrAnalysis { 136 public: 137 MipsMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {} 138 139 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, 140 uint64_t &Target) const override { 141 unsigned NumOps = Inst.getNumOperands(); 142 if (NumOps == 0) 143 return false; 144 switch (Info->get(Inst.getOpcode()).OpInfo[NumOps - 1].OperandType) { 145 case MCOI::OPERAND_UNKNOWN: 146 case MCOI::OPERAND_IMMEDIATE: { 147 // j, jal, jalx, jals 148 // Absolute branch within the current 256 MB-aligned region 149 uint64_t Region = Addr & ~uint64_t(0xfffffff); 150 Target = Region + Inst.getOperand(NumOps - 1).getImm(); 151 return true; 152 } 153 case MCOI::OPERAND_PCREL: 154 // b, beq ... 155 Target = Addr + Inst.getOperand(NumOps - 1).getImm(); 156 return true; 157 default: 158 return false; 159 } 160 } 161 }; 162 } 163 164 static MCInstrAnalysis *createMipsMCInstrAnalysis(const MCInstrInfo *Info) { 165 return new MipsMCInstrAnalysis(Info); 166 } 167 168 extern "C" void LLVMInitializeMipsTargetMC() { 169 for (Target *T : {&getTheMipsTarget(), &getTheMipselTarget(), 170 &getTheMips64Target(), &getTheMips64elTarget()}) { 171 // Register the MC asm info. 172 RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo); 173 174 // Register the MC instruction info. 175 TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo); 176 177 // Register the MC register info. 178 TargetRegistry::RegisterMCRegInfo(*T, createMipsMCRegisterInfo); 179 180 // Register the elf streamer. 181 TargetRegistry::RegisterELFStreamer(*T, createMCStreamer); 182 183 // Register the asm target streamer. 184 TargetRegistry::RegisterAsmTargetStreamer(*T, createMipsAsmTargetStreamer); 185 186 TargetRegistry::RegisterNullTargetStreamer(*T, 187 createMipsNullTargetStreamer); 188 189 // Register the MC subtarget info. 190 TargetRegistry::RegisterMCSubtargetInfo(*T, createMipsMCSubtargetInfo); 191 192 // Register the MC instruction analyzer. 193 TargetRegistry::RegisterMCInstrAnalysis(*T, createMipsMCInstrAnalysis); 194 195 // Register the MCInstPrinter. 196 TargetRegistry::RegisterMCInstPrinter(*T, createMipsMCInstPrinter); 197 198 TargetRegistry::RegisterObjectTargetStreamer( 199 *T, createMipsObjectTargetStreamer); 200 201 // Register the asm backend. 202 TargetRegistry::RegisterMCAsmBackend(*T, createMipsAsmBackend); 203 } 204 205 // Register the MC Code Emitter 206 for (Target *T : {&getTheMipsTarget(), &getTheMips64Target()}) 207 TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEB); 208 209 for (Target *T : {&getTheMipselTarget(), &getTheMips64elTarget()}) 210 TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL); 211 } 212