1 //===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides Mips specific target descriptions. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MipsMCTargetDesc.h" 14 #include "MipsAsmBackend.h" 15 #include "MipsBaseInfo.h" 16 #include "MipsELFStreamer.h" 17 #include "MipsInstPrinter.h" 18 #include "MipsMCAsmInfo.h" 19 #include "MipsMCNaCl.h" 20 #include "MipsTargetStreamer.h" 21 #include "TargetInfo/MipsTargetInfo.h" 22 #include "llvm/MC/MCCodeEmitter.h" 23 #include "llvm/MC/MCELFStreamer.h" 24 #include "llvm/MC/MCInstrAnalysis.h" 25 #include "llvm/MC/MCInstrInfo.h" 26 #include "llvm/MC/MCObjectWriter.h" 27 #include "llvm/MC/MCRegisterInfo.h" 28 #include "llvm/MC/MCSubtargetInfo.h" 29 #include "llvm/MC/MCSymbol.h" 30 #include "llvm/MC/MachineLocation.h" 31 #include "llvm/MC/TargetRegistry.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/FormattedStream.h" 34 #include "llvm/TargetParser/Triple.h" 35 36 using namespace llvm; 37 38 #define GET_INSTRINFO_MC_DESC 39 #define ENABLE_INSTR_PREDICATE_VERIFIER 40 #include "MipsGenInstrInfo.inc" 41 42 #define GET_SUBTARGETINFO_MC_DESC 43 #include "MipsGenSubtargetInfo.inc" 44 45 #define GET_REGINFO_MC_DESC 46 #include "MipsGenRegisterInfo.inc" 47 48 /// Select the Mips CPU for the given triple and cpu name. 49 StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) { 50 if (CPU.empty() || CPU == "generic") { 51 if (TT.getSubArch() == llvm::Triple::MipsSubArch_r6) { 52 if (TT.isMIPS32()) 53 CPU = "mips32r6"; 54 else 55 CPU = "mips64r6"; 56 } else { 57 if (TT.isMIPS32()) 58 CPU = "mips32"; 59 else 60 CPU = "mips64"; 61 } 62 } 63 return CPU; 64 } 65 66 static MCInstrInfo *createMipsMCInstrInfo() { 67 MCInstrInfo *X = new MCInstrInfo(); 68 InitMipsMCInstrInfo(X); 69 return X; 70 } 71 72 static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) { 73 MCRegisterInfo *X = new MCRegisterInfo(); 74 InitMipsMCRegisterInfo(X, Mips::RA); 75 return X; 76 } 77 78 static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT, 79 StringRef CPU, StringRef FS) { 80 CPU = MIPS_MC::selectMipsCPU(TT, CPU); 81 return createMipsMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); 82 } 83 84 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, 85 const Triple &TT, 86 const MCTargetOptions &Options) { 87 MCAsmInfo *MAI = new MipsMCAsmInfo(TT, Options); 88 89 unsigned SP = MRI.getDwarfRegNum(Mips::SP, true); 90 MCCFIInstruction Inst = MCCFIInstruction::createDefCfaRegister(nullptr, SP); 91 MAI->addInitialFrameState(Inst); 92 93 return MAI; 94 } 95 96 static MCInstPrinter *createMipsMCInstPrinter(const Triple &T, 97 unsigned SyntaxVariant, 98 const MCAsmInfo &MAI, 99 const MCInstrInfo &MII, 100 const MCRegisterInfo &MRI) { 101 return new MipsInstPrinter(MAI, MII, MRI); 102 } 103 104 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context, 105 std::unique_ptr<MCAsmBackend> &&MAB, 106 std::unique_ptr<MCObjectWriter> &&OW, 107 std::unique_ptr<MCCodeEmitter> &&Emitter, 108 bool RelaxAll) { 109 MCStreamer *S; 110 if (!T.isOSNaCl()) 111 S = createMipsELFStreamer(Context, std::move(MAB), std::move(OW), 112 std::move(Emitter), RelaxAll); 113 else 114 S = createMipsNaClELFStreamer(Context, std::move(MAB), std::move(OW), 115 std::move(Emitter), RelaxAll); 116 return S; 117 } 118 119 static MCTargetStreamer *createMipsAsmTargetStreamer(MCStreamer &S, 120 formatted_raw_ostream &OS, 121 MCInstPrinter *InstPrint, 122 bool isVerboseAsm) { 123 return new MipsTargetAsmStreamer(S, OS); 124 } 125 126 static MCTargetStreamer *createMipsNullTargetStreamer(MCStreamer &S) { 127 return new MipsTargetStreamer(S); 128 } 129 130 static MCTargetStreamer * 131 createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { 132 return new MipsTargetELFStreamer(S, STI); 133 } 134 135 namespace { 136 137 class MipsMCInstrAnalysis : public MCInstrAnalysis { 138 public: 139 MipsMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {} 140 141 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, 142 uint64_t &Target) const override { 143 unsigned NumOps = Inst.getNumOperands(); 144 if (NumOps == 0) 145 return false; 146 switch (Info->get(Inst.getOpcode()).operands()[NumOps - 1].OperandType) { 147 case MCOI::OPERAND_UNKNOWN: 148 case MCOI::OPERAND_IMMEDIATE: { 149 // j, jal, jalx, jals 150 // Absolute branch within the current 256 MB-aligned region 151 uint64_t Region = Addr & ~uint64_t(0xfffffff); 152 Target = Region + Inst.getOperand(NumOps - 1).getImm(); 153 return true; 154 } 155 case MCOI::OPERAND_PCREL: 156 // b, beq ... 157 Target = Addr + Inst.getOperand(NumOps - 1).getImm(); 158 return true; 159 default: 160 return false; 161 } 162 } 163 }; 164 } 165 166 static MCInstrAnalysis *createMipsMCInstrAnalysis(const MCInstrInfo *Info) { 167 return new MipsMCInstrAnalysis(Info); 168 } 169 170 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTargetMC() { 171 for (Target *T : {&getTheMipsTarget(), &getTheMipselTarget(), 172 &getTheMips64Target(), &getTheMips64elTarget()}) { 173 // Register the MC asm info. 174 RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo); 175 176 // Register the MC instruction info. 177 TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo); 178 179 // Register the MC register info. 180 TargetRegistry::RegisterMCRegInfo(*T, createMipsMCRegisterInfo); 181 182 // Register the elf streamer. 183 TargetRegistry::RegisterELFStreamer(*T, createMCStreamer); 184 185 // Register the asm target streamer. 186 TargetRegistry::RegisterAsmTargetStreamer(*T, createMipsAsmTargetStreamer); 187 188 TargetRegistry::RegisterNullTargetStreamer(*T, 189 createMipsNullTargetStreamer); 190 191 // Register the MC subtarget info. 192 TargetRegistry::RegisterMCSubtargetInfo(*T, createMipsMCSubtargetInfo); 193 194 // Register the MC instruction analyzer. 195 TargetRegistry::RegisterMCInstrAnalysis(*T, createMipsMCInstrAnalysis); 196 197 // Register the MCInstPrinter. 198 TargetRegistry::RegisterMCInstPrinter(*T, createMipsMCInstPrinter); 199 200 TargetRegistry::RegisterObjectTargetStreamer( 201 *T, createMipsObjectTargetStreamer); 202 203 // Register the asm backend. 204 TargetRegistry::RegisterMCAsmBackend(*T, createMipsAsmBackend); 205 } 206 207 // Register the MC Code Emitter 208 for (Target *T : {&getTheMipsTarget(), &getTheMips64Target()}) 209 TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEB); 210 211 for (Target *T : {&getTheMipselTarget(), &getTheMips64elTarget()}) 212 TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL); 213 } 214